ClearSpeed Petapath Cn


ClearSpeed produces computational accelerators for HPC computing, including the CSX600 and CSX700 chips, and the “Advance” full-size PCI-X card that sports two CSX600 chips. The CSX architecture is a family of processors based on ClearSpeed’s multi-threaded array processor (MTAP) core. CSX processors can be used as application accelerators, alongside general-purpose processors such as those from Intel or AMD.

Unlike the GPUs, the ClearSpeed processors were made to operate on 64-bit floating-point data from the start and full error correction is present in the ClearSpeed processors. Furthermore, a Control & Debug unit present in an MTAP enables debugging within the accelerator on the PE level. This is a facility that is missing in GPUs and the FPGA accelerators.

Petapath, a spin-off of ClearSpeed especially for HPC, markets the so-called Feynman e740 and e780 devices. These units pack 4, resp. 8 e710 cards in one unit and can be connected by high-speed PCI Express ( 16× Gen. 2 PCIe at 8 GB/s) to a host processor. There is another feature that is peculiar to the e720 card: its power consumption is extremely low

The ClearSpeed Cn language is based on ANSI C with extensions to support the data-parallel architecture of the CSX processors. The main addition to standard C is the definition of mono (scalar) and poly (parallel) data types. The qualifier poly implies that each PE has its own copy of a value. For example, the definition poly int X; implies that, on the CSX600 with 96 PEs, there exist 96 copies of integer variable X, each having the same address within its PE’s local storage.

The ClearSpeed Software Development Kit (SDK) allows developers to write code to utilize the acceleration of the Advance boards. It consists of:
  • ANSI C-based optimizing compiler for the CSX600 and CSX700
  • Macro assembler
  • Linker, dynamic loader, debugger, Profiler, Eclipse IDE and other tools.
  • Various standard C libraries (most include support for both mono and poly data)

PRACE has evaluated prototypes based on Petapath/Clearspeed, including a system composed of ClearSpeed/PetaPath accelerator boards together with the ClearSpeed programming language Cn.

At the Netherlands Computing Facility in Amsterdam, Petapath and HP delivered a power-efficient system, built on eight HP SL170 servers and next generation accelerator prototypes. The system achieves a peak performance of 10 teraflop/s double precision, which is equivalent to more then 60 conventional servers. The system consumes only 6kW of power.

At the CINES supercomputing centre in Montpelier, France, Petapath incorporated the ClearSpeed accelerator technology into a conventional cluster designed by SGI and increased its performance by 50%, with only a 10% increase in power dissipation.

Each technology and architecture is currently being assessed with regard to peak performance/efficiency; programmability; energy efficiency; density; cooling and cost.

WP8.1.10 report on Clearspeed on Petapath concludes:
Future for Petapath looks rather dim:

  • ClearSpeed does not make haste with a successor of the CSX700 chip.
  • The two-stage data transfer makes it more difficult to achieve optimal performance then users expect.
  • The Cn programming model is fairly different from common experience.

The SDK is provided with a single-user floating license. Time limited evaluation licenses are also available. No license is required, and no royalties payable, on any software developed with the SDK. The Cn standard libraries are licensed under the terms of the GNU LGPL or similar terms and any software linked with those libraries must comply with those license terms.

Additional Info: