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/*
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 *  PPC emulation micro-operations for qemu.
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 * 
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 *  Copyright (c) 2003 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "config.h"
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#include "exec.h"
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//#define DEBUG_OP
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#define regs (env)
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#define Ts0 (int32_t)T0
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#define Ts1 (int32_t)T1
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#define Ts2 (int32_t)T2
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#define FT0 (env->ft0)
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#define FT1 (env->ft1)
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#define FT2 (env->ft2)
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#define FTS0 ((float)env->ft0)
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#define FTS1 ((float)env->ft1)
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#define FTS2 ((float)env->ft2)
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#define PPC_OP(name) void glue(op_, name)(void)
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#define REG 0
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#include "op_template.h"
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#define REG 1
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#include "op_template.h"
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#define REG 2
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#include "op_template.h"
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#define REG 3
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#include "op_template.h"
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#define REG 4
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#include "op_template.h"
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#define REG 5
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#include "op_template.h"
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#define REG 6
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#include "op_template.h"
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#define REG 7
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#include "op_template.h"
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#define REG 8
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#include "op_template.h"
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#define REG 9
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#include "op_template.h"
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#define REG 10
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#include "op_template.h"
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#define REG 11
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#include "op_template.h"
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#define REG 12
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#include "op_template.h"
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#define REG 13
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#include "op_template.h"
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#define REG 14
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#include "op_template.h"
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#define REG 15
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#include "op_template.h"
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#define REG 16
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#include "op_template.h"
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#define REG 17
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#include "op_template.h"
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#define REG 18
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#include "op_template.h"
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#define REG 19
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#include "op_template.h"
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#define REG 20
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#include "op_template.h"
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#define REG 21
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#include "op_template.h"
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#define REG 22
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#include "op_template.h"
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#define REG 23
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#include "op_template.h"
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#define REG 24
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#include "op_template.h"
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#define REG 25
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#include "op_template.h"
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#define REG 26
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#include "op_template.h"
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#define REG 27
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#include "op_template.h"
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#define REG 28
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#include "op_template.h"
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#define REG 29
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#include "op_template.h"
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#define REG 30
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#include "op_template.h"
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#define REG 31
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#include "op_template.h"
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/* PPC state maintenance operations */
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/* set_Rc0 */
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PPC_OP(set_Rc0)
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{
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    uint32_t tmp;
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    if (Ts0 < 0) {
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        tmp = 0x08;
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    } else if (Ts0 > 0) {
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        tmp = 0x04;
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    } else {
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        tmp = 0x02;
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    }
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    env->crf[0] = tmp;
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    RETURN();
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}
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PPC_OP(set_Rc0_ov)
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{
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    uint32_t tmp;
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    if (Ts0 < 0) {
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        tmp = 0x08;
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    } else if (Ts0 > 0) {
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        tmp = 0x04;
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    } else {
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        tmp = 0x02;
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    }
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    tmp |= xer_ov;
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    env->crf[0] = tmp;
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    RETURN();
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}
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/* reset_Rc0 */
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PPC_OP(reset_Rc0)
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{
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    env->crf[0] = 0x02 | xer_ov;
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    RETURN();
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}
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/* set_Rc0_1 */
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PPC_OP(set_Rc0_1)
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{
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    env->crf[0] = 0x04 | xer_ov;
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    RETURN();
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}
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/* Set Rc1 (for floating point arithmetic) */
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PPC_OP(set_Rc1)
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{
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    env->crf[1] = regs->fpscr[7];
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    RETURN();
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}
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/* Constants load */
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PPC_OP(set_T0)
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{
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    T0 = PARAM(1);
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    RETURN();
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}
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PPC_OP(set_T1)
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{
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    T1 = PARAM(1);
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    RETURN();
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}
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PPC_OP(set_T2)
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{
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    T2 = PARAM(1);
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    RETURN();
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}
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/* Generate exceptions */
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PPC_OP(queue_exception_err)
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{
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    do_queue_exception_err(PARAM(1), PARAM(2));
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}
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PPC_OP(queue_exception)
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{
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    do_queue_exception(PARAM(1));
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}
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PPC_OP(process_exceptions)
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{
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    env->nip = PARAM(1);
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    if (env->exceptions != 0) {
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        do_check_exception_state();
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    }
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}
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/* Segment registers load and store with immediate index */
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PPC_OP(load_srin)
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{
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    T0 = regs->sr[T1 >> 28];
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    RETURN();
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}
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PPC_OP(store_srin)
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{
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#if defined (DEBUG_OP)
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    dump_store_sr(T1 >> 28);
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#endif
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    regs->sr[T1 >> 28] = T0;
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    RETURN();
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}
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PPC_OP(load_sdr1)
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{
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    T0 = regs->sdr1;
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    RETURN();
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}
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PPC_OP(store_sdr1)
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{
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    regs->sdr1 = T0;
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    RETURN();
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}
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PPC_OP(exit_tb)
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{
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    EXIT_TB();
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}
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/* Load/store special registers */
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PPC_OP(load_cr)
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{
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    do_load_cr();
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    RETURN();
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}
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PPC_OP(store_cr)
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{
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    do_store_cr(PARAM(1));
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    RETURN();
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}
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PPC_OP(load_xer_cr)
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{
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    T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1);
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    RETURN();
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}
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PPC_OP(clear_xer_cr)
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{
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    xer_so = 0;
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    xer_ov = 0;
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    xer_ca = 0;
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    RETURN();
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}
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PPC_OP(load_xer_bc)
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{
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    T1 = xer_bc;
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    RETURN();
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}
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PPC_OP(load_xer)
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{
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    do_load_xer();
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    RETURN();
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}
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PPC_OP(store_xer)
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{
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    do_store_xer();
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    RETURN();
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}
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PPC_OP(load_msr)
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{
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    do_load_msr();
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    RETURN();
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}
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PPC_OP(store_msr)
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{
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    do_store_msr();
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    RETURN();
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}
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/* SPR */
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PPC_OP(load_spr)
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{
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    T0 = regs->spr[PARAM(1)];
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    RETURN();
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}
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PPC_OP(store_spr)
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{
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    regs->spr[PARAM(1)] = T0;
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    RETURN();
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}
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PPC_OP(load_lr)
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{
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    T0 = regs->lr;
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    RETURN();
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}
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PPC_OP(store_lr)
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{
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    regs->lr = T0;
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    RETURN();
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}
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PPC_OP(load_ctr)
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{
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    T0 = regs->ctr;
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    RETURN();
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}
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PPC_OP(store_ctr)
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{
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    regs->ctr = T0;
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    RETURN();
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}
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/* Update time base */
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PPC_OP(update_tb)
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{
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    T0 = regs->tb[0];
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    T1 = T0;
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    T0 += PARAM(1);
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#if defined (DEBUG_OP)
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    dump_update_tb(PARAM(1));
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#endif
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    if (T0 < T1) {
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        T1 = regs->tb[1] + 1;
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        regs->tb[1] = T1;
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    }
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    regs->tb[0] = T0;
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    RETURN();
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}
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PPC_OP(load_tb)
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{
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    T0 = regs->tb[PARAM(1)];
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    RETURN();
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}
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PPC_OP(store_tb)
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{
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    regs->tb[PARAM(1)] = T0;
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#if defined (DEBUG_OP)
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    dump_store_tb(PARAM(1));
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#endif
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    RETURN();
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}
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/* Update decrementer */
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PPC_OP(update_decr)
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{
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    T0 = regs->decr;
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    T1 = T0;
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    T0 -= PARAM(1);
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    regs->decr = T0;
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    if (PARAM(1) > T1) {
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        do_queue_exception(EXCP_DECR);
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    }
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    RETURN();
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}
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PPC_OP(store_decr)
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{
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    T1 = regs->decr;
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    regs->decr = T0;
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    if (Ts0 < 0 && Ts1 > 0) {
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        do_queue_exception(EXCP_DECR);
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    }
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    RETURN();
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}
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PPC_OP(load_ibat)
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{
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    T0 = regs->IBAT[PARAM(1)][PARAM(2)];
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}
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PPC_OP(store_ibat)
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{
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#if defined (DEBUG_OP)
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    dump_store_ibat(PARAM(1), PARAM(2));
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#endif
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    regs->IBAT[PARAM(1)][PARAM(2)] = T0;
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}
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PPC_OP(load_dbat)
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{
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    T0 = regs->DBAT[PARAM(1)][PARAM(2)];
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}
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PPC_OP(store_dbat)
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{
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#if defined (DEBUG_OP)
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    dump_store_dbat(PARAM(1), PARAM(2));
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#endif
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    regs->DBAT[PARAM(1)][PARAM(2)] = T0;
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}
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/* FPSCR */
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PPC_OP(load_fpscr)
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{
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    do_load_fpscr();
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    RETURN();
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}
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PPC_OP(store_fpscr)
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{
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    do_store_fpscr(PARAM(1));
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    RETURN();
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}
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PPC_OP(reset_scrfx)
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{
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    regs->fpscr[7] &= ~0x8;
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    RETURN();
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}
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/* crf operations */
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PPC_OP(getbit_T0)
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{
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    T0 = (T0 >> PARAM(1)) & 1;
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    RETURN();
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}
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PPC_OP(getbit_T1)
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{
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    T1 = (T1 >> PARAM(1)) & 1;
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    RETURN();
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}
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PPC_OP(setcrfbit)
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{
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    T1 = (T1 & PARAM(1)) | (T0 << PARAM(2)); 
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    RETURN();
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}
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475 79aceca5 bellard
/* Branch */
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#if 0
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#define EIP regs->nip
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#define TB_DO_JUMP(name, tb, n, target) JUMP_TB(name, tb, n, target)
479 9a64fbe4 bellard
#else
480 9a64fbe4 bellard
#define TB_DO_JUMP(name, tb, n, target) regs->nip = target;
481 9a64fbe4 bellard
#endif
482 9a64fbe4 bellard
483 79aceca5 bellard
#define __PPC_OP_B(name, target)                                              \
484 79aceca5 bellard
PPC_OP(name)                                                                  \
485 79aceca5 bellard
{                                                                             \
486 9a64fbe4 bellard
    TB_DO_JUMP(glue(op_, name), T1, 0, (target));                             \
487 79aceca5 bellard
    RETURN();                                                                 \
488 79aceca5 bellard
}
489 79aceca5 bellard
490 9a64fbe4 bellard
#define __PPC_OP_BL(name, target, link)                                       \
491 79aceca5 bellard
PPC_OP(name)                                                                  \
492 79aceca5 bellard
{                                                                             \
493 9a64fbe4 bellard
    regs->lr = (link);                                                        \
494 9a64fbe4 bellard
    TB_DO_JUMP(glue(op_, name), T1, 0, (target));                             \
495 79aceca5 bellard
    RETURN();                                                                 \
496 79aceca5 bellard
}
497 79aceca5 bellard
498 9a64fbe4 bellard
#define PPC_OP_B(name, target, link)                                          \
499 79aceca5 bellard
__PPC_OP_B(name, target);                                                     \
500 9a64fbe4 bellard
__PPC_OP_BL(glue(name, l), target, link)
501 79aceca5 bellard
502 79aceca5 bellard
#define __PPC_OP_BC(name, cond, target)                                       \
503 79aceca5 bellard
PPC_OP(name)                                                                  \
504 79aceca5 bellard
{                                                                             \
505 79aceca5 bellard
    if (cond) {                                                               \
506 9a64fbe4 bellard
        TB_DO_JUMP(glue(op_, name), T1, 1, (target));                         \
507 79aceca5 bellard
    } else {                                                                  \
508 9a64fbe4 bellard
        TB_DO_JUMP(glue(op_, name), T1, 0, PARAM(1));                         \
509 79aceca5 bellard
    }                                                                         \
510 79aceca5 bellard
    RETURN();                                                                 \
511 79aceca5 bellard
}
512 79aceca5 bellard
513 79aceca5 bellard
#define __PPC_OP_BCL(name, cond, target)                                      \
514 79aceca5 bellard
PPC_OP(name)                                                                  \
515 79aceca5 bellard
{                                                                             \
516 9a64fbe4 bellard
    regs->lr = PARAM(1);                                                      \
517 79aceca5 bellard
    if (cond) {                                                               \
518 9a64fbe4 bellard
        TB_DO_JUMP(glue(op_, name), T1, 1, (target));                         \
519 79aceca5 bellard
    } else {                                                                  \
520 9a64fbe4 bellard
        TB_DO_JUMP(glue(op_, name), T1, 0, PARAM(1));                         \
521 9a64fbe4 bellard
    }                                                                         \
522 9a64fbe4 bellard
    RETURN();                                                                 \
523 9a64fbe4 bellard
}
524 9a64fbe4 bellard
525 9a64fbe4 bellard
#define __PPC_OP_BCLRL(name, cond, target)                                    \
526 9a64fbe4 bellard
PPC_OP(name)                                                                  \
527 9a64fbe4 bellard
{                                                                             \
528 9a64fbe4 bellard
    T2 = (target);                                                            \
529 9a64fbe4 bellard
    regs->lr = PARAM(1);                                                      \
530 9a64fbe4 bellard
    if (cond) {                                                               \
531 9a64fbe4 bellard
        TB_DO_JUMP(glue(op_, name), T1, 1, T2);                               \
532 9a64fbe4 bellard
    } else {                                                                  \
533 9a64fbe4 bellard
        TB_DO_JUMP(glue(op_, name), T1, 0, PARAM(1));                         \
534 79aceca5 bellard
    }                                                                         \
535 79aceca5 bellard
    RETURN();                                                                 \
536 79aceca5 bellard
}
537 79aceca5 bellard
538 79aceca5 bellard
#define _PPC_OP_BC(name, namel, cond, target)                                 \
539 79aceca5 bellard
__PPC_OP_BC(name, cond, target);                                              \
540 79aceca5 bellard
__PPC_OP_BCL(namel, cond, target)
541 79aceca5 bellard
542 79aceca5 bellard
/* Branch to target */
543 79aceca5 bellard
#define PPC_OP_BC(name, cond)                                                 \
544 79aceca5 bellard
_PPC_OP_BC(b_##name, bl_##name, cond, PARAM(2))
545 79aceca5 bellard
546 9a64fbe4 bellard
PPC_OP_B(b, PARAM(1), PARAM(2));
547 9a64fbe4 bellard
PPC_OP_BC(ctr,        (regs->ctr != 0));
548 9a64fbe4 bellard
PPC_OP_BC(ctr_true,   (regs->ctr != 0 && (T0 & PARAM(3)) != 0));
549 9a64fbe4 bellard
PPC_OP_BC(ctr_false,  (regs->ctr != 0 && (T0 & PARAM(3)) == 0));
550 9a64fbe4 bellard
PPC_OP_BC(ctrz,       (regs->ctr == 0));
551 9a64fbe4 bellard
PPC_OP_BC(ctrz_true,  (regs->ctr == 0 && (T0 & PARAM(3)) != 0));
552 9a64fbe4 bellard
PPC_OP_BC(ctrz_false, (regs->ctr == 0 && (T0 & PARAM(3)) == 0));
553 79aceca5 bellard
PPC_OP_BC(true,       ((T0 & PARAM(3)) != 0));
554 79aceca5 bellard
PPC_OP_BC(false,      ((T0 & PARAM(3)) == 0));
555 79aceca5 bellard
556 79aceca5 bellard
/* Branch to CTR */
557 79aceca5 bellard
#define PPC_OP_BCCTR(name, cond)                                              \
558 9a64fbe4 bellard
_PPC_OP_BC(bctr_##name, bctrl_##name, cond, regs->ctr & ~0x03)
559 9a64fbe4 bellard
560 9a64fbe4 bellard
PPC_OP_B(bctr, regs->ctr & ~0x03, PARAM(1));
561 9a64fbe4 bellard
PPC_OP_BCCTR(ctr,        (regs->ctr != 0));
562 9a64fbe4 bellard
PPC_OP_BCCTR(ctr_true,   (regs->ctr != 0 && (T0 & PARAM(2)) != 0));
563 9a64fbe4 bellard
PPC_OP_BCCTR(ctr_false,  (regs->ctr != 0 && (T0 & PARAM(2)) == 0));
564 9a64fbe4 bellard
PPC_OP_BCCTR(ctrz,       (regs->ctr == 0));
565 9a64fbe4 bellard
PPC_OP_BCCTR(ctrz_true,  (regs->ctr == 0 && (T0 & PARAM(2)) != 0));
566 9a64fbe4 bellard
PPC_OP_BCCTR(ctrz_false, (regs->ctr == 0 && (T0 & PARAM(2)) == 0));
567 79aceca5 bellard
PPC_OP_BCCTR(true,       ((T0 & PARAM(2)) != 0));
568 79aceca5 bellard
PPC_OP_BCCTR(false,      ((T0 & PARAM(2)) == 0));
569 79aceca5 bellard
570 79aceca5 bellard
/* Branch to LR */
571 79aceca5 bellard
#define PPC_OP_BCLR(name, cond)                                               \
572 9a64fbe4 bellard
__PPC_OP_BC(blr_##name, cond, regs->lr & ~0x03);                              \
573 9a64fbe4 bellard
__PPC_OP_BCLRL(blrl_##name, cond, regs->lr & ~0x03)
574 9a64fbe4 bellard
575 9a64fbe4 bellard
__PPC_OP_B(blr, regs->lr & ~0x03);
576 9a64fbe4 bellard
PPC_OP(blrl)
577 9a64fbe4 bellard
{
578 9a64fbe4 bellard
    T0 = regs->lr & ~0x03;
579 9a64fbe4 bellard
    regs->lr = PARAM(1);
580 9a64fbe4 bellard
    TB_DO_JUMP(op_blrl, T1, 0, T0);
581 9a64fbe4 bellard
    RETURN();
582 9a64fbe4 bellard
}
583 9a64fbe4 bellard
PPC_OP_BCLR(ctr,        (regs->ctr != 0));
584 9a64fbe4 bellard
PPC_OP_BCLR(ctr_true,   (regs->ctr != 0 && (T0 & PARAM(2)) != 0));
585 9a64fbe4 bellard
PPC_OP_BCLR(ctr_false,  (regs->ctr != 0 && (T0 & PARAM(2)) == 0));
586 9a64fbe4 bellard
PPC_OP_BCLR(ctrz,       (regs->ctr == 0));
587 9a64fbe4 bellard
PPC_OP_BCLR(ctrz_true,  (regs->ctr == 0 && (T0 & PARAM(2)) != 0));
588 9a64fbe4 bellard
PPC_OP_BCLR(ctrz_false, (regs->ctr == 0 && (T0 & PARAM(2)) == 0));
589 79aceca5 bellard
PPC_OP_BCLR(true,       ((T0 & PARAM(2)) != 0));
590 79aceca5 bellard
PPC_OP_BCLR(false,      ((T0 & PARAM(2)) == 0));
591 79aceca5 bellard
592 79aceca5 bellard
/* CTR maintenance */
593 79aceca5 bellard
PPC_OP(dec_ctr)
594 79aceca5 bellard
{
595 9a64fbe4 bellard
    regs->ctr--;
596 79aceca5 bellard
    RETURN();
597 79aceca5 bellard
}
598 79aceca5 bellard
599 79aceca5 bellard
/***                           Integer arithmetic                          ***/
600 79aceca5 bellard
/* add */
601 79aceca5 bellard
PPC_OP(add)
602 79aceca5 bellard
{
603 79aceca5 bellard
    T0 += T1;
604 79aceca5 bellard
    RETURN();
605 79aceca5 bellard
}
606 79aceca5 bellard
607 79aceca5 bellard
PPC_OP(addo)
608 79aceca5 bellard
{
609 79aceca5 bellard
    T2 = T0;
610 79aceca5 bellard
    T0 += T1;
611 79aceca5 bellard
    if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) {
612 79aceca5 bellard
        xer_so = 1;
613 79aceca5 bellard
        xer_ov = 1;
614 79aceca5 bellard
    } else {
615 79aceca5 bellard
        xer_ov = 0;
616 79aceca5 bellard
    }
617 79aceca5 bellard
    RETURN();
618 79aceca5 bellard
}
619 79aceca5 bellard
620 79aceca5 bellard
/* add carrying */
621 79aceca5 bellard
PPC_OP(addc)
622 79aceca5 bellard
{
623 79aceca5 bellard
    T2 = T0;
624 79aceca5 bellard
    T0 += T1;
625 79aceca5 bellard
    if (T0 < T2) {
626 79aceca5 bellard
        xer_ca = 1;
627 79aceca5 bellard
    } else {
628 79aceca5 bellard
        xer_ca = 0;
629 79aceca5 bellard
    }
630 79aceca5 bellard
    RETURN();
631 79aceca5 bellard
}
632 79aceca5 bellard
633 79aceca5 bellard
PPC_OP(addco)
634 79aceca5 bellard
{
635 79aceca5 bellard
    T2 = T0;
636 79aceca5 bellard
    T0 += T1;
637 79aceca5 bellard
    if (T0 < T2) {
638 79aceca5 bellard
        xer_ca = 1;
639 79aceca5 bellard
    } else {
640 79aceca5 bellard
        xer_ca = 0;
641 79aceca5 bellard
    }
642 79aceca5 bellard
    if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) {
643 79aceca5 bellard
        xer_so = 1;
644 79aceca5 bellard
        xer_ov = 1;
645 79aceca5 bellard
    } else {
646 79aceca5 bellard
        xer_ov = 0;
647 79aceca5 bellard
    }
648 79aceca5 bellard
    RETURN();
649 79aceca5 bellard
}
650 79aceca5 bellard
651 79aceca5 bellard
/* add extended */
652 79aceca5 bellard
/* candidate for helper (too long) */
653 79aceca5 bellard
PPC_OP(adde)
654 79aceca5 bellard
{
655 79aceca5 bellard
    T2 = T0;
656 79aceca5 bellard
    T0 += T1 + xer_ca;
657 79aceca5 bellard
    if (T0 < T2 || (xer_ca == 1 && T0 == T2)) {
658 79aceca5 bellard
        xer_ca = 1;
659 79aceca5 bellard
    } else {
660 79aceca5 bellard
        xer_ca = 0;
661 79aceca5 bellard
    }
662 79aceca5 bellard
    RETURN();
663 79aceca5 bellard
}
664 79aceca5 bellard
665 79aceca5 bellard
PPC_OP(addeo)
666 79aceca5 bellard
{
667 79aceca5 bellard
    T2 = T0;
668 79aceca5 bellard
    T0 += T1 + xer_ca;
669 79aceca5 bellard
    if (T0 < T2 || (xer_ca == 1 && T0 == T2)) {
670 79aceca5 bellard
        xer_ca = 1;
671 79aceca5 bellard
    } else {
672 79aceca5 bellard
        xer_ca = 0;
673 79aceca5 bellard
    }
674 79aceca5 bellard
    if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) {
675 79aceca5 bellard
        xer_so = 1;
676 79aceca5 bellard
        xer_ov = 1;
677 79aceca5 bellard
    } else {
678 79aceca5 bellard
        xer_ov = 0;
679 79aceca5 bellard
    }
680 79aceca5 bellard
    RETURN();
681 79aceca5 bellard
}
682 79aceca5 bellard
683 79aceca5 bellard
/* add immediate */
684 79aceca5 bellard
PPC_OP(addi)
685 79aceca5 bellard
{
686 79aceca5 bellard
    T0 += PARAM(1);
687 79aceca5 bellard
    RETURN();
688 79aceca5 bellard
}
689 79aceca5 bellard
690 79aceca5 bellard
/* add immediate carrying */
691 79aceca5 bellard
PPC_OP(addic)
692 79aceca5 bellard
{
693 79aceca5 bellard
    T1 = T0;
694 79aceca5 bellard
    T0 += PARAM(1);
695 79aceca5 bellard
    if (T0 < T1) {
696 79aceca5 bellard
        xer_ca = 1;
697 79aceca5 bellard
    } else {
698 79aceca5 bellard
        xer_ca = 0;
699 79aceca5 bellard
    }
700 79aceca5 bellard
    RETURN();
701 79aceca5 bellard
}
702 79aceca5 bellard
703 79aceca5 bellard
/* add to minus one extended */
704 79aceca5 bellard
PPC_OP(addme)
705 79aceca5 bellard
{
706 79aceca5 bellard
    T1 = T0;
707 79aceca5 bellard
    T0 += xer_ca + (-1);
708 79aceca5 bellard
    if (T1 != 0)
709 79aceca5 bellard
        xer_ca = 1;
710 79aceca5 bellard
    RETURN();
711 79aceca5 bellard
}
712 79aceca5 bellard
713 79aceca5 bellard
PPC_OP(addmeo)
714 79aceca5 bellard
{
715 79aceca5 bellard
    T1 = T0;
716 79aceca5 bellard
    T0 += xer_ca + (-1);
717 79aceca5 bellard
    if (T1 & (T1 ^ T0) & (1 << 31)) {
718 79aceca5 bellard
        xer_so = 1;
719 79aceca5 bellard
        xer_ov = 1;
720 79aceca5 bellard
    } else {
721 79aceca5 bellard
        xer_ov = 0;
722 79aceca5 bellard
    }
723 79aceca5 bellard
    if (T1 != 0)
724 79aceca5 bellard
        xer_ca = 1;
725 79aceca5 bellard
    RETURN();
726 79aceca5 bellard
}
727 79aceca5 bellard
728 79aceca5 bellard
/* add to zero extended */
729 79aceca5 bellard
PPC_OP(addze)
730 79aceca5 bellard
{
731 79aceca5 bellard
    T1 = T0;
732 79aceca5 bellard
    T0 += xer_ca;
733 79aceca5 bellard
    if (T0 < T1) {
734 79aceca5 bellard
        xer_ca = 1;
735 79aceca5 bellard
    } else {
736 79aceca5 bellard
        xer_ca = 0;
737 79aceca5 bellard
    }
738 79aceca5 bellard
    RETURN();
739 79aceca5 bellard
}
740 79aceca5 bellard
741 79aceca5 bellard
PPC_OP(addzeo)
742 79aceca5 bellard
{
743 79aceca5 bellard
    T1 = T0;
744 79aceca5 bellard
    T0 += xer_ca;
745 79aceca5 bellard
    if ((T1 ^ (-1)) & (T1 ^ T0) & (1 << 31)) {
746 79aceca5 bellard
        xer_so = 1;
747 79aceca5 bellard
        xer_ov = 1;
748 79aceca5 bellard
    } else {
749 79aceca5 bellard
        xer_ov = 0;
750 79aceca5 bellard
    }
751 79aceca5 bellard
    if (T0 < T1) {
752 79aceca5 bellard
        xer_ca = 1;
753 79aceca5 bellard
    } else {
754 79aceca5 bellard
        xer_ca = 0;
755 79aceca5 bellard
    }
756 79aceca5 bellard
    RETURN();
757 79aceca5 bellard
}
758 79aceca5 bellard
759 79aceca5 bellard
/* divide word */
760 79aceca5 bellard
/* candidate for helper (too long) */
761 79aceca5 bellard
PPC_OP(divw)
762 79aceca5 bellard
{
763 79aceca5 bellard
    if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) {
764 79aceca5 bellard
        Ts0 = (-1) * (T0 >> 31);
765 79aceca5 bellard
    } else {
766 79aceca5 bellard
        Ts0 /= Ts1;
767 79aceca5 bellard
    }
768 79aceca5 bellard
    RETURN();
769 79aceca5 bellard
}
770 79aceca5 bellard
771 79aceca5 bellard
PPC_OP(divwo)
772 79aceca5 bellard
{
773 79aceca5 bellard
    if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) {
774 79aceca5 bellard
        xer_so = 1;
775 79aceca5 bellard
        xer_ov = 1;
776 79aceca5 bellard
        T0 = (-1) * (T0 >> 31);
777 79aceca5 bellard
    } else {
778 79aceca5 bellard
        xer_ov = 0;
779 79aceca5 bellard
        Ts0 /= Ts1;
780 79aceca5 bellard
    }
781 79aceca5 bellard
    RETURN();
782 79aceca5 bellard
}
783 79aceca5 bellard
784 79aceca5 bellard
/* divide word unsigned */
785 79aceca5 bellard
PPC_OP(divwu)
786 79aceca5 bellard
{
787 79aceca5 bellard
    if (T1 == 0) {
788 79aceca5 bellard
        T0 = 0;
789 79aceca5 bellard
    } else {
790 79aceca5 bellard
        T0 /= T1;
791 79aceca5 bellard
    }
792 79aceca5 bellard
    RETURN();
793 79aceca5 bellard
}
794 79aceca5 bellard
795 79aceca5 bellard
PPC_OP(divwuo)
796 79aceca5 bellard
{
797 79aceca5 bellard
    if (T1 == 0) {
798 79aceca5 bellard
        xer_so = 1;
799 79aceca5 bellard
        xer_ov = 1;
800 79aceca5 bellard
        T0 = 0;
801 79aceca5 bellard
    } else {
802 79aceca5 bellard
        xer_ov = 0;
803 79aceca5 bellard
        T0 /= T1;
804 79aceca5 bellard
    }
805 79aceca5 bellard
    RETURN();
806 79aceca5 bellard
}
807 79aceca5 bellard
808 79aceca5 bellard
/* multiply high word */
809 79aceca5 bellard
PPC_OP(mulhw)
810 79aceca5 bellard
{
811 79aceca5 bellard
    Ts0 = ((int64_t)Ts0 * (int64_t)Ts1) >> 32;
812 79aceca5 bellard
    RETURN();
813 79aceca5 bellard
}
814 79aceca5 bellard
815 79aceca5 bellard
/* multiply high word unsigned */
816 79aceca5 bellard
PPC_OP(mulhwu)
817 79aceca5 bellard
{
818 79aceca5 bellard
    T0 = ((uint64_t)T0 * (uint64_t)T1) >> 32;
819 79aceca5 bellard
    RETURN();
820 79aceca5 bellard
}
821 79aceca5 bellard
822 79aceca5 bellard
/* multiply low immediate */
823 79aceca5 bellard
PPC_OP(mulli)
824 79aceca5 bellard
{
825 79aceca5 bellard
    Ts0 *= SPARAM(1);
826 79aceca5 bellard
    RETURN();
827 79aceca5 bellard
}
828 79aceca5 bellard
829 79aceca5 bellard
/* multiply low word */
830 79aceca5 bellard
PPC_OP(mullw)
831 79aceca5 bellard
{
832 79aceca5 bellard
    T0 *= T1;
833 79aceca5 bellard
    RETURN();
834 79aceca5 bellard
}
835 79aceca5 bellard
836 79aceca5 bellard
PPC_OP(mullwo)
837 79aceca5 bellard
{
838 79aceca5 bellard
    int64_t res = (int64_t)Ts0 * (int64_t)Ts1;
839 79aceca5 bellard
840 79aceca5 bellard
    if ((int32_t)res != res) {
841 79aceca5 bellard
        xer_ov = 1;
842 79aceca5 bellard
        xer_so = 1;
843 79aceca5 bellard
    } else {
844 79aceca5 bellard
        xer_ov = 0;
845 79aceca5 bellard
    }
846 79aceca5 bellard
    Ts0 = res;
847 79aceca5 bellard
    RETURN();
848 79aceca5 bellard
}
849 79aceca5 bellard
850 79aceca5 bellard
/* negate */
851 79aceca5 bellard
PPC_OP(neg)
852 79aceca5 bellard
{
853 79aceca5 bellard
    if (T0 != 0x80000000) {
854 79aceca5 bellard
        Ts0 = -Ts0;
855 79aceca5 bellard
    }
856 79aceca5 bellard
    RETURN();
857 79aceca5 bellard
}
858 79aceca5 bellard
859 79aceca5 bellard
PPC_OP(nego)
860 79aceca5 bellard
{
861 79aceca5 bellard
    if (T0 == 0x80000000) {
862 79aceca5 bellard
        xer_ov = 1;
863 79aceca5 bellard
        xer_so = 1;
864 79aceca5 bellard
    } else {
865 79aceca5 bellard
        xer_ov = 0;
866 79aceca5 bellard
        Ts0 = -Ts0;
867 79aceca5 bellard
    }
868 79aceca5 bellard
    RETURN();
869 79aceca5 bellard
}
870 79aceca5 bellard
871 79aceca5 bellard
/* substract from */
872 79aceca5 bellard
PPC_OP(subf)
873 79aceca5 bellard
{
874 79aceca5 bellard
    T0 = T1 - T0;
875 79aceca5 bellard
    RETURN();
876 79aceca5 bellard
}
877 79aceca5 bellard
878 79aceca5 bellard
PPC_OP(subfo)
879 79aceca5 bellard
{
880 79aceca5 bellard
    T2 = T0;
881 79aceca5 bellard
    T0 = T1 - T0;
882 79aceca5 bellard
    if (((~T2) ^ T1 ^ (-1)) & ((~T2) ^ T0) & (1 << 31)) {
883 79aceca5 bellard
        xer_so = 1;
884 79aceca5 bellard
        xer_ov = 1;
885 79aceca5 bellard
    } else {
886 79aceca5 bellard
        xer_ov = 0;
887 79aceca5 bellard
    }
888 79aceca5 bellard
    RETURN();
889 79aceca5 bellard
}
890 79aceca5 bellard
891 79aceca5 bellard
/* substract from carrying */
892 79aceca5 bellard
PPC_OP(subfc)
893 79aceca5 bellard
{
894 79aceca5 bellard
    T0 = T1 - T0;
895 79aceca5 bellard
    if (T0 <= T1) {
896 79aceca5 bellard
        xer_ca = 1;
897 79aceca5 bellard
    } else {
898 79aceca5 bellard
        xer_ca = 0;
899 79aceca5 bellard
    }
900 79aceca5 bellard
    RETURN();
901 79aceca5 bellard
}
902 79aceca5 bellard
903 79aceca5 bellard
PPC_OP(subfco)
904 79aceca5 bellard
{
905 79aceca5 bellard
    T2 = T0;
906 79aceca5 bellard
    T0 = T1 - T0;
907 79aceca5 bellard
    if (T0 <= T1) {
908 79aceca5 bellard
        xer_ca = 1;
909 79aceca5 bellard
    } else {
910 79aceca5 bellard
        xer_ca = 0;
911 79aceca5 bellard
    }
912 79aceca5 bellard
    if (((~T2) ^ T1 ^ (-1)) & ((~T2) ^ T0) & (1 << 31)) {
913 79aceca5 bellard
        xer_so = 1;
914 79aceca5 bellard
        xer_ov = 1;
915 79aceca5 bellard
    } else {
916 79aceca5 bellard
        xer_ov = 0;
917 79aceca5 bellard
    }
918 79aceca5 bellard
    RETURN();
919 79aceca5 bellard
}
920 79aceca5 bellard
921 79aceca5 bellard
/* substract from extended */
922 79aceca5 bellard
/* candidate for helper (too long) */
923 79aceca5 bellard
PPC_OP(subfe)
924 79aceca5 bellard
{
925 79aceca5 bellard
    T0 = T1 + ~T0 + xer_ca;
926 79aceca5 bellard
    if (T0 < T1 || (xer_ca == 1 && T0 == T1)) {
927 79aceca5 bellard
        xer_ca = 1;
928 79aceca5 bellard
    } else {
929 79aceca5 bellard
        xer_ca = 0;
930 79aceca5 bellard
    }
931 79aceca5 bellard
    RETURN();
932 79aceca5 bellard
}
933 79aceca5 bellard
934 79aceca5 bellard
PPC_OP(subfeo)
935 79aceca5 bellard
{
936 79aceca5 bellard
    T2 = T0;
937 79aceca5 bellard
    T0 = T1 + ~T0 + xer_ca;
938 79aceca5 bellard
    if ((~T2 ^ T1 ^ (-1)) & (~T2 ^ T0) & (1 << 31)) {
939 79aceca5 bellard
        xer_so = 1;
940 79aceca5 bellard
        xer_ov = 1;
941 79aceca5 bellard
    } else {
942 79aceca5 bellard
        xer_ov = 0;
943 79aceca5 bellard
    }
944 79aceca5 bellard
    if (T0 < T1 || (xer_ca == 1 && T0 == T1)) {
945 79aceca5 bellard
        xer_ca = 1;
946 79aceca5 bellard
    } else {
947 79aceca5 bellard
        xer_ca = 0;
948 79aceca5 bellard
    }
949 79aceca5 bellard
    RETURN();
950 79aceca5 bellard
}
951 79aceca5 bellard
952 79aceca5 bellard
/* substract from immediate carrying */
953 79aceca5 bellard
PPC_OP(subfic)
954 79aceca5 bellard
{
955 79aceca5 bellard
    T0 = PARAM(1) + ~T0 + 1;
956 79aceca5 bellard
    if (T0 <= PARAM(1)) {
957 79aceca5 bellard
        xer_ca = 1;
958 79aceca5 bellard
    } else {
959 79aceca5 bellard
        xer_ca = 0;
960 79aceca5 bellard
    }
961 79aceca5 bellard
    RETURN();
962 79aceca5 bellard
}
963 79aceca5 bellard
964 79aceca5 bellard
/* substract from minus one extended */
965 79aceca5 bellard
PPC_OP(subfme)
966 79aceca5 bellard
{
967 79aceca5 bellard
    T0 = ~T0 + xer_ca - 1;
968 79aceca5 bellard
969 79aceca5 bellard
    if (T0 != -1)
970 79aceca5 bellard
        xer_ca = 1;
971 79aceca5 bellard
    RETURN();
972 79aceca5 bellard
}
973 79aceca5 bellard
974 79aceca5 bellard
PPC_OP(subfmeo)
975 79aceca5 bellard
{
976 79aceca5 bellard
    T1 = T0;
977 79aceca5 bellard
    T0 = ~T0 + xer_ca - 1;
978 79aceca5 bellard
    if (~T1 & (~T1 ^ T0) & (1 << 31)) {
979 79aceca5 bellard
        xer_so = 1;
980 79aceca5 bellard
        xer_ov = 1;
981 79aceca5 bellard
    } else {
982 79aceca5 bellard
        xer_ov = 0;
983 79aceca5 bellard
    }
984 79aceca5 bellard
    if (T1 != -1)
985 79aceca5 bellard
        xer_ca = 1;
986 79aceca5 bellard
    RETURN();
987 79aceca5 bellard
}
988 79aceca5 bellard
989 79aceca5 bellard
/* substract from zero extended */
990 79aceca5 bellard
PPC_OP(subfze)
991 79aceca5 bellard
{
992 79aceca5 bellard
    T1 = ~T0;
993 79aceca5 bellard
    T0 = T1 + xer_ca;
994 79aceca5 bellard
    if (T0 < T1) {
995 79aceca5 bellard
        xer_ca = 1;
996 79aceca5 bellard
    } else {
997 79aceca5 bellard
        xer_ca = 0;
998 79aceca5 bellard
    }
999 79aceca5 bellard
    RETURN();
1000 79aceca5 bellard
}
1001 79aceca5 bellard
1002 79aceca5 bellard
PPC_OP(subfzeo)
1003 79aceca5 bellard
{
1004 79aceca5 bellard
    T1 = T0;
1005 79aceca5 bellard
    T0 = ~T0 + xer_ca;
1006 79aceca5 bellard
    if ((~T1 ^ (-1)) & ((~T1) ^ T0) & (1 << 31)) {
1007 79aceca5 bellard
        xer_ov = 1;
1008 79aceca5 bellard
        xer_so = 1;
1009 79aceca5 bellard
    } else {
1010 79aceca5 bellard
        xer_ov = 0;
1011 79aceca5 bellard
    }
1012 79aceca5 bellard
    if (T0 < ~T1) {
1013 79aceca5 bellard
        xer_ca = 1;
1014 79aceca5 bellard
    } else {
1015 79aceca5 bellard
        xer_ca = 0;
1016 79aceca5 bellard
    }
1017 79aceca5 bellard
    RETURN();
1018 79aceca5 bellard
}
1019 79aceca5 bellard
1020 79aceca5 bellard
/***                           Integer comparison                          ***/
1021 79aceca5 bellard
/* compare */
1022 79aceca5 bellard
PPC_OP(cmp)
1023 79aceca5 bellard
{
1024 79aceca5 bellard
    if (Ts0 < Ts1) {
1025 79aceca5 bellard
        T0 = 0x08;
1026 79aceca5 bellard
    } else if (Ts0 > Ts1) {
1027 79aceca5 bellard
        T0 = 0x04;
1028 79aceca5 bellard
    } else {
1029 79aceca5 bellard
        T0 = 0x02;
1030 79aceca5 bellard
    }
1031 79aceca5 bellard
    RETURN();
1032 79aceca5 bellard
}
1033 79aceca5 bellard
1034 79aceca5 bellard
/* compare immediate */
1035 79aceca5 bellard
PPC_OP(cmpi)
1036 79aceca5 bellard
{
1037 79aceca5 bellard
    if (Ts0 < SPARAM(1)) {
1038 79aceca5 bellard
        T0 = 0x08;
1039 79aceca5 bellard
    } else if (Ts0 > SPARAM(1)) {
1040 79aceca5 bellard
        T0 = 0x04;
1041 79aceca5 bellard
    } else {
1042 79aceca5 bellard
        T0 = 0x02;
1043 79aceca5 bellard
    }
1044 79aceca5 bellard
    RETURN();
1045 79aceca5 bellard
}
1046 79aceca5 bellard
1047 79aceca5 bellard
/* compare logical */
1048 79aceca5 bellard
PPC_OP(cmpl)
1049 79aceca5 bellard
{
1050 79aceca5 bellard
    if (T0 < T1) {
1051 79aceca5 bellard
        T0 = 0x08;
1052 79aceca5 bellard
    } else if (T0 > T1) {
1053 79aceca5 bellard
        T0 = 0x04;
1054 79aceca5 bellard
    } else {
1055 79aceca5 bellard
        T0 = 0x02;
1056 79aceca5 bellard
    }
1057 79aceca5 bellard
    RETURN();
1058 79aceca5 bellard
}
1059 79aceca5 bellard
1060 79aceca5 bellard
/* compare logical immediate */
1061 79aceca5 bellard
PPC_OP(cmpli)
1062 79aceca5 bellard
{
1063 79aceca5 bellard
    if (T0 < PARAM(1)) {
1064 79aceca5 bellard
        T0 = 0x08;
1065 79aceca5 bellard
    } else if (T0 > PARAM(1)) {
1066 79aceca5 bellard
        T0 = 0x04;
1067 79aceca5 bellard
    } else {
1068 79aceca5 bellard
        T0 = 0x02;
1069 79aceca5 bellard
    }
1070 79aceca5 bellard
    RETURN();
1071 79aceca5 bellard
}
1072 79aceca5 bellard
1073 79aceca5 bellard
/***                            Integer logical                            ***/
1074 79aceca5 bellard
/* and */
1075 79aceca5 bellard
PPC_OP(and)
1076 79aceca5 bellard
{
1077 79aceca5 bellard
    T0 &= T1;
1078 79aceca5 bellard
    RETURN();
1079 79aceca5 bellard
}
1080 79aceca5 bellard
1081 79aceca5 bellard
/* andc */
1082 79aceca5 bellard
PPC_OP(andc)
1083 79aceca5 bellard
{
1084 79aceca5 bellard
    T0 &= ~T1;
1085 79aceca5 bellard
    RETURN();
1086 79aceca5 bellard
}
1087 79aceca5 bellard
1088 79aceca5 bellard
/* andi. */
1089 79aceca5 bellard
PPC_OP(andi_)
1090 79aceca5 bellard
{
1091 79aceca5 bellard
    T0 &= PARAM(1);
1092 79aceca5 bellard
    RETURN();
1093 79aceca5 bellard
}
1094 79aceca5 bellard
1095 79aceca5 bellard
/* count leading zero */
1096 79aceca5 bellard
PPC_OP(cntlzw)
1097 79aceca5 bellard
{
1098 79aceca5 bellard
    T1 = T0;
1099 79aceca5 bellard
    for (T0 = 32; T1 > 0; T0--)
1100 79aceca5 bellard
        T1 = T1 >> 1;
1101 79aceca5 bellard
    RETURN();
1102 79aceca5 bellard
}
1103 79aceca5 bellard
1104 79aceca5 bellard
/* eqv */
1105 79aceca5 bellard
PPC_OP(eqv)
1106 79aceca5 bellard
{
1107 79aceca5 bellard
    T0 = ~(T0 ^ T1);
1108 79aceca5 bellard
    RETURN();
1109 79aceca5 bellard
}
1110 79aceca5 bellard
1111 79aceca5 bellard
/* extend sign byte */
1112 79aceca5 bellard
PPC_OP(extsb)
1113 79aceca5 bellard
{
1114 79aceca5 bellard
    Ts0 = s_ext8(Ts0);
1115 79aceca5 bellard
    RETURN();
1116 79aceca5 bellard
}
1117 79aceca5 bellard
1118 79aceca5 bellard
/* extend sign half word */
1119 79aceca5 bellard
PPC_OP(extsh)
1120 79aceca5 bellard
{
1121 79aceca5 bellard
    Ts0 = s_ext16(Ts0);
1122 79aceca5 bellard
    RETURN();
1123 79aceca5 bellard
}
1124 79aceca5 bellard
1125 79aceca5 bellard
/* nand */
1126 79aceca5 bellard
PPC_OP(nand)
1127 79aceca5 bellard
{
1128 79aceca5 bellard
    T0 = ~(T0 & T1);
1129 79aceca5 bellard
    RETURN();
1130 79aceca5 bellard
}
1131 79aceca5 bellard
1132 79aceca5 bellard
/* nor */
1133 79aceca5 bellard
PPC_OP(nor)
1134 79aceca5 bellard
{
1135 79aceca5 bellard
    T0 = ~(T0 | T1);
1136 79aceca5 bellard
    RETURN();
1137 79aceca5 bellard
}
1138 79aceca5 bellard
1139 79aceca5 bellard
/* or */
1140 79aceca5 bellard
PPC_OP(or)
1141 79aceca5 bellard
{
1142 79aceca5 bellard
    T0 |= T1;
1143 79aceca5 bellard
    RETURN();
1144 79aceca5 bellard
}
1145 79aceca5 bellard
1146 79aceca5 bellard
/* orc */
1147 79aceca5 bellard
PPC_OP(orc)
1148 79aceca5 bellard
{
1149 79aceca5 bellard
    T0 |= ~T1;
1150 79aceca5 bellard
    RETURN();
1151 79aceca5 bellard
}
1152 79aceca5 bellard
1153 79aceca5 bellard
/* ori */
1154 79aceca5 bellard
PPC_OP(ori)
1155 79aceca5 bellard
{
1156 79aceca5 bellard
    T0 |= PARAM(1);
1157 79aceca5 bellard
    RETURN();
1158 79aceca5 bellard
}
1159 79aceca5 bellard
1160 79aceca5 bellard
/* xor */
1161 79aceca5 bellard
PPC_OP(xor)
1162 79aceca5 bellard
{
1163 79aceca5 bellard
    T0 ^= T1;
1164 79aceca5 bellard
    RETURN();
1165 79aceca5 bellard
}
1166 79aceca5 bellard
1167 79aceca5 bellard
/* xori */
1168 79aceca5 bellard
PPC_OP(xori)
1169 79aceca5 bellard
{
1170 79aceca5 bellard
    T0 ^= PARAM(1);
1171 79aceca5 bellard
    RETURN();
1172 79aceca5 bellard
}
1173 79aceca5 bellard
1174 79aceca5 bellard
/***                             Integer rotate                            ***/
1175 79aceca5 bellard
/* rotate left word immediate then mask insert */
1176 79aceca5 bellard
PPC_OP(rlwimi)
1177 79aceca5 bellard
{
1178 fb0eaffc bellard
    T0 = (rotl(T0, PARAM(1)) & PARAM(2)) | (T1 & PARAM(3));
1179 79aceca5 bellard
    RETURN();
1180 79aceca5 bellard
}
1181 79aceca5 bellard
1182 79aceca5 bellard
/* rotate left immediate then and with mask insert */
1183 79aceca5 bellard
PPC_OP(rotlwi)
1184 79aceca5 bellard
{
1185 79aceca5 bellard
    T0 = rotl(T0, PARAM(1));
1186 79aceca5 bellard
    RETURN();
1187 79aceca5 bellard
}
1188 79aceca5 bellard
1189 79aceca5 bellard
PPC_OP(slwi)
1190 79aceca5 bellard
{
1191 79aceca5 bellard
    T0 = T0 << PARAM(1);
1192 79aceca5 bellard
    RETURN();
1193 79aceca5 bellard
}
1194 79aceca5 bellard
1195 79aceca5 bellard
PPC_OP(srwi)
1196 79aceca5 bellard
{
1197 79aceca5 bellard
    T0 = T0 >> PARAM(1);
1198 79aceca5 bellard
    RETURN();
1199 79aceca5 bellard
}
1200 79aceca5 bellard
1201 79aceca5 bellard
/* rotate left word then and with mask insert */
1202 79aceca5 bellard
PPC_OP(rlwinm)
1203 79aceca5 bellard
{
1204 79aceca5 bellard
    T0 = rotl(T0, PARAM(1)) & PARAM(2);
1205 79aceca5 bellard
    RETURN();
1206 79aceca5 bellard
}
1207 79aceca5 bellard
1208 79aceca5 bellard
PPC_OP(rotl)
1209 79aceca5 bellard
{
1210 79aceca5 bellard
    T0 = rotl(T0, T1);
1211 79aceca5 bellard
    RETURN();
1212 79aceca5 bellard
}
1213 79aceca5 bellard
1214 79aceca5 bellard
PPC_OP(rlwnm)
1215 79aceca5 bellard
{
1216 79aceca5 bellard
    T0 = rotl(T0, T1) & PARAM(1);
1217 79aceca5 bellard
    RETURN();
1218 79aceca5 bellard
}
1219 79aceca5 bellard
1220 79aceca5 bellard
/***                             Integer shift                             ***/
1221 79aceca5 bellard
/* shift left word */
1222 79aceca5 bellard
PPC_OP(slw)
1223 79aceca5 bellard
{
1224 79aceca5 bellard
    if (T1 & 0x20) {
1225 79aceca5 bellard
        T0 = 0;
1226 79aceca5 bellard
    } else {
1227 79aceca5 bellard
        T0 = T0 << T1;
1228 79aceca5 bellard
    }
1229 79aceca5 bellard
    RETURN();
1230 79aceca5 bellard
}
1231 79aceca5 bellard
1232 79aceca5 bellard
/* shift right algebraic word */
1233 79aceca5 bellard
PPC_OP(sraw)
1234 79aceca5 bellard
{
1235 9a64fbe4 bellard
    do_sraw();
1236 79aceca5 bellard
    RETURN();
1237 79aceca5 bellard
}
1238 79aceca5 bellard
1239 79aceca5 bellard
/* shift right algebraic word immediate */
1240 79aceca5 bellard
PPC_OP(srawi)
1241 79aceca5 bellard
{
1242 79aceca5 bellard
    Ts1 = Ts0;
1243 79aceca5 bellard
    Ts0 = Ts0 >> PARAM(1);
1244 79aceca5 bellard
    if (Ts1 < 0 && (Ts1 & PARAM(2)) != 0) {
1245 79aceca5 bellard
        xer_ca = 1;
1246 79aceca5 bellard
    } else {
1247 79aceca5 bellard
        xer_ca = 0;
1248 79aceca5 bellard
    }
1249 79aceca5 bellard
    RETURN();
1250 79aceca5 bellard
}
1251 79aceca5 bellard
1252 79aceca5 bellard
/* shift right word */
1253 79aceca5 bellard
PPC_OP(srw)
1254 79aceca5 bellard
{
1255 79aceca5 bellard
    if (T1 & 0x20) {
1256 79aceca5 bellard
        T0 = 0;
1257 79aceca5 bellard
    } else {
1258 79aceca5 bellard
        T0 = T0 >> T1;
1259 79aceca5 bellard
    }
1260 79aceca5 bellard
    RETURN();
1261 79aceca5 bellard
}
1262 79aceca5 bellard
1263 79aceca5 bellard
/***                       Floating-Point arithmetic                       ***/
1264 9a64fbe4 bellard
/* fadd - fadd. */
1265 9a64fbe4 bellard
PPC_OP(fadd)
1266 79aceca5 bellard
{
1267 9a64fbe4 bellard
    FT0 += FT1;
1268 79aceca5 bellard
    RETURN();
1269 79aceca5 bellard
}
1270 79aceca5 bellard
1271 9a64fbe4 bellard
/* fadds - fadds. */
1272 9a64fbe4 bellard
PPC_OP(fadds)
1273 79aceca5 bellard
{
1274 9a64fbe4 bellard
    FTS0 += FTS1;
1275 79aceca5 bellard
    RETURN();
1276 79aceca5 bellard
}
1277 79aceca5 bellard
1278 9a64fbe4 bellard
/* fsub - fsub. */
1279 9a64fbe4 bellard
PPC_OP(fsub)
1280 79aceca5 bellard
{
1281 9a64fbe4 bellard
    FT0 -= FT1;
1282 79aceca5 bellard
    RETURN();
1283 79aceca5 bellard
}
1284 79aceca5 bellard
1285 9a64fbe4 bellard
/* fsubs - fsubs. */
1286 9a64fbe4 bellard
PPC_OP(fsubs)
1287 79aceca5 bellard
{
1288 9a64fbe4 bellard
    FTS0 -= FTS1;
1289 79aceca5 bellard
    RETURN();
1290 79aceca5 bellard
}
1291 79aceca5 bellard
1292 9a64fbe4 bellard
/* fmul - fmul. */
1293 9a64fbe4 bellard
PPC_OP(fmul)
1294 79aceca5 bellard
{
1295 9a64fbe4 bellard
    FT0 *= FT1;
1296 79aceca5 bellard
    RETURN();
1297 79aceca5 bellard
}
1298 79aceca5 bellard
1299 9a64fbe4 bellard
/* fmuls - fmuls. */
1300 9a64fbe4 bellard
PPC_OP(fmuls)
1301 79aceca5 bellard
{
1302 9a64fbe4 bellard
    FTS0 *= FTS1;
1303 79aceca5 bellard
    RETURN();
1304 79aceca5 bellard
}
1305 79aceca5 bellard
1306 9a64fbe4 bellard
/* fdiv - fdiv. */
1307 9a64fbe4 bellard
PPC_OP(fdiv)
1308 79aceca5 bellard
{
1309 9a64fbe4 bellard
    FT0 /= FT1;
1310 79aceca5 bellard
    RETURN();
1311 79aceca5 bellard
}
1312 79aceca5 bellard
1313 9a64fbe4 bellard
/* fdivs - fdivs. */
1314 9a64fbe4 bellard
PPC_OP(fdivs)
1315 79aceca5 bellard
{
1316 9a64fbe4 bellard
    FTS0 /= FTS1;
1317 79aceca5 bellard
    RETURN();
1318 79aceca5 bellard
}
1319 28b6751f bellard
1320 9a64fbe4 bellard
/* fsqrt - fsqrt. */
1321 9a64fbe4 bellard
PPC_OP(fsqrt)
1322 28b6751f bellard
{
1323 9a64fbe4 bellard
    do_fsqrt();
1324 9a64fbe4 bellard
    RETURN();
1325 28b6751f bellard
}
1326 28b6751f bellard
1327 9a64fbe4 bellard
/* fsqrts - fsqrts. */
1328 9a64fbe4 bellard
PPC_OP(fsqrts)
1329 28b6751f bellard
{
1330 9a64fbe4 bellard
    do_fsqrts();
1331 9a64fbe4 bellard
    RETURN();
1332 28b6751f bellard
}
1333 28b6751f bellard
1334 9a64fbe4 bellard
/* fres - fres. */
1335 9a64fbe4 bellard
PPC_OP(fres)
1336 28b6751f bellard
{
1337 9a64fbe4 bellard
    do_fres();
1338 9a64fbe4 bellard
    RETURN();
1339 28b6751f bellard
}
1340 28b6751f bellard
1341 9a64fbe4 bellard
/* frsqrte  - frsqrte. */
1342 9a64fbe4 bellard
PPC_OP(frsqrte)
1343 28b6751f bellard
{
1344 9a64fbe4 bellard
    do_fsqrte();
1345 9a64fbe4 bellard
    RETURN();
1346 28b6751f bellard
}
1347 28b6751f bellard
1348 9a64fbe4 bellard
/* fsel - fsel. */
1349 9a64fbe4 bellard
PPC_OP(fsel)
1350 28b6751f bellard
{
1351 9a64fbe4 bellard
    do_fsel();
1352 9a64fbe4 bellard
    RETURN();
1353 28b6751f bellard
}
1354 28b6751f bellard
1355 9a64fbe4 bellard
/***                     Floating-Point multiply-and-add                   ***/
1356 9a64fbe4 bellard
/* fmadd - fmadd. */
1357 9a64fbe4 bellard
PPC_OP(fmadd)
1358 28b6751f bellard
{
1359 9a64fbe4 bellard
    FT0 = (FT0 * FT1) + FT2;
1360 9a64fbe4 bellard
    RETURN();
1361 28b6751f bellard
}
1362 28b6751f bellard
1363 9a64fbe4 bellard
/* fmadds - fmadds. */
1364 9a64fbe4 bellard
PPC_OP(fmadds)
1365 28b6751f bellard
{
1366 9a64fbe4 bellard
    FTS0 = (FTS0 * FTS1) + FTS2;
1367 9a64fbe4 bellard
    RETURN();
1368 28b6751f bellard
}
1369 28b6751f bellard
1370 9a64fbe4 bellard
/* fmsub - fmsub. */
1371 9a64fbe4 bellard
PPC_OP(fmsub)
1372 28b6751f bellard
{
1373 9a64fbe4 bellard
    FT0 = (FT0 * FT1) - FT2;
1374 9a64fbe4 bellard
    RETURN();
1375 28b6751f bellard
}
1376 28b6751f bellard
1377 9a64fbe4 bellard
/* fmsubs - fmsubs. */
1378 9a64fbe4 bellard
PPC_OP(fmsubs)
1379 28b6751f bellard
{
1380 9a64fbe4 bellard
    FTS0 = (FTS0 * FTS1) - FTS2;
1381 9a64fbe4 bellard
    RETURN();
1382 28b6751f bellard
}
1383 28b6751f bellard
1384 9a64fbe4 bellard
/* fnmadd - fnmadd. - fnmadds - fnmadds. */
1385 9a64fbe4 bellard
PPC_OP(fnmadd)
1386 28b6751f bellard
{
1387 9a64fbe4 bellard
    FT0 = -((FT0 * FT1) + FT2);
1388 9a64fbe4 bellard
    RETURN();
1389 28b6751f bellard
}
1390 28b6751f bellard
1391 9a64fbe4 bellard
/* fnmadds - fnmadds. */
1392 9a64fbe4 bellard
PPC_OP(fnmadds)
1393 28b6751f bellard
{
1394 9a64fbe4 bellard
    FTS0 = -((FTS0 * FTS1) + FTS2);
1395 9a64fbe4 bellard
    RETURN();
1396 28b6751f bellard
}
1397 28b6751f bellard
1398 9a64fbe4 bellard
/* fnmsub - fnmsub. */
1399 9a64fbe4 bellard
PPC_OP(fnmsub)
1400 28b6751f bellard
{
1401 9a64fbe4 bellard
    FT0 = -((FT0 * FT1) - FT2);
1402 9a64fbe4 bellard
    RETURN();
1403 28b6751f bellard
}
1404 28b6751f bellard
1405 9a64fbe4 bellard
/* fnmsubs - fnmsubs. */
1406 9a64fbe4 bellard
PPC_OP(fnmsubs)
1407 28b6751f bellard
{
1408 9a64fbe4 bellard
    FTS0 = -((FTS0 * FTS1) - FTS2);
1409 9a64fbe4 bellard
    RETURN();
1410 28b6751f bellard
}
1411 28b6751f bellard
1412 9a64fbe4 bellard
/***                     Floating-Point round & convert                    ***/
1413 9a64fbe4 bellard
/* frsp - frsp. */
1414 9a64fbe4 bellard
PPC_OP(frsp)
1415 28b6751f bellard
{
1416 9a64fbe4 bellard
    FT0 = FTS0;
1417 9a64fbe4 bellard
    RETURN();
1418 28b6751f bellard
}
1419 28b6751f bellard
1420 9a64fbe4 bellard
/* fctiw - fctiw. */
1421 9a64fbe4 bellard
PPC_OP(fctiw)
1422 28b6751f bellard
{
1423 9a64fbe4 bellard
    do_fctiw();
1424 9a64fbe4 bellard
    RETURN();
1425 28b6751f bellard
}
1426 28b6751f bellard
1427 9a64fbe4 bellard
/* fctiwz - fctiwz. */
1428 9a64fbe4 bellard
PPC_OP(fctiwz)
1429 28b6751f bellard
{
1430 9a64fbe4 bellard
    do_fctiwz();
1431 9a64fbe4 bellard
    RETURN();
1432 28b6751f bellard
}
1433 28b6751f bellard
1434 9a64fbe4 bellard
1435 9a64fbe4 bellard
/***                         Floating-Point compare                        ***/
1436 9a64fbe4 bellard
/* fcmpu */
1437 9a64fbe4 bellard
PPC_OP(fcmpu)
1438 28b6751f bellard
{
1439 9a64fbe4 bellard
    do_fcmpu();
1440 9a64fbe4 bellard
    RETURN();
1441 28b6751f bellard
}
1442 28b6751f bellard
1443 9a64fbe4 bellard
/* fcmpo */
1444 9a64fbe4 bellard
PPC_OP(fcmpo)
1445 28b6751f bellard
{
1446 9a64fbe4 bellard
    do_fcmpo();
1447 9a64fbe4 bellard
    RETURN();
1448 fb0eaffc bellard
}
1449 fb0eaffc bellard
1450 9a64fbe4 bellard
/***                         Floating-point move                           ***/
1451 9a64fbe4 bellard
/* fabs */
1452 9a64fbe4 bellard
PPC_OP(fabs)
1453 fb0eaffc bellard
{
1454 9a64fbe4 bellard
    do_fabs();
1455 fb0eaffc bellard
    RETURN();
1456 fb0eaffc bellard
}
1457 fb0eaffc bellard
1458 9a64fbe4 bellard
/* fnabs */
1459 9a64fbe4 bellard
PPC_OP(fnabs)
1460 fb0eaffc bellard
{
1461 9a64fbe4 bellard
    do_fnabs();
1462 fb0eaffc bellard
    RETURN();
1463 fb0eaffc bellard
}
1464 fb0eaffc bellard
1465 9a64fbe4 bellard
/* fneg */
1466 9a64fbe4 bellard
PPC_OP(fneg)
1467 fb0eaffc bellard
{
1468 9a64fbe4 bellard
    FT0 = -FT0;
1469 fb0eaffc bellard
    RETURN();
1470 fb0eaffc bellard
}
1471 fb0eaffc bellard
1472 9a64fbe4 bellard
/* Load and store */
1473 9a64fbe4 bellard
#if defined(CONFIG_USER_ONLY)
1474 9a64fbe4 bellard
#define MEMSUFFIX _raw
1475 9a64fbe4 bellard
#include "op_mem.h"
1476 9a64fbe4 bellard
#else
1477 9a64fbe4 bellard
#define MEMSUFFIX _user
1478 9a64fbe4 bellard
#include "op_mem.h"
1479 9a64fbe4 bellard
1480 9a64fbe4 bellard
#define MEMSUFFIX _kernel
1481 9a64fbe4 bellard
#include "op_mem.h"
1482 9a64fbe4 bellard
#endif
1483 9a64fbe4 bellard
1484 9a64fbe4 bellard
/* Return from interrupt */
1485 9a64fbe4 bellard
PPC_OP(rfi)
1486 fb0eaffc bellard
{
1487 9a64fbe4 bellard
    T0 = regs->spr[SRR1] & ~0xFFFF0000;
1488 9a64fbe4 bellard
    do_store_msr();
1489 9a64fbe4 bellard
    do_tlbia();
1490 9a64fbe4 bellard
    dump_rfi();
1491 9a64fbe4 bellard
    regs->nip = regs->spr[SRR0] & ~0x00000003;
1492 9a64fbe4 bellard
    if (env->exceptions != 0) {
1493 9a64fbe4 bellard
        do_check_exception_state();
1494 fb0eaffc bellard
    }
1495 fb0eaffc bellard
    RETURN();
1496 fb0eaffc bellard
}
1497 fb0eaffc bellard
1498 9a64fbe4 bellard
/* Trap word */
1499 9a64fbe4 bellard
PPC_OP(tw)
1500 fb0eaffc bellard
{
1501 9a64fbe4 bellard
    if ((Ts0 < Ts1 && (PARAM(1) & 0x10)) ||
1502 9a64fbe4 bellard
        (Ts0 > Ts1 && (PARAM(1) & 0x08)) ||
1503 9a64fbe4 bellard
        (Ts0 == Ts1 && (PARAM(1) & 0x04)) ||
1504 9a64fbe4 bellard
        (T0 < T1 && (PARAM(1) & 0x02)) ||
1505 9a64fbe4 bellard
        (T0 > T1 && (PARAM(1) & 0x01)))
1506 9a64fbe4 bellard
        do_queue_exception_err(EXCP_PROGRAM, EXCP_TRAP);
1507 fb0eaffc bellard
    RETURN();
1508 fb0eaffc bellard
}
1509 fb0eaffc bellard
1510 9a64fbe4 bellard
PPC_OP(twi)
1511 fb0eaffc bellard
{
1512 9a64fbe4 bellard
    if ((Ts0 < SPARAM(1) && (PARAM(2) & 0x10)) ||
1513 9a64fbe4 bellard
        (Ts0 > SPARAM(1) && (PARAM(2) & 0x08)) ||
1514 9a64fbe4 bellard
        (Ts0 == SPARAM(1) && (PARAM(2) & 0x04)) ||
1515 9a64fbe4 bellard
        (T0 < (uint32_t)SPARAM(1) && (PARAM(2) & 0x02)) ||
1516 9a64fbe4 bellard
        (T0 > (uint32_t)SPARAM(1) && (PARAM(2) & 0x01)))
1517 9a64fbe4 bellard
        do_queue_exception_err(EXCP_PROGRAM, EXCP_TRAP);
1518 fb0eaffc bellard
    RETURN();
1519 fb0eaffc bellard
}
1520 fb0eaffc bellard
1521 fb0eaffc bellard
/* Instruction cache block invalidate */
1522 9a64fbe4 bellard
PPC_OP(icbi)
1523 fb0eaffc bellard
{
1524 fb0eaffc bellard
    do_icbi();
1525 fb0eaffc bellard
    RETURN();
1526 fb0eaffc bellard
}
1527 fb0eaffc bellard
1528 9a64fbe4 bellard
/* tlbia */
1529 9a64fbe4 bellard
PPC_OP(tlbia)
1530 fb0eaffc bellard
{
1531 9a64fbe4 bellard
    do_tlbia();
1532 9a64fbe4 bellard
    RETURN();
1533 9a64fbe4 bellard
}
1534 9a64fbe4 bellard
1535 9a64fbe4 bellard
/* tlbie */
1536 9a64fbe4 bellard
PPC_OP(tlbie)
1537 9a64fbe4 bellard
{
1538 9a64fbe4 bellard
    do_tlbie();
1539 fb0eaffc bellard
    RETURN();
1540 28b6751f bellard
}