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tcg-target.c 51.9 kB
tcg-target.h 3.2 kB

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# Date Author Comment
0085bd51 04/26/2010 09:06 pm Richard Henderson

tcg-hppa: Constrain immediate inputs to and_i32, or_i32, andc_i32.

Define "M" constraint for and_mask_p and "O" constraint for or_mask_p.
Assume that inputs are correct in tcg_out_ori and tcg_out_andi.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
3e1f46ea 04/08/2010 12:57 pm Richard Henderson

tcg-hppa: Don't try to calls to non-constant addresses.

PA-RISC uses procedure descriptors. We'd need to emit a call to
the millicode routine $$dyncall. However, this situation doesn't
actually arise, since we always have the descriptor available at
TCG code generation time....
91493631 04/08/2010 12:57 pm Richard Henderson

tcg-hppa: Fix in/out register overlap in add2/sub2.

Handle the output log part overlapping the input high parts.
Also, improve sub2 to handle some constants the second input low part.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
fd76e73a 04/08/2010 12:11 pm Richard Henderson

tcg-hppa: Finish the port.

Delete inline functions from tcg-target.h that don't need to be there,
move the others to tcg-target.c. Add 'Z', 'I', 'J' constraints for
0, signed 11-bit, and signed 5-bit respectively. Add GUEST_BASE support
similar to ppc64, with the value stored in a register. Add missing...
86feb1c8 03/27/2010 12:01 am Richard Henderson

tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.

Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands
sign-extended in 64-bit registers (regardless of the "real" sign
of the operand). For that, we need to be able to distinguish
between a 32-bit load with a 32-bit result and a 32-bit load with...
a9751609 03/26/2010 10:28 pm Richard Henderson

tcg: Name the opcode enumeration.

Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
a63b5829 03/26/2010 09:48 pm Paolo Bonzini

remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Aurelien Jarno <>
31d66551 03/14/2010 11:04 pm Aurelien Jarno

tcg: add div/rem 32-bit helpers

Some targets like ARM would benefit to use 32-bit helpers for
div/rem/divu/remu.

Create a #define for div2 so that targets can select between
div, div2 and helper implementation. Use the helper version if none
of the #define are present....
30c0c76c 02/22/2010 06:38 pm Jay Foad

tcg: fix build on 32-bit hppa, ppc and sparc hosts

The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.

Signed-off-by: Jay Foad <>
Signed-off-by: malc <>
d89c682f 09/25/2009 05:31 pm Stefan Weil

Suppress some variants of English in comments

Replace surpress, supress by suppress.

Signed-off-by: Stefan Weil <>
Signed-off-by: Aurelien Jarno <>

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