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1 | 8ecc7913 | j_mayer | /*
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2 | 8ecc7913 | j_mayer | * QEMU PowerPC 405 embedded processors emulation
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3 | 5fafdf24 | ths | *
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4 | 8ecc7913 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | 8ecc7913 | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 8ecc7913 | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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8 | 8ecc7913 | j_mayer | * in the Software without restriction, including without limitation the rights
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9 | 8ecc7913 | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 8ecc7913 | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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11 | 8ecc7913 | j_mayer | * furnished to do so, subject to the following conditions:
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12 | 8ecc7913 | j_mayer | *
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13 | 8ecc7913 | j_mayer | * The above copyright notice and this permission notice shall be included in
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14 | 8ecc7913 | j_mayer | * all copies or substantial portions of the Software.
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15 | 8ecc7913 | j_mayer | *
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16 | 8ecc7913 | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 8ecc7913 | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 8ecc7913 | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 8ecc7913 | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 8ecc7913 | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 8ecc7913 | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 8ecc7913 | j_mayer | * THE SOFTWARE.
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23 | 8ecc7913 | j_mayer | */
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24 | 8ecc7913 | j_mayer | #include "vl.h" |
25 | 04f20795 | j_mayer | #include "ppc405.h" |
26 | 8ecc7913 | j_mayer | |
27 | 8ecc7913 | j_mayer | extern int loglevel; |
28 | 8ecc7913 | j_mayer | extern FILE *logfile;
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29 | 8ecc7913 | j_mayer | |
30 | 8ecc7913 | j_mayer | #define DEBUG_OPBA
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31 | 8ecc7913 | j_mayer | #define DEBUG_SDRAM
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32 | 8ecc7913 | j_mayer | #define DEBUG_GPIO
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33 | 8ecc7913 | j_mayer | #define DEBUG_SERIAL
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34 | 8ecc7913 | j_mayer | #define DEBUG_OCM
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35 | 9c02f1a2 | j_mayer | //#define DEBUG_I2C
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36 | 9c02f1a2 | j_mayer | #define DEBUG_GPT
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37 | 9c02f1a2 | j_mayer | #define DEBUG_MAL
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38 | 8ecc7913 | j_mayer | #define DEBUG_CLOCKS
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39 | 9c02f1a2 | j_mayer | //#define DEBUG_UNASSIGNED
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40 | 8ecc7913 | j_mayer | |
41 | b8d3f5d1 | j_mayer | ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
42 | b8d3f5d1 | j_mayer | uint32_t flags) |
43 | 04f20795 | j_mayer | { |
44 | 04f20795 | j_mayer | ram_addr_t bdloc; |
45 | 04f20795 | j_mayer | int i, n;
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46 | 04f20795 | j_mayer | |
47 | 04f20795 | j_mayer | /* We put the bd structure at the top of memory */
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48 | be58fc7c | j_mayer | if (bd->bi_memsize >= 0x01000000UL) |
49 | be58fc7c | j_mayer | bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); |
50 | be58fc7c | j_mayer | else
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51 | be58fc7c | j_mayer | bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); |
52 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
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53 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
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54 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
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55 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
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56 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
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57 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
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58 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
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59 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
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60 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
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61 | 04f20795 | j_mayer | for (i = 0; i < 6; i++) |
62 | 04f20795 | j_mayer | stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
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63 | 04f20795 | j_mayer | stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
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64 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
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65 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
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66 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
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67 | 04f20795 | j_mayer | for (i = 0; i < 4; i++) |
68 | 04f20795 | j_mayer | stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
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69 | 04f20795 | j_mayer | for (i = 0; i < 32; i++) |
70 | 04f20795 | j_mayer | stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
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71 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
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72 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
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73 | 04f20795 | j_mayer | for (i = 0; i < 6; i++) |
74 | 04f20795 | j_mayer | stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
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75 | 04f20795 | j_mayer | n = 0x6A;
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76 | b8d3f5d1 | j_mayer | if (flags & 0x00000001) { |
77 | 04f20795 | j_mayer | for (i = 0; i < 6; i++) |
78 | 04f20795 | j_mayer | stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]); |
79 | 04f20795 | j_mayer | } |
80 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq); |
81 | 04f20795 | j_mayer | n += 4;
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82 | 04f20795 | j_mayer | for (i = 0; i < 2; i++) { |
83 | 04f20795 | j_mayer | stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]); |
84 | 04f20795 | j_mayer | n += 4;
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85 | 04f20795 | j_mayer | } |
86 | 04f20795 | j_mayer | |
87 | 04f20795 | j_mayer | return bdloc;
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88 | 04f20795 | j_mayer | } |
89 | 04f20795 | j_mayer | |
90 | 8ecc7913 | j_mayer | /*****************************************************************************/
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91 | 8ecc7913 | j_mayer | /* Shared peripherals */
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92 | 8ecc7913 | j_mayer | |
93 | 8ecc7913 | j_mayer | /*****************************************************************************/
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94 | 8ecc7913 | j_mayer | /* Peripheral local bus arbitrer */
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95 | 8ecc7913 | j_mayer | enum {
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96 | 8ecc7913 | j_mayer | PLB0_BESR = 0x084,
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97 | 8ecc7913 | j_mayer | PLB0_BEAR = 0x086,
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98 | 8ecc7913 | j_mayer | PLB0_ACR = 0x087,
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99 | 8ecc7913 | j_mayer | }; |
100 | 8ecc7913 | j_mayer | |
101 | 8ecc7913 | j_mayer | typedef struct ppc4xx_plb_t ppc4xx_plb_t; |
102 | 8ecc7913 | j_mayer | struct ppc4xx_plb_t {
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103 | 8ecc7913 | j_mayer | uint32_t acr; |
104 | 8ecc7913 | j_mayer | uint32_t bear; |
105 | 8ecc7913 | j_mayer | uint32_t besr; |
106 | 8ecc7913 | j_mayer | }; |
107 | 8ecc7913 | j_mayer | |
108 | 8ecc7913 | j_mayer | static target_ulong dcr_read_plb (void *opaque, int dcrn) |
109 | 8ecc7913 | j_mayer | { |
110 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
111 | 8ecc7913 | j_mayer | target_ulong ret; |
112 | 8ecc7913 | j_mayer | |
113 | 8ecc7913 | j_mayer | plb = opaque; |
114 | 8ecc7913 | j_mayer | switch (dcrn) {
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115 | 8ecc7913 | j_mayer | case PLB0_ACR:
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116 | 8ecc7913 | j_mayer | ret = plb->acr; |
117 | 8ecc7913 | j_mayer | break;
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118 | 8ecc7913 | j_mayer | case PLB0_BEAR:
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119 | 8ecc7913 | j_mayer | ret = plb->bear; |
120 | 8ecc7913 | j_mayer | break;
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121 | 8ecc7913 | j_mayer | case PLB0_BESR:
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122 | 8ecc7913 | j_mayer | ret = plb->besr; |
123 | 8ecc7913 | j_mayer | break;
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124 | 8ecc7913 | j_mayer | default:
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125 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
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126 | 8ecc7913 | j_mayer | ret = 0;
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127 | 8ecc7913 | j_mayer | break;
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128 | 8ecc7913 | j_mayer | } |
129 | 8ecc7913 | j_mayer | |
130 | 8ecc7913 | j_mayer | return ret;
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131 | 8ecc7913 | j_mayer | } |
132 | 8ecc7913 | j_mayer | |
133 | 8ecc7913 | j_mayer | static void dcr_write_plb (void *opaque, int dcrn, target_ulong val) |
134 | 8ecc7913 | j_mayer | { |
135 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
136 | 8ecc7913 | j_mayer | |
137 | 8ecc7913 | j_mayer | plb = opaque; |
138 | 8ecc7913 | j_mayer | switch (dcrn) {
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139 | 8ecc7913 | j_mayer | case PLB0_ACR:
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140 | 9c02f1a2 | j_mayer | /* We don't care about the actual parameters written as
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141 | 9c02f1a2 | j_mayer | * we don't manage any priorities on the bus
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142 | 9c02f1a2 | j_mayer | */
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143 | 9c02f1a2 | j_mayer | plb->acr = val & 0xF8000000;
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144 | 8ecc7913 | j_mayer | break;
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145 | 8ecc7913 | j_mayer | case PLB0_BEAR:
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146 | 8ecc7913 | j_mayer | /* Read only */
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147 | 8ecc7913 | j_mayer | break;
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148 | 8ecc7913 | j_mayer | case PLB0_BESR:
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149 | 8ecc7913 | j_mayer | /* Write-clear */
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150 | 8ecc7913 | j_mayer | plb->besr &= ~val; |
151 | 8ecc7913 | j_mayer | break;
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152 | 8ecc7913 | j_mayer | } |
153 | 8ecc7913 | j_mayer | } |
154 | 8ecc7913 | j_mayer | |
155 | 8ecc7913 | j_mayer | static void ppc4xx_plb_reset (void *opaque) |
156 | 8ecc7913 | j_mayer | { |
157 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
158 | 8ecc7913 | j_mayer | |
159 | 8ecc7913 | j_mayer | plb = opaque; |
160 | 8ecc7913 | j_mayer | plb->acr = 0x00000000;
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161 | 8ecc7913 | j_mayer | plb->bear = 0x00000000;
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162 | 8ecc7913 | j_mayer | plb->besr = 0x00000000;
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163 | 8ecc7913 | j_mayer | } |
164 | 8ecc7913 | j_mayer | |
165 | 8ecc7913 | j_mayer | void ppc4xx_plb_init (CPUState *env)
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166 | 8ecc7913 | j_mayer | { |
167 | 8ecc7913 | j_mayer | ppc4xx_plb_t *plb; |
168 | 8ecc7913 | j_mayer | |
169 | 8ecc7913 | j_mayer | plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
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170 | 8ecc7913 | j_mayer | if (plb != NULL) { |
171 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); |
172 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); |
173 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); |
174 | 8ecc7913 | j_mayer | ppc4xx_plb_reset(plb); |
175 | 8ecc7913 | j_mayer | qemu_register_reset(ppc4xx_plb_reset, plb); |
176 | 8ecc7913 | j_mayer | } |
177 | 8ecc7913 | j_mayer | } |
178 | 8ecc7913 | j_mayer | |
179 | 8ecc7913 | j_mayer | /*****************************************************************************/
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180 | 8ecc7913 | j_mayer | /* PLB to OPB bridge */
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181 | 8ecc7913 | j_mayer | enum {
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182 | 8ecc7913 | j_mayer | POB0_BESR0 = 0x0A0,
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183 | 8ecc7913 | j_mayer | POB0_BESR1 = 0x0A2,
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184 | 8ecc7913 | j_mayer | POB0_BEAR = 0x0A4,
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185 | 8ecc7913 | j_mayer | }; |
186 | 8ecc7913 | j_mayer | |
187 | 8ecc7913 | j_mayer | typedef struct ppc4xx_pob_t ppc4xx_pob_t; |
188 | 8ecc7913 | j_mayer | struct ppc4xx_pob_t {
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189 | 8ecc7913 | j_mayer | uint32_t bear; |
190 | 8ecc7913 | j_mayer | uint32_t besr[2];
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191 | 8ecc7913 | j_mayer | }; |
192 | 8ecc7913 | j_mayer | |
193 | 8ecc7913 | j_mayer | static target_ulong dcr_read_pob (void *opaque, int dcrn) |
194 | 8ecc7913 | j_mayer | { |
195 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
196 | 8ecc7913 | j_mayer | target_ulong ret; |
197 | 8ecc7913 | j_mayer | |
198 | 8ecc7913 | j_mayer | pob = opaque; |
199 | 8ecc7913 | j_mayer | switch (dcrn) {
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200 | 8ecc7913 | j_mayer | case POB0_BEAR:
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201 | 8ecc7913 | j_mayer | ret = pob->bear; |
202 | 8ecc7913 | j_mayer | break;
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203 | 8ecc7913 | j_mayer | case POB0_BESR0:
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204 | 8ecc7913 | j_mayer | case POB0_BESR1:
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205 | 8ecc7913 | j_mayer | ret = pob->besr[dcrn - POB0_BESR0]; |
206 | 8ecc7913 | j_mayer | break;
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207 | 8ecc7913 | j_mayer | default:
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208 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
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209 | 8ecc7913 | j_mayer | ret = 0;
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210 | 8ecc7913 | j_mayer | break;
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211 | 8ecc7913 | j_mayer | } |
212 | 8ecc7913 | j_mayer | |
213 | 8ecc7913 | j_mayer | return ret;
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214 | 8ecc7913 | j_mayer | } |
215 | 8ecc7913 | j_mayer | |
216 | 8ecc7913 | j_mayer | static void dcr_write_pob (void *opaque, int dcrn, target_ulong val) |
217 | 8ecc7913 | j_mayer | { |
218 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
219 | 8ecc7913 | j_mayer | |
220 | 8ecc7913 | j_mayer | pob = opaque; |
221 | 8ecc7913 | j_mayer | switch (dcrn) {
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222 | 8ecc7913 | j_mayer | case POB0_BEAR:
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223 | 8ecc7913 | j_mayer | /* Read only */
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224 | 8ecc7913 | j_mayer | break;
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225 | 8ecc7913 | j_mayer | case POB0_BESR0:
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226 | 8ecc7913 | j_mayer | case POB0_BESR1:
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227 | 8ecc7913 | j_mayer | /* Write-clear */
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228 | 8ecc7913 | j_mayer | pob->besr[dcrn - POB0_BESR0] &= ~val; |
229 | 8ecc7913 | j_mayer | break;
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230 | 8ecc7913 | j_mayer | } |
231 | 8ecc7913 | j_mayer | } |
232 | 8ecc7913 | j_mayer | |
233 | 8ecc7913 | j_mayer | static void ppc4xx_pob_reset (void *opaque) |
234 | 8ecc7913 | j_mayer | { |
235 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
236 | 8ecc7913 | j_mayer | |
237 | 8ecc7913 | j_mayer | pob = opaque; |
238 | 8ecc7913 | j_mayer | /* No error */
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239 | 8ecc7913 | j_mayer | pob->bear = 0x00000000;
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240 | 8ecc7913 | j_mayer | pob->besr[0] = 0x0000000; |
241 | 8ecc7913 | j_mayer | pob->besr[1] = 0x0000000; |
242 | 8ecc7913 | j_mayer | } |
243 | 8ecc7913 | j_mayer | |
244 | 8ecc7913 | j_mayer | void ppc4xx_pob_init (CPUState *env)
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245 | 8ecc7913 | j_mayer | { |
246 | 8ecc7913 | j_mayer | ppc4xx_pob_t *pob; |
247 | 8ecc7913 | j_mayer | |
248 | 8ecc7913 | j_mayer | pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
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249 | 8ecc7913 | j_mayer | if (pob != NULL) { |
250 | 8ecc7913 | j_mayer | ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); |
251 | 8ecc7913 | j_mayer | ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); |
252 | 8ecc7913 | j_mayer | ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); |
253 | 8ecc7913 | j_mayer | qemu_register_reset(ppc4xx_pob_reset, pob); |
254 | 8ecc7913 | j_mayer | ppc4xx_pob_reset(env); |
255 | 8ecc7913 | j_mayer | } |
256 | 8ecc7913 | j_mayer | } |
257 | 8ecc7913 | j_mayer | |
258 | 8ecc7913 | j_mayer | /*****************************************************************************/
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259 | 8ecc7913 | j_mayer | /* OPB arbitrer */
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260 | 8ecc7913 | j_mayer | typedef struct ppc4xx_opba_t ppc4xx_opba_t; |
261 | 8ecc7913 | j_mayer | struct ppc4xx_opba_t {
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262 | 9c02f1a2 | j_mayer | target_phys_addr_t base; |
263 | 8ecc7913 | j_mayer | uint8_t cr; |
264 | 8ecc7913 | j_mayer | uint8_t pr; |
265 | 8ecc7913 | j_mayer | }; |
266 | 8ecc7913 | j_mayer | |
267 | 8ecc7913 | j_mayer | static uint32_t opba_readb (void *opaque, target_phys_addr_t addr) |
268 | 8ecc7913 | j_mayer | { |
269 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
270 | 8ecc7913 | j_mayer | uint32_t ret; |
271 | 8ecc7913 | j_mayer | |
272 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
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273 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
274 | 8ecc7913 | j_mayer | #endif
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275 | 8ecc7913 | j_mayer | opba = opaque; |
276 | 8ecc7913 | j_mayer | switch (addr - opba->base) {
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277 | 8ecc7913 | j_mayer | case 0x00: |
278 | 8ecc7913 | j_mayer | ret = opba->cr; |
279 | 8ecc7913 | j_mayer | break;
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280 | 8ecc7913 | j_mayer | case 0x01: |
281 | 8ecc7913 | j_mayer | ret = opba->pr; |
282 | 8ecc7913 | j_mayer | break;
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283 | 8ecc7913 | j_mayer | default:
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284 | 8ecc7913 | j_mayer | ret = 0x00;
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285 | 8ecc7913 | j_mayer | break;
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286 | 8ecc7913 | j_mayer | } |
287 | 8ecc7913 | j_mayer | |
288 | 8ecc7913 | j_mayer | return ret;
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289 | 8ecc7913 | j_mayer | } |
290 | 8ecc7913 | j_mayer | |
291 | 8ecc7913 | j_mayer | static void opba_writeb (void *opaque, |
292 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
293 | 8ecc7913 | j_mayer | { |
294 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
295 | 8ecc7913 | j_mayer | |
296 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
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297 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
298 | 8ecc7913 | j_mayer | #endif
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299 | 8ecc7913 | j_mayer | opba = opaque; |
300 | 8ecc7913 | j_mayer | switch (addr - opba->base) {
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301 | 8ecc7913 | j_mayer | case 0x00: |
302 | 8ecc7913 | j_mayer | opba->cr = value & 0xF8;
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303 | 8ecc7913 | j_mayer | break;
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304 | 8ecc7913 | j_mayer | case 0x01: |
305 | 8ecc7913 | j_mayer | opba->pr = value & 0xFF;
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306 | 8ecc7913 | j_mayer | break;
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307 | 8ecc7913 | j_mayer | default:
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308 | 8ecc7913 | j_mayer | break;
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309 | 8ecc7913 | j_mayer | } |
310 | 8ecc7913 | j_mayer | } |
311 | 8ecc7913 | j_mayer | |
312 | 8ecc7913 | j_mayer | static uint32_t opba_readw (void *opaque, target_phys_addr_t addr) |
313 | 8ecc7913 | j_mayer | { |
314 | 8ecc7913 | j_mayer | uint32_t ret; |
315 | 8ecc7913 | j_mayer | |
316 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
317 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
318 | 8ecc7913 | j_mayer | #endif
|
319 | 8ecc7913 | j_mayer | ret = opba_readb(opaque, addr) << 8;
|
320 | 8ecc7913 | j_mayer | ret |= opba_readb(opaque, addr + 1);
|
321 | 8ecc7913 | j_mayer | |
322 | 8ecc7913 | j_mayer | return ret;
|
323 | 8ecc7913 | j_mayer | } |
324 | 8ecc7913 | j_mayer | |
325 | 8ecc7913 | j_mayer | static void opba_writew (void *opaque, |
326 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
327 | 8ecc7913 | j_mayer | { |
328 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
329 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
330 | 8ecc7913 | j_mayer | #endif
|
331 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr, value >> 8);
|
332 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr + 1, value);
|
333 | 8ecc7913 | j_mayer | } |
334 | 8ecc7913 | j_mayer | |
335 | 8ecc7913 | j_mayer | static uint32_t opba_readl (void *opaque, target_phys_addr_t addr) |
336 | 8ecc7913 | j_mayer | { |
337 | 8ecc7913 | j_mayer | uint32_t ret; |
338 | 8ecc7913 | j_mayer | |
339 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
340 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
341 | 8ecc7913 | j_mayer | #endif
|
342 | 8ecc7913 | j_mayer | ret = opba_readb(opaque, addr) << 24;
|
343 | 8ecc7913 | j_mayer | ret |= opba_readb(opaque, addr + 1) << 16; |
344 | 8ecc7913 | j_mayer | |
345 | 8ecc7913 | j_mayer | return ret;
|
346 | 8ecc7913 | j_mayer | } |
347 | 8ecc7913 | j_mayer | |
348 | 8ecc7913 | j_mayer | static void opba_writel (void *opaque, |
349 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
350 | 8ecc7913 | j_mayer | { |
351 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
352 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
353 | 8ecc7913 | j_mayer | #endif
|
354 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr, value >> 24);
|
355 | 8ecc7913 | j_mayer | opba_writeb(opaque, addr + 1, value >> 16); |
356 | 8ecc7913 | j_mayer | } |
357 | 8ecc7913 | j_mayer | |
358 | 8ecc7913 | j_mayer | static CPUReadMemoryFunc *opba_read[] = {
|
359 | 8ecc7913 | j_mayer | &opba_readb, |
360 | 8ecc7913 | j_mayer | &opba_readw, |
361 | 8ecc7913 | j_mayer | &opba_readl, |
362 | 8ecc7913 | j_mayer | }; |
363 | 8ecc7913 | j_mayer | |
364 | 8ecc7913 | j_mayer | static CPUWriteMemoryFunc *opba_write[] = {
|
365 | 8ecc7913 | j_mayer | &opba_writeb, |
366 | 8ecc7913 | j_mayer | &opba_writew, |
367 | 8ecc7913 | j_mayer | &opba_writel, |
368 | 8ecc7913 | j_mayer | }; |
369 | 8ecc7913 | j_mayer | |
370 | 8ecc7913 | j_mayer | static void ppc4xx_opba_reset (void *opaque) |
371 | 8ecc7913 | j_mayer | { |
372 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
373 | 8ecc7913 | j_mayer | |
374 | 8ecc7913 | j_mayer | opba = opaque; |
375 | 8ecc7913 | j_mayer | opba->cr = 0x00; /* No dynamic priorities - park disabled */ |
376 | 8ecc7913 | j_mayer | opba->pr = 0x11;
|
377 | 8ecc7913 | j_mayer | } |
378 | 8ecc7913 | j_mayer | |
379 | 9c02f1a2 | j_mayer | void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
380 | 9c02f1a2 | j_mayer | target_phys_addr_t offset) |
381 | 8ecc7913 | j_mayer | { |
382 | 8ecc7913 | j_mayer | ppc4xx_opba_t *opba; |
383 | 8ecc7913 | j_mayer | |
384 | 8ecc7913 | j_mayer | opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
|
385 | 8ecc7913 | j_mayer | if (opba != NULL) { |
386 | 9c02f1a2 | j_mayer | opba->base = offset; |
387 | 8ecc7913 | j_mayer | #ifdef DEBUG_OPBA
|
388 | 9c02f1a2 | j_mayer | printf("%s: offset=" PADDRX "\n", __func__, offset); |
389 | 8ecc7913 | j_mayer | #endif
|
390 | 8ecc7913 | j_mayer | ppc4xx_mmio_register(env, mmio, offset, 0x002,
|
391 | 8ecc7913 | j_mayer | opba_read, opba_write, opba); |
392 | 8ecc7913 | j_mayer | qemu_register_reset(ppc4xx_opba_reset, opba); |
393 | 8ecc7913 | j_mayer | ppc4xx_opba_reset(opba); |
394 | 8ecc7913 | j_mayer | } |
395 | 8ecc7913 | j_mayer | } |
396 | 8ecc7913 | j_mayer | |
397 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
398 | 8ecc7913 | j_mayer | /* Code decompression controller */
|
399 | 8ecc7913 | j_mayer | /* XXX: TODO */
|
400 | 8ecc7913 | j_mayer | |
401 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
402 | 8ecc7913 | j_mayer | /* SDRAM controller */
|
403 | 8ecc7913 | j_mayer | typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; |
404 | 8ecc7913 | j_mayer | struct ppc4xx_sdram_t {
|
405 | 8ecc7913 | j_mayer | uint32_t addr; |
406 | 8ecc7913 | j_mayer | int nbanks;
|
407 | 71db710f | blueswir1 | target_phys_addr_t ram_bases[4];
|
408 | 71db710f | blueswir1 | target_phys_addr_t ram_sizes[4];
|
409 | 8ecc7913 | j_mayer | uint32_t besr0; |
410 | 8ecc7913 | j_mayer | uint32_t besr1; |
411 | 8ecc7913 | j_mayer | uint32_t bear; |
412 | 8ecc7913 | j_mayer | uint32_t cfg; |
413 | 8ecc7913 | j_mayer | uint32_t status; |
414 | 8ecc7913 | j_mayer | uint32_t rtr; |
415 | 8ecc7913 | j_mayer | uint32_t pmit; |
416 | 8ecc7913 | j_mayer | uint32_t bcr[4];
|
417 | 8ecc7913 | j_mayer | uint32_t tr; |
418 | 8ecc7913 | j_mayer | uint32_t ecccfg; |
419 | 8ecc7913 | j_mayer | uint32_t eccesr; |
420 | 8ecc7913 | j_mayer | qemu_irq irq; |
421 | 8ecc7913 | j_mayer | }; |
422 | 8ecc7913 | j_mayer | |
423 | 8ecc7913 | j_mayer | enum {
|
424 | 8ecc7913 | j_mayer | SDRAM0_CFGADDR = 0x010,
|
425 | 8ecc7913 | j_mayer | SDRAM0_CFGDATA = 0x011,
|
426 | 8ecc7913 | j_mayer | }; |
427 | 8ecc7913 | j_mayer | |
428 | 36081602 | j_mayer | static uint32_t sdram_bcr (target_phys_addr_t ram_base,
|
429 | 36081602 | j_mayer | target_phys_addr_t ram_size) |
430 | 8ecc7913 | j_mayer | { |
431 | 8ecc7913 | j_mayer | uint32_t bcr; |
432 | 8ecc7913 | j_mayer | |
433 | 8ecc7913 | j_mayer | switch (ram_size) {
|
434 | 8ecc7913 | j_mayer | case (4 * 1024 * 1024): |
435 | 8ecc7913 | j_mayer | bcr = 0x00000000;
|
436 | 8ecc7913 | j_mayer | break;
|
437 | 8ecc7913 | j_mayer | case (8 * 1024 * 1024): |
438 | 8ecc7913 | j_mayer | bcr = 0x00020000;
|
439 | 8ecc7913 | j_mayer | break;
|
440 | 8ecc7913 | j_mayer | case (16 * 1024 * 1024): |
441 | 8ecc7913 | j_mayer | bcr = 0x00040000;
|
442 | 8ecc7913 | j_mayer | break;
|
443 | 8ecc7913 | j_mayer | case (32 * 1024 * 1024): |
444 | 8ecc7913 | j_mayer | bcr = 0x00060000;
|
445 | 8ecc7913 | j_mayer | break;
|
446 | 8ecc7913 | j_mayer | case (64 * 1024 * 1024): |
447 | 8ecc7913 | j_mayer | bcr = 0x00080000;
|
448 | 8ecc7913 | j_mayer | break;
|
449 | 8ecc7913 | j_mayer | case (128 * 1024 * 1024): |
450 | 8ecc7913 | j_mayer | bcr = 0x000A0000;
|
451 | 8ecc7913 | j_mayer | break;
|
452 | 8ecc7913 | j_mayer | case (256 * 1024 * 1024): |
453 | 8ecc7913 | j_mayer | bcr = 0x000C0000;
|
454 | 8ecc7913 | j_mayer | break;
|
455 | 8ecc7913 | j_mayer | default:
|
456 | be58fc7c | j_mayer | printf("%s: invalid RAM size " TARGET_FMT_plx "\n", |
457 | be58fc7c | j_mayer | __func__, ram_size); |
458 | 8ecc7913 | j_mayer | return 0x00000000; |
459 | 8ecc7913 | j_mayer | } |
460 | 8ecc7913 | j_mayer | bcr |= ram_base & 0xFF800000;
|
461 | 8ecc7913 | j_mayer | bcr |= 1;
|
462 | 8ecc7913 | j_mayer | |
463 | 8ecc7913 | j_mayer | return bcr;
|
464 | 8ecc7913 | j_mayer | } |
465 | 8ecc7913 | j_mayer | |
466 | 71db710f | blueswir1 | static inline target_phys_addr_t sdram_base (uint32_t bcr) |
467 | 8ecc7913 | j_mayer | { |
468 | 8ecc7913 | j_mayer | return bcr & 0xFF800000; |
469 | 8ecc7913 | j_mayer | } |
470 | 8ecc7913 | j_mayer | |
471 | 8ecc7913 | j_mayer | static target_ulong sdram_size (uint32_t bcr)
|
472 | 8ecc7913 | j_mayer | { |
473 | 8ecc7913 | j_mayer | target_ulong size; |
474 | 8ecc7913 | j_mayer | int sh;
|
475 | 8ecc7913 | j_mayer | |
476 | 8ecc7913 | j_mayer | sh = (bcr >> 17) & 0x7; |
477 | 8ecc7913 | j_mayer | if (sh == 7) |
478 | 8ecc7913 | j_mayer | size = -1;
|
479 | 8ecc7913 | j_mayer | else
|
480 | 8ecc7913 | j_mayer | size = (4 * 1024 * 1024) << sh; |
481 | 8ecc7913 | j_mayer | |
482 | 8ecc7913 | j_mayer | return size;
|
483 | 8ecc7913 | j_mayer | } |
484 | 8ecc7913 | j_mayer | |
485 | 8ecc7913 | j_mayer | static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled) |
486 | 8ecc7913 | j_mayer | { |
487 | 8ecc7913 | j_mayer | if (*bcrp & 0x00000001) { |
488 | 8ecc7913 | j_mayer | /* Unmap RAM */
|
489 | 8ecc7913 | j_mayer | #ifdef DEBUG_SDRAM
|
490 | be58fc7c | j_mayer | printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
491 | be58fc7c | j_mayer | __func__, sdram_base(*bcrp), sdram_size(*bcrp)); |
492 | 8ecc7913 | j_mayer | #endif
|
493 | 8ecc7913 | j_mayer | cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp), |
494 | 8ecc7913 | j_mayer | IO_MEM_UNASSIGNED); |
495 | 8ecc7913 | j_mayer | } |
496 | 8ecc7913 | j_mayer | *bcrp = bcr & 0xFFDEE001;
|
497 | 8ecc7913 | j_mayer | if (enabled && (bcr & 0x00000001)) { |
498 | 8ecc7913 | j_mayer | #ifdef DEBUG_SDRAM
|
499 | be58fc7c | j_mayer | printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
500 | be58fc7c | j_mayer | __func__, sdram_base(bcr), sdram_size(bcr)); |
501 | 8ecc7913 | j_mayer | #endif
|
502 | 8ecc7913 | j_mayer | cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), |
503 | 8ecc7913 | j_mayer | sdram_base(bcr) | IO_MEM_RAM); |
504 | 8ecc7913 | j_mayer | } |
505 | 8ecc7913 | j_mayer | } |
506 | 8ecc7913 | j_mayer | |
507 | 8ecc7913 | j_mayer | static void sdram_map_bcr (ppc4xx_sdram_t *sdram) |
508 | 8ecc7913 | j_mayer | { |
509 | 8ecc7913 | j_mayer | int i;
|
510 | 8ecc7913 | j_mayer | |
511 | 8ecc7913 | j_mayer | for (i = 0; i < sdram->nbanks; i++) { |
512 | 8ecc7913 | j_mayer | if (sdram->ram_sizes[i] != 0) { |
513 | 8ecc7913 | j_mayer | sdram_set_bcr(&sdram->bcr[i], |
514 | 8ecc7913 | j_mayer | sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), |
515 | 8ecc7913 | j_mayer | 1);
|
516 | 8ecc7913 | j_mayer | } else {
|
517 | 8ecc7913 | j_mayer | sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); |
518 | 8ecc7913 | j_mayer | } |
519 | 8ecc7913 | j_mayer | } |
520 | 8ecc7913 | j_mayer | } |
521 | 8ecc7913 | j_mayer | |
522 | 8ecc7913 | j_mayer | static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) |
523 | 8ecc7913 | j_mayer | { |
524 | 8ecc7913 | j_mayer | int i;
|
525 | 8ecc7913 | j_mayer | |
526 | 8ecc7913 | j_mayer | for (i = 0; i < sdram->nbanks; i++) { |
527 | 04f20795 | j_mayer | #ifdef DEBUG_SDRAM
|
528 | be58fc7c | j_mayer | printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n", |
529 | be58fc7c | j_mayer | __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i])); |
530 | 04f20795 | j_mayer | #endif
|
531 | 8ecc7913 | j_mayer | cpu_register_physical_memory(sdram_base(sdram->bcr[i]), |
532 | 8ecc7913 | j_mayer | sdram_size(sdram->bcr[i]), |
533 | 8ecc7913 | j_mayer | IO_MEM_UNASSIGNED); |
534 | 8ecc7913 | j_mayer | } |
535 | 8ecc7913 | j_mayer | } |
536 | 8ecc7913 | j_mayer | |
537 | 8ecc7913 | j_mayer | static target_ulong dcr_read_sdram (void *opaque, int dcrn) |
538 | 8ecc7913 | j_mayer | { |
539 | 8ecc7913 | j_mayer | ppc4xx_sdram_t *sdram; |
540 | 8ecc7913 | j_mayer | target_ulong ret; |
541 | 8ecc7913 | j_mayer | |
542 | 8ecc7913 | j_mayer | sdram = opaque; |
543 | 8ecc7913 | j_mayer | switch (dcrn) {
|
544 | 8ecc7913 | j_mayer | case SDRAM0_CFGADDR:
|
545 | 8ecc7913 | j_mayer | ret = sdram->addr; |
546 | 8ecc7913 | j_mayer | break;
|
547 | 8ecc7913 | j_mayer | case SDRAM0_CFGDATA:
|
548 | 8ecc7913 | j_mayer | switch (sdram->addr) {
|
549 | 8ecc7913 | j_mayer | case 0x00: /* SDRAM_BESR0 */ |
550 | 8ecc7913 | j_mayer | ret = sdram->besr0; |
551 | 8ecc7913 | j_mayer | break;
|
552 | 8ecc7913 | j_mayer | case 0x08: /* SDRAM_BESR1 */ |
553 | 8ecc7913 | j_mayer | ret = sdram->besr1; |
554 | 8ecc7913 | j_mayer | break;
|
555 | 8ecc7913 | j_mayer | case 0x10: /* SDRAM_BEAR */ |
556 | 8ecc7913 | j_mayer | ret = sdram->bear; |
557 | 8ecc7913 | j_mayer | break;
|
558 | 8ecc7913 | j_mayer | case 0x20: /* SDRAM_CFG */ |
559 | 8ecc7913 | j_mayer | ret = sdram->cfg; |
560 | 8ecc7913 | j_mayer | break;
|
561 | 8ecc7913 | j_mayer | case 0x24: /* SDRAM_STATUS */ |
562 | 8ecc7913 | j_mayer | ret = sdram->status; |
563 | 8ecc7913 | j_mayer | break;
|
564 | 8ecc7913 | j_mayer | case 0x30: /* SDRAM_RTR */ |
565 | 8ecc7913 | j_mayer | ret = sdram->rtr; |
566 | 8ecc7913 | j_mayer | break;
|
567 | 8ecc7913 | j_mayer | case 0x34: /* SDRAM_PMIT */ |
568 | 8ecc7913 | j_mayer | ret = sdram->pmit; |
569 | 8ecc7913 | j_mayer | break;
|
570 | 8ecc7913 | j_mayer | case 0x40: /* SDRAM_B0CR */ |
571 | 8ecc7913 | j_mayer | ret = sdram->bcr[0];
|
572 | 8ecc7913 | j_mayer | break;
|
573 | 8ecc7913 | j_mayer | case 0x44: /* SDRAM_B1CR */ |
574 | 8ecc7913 | j_mayer | ret = sdram->bcr[1];
|
575 | 8ecc7913 | j_mayer | break;
|
576 | 8ecc7913 | j_mayer | case 0x48: /* SDRAM_B2CR */ |
577 | 8ecc7913 | j_mayer | ret = sdram->bcr[2];
|
578 | 8ecc7913 | j_mayer | break;
|
579 | 8ecc7913 | j_mayer | case 0x4C: /* SDRAM_B3CR */ |
580 | 8ecc7913 | j_mayer | ret = sdram->bcr[3];
|
581 | 8ecc7913 | j_mayer | break;
|
582 | 8ecc7913 | j_mayer | case 0x80: /* SDRAM_TR */ |
583 | 8ecc7913 | j_mayer | ret = -1; /* ? */ |
584 | 8ecc7913 | j_mayer | break;
|
585 | 8ecc7913 | j_mayer | case 0x94: /* SDRAM_ECCCFG */ |
586 | 8ecc7913 | j_mayer | ret = sdram->ecccfg; |
587 | 8ecc7913 | j_mayer | break;
|
588 | 8ecc7913 | j_mayer | case 0x98: /* SDRAM_ECCESR */ |
589 | 8ecc7913 | j_mayer | ret = sdram->eccesr; |
590 | 8ecc7913 | j_mayer | break;
|
591 | 8ecc7913 | j_mayer | default: /* Error */ |
592 | 8ecc7913 | j_mayer | ret = -1;
|
593 | 8ecc7913 | j_mayer | break;
|
594 | 8ecc7913 | j_mayer | } |
595 | 8ecc7913 | j_mayer | break;
|
596 | 8ecc7913 | j_mayer | default:
|
597 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
|
598 | 8ecc7913 | j_mayer | ret = 0x00000000;
|
599 | 8ecc7913 | j_mayer | break;
|
600 | 8ecc7913 | j_mayer | } |
601 | 8ecc7913 | j_mayer | |
602 | 8ecc7913 | j_mayer | return ret;
|
603 | 8ecc7913 | j_mayer | } |
604 | 8ecc7913 | j_mayer | |
605 | 8ecc7913 | j_mayer | static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val) |
606 | 8ecc7913 | j_mayer | { |
607 | 8ecc7913 | j_mayer | ppc4xx_sdram_t *sdram; |
608 | 8ecc7913 | j_mayer | |
609 | 8ecc7913 | j_mayer | sdram = opaque; |
610 | 8ecc7913 | j_mayer | switch (dcrn) {
|
611 | 8ecc7913 | j_mayer | case SDRAM0_CFGADDR:
|
612 | 8ecc7913 | j_mayer | sdram->addr = val; |
613 | 8ecc7913 | j_mayer | break;
|
614 | 8ecc7913 | j_mayer | case SDRAM0_CFGDATA:
|
615 | 8ecc7913 | j_mayer | switch (sdram->addr) {
|
616 | 8ecc7913 | j_mayer | case 0x00: /* SDRAM_BESR0 */ |
617 | 8ecc7913 | j_mayer | sdram->besr0 &= ~val; |
618 | 8ecc7913 | j_mayer | break;
|
619 | 8ecc7913 | j_mayer | case 0x08: /* SDRAM_BESR1 */ |
620 | 8ecc7913 | j_mayer | sdram->besr1 &= ~val; |
621 | 8ecc7913 | j_mayer | break;
|
622 | 8ecc7913 | j_mayer | case 0x10: /* SDRAM_BEAR */ |
623 | 8ecc7913 | j_mayer | sdram->bear = val; |
624 | 8ecc7913 | j_mayer | break;
|
625 | 8ecc7913 | j_mayer | case 0x20: /* SDRAM_CFG */ |
626 | 8ecc7913 | j_mayer | val &= 0xFFE00000;
|
627 | 8ecc7913 | j_mayer | if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { |
628 | 8ecc7913 | j_mayer | #ifdef DEBUG_SDRAM
|
629 | 8ecc7913 | j_mayer | printf("%s: enable SDRAM controller\n", __func__);
|
630 | 8ecc7913 | j_mayer | #endif
|
631 | 8ecc7913 | j_mayer | /* validate all RAM mappings */
|
632 | 8ecc7913 | j_mayer | sdram_map_bcr(sdram); |
633 | 8ecc7913 | j_mayer | sdram->status &= ~0x80000000;
|
634 | 8ecc7913 | j_mayer | } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { |
635 | 8ecc7913 | j_mayer | #ifdef DEBUG_SDRAM
|
636 | 8ecc7913 | j_mayer | printf("%s: disable SDRAM controller\n", __func__);
|
637 | 8ecc7913 | j_mayer | #endif
|
638 | 8ecc7913 | j_mayer | /* invalidate all RAM mappings */
|
639 | 8ecc7913 | j_mayer | sdram_unmap_bcr(sdram); |
640 | 8ecc7913 | j_mayer | sdram->status |= 0x80000000;
|
641 | 8ecc7913 | j_mayer | } |
642 | 8ecc7913 | j_mayer | if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) |
643 | 8ecc7913 | j_mayer | sdram->status |= 0x40000000;
|
644 | 8ecc7913 | j_mayer | else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) |
645 | 8ecc7913 | j_mayer | sdram->status &= ~0x40000000;
|
646 | 8ecc7913 | j_mayer | sdram->cfg = val; |
647 | 8ecc7913 | j_mayer | break;
|
648 | 8ecc7913 | j_mayer | case 0x24: /* SDRAM_STATUS */ |
649 | 8ecc7913 | j_mayer | /* Read-only register */
|
650 | 8ecc7913 | j_mayer | break;
|
651 | 8ecc7913 | j_mayer | case 0x30: /* SDRAM_RTR */ |
652 | 8ecc7913 | j_mayer | sdram->rtr = val & 0x3FF80000;
|
653 | 8ecc7913 | j_mayer | break;
|
654 | 8ecc7913 | j_mayer | case 0x34: /* SDRAM_PMIT */ |
655 | 8ecc7913 | j_mayer | sdram->pmit = (val & 0xF8000000) | 0x07C00000; |
656 | 8ecc7913 | j_mayer | break;
|
657 | 8ecc7913 | j_mayer | case 0x40: /* SDRAM_B0CR */ |
658 | 8ecc7913 | j_mayer | sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); |
659 | 8ecc7913 | j_mayer | break;
|
660 | 8ecc7913 | j_mayer | case 0x44: /* SDRAM_B1CR */ |
661 | 8ecc7913 | j_mayer | sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); |
662 | 8ecc7913 | j_mayer | break;
|
663 | 8ecc7913 | j_mayer | case 0x48: /* SDRAM_B2CR */ |
664 | 8ecc7913 | j_mayer | sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); |
665 | 8ecc7913 | j_mayer | break;
|
666 | 8ecc7913 | j_mayer | case 0x4C: /* SDRAM_B3CR */ |
667 | 8ecc7913 | j_mayer | sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); |
668 | 8ecc7913 | j_mayer | break;
|
669 | 8ecc7913 | j_mayer | case 0x80: /* SDRAM_TR */ |
670 | 8ecc7913 | j_mayer | sdram->tr = val & 0x018FC01F;
|
671 | 8ecc7913 | j_mayer | break;
|
672 | 8ecc7913 | j_mayer | case 0x94: /* SDRAM_ECCCFG */ |
673 | 8ecc7913 | j_mayer | sdram->ecccfg = val & 0x00F00000;
|
674 | 8ecc7913 | j_mayer | break;
|
675 | 8ecc7913 | j_mayer | case 0x98: /* SDRAM_ECCESR */ |
676 | 8ecc7913 | j_mayer | val &= 0xFFF0F000;
|
677 | 8ecc7913 | j_mayer | if (sdram->eccesr == 0 && val != 0) |
678 | 8ecc7913 | j_mayer | qemu_irq_raise(sdram->irq); |
679 | 8ecc7913 | j_mayer | else if (sdram->eccesr != 0 && val == 0) |
680 | 8ecc7913 | j_mayer | qemu_irq_lower(sdram->irq); |
681 | 8ecc7913 | j_mayer | sdram->eccesr = val; |
682 | 8ecc7913 | j_mayer | break;
|
683 | 8ecc7913 | j_mayer | default: /* Error */ |
684 | 8ecc7913 | j_mayer | break;
|
685 | 8ecc7913 | j_mayer | } |
686 | 8ecc7913 | j_mayer | break;
|
687 | 8ecc7913 | j_mayer | } |
688 | 8ecc7913 | j_mayer | } |
689 | 8ecc7913 | j_mayer | |
690 | 8ecc7913 | j_mayer | static void sdram_reset (void *opaque) |
691 | 8ecc7913 | j_mayer | { |
692 | 8ecc7913 | j_mayer | ppc4xx_sdram_t *sdram; |
693 | 8ecc7913 | j_mayer | |
694 | 8ecc7913 | j_mayer | sdram = opaque; |
695 | 8ecc7913 | j_mayer | sdram->addr = 0x00000000;
|
696 | 8ecc7913 | j_mayer | sdram->bear = 0x00000000;
|
697 | 8ecc7913 | j_mayer | sdram->besr0 = 0x00000000; /* No error */ |
698 | 8ecc7913 | j_mayer | sdram->besr1 = 0x00000000; /* No error */ |
699 | 8ecc7913 | j_mayer | sdram->cfg = 0x00000000;
|
700 | 8ecc7913 | j_mayer | sdram->ecccfg = 0x00000000; /* No ECC */ |
701 | 8ecc7913 | j_mayer | sdram->eccesr = 0x00000000; /* No error */ |
702 | 8ecc7913 | j_mayer | sdram->pmit = 0x07C00000;
|
703 | 8ecc7913 | j_mayer | sdram->rtr = 0x05F00000;
|
704 | 8ecc7913 | j_mayer | sdram->tr = 0x00854009;
|
705 | 8ecc7913 | j_mayer | /* We pre-initialize RAM banks */
|
706 | 8ecc7913 | j_mayer | sdram->status = 0x00000000;
|
707 | 8ecc7913 | j_mayer | sdram->cfg = 0x00800000;
|
708 | 8ecc7913 | j_mayer | sdram_unmap_bcr(sdram); |
709 | 8ecc7913 | j_mayer | } |
710 | 8ecc7913 | j_mayer | |
711 | 8ecc7913 | j_mayer | void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
712 | 71db710f | blueswir1 | target_phys_addr_t *ram_bases, |
713 | 71db710f | blueswir1 | target_phys_addr_t *ram_sizes, |
714 | 04f20795 | j_mayer | int do_init)
|
715 | 8ecc7913 | j_mayer | { |
716 | 8ecc7913 | j_mayer | ppc4xx_sdram_t *sdram; |
717 | 8ecc7913 | j_mayer | |
718 | 8ecc7913 | j_mayer | sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
|
719 | 8ecc7913 | j_mayer | if (sdram != NULL) { |
720 | 8ecc7913 | j_mayer | sdram->irq = irq; |
721 | 8ecc7913 | j_mayer | sdram->nbanks = nbanks; |
722 | 71db710f | blueswir1 | memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
723 | 36081602 | j_mayer | memcpy(sdram->ram_bases, ram_bases, |
724 | 36081602 | j_mayer | nbanks * sizeof(target_phys_addr_t));
|
725 | 71db710f | blueswir1 | memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); |
726 | 36081602 | j_mayer | memcpy(sdram->ram_sizes, ram_sizes, |
727 | 36081602 | j_mayer | nbanks * sizeof(target_phys_addr_t));
|
728 | 8ecc7913 | j_mayer | sdram_reset(sdram); |
729 | 8ecc7913 | j_mayer | qemu_register_reset(&sdram_reset, sdram); |
730 | 8ecc7913 | j_mayer | ppc_dcr_register(env, SDRAM0_CFGADDR, |
731 | 8ecc7913 | j_mayer | sdram, &dcr_read_sdram, &dcr_write_sdram); |
732 | 8ecc7913 | j_mayer | ppc_dcr_register(env, SDRAM0_CFGDATA, |
733 | 8ecc7913 | j_mayer | sdram, &dcr_read_sdram, &dcr_write_sdram); |
734 | 04f20795 | j_mayer | if (do_init)
|
735 | 04f20795 | j_mayer | sdram_map_bcr(sdram); |
736 | 8ecc7913 | j_mayer | } |
737 | 8ecc7913 | j_mayer | } |
738 | 8ecc7913 | j_mayer | |
739 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
740 | 8ecc7913 | j_mayer | /* Peripheral controller */
|
741 | 8ecc7913 | j_mayer | typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; |
742 | 8ecc7913 | j_mayer | struct ppc4xx_ebc_t {
|
743 | 8ecc7913 | j_mayer | uint32_t addr; |
744 | 8ecc7913 | j_mayer | uint32_t bcr[8];
|
745 | 8ecc7913 | j_mayer | uint32_t bap[8];
|
746 | 8ecc7913 | j_mayer | uint32_t bear; |
747 | 8ecc7913 | j_mayer | uint32_t besr0; |
748 | 8ecc7913 | j_mayer | uint32_t besr1; |
749 | 8ecc7913 | j_mayer | uint32_t cfg; |
750 | 8ecc7913 | j_mayer | }; |
751 | 8ecc7913 | j_mayer | |
752 | 8ecc7913 | j_mayer | enum {
|
753 | 8ecc7913 | j_mayer | EBC0_CFGADDR = 0x012,
|
754 | 8ecc7913 | j_mayer | EBC0_CFGDATA = 0x013,
|
755 | 8ecc7913 | j_mayer | }; |
756 | 8ecc7913 | j_mayer | |
757 | 8ecc7913 | j_mayer | static target_ulong dcr_read_ebc (void *opaque, int dcrn) |
758 | 8ecc7913 | j_mayer | { |
759 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
760 | 8ecc7913 | j_mayer | target_ulong ret; |
761 | 8ecc7913 | j_mayer | |
762 | 8ecc7913 | j_mayer | ebc = opaque; |
763 | 8ecc7913 | j_mayer | switch (dcrn) {
|
764 | 8ecc7913 | j_mayer | case EBC0_CFGADDR:
|
765 | 8ecc7913 | j_mayer | ret = ebc->addr; |
766 | 8ecc7913 | j_mayer | break;
|
767 | 8ecc7913 | j_mayer | case EBC0_CFGDATA:
|
768 | 8ecc7913 | j_mayer | switch (ebc->addr) {
|
769 | 8ecc7913 | j_mayer | case 0x00: /* B0CR */ |
770 | 8ecc7913 | j_mayer | ret = ebc->bcr[0];
|
771 | 8ecc7913 | j_mayer | break;
|
772 | 8ecc7913 | j_mayer | case 0x01: /* B1CR */ |
773 | 8ecc7913 | j_mayer | ret = ebc->bcr[1];
|
774 | 8ecc7913 | j_mayer | break;
|
775 | 8ecc7913 | j_mayer | case 0x02: /* B2CR */ |
776 | 8ecc7913 | j_mayer | ret = ebc->bcr[2];
|
777 | 8ecc7913 | j_mayer | break;
|
778 | 8ecc7913 | j_mayer | case 0x03: /* B3CR */ |
779 | 8ecc7913 | j_mayer | ret = ebc->bcr[3];
|
780 | 8ecc7913 | j_mayer | break;
|
781 | 8ecc7913 | j_mayer | case 0x04: /* B4CR */ |
782 | 8ecc7913 | j_mayer | ret = ebc->bcr[4];
|
783 | 8ecc7913 | j_mayer | break;
|
784 | 8ecc7913 | j_mayer | case 0x05: /* B5CR */ |
785 | 8ecc7913 | j_mayer | ret = ebc->bcr[5];
|
786 | 8ecc7913 | j_mayer | break;
|
787 | 8ecc7913 | j_mayer | case 0x06: /* B6CR */ |
788 | 8ecc7913 | j_mayer | ret = ebc->bcr[6];
|
789 | 8ecc7913 | j_mayer | break;
|
790 | 8ecc7913 | j_mayer | case 0x07: /* B7CR */ |
791 | 8ecc7913 | j_mayer | ret = ebc->bcr[7];
|
792 | 8ecc7913 | j_mayer | break;
|
793 | 8ecc7913 | j_mayer | case 0x10: /* B0AP */ |
794 | 8ecc7913 | j_mayer | ret = ebc->bap[0];
|
795 | 8ecc7913 | j_mayer | break;
|
796 | 8ecc7913 | j_mayer | case 0x11: /* B1AP */ |
797 | 8ecc7913 | j_mayer | ret = ebc->bap[1];
|
798 | 8ecc7913 | j_mayer | break;
|
799 | 8ecc7913 | j_mayer | case 0x12: /* B2AP */ |
800 | 8ecc7913 | j_mayer | ret = ebc->bap[2];
|
801 | 8ecc7913 | j_mayer | break;
|
802 | 8ecc7913 | j_mayer | case 0x13: /* B3AP */ |
803 | 8ecc7913 | j_mayer | ret = ebc->bap[3];
|
804 | 8ecc7913 | j_mayer | break;
|
805 | 8ecc7913 | j_mayer | case 0x14: /* B4AP */ |
806 | 8ecc7913 | j_mayer | ret = ebc->bap[4];
|
807 | 8ecc7913 | j_mayer | break;
|
808 | 8ecc7913 | j_mayer | case 0x15: /* B5AP */ |
809 | 8ecc7913 | j_mayer | ret = ebc->bap[5];
|
810 | 8ecc7913 | j_mayer | break;
|
811 | 8ecc7913 | j_mayer | case 0x16: /* B6AP */ |
812 | 8ecc7913 | j_mayer | ret = ebc->bap[6];
|
813 | 8ecc7913 | j_mayer | break;
|
814 | 8ecc7913 | j_mayer | case 0x17: /* B7AP */ |
815 | 8ecc7913 | j_mayer | ret = ebc->bap[7];
|
816 | 8ecc7913 | j_mayer | break;
|
817 | 8ecc7913 | j_mayer | case 0x20: /* BEAR */ |
818 | 8ecc7913 | j_mayer | ret = ebc->bear; |
819 | 8ecc7913 | j_mayer | break;
|
820 | 8ecc7913 | j_mayer | case 0x21: /* BESR0 */ |
821 | 8ecc7913 | j_mayer | ret = ebc->besr0; |
822 | 8ecc7913 | j_mayer | break;
|
823 | 8ecc7913 | j_mayer | case 0x22: /* BESR1 */ |
824 | 8ecc7913 | j_mayer | ret = ebc->besr1; |
825 | 8ecc7913 | j_mayer | break;
|
826 | 8ecc7913 | j_mayer | case 0x23: /* CFG */ |
827 | 8ecc7913 | j_mayer | ret = ebc->cfg; |
828 | 8ecc7913 | j_mayer | break;
|
829 | 8ecc7913 | j_mayer | default:
|
830 | 8ecc7913 | j_mayer | ret = 0x00000000;
|
831 | 8ecc7913 | j_mayer | break;
|
832 | 8ecc7913 | j_mayer | } |
833 | 8ecc7913 | j_mayer | default:
|
834 | 8ecc7913 | j_mayer | ret = 0x00000000;
|
835 | 8ecc7913 | j_mayer | break;
|
836 | 8ecc7913 | j_mayer | } |
837 | 8ecc7913 | j_mayer | |
838 | 8ecc7913 | j_mayer | return ret;
|
839 | 8ecc7913 | j_mayer | } |
840 | 8ecc7913 | j_mayer | |
841 | 8ecc7913 | j_mayer | static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val) |
842 | 8ecc7913 | j_mayer | { |
843 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
844 | 8ecc7913 | j_mayer | |
845 | 8ecc7913 | j_mayer | ebc = opaque; |
846 | 8ecc7913 | j_mayer | switch (dcrn) {
|
847 | 8ecc7913 | j_mayer | case EBC0_CFGADDR:
|
848 | 8ecc7913 | j_mayer | ebc->addr = val; |
849 | 8ecc7913 | j_mayer | break;
|
850 | 8ecc7913 | j_mayer | case EBC0_CFGDATA:
|
851 | 8ecc7913 | j_mayer | switch (ebc->addr) {
|
852 | 8ecc7913 | j_mayer | case 0x00: /* B0CR */ |
853 | 8ecc7913 | j_mayer | break;
|
854 | 8ecc7913 | j_mayer | case 0x01: /* B1CR */ |
855 | 8ecc7913 | j_mayer | break;
|
856 | 8ecc7913 | j_mayer | case 0x02: /* B2CR */ |
857 | 8ecc7913 | j_mayer | break;
|
858 | 8ecc7913 | j_mayer | case 0x03: /* B3CR */ |
859 | 8ecc7913 | j_mayer | break;
|
860 | 8ecc7913 | j_mayer | case 0x04: /* B4CR */ |
861 | 8ecc7913 | j_mayer | break;
|
862 | 8ecc7913 | j_mayer | case 0x05: /* B5CR */ |
863 | 8ecc7913 | j_mayer | break;
|
864 | 8ecc7913 | j_mayer | case 0x06: /* B6CR */ |
865 | 8ecc7913 | j_mayer | break;
|
866 | 8ecc7913 | j_mayer | case 0x07: /* B7CR */ |
867 | 8ecc7913 | j_mayer | break;
|
868 | 8ecc7913 | j_mayer | case 0x10: /* B0AP */ |
869 | 8ecc7913 | j_mayer | break;
|
870 | 8ecc7913 | j_mayer | case 0x11: /* B1AP */ |
871 | 8ecc7913 | j_mayer | break;
|
872 | 8ecc7913 | j_mayer | case 0x12: /* B2AP */ |
873 | 8ecc7913 | j_mayer | break;
|
874 | 8ecc7913 | j_mayer | case 0x13: /* B3AP */ |
875 | 8ecc7913 | j_mayer | break;
|
876 | 8ecc7913 | j_mayer | case 0x14: /* B4AP */ |
877 | 8ecc7913 | j_mayer | break;
|
878 | 8ecc7913 | j_mayer | case 0x15: /* B5AP */ |
879 | 8ecc7913 | j_mayer | break;
|
880 | 8ecc7913 | j_mayer | case 0x16: /* B6AP */ |
881 | 8ecc7913 | j_mayer | break;
|
882 | 8ecc7913 | j_mayer | case 0x17: /* B7AP */ |
883 | 8ecc7913 | j_mayer | break;
|
884 | 8ecc7913 | j_mayer | case 0x20: /* BEAR */ |
885 | 8ecc7913 | j_mayer | break;
|
886 | 8ecc7913 | j_mayer | case 0x21: /* BESR0 */ |
887 | 8ecc7913 | j_mayer | break;
|
888 | 8ecc7913 | j_mayer | case 0x22: /* BESR1 */ |
889 | 8ecc7913 | j_mayer | break;
|
890 | 8ecc7913 | j_mayer | case 0x23: /* CFG */ |
891 | 8ecc7913 | j_mayer | break;
|
892 | 8ecc7913 | j_mayer | default:
|
893 | 8ecc7913 | j_mayer | break;
|
894 | 8ecc7913 | j_mayer | } |
895 | 8ecc7913 | j_mayer | break;
|
896 | 8ecc7913 | j_mayer | default:
|
897 | 8ecc7913 | j_mayer | break;
|
898 | 8ecc7913 | j_mayer | } |
899 | 8ecc7913 | j_mayer | } |
900 | 8ecc7913 | j_mayer | |
901 | 8ecc7913 | j_mayer | static void ebc_reset (void *opaque) |
902 | 8ecc7913 | j_mayer | { |
903 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
904 | 8ecc7913 | j_mayer | int i;
|
905 | 8ecc7913 | j_mayer | |
906 | 8ecc7913 | j_mayer | ebc = opaque; |
907 | 8ecc7913 | j_mayer | ebc->addr = 0x00000000;
|
908 | 8ecc7913 | j_mayer | ebc->bap[0] = 0x7F8FFE80; |
909 | 8ecc7913 | j_mayer | ebc->bcr[0] = 0xFFE28000; |
910 | 8ecc7913 | j_mayer | for (i = 0; i < 8; i++) { |
911 | 8ecc7913 | j_mayer | ebc->bap[i] = 0x00000000;
|
912 | 8ecc7913 | j_mayer | ebc->bcr[i] = 0x00000000;
|
913 | 8ecc7913 | j_mayer | } |
914 | 8ecc7913 | j_mayer | ebc->besr0 = 0x00000000;
|
915 | 8ecc7913 | j_mayer | ebc->besr1 = 0x00000000;
|
916 | 9c02f1a2 | j_mayer | ebc->cfg = 0x80400000;
|
917 | 8ecc7913 | j_mayer | } |
918 | 8ecc7913 | j_mayer | |
919 | 8ecc7913 | j_mayer | void ppc405_ebc_init (CPUState *env)
|
920 | 8ecc7913 | j_mayer | { |
921 | 8ecc7913 | j_mayer | ppc4xx_ebc_t *ebc; |
922 | 8ecc7913 | j_mayer | |
923 | 8ecc7913 | j_mayer | ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
|
924 | 8ecc7913 | j_mayer | if (ebc != NULL) { |
925 | 8ecc7913 | j_mayer | ebc_reset(ebc); |
926 | 8ecc7913 | j_mayer | qemu_register_reset(&ebc_reset, ebc); |
927 | 8ecc7913 | j_mayer | ppc_dcr_register(env, EBC0_CFGADDR, |
928 | 8ecc7913 | j_mayer | ebc, &dcr_read_ebc, &dcr_write_ebc); |
929 | 8ecc7913 | j_mayer | ppc_dcr_register(env, EBC0_CFGDATA, |
930 | 8ecc7913 | j_mayer | ebc, &dcr_read_ebc, &dcr_write_ebc); |
931 | 8ecc7913 | j_mayer | } |
932 | 8ecc7913 | j_mayer | } |
933 | 8ecc7913 | j_mayer | |
934 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
935 | 8ecc7913 | j_mayer | /* DMA controller */
|
936 | 8ecc7913 | j_mayer | enum {
|
937 | 8ecc7913 | j_mayer | DMA0_CR0 = 0x100,
|
938 | 8ecc7913 | j_mayer | DMA0_CT0 = 0x101,
|
939 | 8ecc7913 | j_mayer | DMA0_DA0 = 0x102,
|
940 | 8ecc7913 | j_mayer | DMA0_SA0 = 0x103,
|
941 | 8ecc7913 | j_mayer | DMA0_SG0 = 0x104,
|
942 | 8ecc7913 | j_mayer | DMA0_CR1 = 0x108,
|
943 | 8ecc7913 | j_mayer | DMA0_CT1 = 0x109,
|
944 | 8ecc7913 | j_mayer | DMA0_DA1 = 0x10A,
|
945 | 8ecc7913 | j_mayer | DMA0_SA1 = 0x10B,
|
946 | 8ecc7913 | j_mayer | DMA0_SG1 = 0x10C,
|
947 | 8ecc7913 | j_mayer | DMA0_CR2 = 0x110,
|
948 | 8ecc7913 | j_mayer | DMA0_CT2 = 0x111,
|
949 | 8ecc7913 | j_mayer | DMA0_DA2 = 0x112,
|
950 | 8ecc7913 | j_mayer | DMA0_SA2 = 0x113,
|
951 | 8ecc7913 | j_mayer | DMA0_SG2 = 0x114,
|
952 | 8ecc7913 | j_mayer | DMA0_CR3 = 0x118,
|
953 | 8ecc7913 | j_mayer | DMA0_CT3 = 0x119,
|
954 | 8ecc7913 | j_mayer | DMA0_DA3 = 0x11A,
|
955 | 8ecc7913 | j_mayer | DMA0_SA3 = 0x11B,
|
956 | 8ecc7913 | j_mayer | DMA0_SG3 = 0x11C,
|
957 | 8ecc7913 | j_mayer | DMA0_SR = 0x120,
|
958 | 8ecc7913 | j_mayer | DMA0_SGC = 0x123,
|
959 | 8ecc7913 | j_mayer | DMA0_SLP = 0x125,
|
960 | 8ecc7913 | j_mayer | DMA0_POL = 0x126,
|
961 | 8ecc7913 | j_mayer | }; |
962 | 8ecc7913 | j_mayer | |
963 | 8ecc7913 | j_mayer | typedef struct ppc405_dma_t ppc405_dma_t; |
964 | 8ecc7913 | j_mayer | struct ppc405_dma_t {
|
965 | 8ecc7913 | j_mayer | qemu_irq irqs[4];
|
966 | 8ecc7913 | j_mayer | uint32_t cr[4];
|
967 | 8ecc7913 | j_mayer | uint32_t ct[4];
|
968 | 8ecc7913 | j_mayer | uint32_t da[4];
|
969 | 8ecc7913 | j_mayer | uint32_t sa[4];
|
970 | 8ecc7913 | j_mayer | uint32_t sg[4];
|
971 | 8ecc7913 | j_mayer | uint32_t sr; |
972 | 8ecc7913 | j_mayer | uint32_t sgc; |
973 | 8ecc7913 | j_mayer | uint32_t slp; |
974 | 8ecc7913 | j_mayer | uint32_t pol; |
975 | 8ecc7913 | j_mayer | }; |
976 | 8ecc7913 | j_mayer | |
977 | 8ecc7913 | j_mayer | static target_ulong dcr_read_dma (void *opaque, int dcrn) |
978 | 8ecc7913 | j_mayer | { |
979 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
980 | 8ecc7913 | j_mayer | |
981 | 8ecc7913 | j_mayer | dma = opaque; |
982 | 8ecc7913 | j_mayer | |
983 | 8ecc7913 | j_mayer | return 0; |
984 | 8ecc7913 | j_mayer | } |
985 | 8ecc7913 | j_mayer | |
986 | 8ecc7913 | j_mayer | static void dcr_write_dma (void *opaque, int dcrn, target_ulong val) |
987 | 8ecc7913 | j_mayer | { |
988 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
989 | 8ecc7913 | j_mayer | |
990 | 8ecc7913 | j_mayer | dma = opaque; |
991 | 8ecc7913 | j_mayer | } |
992 | 8ecc7913 | j_mayer | |
993 | 8ecc7913 | j_mayer | static void ppc405_dma_reset (void *opaque) |
994 | 8ecc7913 | j_mayer | { |
995 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
996 | 8ecc7913 | j_mayer | int i;
|
997 | 8ecc7913 | j_mayer | |
998 | 8ecc7913 | j_mayer | dma = opaque; |
999 | 8ecc7913 | j_mayer | for (i = 0; i < 4; i++) { |
1000 | 8ecc7913 | j_mayer | dma->cr[i] = 0x00000000;
|
1001 | 8ecc7913 | j_mayer | dma->ct[i] = 0x00000000;
|
1002 | 8ecc7913 | j_mayer | dma->da[i] = 0x00000000;
|
1003 | 8ecc7913 | j_mayer | dma->sa[i] = 0x00000000;
|
1004 | 8ecc7913 | j_mayer | dma->sg[i] = 0x00000000;
|
1005 | 8ecc7913 | j_mayer | } |
1006 | 8ecc7913 | j_mayer | dma->sr = 0x00000000;
|
1007 | 8ecc7913 | j_mayer | dma->sgc = 0x00000000;
|
1008 | 8ecc7913 | j_mayer | dma->slp = 0x7C000000;
|
1009 | 8ecc7913 | j_mayer | dma->pol = 0x00000000;
|
1010 | 8ecc7913 | j_mayer | } |
1011 | 8ecc7913 | j_mayer | |
1012 | 8ecc7913 | j_mayer | void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]) |
1013 | 8ecc7913 | j_mayer | { |
1014 | 8ecc7913 | j_mayer | ppc405_dma_t *dma; |
1015 | 8ecc7913 | j_mayer | |
1016 | 8ecc7913 | j_mayer | dma = qemu_mallocz(sizeof(ppc405_dma_t));
|
1017 | 8ecc7913 | j_mayer | if (dma != NULL) { |
1018 | 8ecc7913 | j_mayer | memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); |
1019 | 8ecc7913 | j_mayer | ppc405_dma_reset(dma); |
1020 | 8ecc7913 | j_mayer | qemu_register_reset(&ppc405_dma_reset, dma); |
1021 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CR0, |
1022 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1023 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CT0, |
1024 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1025 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_DA0, |
1026 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1027 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SA0, |
1028 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1029 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SG0, |
1030 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1031 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CR1, |
1032 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1033 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CT1, |
1034 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1035 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_DA1, |
1036 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1037 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SA1, |
1038 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1039 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SG1, |
1040 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1041 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CR2, |
1042 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1043 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CT2, |
1044 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1045 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_DA2, |
1046 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1047 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SA2, |
1048 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1049 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SG2, |
1050 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1051 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CR3, |
1052 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1053 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_CT3, |
1054 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1055 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_DA3, |
1056 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1057 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SA3, |
1058 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1059 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SG3, |
1060 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1061 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SR, |
1062 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1063 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SGC, |
1064 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1065 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_SLP, |
1066 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1067 | 8ecc7913 | j_mayer | ppc_dcr_register(env, DMA0_POL, |
1068 | 8ecc7913 | j_mayer | dma, &dcr_read_dma, &dcr_write_dma); |
1069 | 8ecc7913 | j_mayer | } |
1070 | 8ecc7913 | j_mayer | } |
1071 | 8ecc7913 | j_mayer | |
1072 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
1073 | 8ecc7913 | j_mayer | /* GPIO */
|
1074 | 8ecc7913 | j_mayer | typedef struct ppc405_gpio_t ppc405_gpio_t; |
1075 | 8ecc7913 | j_mayer | struct ppc405_gpio_t {
|
1076 | 9c02f1a2 | j_mayer | target_phys_addr_t base; |
1077 | 8ecc7913 | j_mayer | uint32_t or; |
1078 | 8ecc7913 | j_mayer | uint32_t tcr; |
1079 | 8ecc7913 | j_mayer | uint32_t osrh; |
1080 | 8ecc7913 | j_mayer | uint32_t osrl; |
1081 | 8ecc7913 | j_mayer | uint32_t tsrh; |
1082 | 8ecc7913 | j_mayer | uint32_t tsrl; |
1083 | 8ecc7913 | j_mayer | uint32_t odr; |
1084 | 8ecc7913 | j_mayer | uint32_t ir; |
1085 | 8ecc7913 | j_mayer | uint32_t rr1; |
1086 | 8ecc7913 | j_mayer | uint32_t isr1h; |
1087 | 8ecc7913 | j_mayer | uint32_t isr1l; |
1088 | 8ecc7913 | j_mayer | }; |
1089 | 8ecc7913 | j_mayer | |
1090 | 8ecc7913 | j_mayer | static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr) |
1091 | 8ecc7913 | j_mayer | { |
1092 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
1093 | 8ecc7913 | j_mayer | |
1094 | 8ecc7913 | j_mayer | gpio = opaque; |
1095 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
1096 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
1097 | 8ecc7913 | j_mayer | #endif
|
1098 | 8ecc7913 | j_mayer | |
1099 | 8ecc7913 | j_mayer | return 0; |
1100 | 8ecc7913 | j_mayer | } |
1101 | 8ecc7913 | j_mayer | |
1102 | 8ecc7913 | j_mayer | static void ppc405_gpio_writeb (void *opaque, |
1103 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1104 | 8ecc7913 | j_mayer | { |
1105 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
1106 | 8ecc7913 | j_mayer | |
1107 | 8ecc7913 | j_mayer | gpio = opaque; |
1108 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
1109 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1110 | 8ecc7913 | j_mayer | #endif
|
1111 | 8ecc7913 | j_mayer | } |
1112 | 8ecc7913 | j_mayer | |
1113 | 8ecc7913 | j_mayer | static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr) |
1114 | 8ecc7913 | j_mayer | { |
1115 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
1116 | 8ecc7913 | j_mayer | |
1117 | 8ecc7913 | j_mayer | gpio = opaque; |
1118 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
1119 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
1120 | 8ecc7913 | j_mayer | #endif
|
1121 | 8ecc7913 | j_mayer | |
1122 | 8ecc7913 | j_mayer | return 0; |
1123 | 8ecc7913 | j_mayer | } |
1124 | 8ecc7913 | j_mayer | |
1125 | 8ecc7913 | j_mayer | static void ppc405_gpio_writew (void *opaque, |
1126 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1127 | 8ecc7913 | j_mayer | { |
1128 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
1129 | 8ecc7913 | j_mayer | |
1130 | 8ecc7913 | j_mayer | gpio = opaque; |
1131 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
1132 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1133 | 8ecc7913 | j_mayer | #endif
|
1134 | 8ecc7913 | j_mayer | } |
1135 | 8ecc7913 | j_mayer | |
1136 | 8ecc7913 | j_mayer | static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr) |
1137 | 8ecc7913 | j_mayer | { |
1138 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
1139 | 8ecc7913 | j_mayer | |
1140 | 8ecc7913 | j_mayer | gpio = opaque; |
1141 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
1142 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
1143 | 8ecc7913 | j_mayer | #endif
|
1144 | 8ecc7913 | j_mayer | |
1145 | 8ecc7913 | j_mayer | return 0; |
1146 | 8ecc7913 | j_mayer | } |
1147 | 8ecc7913 | j_mayer | |
1148 | 8ecc7913 | j_mayer | static void ppc405_gpio_writel (void *opaque, |
1149 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1150 | 8ecc7913 | j_mayer | { |
1151 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
1152 | 8ecc7913 | j_mayer | |
1153 | 8ecc7913 | j_mayer | gpio = opaque; |
1154 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
1155 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1156 | 8ecc7913 | j_mayer | #endif
|
1157 | 8ecc7913 | j_mayer | } |
1158 | 8ecc7913 | j_mayer | |
1159 | 8ecc7913 | j_mayer | static CPUReadMemoryFunc *ppc405_gpio_read[] = {
|
1160 | 8ecc7913 | j_mayer | &ppc405_gpio_readb, |
1161 | 8ecc7913 | j_mayer | &ppc405_gpio_readw, |
1162 | 8ecc7913 | j_mayer | &ppc405_gpio_readl, |
1163 | 8ecc7913 | j_mayer | }; |
1164 | 8ecc7913 | j_mayer | |
1165 | 8ecc7913 | j_mayer | static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
|
1166 | 8ecc7913 | j_mayer | &ppc405_gpio_writeb, |
1167 | 8ecc7913 | j_mayer | &ppc405_gpio_writew, |
1168 | 8ecc7913 | j_mayer | &ppc405_gpio_writel, |
1169 | 8ecc7913 | j_mayer | }; |
1170 | 8ecc7913 | j_mayer | |
1171 | 8ecc7913 | j_mayer | static void ppc405_gpio_reset (void *opaque) |
1172 | 8ecc7913 | j_mayer | { |
1173 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
1174 | 8ecc7913 | j_mayer | |
1175 | 8ecc7913 | j_mayer | gpio = opaque; |
1176 | 8ecc7913 | j_mayer | } |
1177 | 8ecc7913 | j_mayer | |
1178 | 9c02f1a2 | j_mayer | void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
1179 | 9c02f1a2 | j_mayer | target_phys_addr_t offset) |
1180 | 8ecc7913 | j_mayer | { |
1181 | 8ecc7913 | j_mayer | ppc405_gpio_t *gpio; |
1182 | 8ecc7913 | j_mayer | |
1183 | 8ecc7913 | j_mayer | gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
|
1184 | 8ecc7913 | j_mayer | if (gpio != NULL) { |
1185 | 9c02f1a2 | j_mayer | gpio->base = offset; |
1186 | 8ecc7913 | j_mayer | ppc405_gpio_reset(gpio); |
1187 | 8ecc7913 | j_mayer | qemu_register_reset(&ppc405_gpio_reset, gpio); |
1188 | 8ecc7913 | j_mayer | #ifdef DEBUG_GPIO
|
1189 | 9c02f1a2 | j_mayer | printf("%s: offset=" PADDRX "\n", __func__, offset); |
1190 | 8ecc7913 | j_mayer | #endif
|
1191 | 8ecc7913 | j_mayer | ppc4xx_mmio_register(env, mmio, offset, 0x038,
|
1192 | 8ecc7913 | j_mayer | ppc405_gpio_read, ppc405_gpio_write, gpio); |
1193 | 8ecc7913 | j_mayer | } |
1194 | 8ecc7913 | j_mayer | } |
1195 | 8ecc7913 | j_mayer | |
1196 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
1197 | 8ecc7913 | j_mayer | /* Serial ports */
|
1198 | 8ecc7913 | j_mayer | static CPUReadMemoryFunc *serial_mm_read[] = {
|
1199 | 8ecc7913 | j_mayer | &serial_mm_readb, |
1200 | 8ecc7913 | j_mayer | &serial_mm_readw, |
1201 | 8ecc7913 | j_mayer | &serial_mm_readl, |
1202 | 8ecc7913 | j_mayer | }; |
1203 | 8ecc7913 | j_mayer | |
1204 | 8ecc7913 | j_mayer | static CPUWriteMemoryFunc *serial_mm_write[] = {
|
1205 | 8ecc7913 | j_mayer | &serial_mm_writeb, |
1206 | 8ecc7913 | j_mayer | &serial_mm_writew, |
1207 | 8ecc7913 | j_mayer | &serial_mm_writel, |
1208 | 8ecc7913 | j_mayer | }; |
1209 | 8ecc7913 | j_mayer | |
1210 | 8ecc7913 | j_mayer | void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
1211 | 9c02f1a2 | j_mayer | target_phys_addr_t offset, qemu_irq irq, |
1212 | 8ecc7913 | j_mayer | CharDriverState *chr) |
1213 | 8ecc7913 | j_mayer | { |
1214 | 8ecc7913 | j_mayer | void *serial;
|
1215 | 8ecc7913 | j_mayer | |
1216 | 8ecc7913 | j_mayer | #ifdef DEBUG_SERIAL
|
1217 | 9c02f1a2 | j_mayer | printf("%s: offset=" PADDRX "\n", __func__, offset); |
1218 | 8ecc7913 | j_mayer | #endif
|
1219 | 9c02f1a2 | j_mayer | serial = serial_mm_init(offset, 0, irq, chr, 0); |
1220 | 8ecc7913 | j_mayer | ppc4xx_mmio_register(env, mmio, offset, 0x008,
|
1221 | 8ecc7913 | j_mayer | serial_mm_read, serial_mm_write, serial); |
1222 | 8ecc7913 | j_mayer | } |
1223 | 8ecc7913 | j_mayer | |
1224 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
1225 | 8ecc7913 | j_mayer | /* On Chip Memory */
|
1226 | 8ecc7913 | j_mayer | enum {
|
1227 | 8ecc7913 | j_mayer | OCM0_ISARC = 0x018,
|
1228 | 8ecc7913 | j_mayer | OCM0_ISACNTL = 0x019,
|
1229 | 8ecc7913 | j_mayer | OCM0_DSARC = 0x01A,
|
1230 | 8ecc7913 | j_mayer | OCM0_DSACNTL = 0x01B,
|
1231 | 8ecc7913 | j_mayer | }; |
1232 | 8ecc7913 | j_mayer | |
1233 | 8ecc7913 | j_mayer | typedef struct ppc405_ocm_t ppc405_ocm_t; |
1234 | 8ecc7913 | j_mayer | struct ppc405_ocm_t {
|
1235 | 8ecc7913 | j_mayer | target_ulong offset; |
1236 | 8ecc7913 | j_mayer | uint32_t isarc; |
1237 | 8ecc7913 | j_mayer | uint32_t isacntl; |
1238 | 8ecc7913 | j_mayer | uint32_t dsarc; |
1239 | 8ecc7913 | j_mayer | uint32_t dsacntl; |
1240 | 8ecc7913 | j_mayer | }; |
1241 | 8ecc7913 | j_mayer | |
1242 | 8ecc7913 | j_mayer | static void ocm_update_mappings (ppc405_ocm_t *ocm, |
1243 | 8ecc7913 | j_mayer | uint32_t isarc, uint32_t isacntl, |
1244 | 8ecc7913 | j_mayer | uint32_t dsarc, uint32_t dsacntl) |
1245 | 8ecc7913 | j_mayer | { |
1246 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
1247 | 8ecc7913 | j_mayer | printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n",
|
1248 | 8ecc7913 | j_mayer | isarc, isacntl, dsarc, dsacntl, |
1249 | 8ecc7913 | j_mayer | ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); |
1250 | 8ecc7913 | j_mayer | #endif
|
1251 | 8ecc7913 | j_mayer | if (ocm->isarc != isarc ||
|
1252 | 8ecc7913 | j_mayer | (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { |
1253 | 8ecc7913 | j_mayer | if (ocm->isacntl & 0x80000000) { |
1254 | 8ecc7913 | j_mayer | /* Unmap previously assigned memory region */
|
1255 | 8ecc7913 | j_mayer | printf("OCM unmap ISA %08x\n", ocm->isarc);
|
1256 | 8ecc7913 | j_mayer | cpu_register_physical_memory(ocm->isarc, 0x04000000,
|
1257 | 8ecc7913 | j_mayer | IO_MEM_UNASSIGNED); |
1258 | 8ecc7913 | j_mayer | } |
1259 | 8ecc7913 | j_mayer | if (isacntl & 0x80000000) { |
1260 | 8ecc7913 | j_mayer | /* Map new instruction memory region */
|
1261 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
1262 | 8ecc7913 | j_mayer | printf("OCM map ISA %08x\n", isarc);
|
1263 | 8ecc7913 | j_mayer | #endif
|
1264 | 8ecc7913 | j_mayer | cpu_register_physical_memory(isarc, 0x04000000,
|
1265 | 8ecc7913 | j_mayer | ocm->offset | IO_MEM_RAM); |
1266 | 8ecc7913 | j_mayer | } |
1267 | 8ecc7913 | j_mayer | } |
1268 | 8ecc7913 | j_mayer | if (ocm->dsarc != dsarc ||
|
1269 | 8ecc7913 | j_mayer | (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { |
1270 | 8ecc7913 | j_mayer | if (ocm->dsacntl & 0x80000000) { |
1271 | 8ecc7913 | j_mayer | /* Beware not to unmap the region we just mapped */
|
1272 | 8ecc7913 | j_mayer | if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { |
1273 | 8ecc7913 | j_mayer | /* Unmap previously assigned memory region */
|
1274 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
1275 | 8ecc7913 | j_mayer | printf("OCM unmap DSA %08x\n", ocm->dsarc);
|
1276 | 8ecc7913 | j_mayer | #endif
|
1277 | 8ecc7913 | j_mayer | cpu_register_physical_memory(ocm->dsarc, 0x04000000,
|
1278 | 8ecc7913 | j_mayer | IO_MEM_UNASSIGNED); |
1279 | 8ecc7913 | j_mayer | } |
1280 | 8ecc7913 | j_mayer | } |
1281 | 8ecc7913 | j_mayer | if (dsacntl & 0x80000000) { |
1282 | 8ecc7913 | j_mayer | /* Beware not to remap the region we just mapped */
|
1283 | 8ecc7913 | j_mayer | if (!(isacntl & 0x80000000) || dsarc != isarc) { |
1284 | 8ecc7913 | j_mayer | /* Map new data memory region */
|
1285 | 8ecc7913 | j_mayer | #ifdef DEBUG_OCM
|
1286 | 8ecc7913 | j_mayer | printf("OCM map DSA %08x\n", dsarc);
|
1287 | 8ecc7913 | j_mayer | #endif
|
1288 | 8ecc7913 | j_mayer | cpu_register_physical_memory(dsarc, 0x04000000,
|
1289 | 8ecc7913 | j_mayer | ocm->offset | IO_MEM_RAM); |
1290 | 8ecc7913 | j_mayer | } |
1291 | 8ecc7913 | j_mayer | } |
1292 | 8ecc7913 | j_mayer | } |
1293 | 8ecc7913 | j_mayer | } |
1294 | 8ecc7913 | j_mayer | |
1295 | 8ecc7913 | j_mayer | static target_ulong dcr_read_ocm (void *opaque, int dcrn) |
1296 | 8ecc7913 | j_mayer | { |
1297 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
1298 | 8ecc7913 | j_mayer | target_ulong ret; |
1299 | 8ecc7913 | j_mayer | |
1300 | 8ecc7913 | j_mayer | ocm = opaque; |
1301 | 8ecc7913 | j_mayer | switch (dcrn) {
|
1302 | 8ecc7913 | j_mayer | case OCM0_ISARC:
|
1303 | 8ecc7913 | j_mayer | ret = ocm->isarc; |
1304 | 8ecc7913 | j_mayer | break;
|
1305 | 8ecc7913 | j_mayer | case OCM0_ISACNTL:
|
1306 | 8ecc7913 | j_mayer | ret = ocm->isacntl; |
1307 | 8ecc7913 | j_mayer | break;
|
1308 | 8ecc7913 | j_mayer | case OCM0_DSARC:
|
1309 | 8ecc7913 | j_mayer | ret = ocm->dsarc; |
1310 | 8ecc7913 | j_mayer | break;
|
1311 | 8ecc7913 | j_mayer | case OCM0_DSACNTL:
|
1312 | 8ecc7913 | j_mayer | ret = ocm->dsacntl; |
1313 | 8ecc7913 | j_mayer | break;
|
1314 | 8ecc7913 | j_mayer | default:
|
1315 | 8ecc7913 | j_mayer | ret = 0;
|
1316 | 8ecc7913 | j_mayer | break;
|
1317 | 8ecc7913 | j_mayer | } |
1318 | 8ecc7913 | j_mayer | |
1319 | 8ecc7913 | j_mayer | return ret;
|
1320 | 8ecc7913 | j_mayer | } |
1321 | 8ecc7913 | j_mayer | |
1322 | 8ecc7913 | j_mayer | static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val) |
1323 | 8ecc7913 | j_mayer | { |
1324 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
1325 | 8ecc7913 | j_mayer | uint32_t isarc, dsarc, isacntl, dsacntl; |
1326 | 8ecc7913 | j_mayer | |
1327 | 8ecc7913 | j_mayer | ocm = opaque; |
1328 | 8ecc7913 | j_mayer | isarc = ocm->isarc; |
1329 | 8ecc7913 | j_mayer | dsarc = ocm->dsarc; |
1330 | 8ecc7913 | j_mayer | isacntl = ocm->isacntl; |
1331 | 8ecc7913 | j_mayer | dsacntl = ocm->dsacntl; |
1332 | 8ecc7913 | j_mayer | switch (dcrn) {
|
1333 | 8ecc7913 | j_mayer | case OCM0_ISARC:
|
1334 | 8ecc7913 | j_mayer | isarc = val & 0xFC000000;
|
1335 | 8ecc7913 | j_mayer | break;
|
1336 | 8ecc7913 | j_mayer | case OCM0_ISACNTL:
|
1337 | 8ecc7913 | j_mayer | isacntl = val & 0xC0000000;
|
1338 | 8ecc7913 | j_mayer | break;
|
1339 | 8ecc7913 | j_mayer | case OCM0_DSARC:
|
1340 | 8ecc7913 | j_mayer | isarc = val & 0xFC000000;
|
1341 | 8ecc7913 | j_mayer | break;
|
1342 | 8ecc7913 | j_mayer | case OCM0_DSACNTL:
|
1343 | 8ecc7913 | j_mayer | isacntl = val & 0xC0000000;
|
1344 | 8ecc7913 | j_mayer | break;
|
1345 | 8ecc7913 | j_mayer | } |
1346 | 8ecc7913 | j_mayer | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
1347 | 8ecc7913 | j_mayer | ocm->isarc = isarc; |
1348 | 8ecc7913 | j_mayer | ocm->dsarc = dsarc; |
1349 | 8ecc7913 | j_mayer | ocm->isacntl = isacntl; |
1350 | 8ecc7913 | j_mayer | ocm->dsacntl = dsacntl; |
1351 | 8ecc7913 | j_mayer | } |
1352 | 8ecc7913 | j_mayer | |
1353 | 8ecc7913 | j_mayer | static void ocm_reset (void *opaque) |
1354 | 8ecc7913 | j_mayer | { |
1355 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
1356 | 8ecc7913 | j_mayer | uint32_t isarc, dsarc, isacntl, dsacntl; |
1357 | 8ecc7913 | j_mayer | |
1358 | 8ecc7913 | j_mayer | ocm = opaque; |
1359 | 8ecc7913 | j_mayer | isarc = 0x00000000;
|
1360 | 8ecc7913 | j_mayer | isacntl = 0x00000000;
|
1361 | 8ecc7913 | j_mayer | dsarc = 0x00000000;
|
1362 | 8ecc7913 | j_mayer | dsacntl = 0x00000000;
|
1363 | 8ecc7913 | j_mayer | ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); |
1364 | 8ecc7913 | j_mayer | ocm->isarc = isarc; |
1365 | 8ecc7913 | j_mayer | ocm->dsarc = dsarc; |
1366 | 8ecc7913 | j_mayer | ocm->isacntl = isacntl; |
1367 | 8ecc7913 | j_mayer | ocm->dsacntl = dsacntl; |
1368 | 8ecc7913 | j_mayer | } |
1369 | 8ecc7913 | j_mayer | |
1370 | 8ecc7913 | j_mayer | void ppc405_ocm_init (CPUState *env, unsigned long offset) |
1371 | 8ecc7913 | j_mayer | { |
1372 | 8ecc7913 | j_mayer | ppc405_ocm_t *ocm; |
1373 | 8ecc7913 | j_mayer | |
1374 | 8ecc7913 | j_mayer | ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
|
1375 | 8ecc7913 | j_mayer | if (ocm != NULL) { |
1376 | 8ecc7913 | j_mayer | ocm->offset = offset; |
1377 | 8ecc7913 | j_mayer | ocm_reset(ocm); |
1378 | 8ecc7913 | j_mayer | qemu_register_reset(&ocm_reset, ocm); |
1379 | 8ecc7913 | j_mayer | ppc_dcr_register(env, OCM0_ISARC, |
1380 | 8ecc7913 | j_mayer | ocm, &dcr_read_ocm, &dcr_write_ocm); |
1381 | 8ecc7913 | j_mayer | ppc_dcr_register(env, OCM0_ISACNTL, |
1382 | 8ecc7913 | j_mayer | ocm, &dcr_read_ocm, &dcr_write_ocm); |
1383 | 8ecc7913 | j_mayer | ppc_dcr_register(env, OCM0_DSARC, |
1384 | 8ecc7913 | j_mayer | ocm, &dcr_read_ocm, &dcr_write_ocm); |
1385 | 8ecc7913 | j_mayer | ppc_dcr_register(env, OCM0_DSACNTL, |
1386 | 8ecc7913 | j_mayer | ocm, &dcr_read_ocm, &dcr_write_ocm); |
1387 | 8ecc7913 | j_mayer | } |
1388 | 8ecc7913 | j_mayer | } |
1389 | 8ecc7913 | j_mayer | |
1390 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
1391 | 8ecc7913 | j_mayer | /* I2C controller */
|
1392 | 8ecc7913 | j_mayer | typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; |
1393 | 8ecc7913 | j_mayer | struct ppc4xx_i2c_t {
|
1394 | 9c02f1a2 | j_mayer | target_phys_addr_t base; |
1395 | 9c02f1a2 | j_mayer | qemu_irq irq; |
1396 | 8ecc7913 | j_mayer | uint8_t mdata; |
1397 | 8ecc7913 | j_mayer | uint8_t lmadr; |
1398 | 8ecc7913 | j_mayer | uint8_t hmadr; |
1399 | 8ecc7913 | j_mayer | uint8_t cntl; |
1400 | 8ecc7913 | j_mayer | uint8_t mdcntl; |
1401 | 8ecc7913 | j_mayer | uint8_t sts; |
1402 | 8ecc7913 | j_mayer | uint8_t extsts; |
1403 | 8ecc7913 | j_mayer | uint8_t sdata; |
1404 | 8ecc7913 | j_mayer | uint8_t lsadr; |
1405 | 8ecc7913 | j_mayer | uint8_t hsadr; |
1406 | 8ecc7913 | j_mayer | uint8_t clkdiv; |
1407 | 8ecc7913 | j_mayer | uint8_t intrmsk; |
1408 | 8ecc7913 | j_mayer | uint8_t xfrcnt; |
1409 | 8ecc7913 | j_mayer | uint8_t xtcntlss; |
1410 | 8ecc7913 | j_mayer | uint8_t directcntl; |
1411 | 8ecc7913 | j_mayer | }; |
1412 | 8ecc7913 | j_mayer | |
1413 | 8ecc7913 | j_mayer | static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr) |
1414 | 8ecc7913 | j_mayer | { |
1415 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
1416 | 8ecc7913 | j_mayer | uint32_t ret; |
1417 | 8ecc7913 | j_mayer | |
1418 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1419 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
1420 | 8ecc7913 | j_mayer | #endif
|
1421 | 8ecc7913 | j_mayer | i2c = opaque; |
1422 | 8ecc7913 | j_mayer | switch (addr - i2c->base) {
|
1423 | 8ecc7913 | j_mayer | case 0x00: |
1424 | 8ecc7913 | j_mayer | // i2c_readbyte(&i2c->mdata);
|
1425 | 8ecc7913 | j_mayer | ret = i2c->mdata; |
1426 | 8ecc7913 | j_mayer | break;
|
1427 | 8ecc7913 | j_mayer | case 0x02: |
1428 | 8ecc7913 | j_mayer | ret = i2c->sdata; |
1429 | 8ecc7913 | j_mayer | break;
|
1430 | 8ecc7913 | j_mayer | case 0x04: |
1431 | 8ecc7913 | j_mayer | ret = i2c->lmadr; |
1432 | 8ecc7913 | j_mayer | break;
|
1433 | 8ecc7913 | j_mayer | case 0x05: |
1434 | 8ecc7913 | j_mayer | ret = i2c->hmadr; |
1435 | 8ecc7913 | j_mayer | break;
|
1436 | 8ecc7913 | j_mayer | case 0x06: |
1437 | 8ecc7913 | j_mayer | ret = i2c->cntl; |
1438 | 8ecc7913 | j_mayer | break;
|
1439 | 8ecc7913 | j_mayer | case 0x07: |
1440 | 8ecc7913 | j_mayer | ret = i2c->mdcntl; |
1441 | 8ecc7913 | j_mayer | break;
|
1442 | 8ecc7913 | j_mayer | case 0x08: |
1443 | 8ecc7913 | j_mayer | ret = i2c->sts; |
1444 | 8ecc7913 | j_mayer | break;
|
1445 | 8ecc7913 | j_mayer | case 0x09: |
1446 | 8ecc7913 | j_mayer | ret = i2c->extsts; |
1447 | 8ecc7913 | j_mayer | break;
|
1448 | 8ecc7913 | j_mayer | case 0x0A: |
1449 | 8ecc7913 | j_mayer | ret = i2c->lsadr; |
1450 | 8ecc7913 | j_mayer | break;
|
1451 | 8ecc7913 | j_mayer | case 0x0B: |
1452 | 8ecc7913 | j_mayer | ret = i2c->hsadr; |
1453 | 8ecc7913 | j_mayer | break;
|
1454 | 8ecc7913 | j_mayer | case 0x0C: |
1455 | 8ecc7913 | j_mayer | ret = i2c->clkdiv; |
1456 | 8ecc7913 | j_mayer | break;
|
1457 | 8ecc7913 | j_mayer | case 0x0D: |
1458 | 8ecc7913 | j_mayer | ret = i2c->intrmsk; |
1459 | 8ecc7913 | j_mayer | break;
|
1460 | 8ecc7913 | j_mayer | case 0x0E: |
1461 | 8ecc7913 | j_mayer | ret = i2c->xfrcnt; |
1462 | 8ecc7913 | j_mayer | break;
|
1463 | 8ecc7913 | j_mayer | case 0x0F: |
1464 | 8ecc7913 | j_mayer | ret = i2c->xtcntlss; |
1465 | 8ecc7913 | j_mayer | break;
|
1466 | 8ecc7913 | j_mayer | case 0x10: |
1467 | 8ecc7913 | j_mayer | ret = i2c->directcntl; |
1468 | 8ecc7913 | j_mayer | break;
|
1469 | 8ecc7913 | j_mayer | default:
|
1470 | 8ecc7913 | j_mayer | ret = 0x00;
|
1471 | 8ecc7913 | j_mayer | break;
|
1472 | 8ecc7913 | j_mayer | } |
1473 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1474 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX " %02x\n", __func__, addr, ret); |
1475 | 8ecc7913 | j_mayer | #endif
|
1476 | 8ecc7913 | j_mayer | |
1477 | 8ecc7913 | j_mayer | return ret;
|
1478 | 8ecc7913 | j_mayer | } |
1479 | 8ecc7913 | j_mayer | |
1480 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_writeb (void *opaque, |
1481 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1482 | 8ecc7913 | j_mayer | { |
1483 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
1484 | 8ecc7913 | j_mayer | |
1485 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1486 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1487 | 8ecc7913 | j_mayer | #endif
|
1488 | 8ecc7913 | j_mayer | i2c = opaque; |
1489 | 8ecc7913 | j_mayer | switch (addr - i2c->base) {
|
1490 | 8ecc7913 | j_mayer | case 0x00: |
1491 | 8ecc7913 | j_mayer | i2c->mdata = value; |
1492 | 8ecc7913 | j_mayer | // i2c_sendbyte(&i2c->mdata);
|
1493 | 8ecc7913 | j_mayer | break;
|
1494 | 8ecc7913 | j_mayer | case 0x02: |
1495 | 8ecc7913 | j_mayer | i2c->sdata = value; |
1496 | 8ecc7913 | j_mayer | break;
|
1497 | 8ecc7913 | j_mayer | case 0x04: |
1498 | 8ecc7913 | j_mayer | i2c->lmadr = value; |
1499 | 8ecc7913 | j_mayer | break;
|
1500 | 8ecc7913 | j_mayer | case 0x05: |
1501 | 8ecc7913 | j_mayer | i2c->hmadr = value; |
1502 | 8ecc7913 | j_mayer | break;
|
1503 | 8ecc7913 | j_mayer | case 0x06: |
1504 | 8ecc7913 | j_mayer | i2c->cntl = value; |
1505 | 8ecc7913 | j_mayer | break;
|
1506 | 8ecc7913 | j_mayer | case 0x07: |
1507 | 8ecc7913 | j_mayer | i2c->mdcntl = value & 0xDF;
|
1508 | 8ecc7913 | j_mayer | break;
|
1509 | 8ecc7913 | j_mayer | case 0x08: |
1510 | 8ecc7913 | j_mayer | i2c->sts &= ~(value & 0x0A);
|
1511 | 8ecc7913 | j_mayer | break;
|
1512 | 8ecc7913 | j_mayer | case 0x09: |
1513 | 8ecc7913 | j_mayer | i2c->extsts &= ~(value & 0x8F);
|
1514 | 8ecc7913 | j_mayer | break;
|
1515 | 8ecc7913 | j_mayer | case 0x0A: |
1516 | 8ecc7913 | j_mayer | i2c->lsadr = value; |
1517 | 8ecc7913 | j_mayer | break;
|
1518 | 8ecc7913 | j_mayer | case 0x0B: |
1519 | 8ecc7913 | j_mayer | i2c->hsadr = value; |
1520 | 8ecc7913 | j_mayer | break;
|
1521 | 8ecc7913 | j_mayer | case 0x0C: |
1522 | 8ecc7913 | j_mayer | i2c->clkdiv = value; |
1523 | 8ecc7913 | j_mayer | break;
|
1524 | 8ecc7913 | j_mayer | case 0x0D: |
1525 | 8ecc7913 | j_mayer | i2c->intrmsk = value; |
1526 | 8ecc7913 | j_mayer | break;
|
1527 | 8ecc7913 | j_mayer | case 0x0E: |
1528 | 8ecc7913 | j_mayer | i2c->xfrcnt = value & 0x77;
|
1529 | 8ecc7913 | j_mayer | break;
|
1530 | 8ecc7913 | j_mayer | case 0x0F: |
1531 | 8ecc7913 | j_mayer | i2c->xtcntlss = value; |
1532 | 8ecc7913 | j_mayer | break;
|
1533 | 8ecc7913 | j_mayer | case 0x10: |
1534 | 8ecc7913 | j_mayer | i2c->directcntl = value & 0x7;
|
1535 | 8ecc7913 | j_mayer | break;
|
1536 | 8ecc7913 | j_mayer | } |
1537 | 8ecc7913 | j_mayer | } |
1538 | 8ecc7913 | j_mayer | |
1539 | 8ecc7913 | j_mayer | static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr) |
1540 | 8ecc7913 | j_mayer | { |
1541 | 8ecc7913 | j_mayer | uint32_t ret; |
1542 | 8ecc7913 | j_mayer | |
1543 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1544 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
1545 | 8ecc7913 | j_mayer | #endif
|
1546 | 8ecc7913 | j_mayer | ret = ppc4xx_i2c_readb(opaque, addr) << 8;
|
1547 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 1);
|
1548 | 8ecc7913 | j_mayer | |
1549 | 8ecc7913 | j_mayer | return ret;
|
1550 | 8ecc7913 | j_mayer | } |
1551 | 8ecc7913 | j_mayer | |
1552 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_writew (void *opaque, |
1553 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1554 | 8ecc7913 | j_mayer | { |
1555 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1556 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1557 | 8ecc7913 | j_mayer | #endif
|
1558 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr, value >> 8);
|
1559 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 1, value);
|
1560 | 8ecc7913 | j_mayer | } |
1561 | 8ecc7913 | j_mayer | |
1562 | 8ecc7913 | j_mayer | static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr) |
1563 | 8ecc7913 | j_mayer | { |
1564 | 8ecc7913 | j_mayer | uint32_t ret; |
1565 | 8ecc7913 | j_mayer | |
1566 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1567 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
1568 | 8ecc7913 | j_mayer | #endif
|
1569 | 8ecc7913 | j_mayer | ret = ppc4xx_i2c_readb(opaque, addr) << 24;
|
1570 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16; |
1571 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8; |
1572 | 8ecc7913 | j_mayer | ret |= ppc4xx_i2c_readb(opaque, addr + 3);
|
1573 | 8ecc7913 | j_mayer | |
1574 | 8ecc7913 | j_mayer | return ret;
|
1575 | 8ecc7913 | j_mayer | } |
1576 | 8ecc7913 | j_mayer | |
1577 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_writel (void *opaque, |
1578 | 8ecc7913 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1579 | 8ecc7913 | j_mayer | { |
1580 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1581 | 8ecc7913 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1582 | 8ecc7913 | j_mayer | #endif
|
1583 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr, value >> 24);
|
1584 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16); |
1585 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8); |
1586 | 8ecc7913 | j_mayer | ppc4xx_i2c_writeb(opaque, addr + 3, value);
|
1587 | 8ecc7913 | j_mayer | } |
1588 | 8ecc7913 | j_mayer | |
1589 | 8ecc7913 | j_mayer | static CPUReadMemoryFunc *i2c_read[] = {
|
1590 | 8ecc7913 | j_mayer | &ppc4xx_i2c_readb, |
1591 | 8ecc7913 | j_mayer | &ppc4xx_i2c_readw, |
1592 | 8ecc7913 | j_mayer | &ppc4xx_i2c_readl, |
1593 | 8ecc7913 | j_mayer | }; |
1594 | 8ecc7913 | j_mayer | |
1595 | 8ecc7913 | j_mayer | static CPUWriteMemoryFunc *i2c_write[] = {
|
1596 | 8ecc7913 | j_mayer | &ppc4xx_i2c_writeb, |
1597 | 8ecc7913 | j_mayer | &ppc4xx_i2c_writew, |
1598 | 8ecc7913 | j_mayer | &ppc4xx_i2c_writel, |
1599 | 8ecc7913 | j_mayer | }; |
1600 | 8ecc7913 | j_mayer | |
1601 | 8ecc7913 | j_mayer | static void ppc4xx_i2c_reset (void *opaque) |
1602 | 8ecc7913 | j_mayer | { |
1603 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
1604 | 8ecc7913 | j_mayer | |
1605 | 8ecc7913 | j_mayer | i2c = opaque; |
1606 | 8ecc7913 | j_mayer | i2c->mdata = 0x00;
|
1607 | 8ecc7913 | j_mayer | i2c->sdata = 0x00;
|
1608 | 8ecc7913 | j_mayer | i2c->cntl = 0x00;
|
1609 | 8ecc7913 | j_mayer | i2c->mdcntl = 0x00;
|
1610 | 8ecc7913 | j_mayer | i2c->sts = 0x00;
|
1611 | 8ecc7913 | j_mayer | i2c->extsts = 0x00;
|
1612 | 8ecc7913 | j_mayer | i2c->clkdiv = 0x00;
|
1613 | 8ecc7913 | j_mayer | i2c->xfrcnt = 0x00;
|
1614 | 8ecc7913 | j_mayer | i2c->directcntl = 0x0F;
|
1615 | 8ecc7913 | j_mayer | } |
1616 | 8ecc7913 | j_mayer | |
1617 | 9c02f1a2 | j_mayer | void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
1618 | 9c02f1a2 | j_mayer | target_phys_addr_t offset, qemu_irq irq) |
1619 | 8ecc7913 | j_mayer | { |
1620 | 8ecc7913 | j_mayer | ppc4xx_i2c_t *i2c; |
1621 | 8ecc7913 | j_mayer | |
1622 | 8ecc7913 | j_mayer | i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
|
1623 | 8ecc7913 | j_mayer | if (i2c != NULL) { |
1624 | 9c02f1a2 | j_mayer | i2c->base = offset; |
1625 | 9c02f1a2 | j_mayer | i2c->irq = irq; |
1626 | 8ecc7913 | j_mayer | ppc4xx_i2c_reset(i2c); |
1627 | 8ecc7913 | j_mayer | #ifdef DEBUG_I2C
|
1628 | 9c02f1a2 | j_mayer | printf("%s: offset=" PADDRX "\n", __func__, offset); |
1629 | 8ecc7913 | j_mayer | #endif
|
1630 | 8ecc7913 | j_mayer | ppc4xx_mmio_register(env, mmio, offset, 0x011,
|
1631 | 8ecc7913 | j_mayer | i2c_read, i2c_write, i2c); |
1632 | 8ecc7913 | j_mayer | qemu_register_reset(ppc4xx_i2c_reset, i2c); |
1633 | 8ecc7913 | j_mayer | } |
1634 | 8ecc7913 | j_mayer | } |
1635 | 8ecc7913 | j_mayer | |
1636 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
1637 | 9c02f1a2 | j_mayer | /* General purpose timers */
|
1638 | 9c02f1a2 | j_mayer | typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; |
1639 | 9c02f1a2 | j_mayer | struct ppc4xx_gpt_t {
|
1640 | 9c02f1a2 | j_mayer | target_phys_addr_t base; |
1641 | 9c02f1a2 | j_mayer | int64_t tb_offset; |
1642 | 9c02f1a2 | j_mayer | uint32_t tb_freq; |
1643 | 9c02f1a2 | j_mayer | struct QEMUTimer *timer;
|
1644 | 9c02f1a2 | j_mayer | qemu_irq irqs[5];
|
1645 | 9c02f1a2 | j_mayer | uint32_t oe; |
1646 | 9c02f1a2 | j_mayer | uint32_t ol; |
1647 | 9c02f1a2 | j_mayer | uint32_t im; |
1648 | 9c02f1a2 | j_mayer | uint32_t is; |
1649 | 9c02f1a2 | j_mayer | uint32_t ie; |
1650 | 9c02f1a2 | j_mayer | uint32_t comp[5];
|
1651 | 9c02f1a2 | j_mayer | uint32_t mask[5];
|
1652 | 9c02f1a2 | j_mayer | }; |
1653 | 9c02f1a2 | j_mayer | |
1654 | 9c02f1a2 | j_mayer | static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr) |
1655 | 9c02f1a2 | j_mayer | { |
1656 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
1657 | 9c02f1a2 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
1658 | 9c02f1a2 | j_mayer | #endif
|
1659 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
1660 | 9c02f1a2 | j_mayer | return -1; |
1661 | 9c02f1a2 | j_mayer | } |
1662 | 9c02f1a2 | j_mayer | |
1663 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_writeb (void *opaque, |
1664 | 9c02f1a2 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1665 | 9c02f1a2 | j_mayer | { |
1666 | 9c02f1a2 | j_mayer | #ifdef DEBUG_I2C
|
1667 | 9c02f1a2 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1668 | 9c02f1a2 | j_mayer | #endif
|
1669 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
1670 | 9c02f1a2 | j_mayer | } |
1671 | 9c02f1a2 | j_mayer | |
1672 | 9c02f1a2 | j_mayer | static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr) |
1673 | 9c02f1a2 | j_mayer | { |
1674 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
1675 | 9c02f1a2 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
1676 | 9c02f1a2 | j_mayer | #endif
|
1677 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
1678 | 9c02f1a2 | j_mayer | return -1; |
1679 | 9c02f1a2 | j_mayer | } |
1680 | 9c02f1a2 | j_mayer | |
1681 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_writew (void *opaque, |
1682 | 9c02f1a2 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1683 | 9c02f1a2 | j_mayer | { |
1684 | 9c02f1a2 | j_mayer | #ifdef DEBUG_I2C
|
1685 | 9c02f1a2 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1686 | 9c02f1a2 | j_mayer | #endif
|
1687 | 9c02f1a2 | j_mayer | /* XXX: generate a bus fault */
|
1688 | 9c02f1a2 | j_mayer | } |
1689 | 9c02f1a2 | j_mayer | |
1690 | 9c02f1a2 | j_mayer | static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) |
1691 | 9c02f1a2 | j_mayer | { |
1692 | 9c02f1a2 | j_mayer | /* XXX: TODO */
|
1693 | 9c02f1a2 | j_mayer | return 0; |
1694 | 9c02f1a2 | j_mayer | } |
1695 | 9c02f1a2 | j_mayer | |
1696 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) |
1697 | 9c02f1a2 | j_mayer | { |
1698 | 9c02f1a2 | j_mayer | /* XXX: TODO */
|
1699 | 9c02f1a2 | j_mayer | } |
1700 | 9c02f1a2 | j_mayer | |
1701 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) |
1702 | 9c02f1a2 | j_mayer | { |
1703 | 9c02f1a2 | j_mayer | uint32_t mask; |
1704 | 9c02f1a2 | j_mayer | int i;
|
1705 | 9c02f1a2 | j_mayer | |
1706 | 9c02f1a2 | j_mayer | mask = 0x80000000;
|
1707 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) { |
1708 | 9c02f1a2 | j_mayer | if (gpt->oe & mask) {
|
1709 | 9c02f1a2 | j_mayer | /* Output is enabled */
|
1710 | 9c02f1a2 | j_mayer | if (ppc4xx_gpt_compare(gpt, i)) {
|
1711 | 9c02f1a2 | j_mayer | /* Comparison is OK */
|
1712 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); |
1713 | 9c02f1a2 | j_mayer | } else {
|
1714 | 9c02f1a2 | j_mayer | /* Comparison is KO */
|
1715 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); |
1716 | 9c02f1a2 | j_mayer | } |
1717 | 9c02f1a2 | j_mayer | } |
1718 | 9c02f1a2 | j_mayer | mask = mask >> 1;
|
1719 | 9c02f1a2 | j_mayer | } |
1720 | 9c02f1a2 | j_mayer | } |
1721 | 9c02f1a2 | j_mayer | |
1722 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) |
1723 | 9c02f1a2 | j_mayer | { |
1724 | 9c02f1a2 | j_mayer | uint32_t mask; |
1725 | 9c02f1a2 | j_mayer | int i;
|
1726 | 9c02f1a2 | j_mayer | |
1727 | 9c02f1a2 | j_mayer | mask = 0x00008000;
|
1728 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) { |
1729 | 9c02f1a2 | j_mayer | if (gpt->is & gpt->im & mask)
|
1730 | 9c02f1a2 | j_mayer | qemu_irq_raise(gpt->irqs[i]); |
1731 | 9c02f1a2 | j_mayer | else
|
1732 | 9c02f1a2 | j_mayer | qemu_irq_lower(gpt->irqs[i]); |
1733 | 9c02f1a2 | j_mayer | mask = mask >> 1;
|
1734 | 9c02f1a2 | j_mayer | } |
1735 | 9c02f1a2 | j_mayer | } |
1736 | 9c02f1a2 | j_mayer | |
1737 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) |
1738 | 9c02f1a2 | j_mayer | { |
1739 | 9c02f1a2 | j_mayer | /* XXX: TODO */
|
1740 | 9c02f1a2 | j_mayer | } |
1741 | 9c02f1a2 | j_mayer | |
1742 | 9c02f1a2 | j_mayer | static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) |
1743 | 9c02f1a2 | j_mayer | { |
1744 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
1745 | 9c02f1a2 | j_mayer | uint32_t ret; |
1746 | 9c02f1a2 | j_mayer | int idx;
|
1747 | 9c02f1a2 | j_mayer | |
1748 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
1749 | 9c02f1a2 | j_mayer | printf("%s: addr " PADDRX "\n", __func__, addr); |
1750 | 9c02f1a2 | j_mayer | #endif
|
1751 | 9c02f1a2 | j_mayer | gpt = opaque; |
1752 | 9c02f1a2 | j_mayer | switch (addr - gpt->base) {
|
1753 | 9c02f1a2 | j_mayer | case 0x00: |
1754 | 9c02f1a2 | j_mayer | /* Time base counter */
|
1755 | 9c02f1a2 | j_mayer | ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, |
1756 | 9c02f1a2 | j_mayer | gpt->tb_freq, ticks_per_sec); |
1757 | 9c02f1a2 | j_mayer | break;
|
1758 | 9c02f1a2 | j_mayer | case 0x10: |
1759 | 9c02f1a2 | j_mayer | /* Output enable */
|
1760 | 9c02f1a2 | j_mayer | ret = gpt->oe; |
1761 | 9c02f1a2 | j_mayer | break;
|
1762 | 9c02f1a2 | j_mayer | case 0x14: |
1763 | 9c02f1a2 | j_mayer | /* Output level */
|
1764 | 9c02f1a2 | j_mayer | ret = gpt->ol; |
1765 | 9c02f1a2 | j_mayer | break;
|
1766 | 9c02f1a2 | j_mayer | case 0x18: |
1767 | 9c02f1a2 | j_mayer | /* Interrupt mask */
|
1768 | 9c02f1a2 | j_mayer | ret = gpt->im; |
1769 | 9c02f1a2 | j_mayer | break;
|
1770 | 9c02f1a2 | j_mayer | case 0x1C: |
1771 | 9c02f1a2 | j_mayer | case 0x20: |
1772 | 9c02f1a2 | j_mayer | /* Interrupt status */
|
1773 | 9c02f1a2 | j_mayer | ret = gpt->is; |
1774 | 9c02f1a2 | j_mayer | break;
|
1775 | 9c02f1a2 | j_mayer | case 0x24: |
1776 | 9c02f1a2 | j_mayer | /* Interrupt enable */
|
1777 | 9c02f1a2 | j_mayer | ret = gpt->ie; |
1778 | 9c02f1a2 | j_mayer | break;
|
1779 | 9c02f1a2 | j_mayer | case 0x80 ... 0x90: |
1780 | 9c02f1a2 | j_mayer | /* Compare timer */
|
1781 | 9c02f1a2 | j_mayer | idx = ((addr - gpt->base) - 0x80) >> 2; |
1782 | 9c02f1a2 | j_mayer | ret = gpt->comp[idx]; |
1783 | 9c02f1a2 | j_mayer | break;
|
1784 | 9c02f1a2 | j_mayer | case 0xC0 ... 0xD0: |
1785 | 9c02f1a2 | j_mayer | /* Compare mask */
|
1786 | 9c02f1a2 | j_mayer | idx = ((addr - gpt->base) - 0xC0) >> 2; |
1787 | 9c02f1a2 | j_mayer | ret = gpt->mask[idx]; |
1788 | 9c02f1a2 | j_mayer | break;
|
1789 | 9c02f1a2 | j_mayer | default:
|
1790 | 9c02f1a2 | j_mayer | ret = -1;
|
1791 | 9c02f1a2 | j_mayer | break;
|
1792 | 9c02f1a2 | j_mayer | } |
1793 | 9c02f1a2 | j_mayer | |
1794 | 9c02f1a2 | j_mayer | return ret;
|
1795 | 9c02f1a2 | j_mayer | } |
1796 | 9c02f1a2 | j_mayer | |
1797 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_writel (void *opaque, |
1798 | 9c02f1a2 | j_mayer | target_phys_addr_t addr, uint32_t value) |
1799 | 9c02f1a2 | j_mayer | { |
1800 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
1801 | 9c02f1a2 | j_mayer | int idx;
|
1802 | 9c02f1a2 | j_mayer | |
1803 | 9c02f1a2 | j_mayer | #ifdef DEBUG_I2C
|
1804 | 9c02f1a2 | j_mayer | printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value); |
1805 | 9c02f1a2 | j_mayer | #endif
|
1806 | 9c02f1a2 | j_mayer | gpt = opaque; |
1807 | 9c02f1a2 | j_mayer | switch (addr - gpt->base) {
|
1808 | 9c02f1a2 | j_mayer | case 0x00: |
1809 | 9c02f1a2 | j_mayer | /* Time base counter */
|
1810 | 9c02f1a2 | j_mayer | gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq) |
1811 | 9c02f1a2 | j_mayer | - qemu_get_clock(vm_clock); |
1812 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
1813 | 9c02f1a2 | j_mayer | break;
|
1814 | 9c02f1a2 | j_mayer | case 0x10: |
1815 | 9c02f1a2 | j_mayer | /* Output enable */
|
1816 | 9c02f1a2 | j_mayer | gpt->oe = value & 0xF8000000;
|
1817 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_outputs(gpt); |
1818 | 9c02f1a2 | j_mayer | break;
|
1819 | 9c02f1a2 | j_mayer | case 0x14: |
1820 | 9c02f1a2 | j_mayer | /* Output level */
|
1821 | 9c02f1a2 | j_mayer | gpt->ol = value & 0xF8000000;
|
1822 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_outputs(gpt); |
1823 | 9c02f1a2 | j_mayer | break;
|
1824 | 9c02f1a2 | j_mayer | case 0x18: |
1825 | 9c02f1a2 | j_mayer | /* Interrupt mask */
|
1826 | 9c02f1a2 | j_mayer | gpt->im = value & 0x0000F800;
|
1827 | 9c02f1a2 | j_mayer | break;
|
1828 | 9c02f1a2 | j_mayer | case 0x1C: |
1829 | 9c02f1a2 | j_mayer | /* Interrupt status set */
|
1830 | 9c02f1a2 | j_mayer | gpt->is |= value & 0x0000F800;
|
1831 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
1832 | 9c02f1a2 | j_mayer | break;
|
1833 | 9c02f1a2 | j_mayer | case 0x20: |
1834 | 9c02f1a2 | j_mayer | /* Interrupt status clear */
|
1835 | 9c02f1a2 | j_mayer | gpt->is &= ~(value & 0x0000F800);
|
1836 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
1837 | 9c02f1a2 | j_mayer | break;
|
1838 | 9c02f1a2 | j_mayer | case 0x24: |
1839 | 9c02f1a2 | j_mayer | /* Interrupt enable */
|
1840 | 9c02f1a2 | j_mayer | gpt->ie = value & 0x0000F800;
|
1841 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
1842 | 9c02f1a2 | j_mayer | break;
|
1843 | 9c02f1a2 | j_mayer | case 0x80 ... 0x90: |
1844 | 9c02f1a2 | j_mayer | /* Compare timer */
|
1845 | 9c02f1a2 | j_mayer | idx = ((addr - gpt->base) - 0x80) >> 2; |
1846 | 9c02f1a2 | j_mayer | gpt->comp[idx] = value & 0xF8000000;
|
1847 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
1848 | 9c02f1a2 | j_mayer | break;
|
1849 | 9c02f1a2 | j_mayer | case 0xC0 ... 0xD0: |
1850 | 9c02f1a2 | j_mayer | /* Compare mask */
|
1851 | 9c02f1a2 | j_mayer | idx = ((addr - gpt->base) - 0xC0) >> 2; |
1852 | 9c02f1a2 | j_mayer | gpt->mask[idx] = value & 0xF8000000;
|
1853 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
1854 | 9c02f1a2 | j_mayer | break;
|
1855 | 9c02f1a2 | j_mayer | } |
1856 | 9c02f1a2 | j_mayer | } |
1857 | 9c02f1a2 | j_mayer | |
1858 | 9c02f1a2 | j_mayer | static CPUReadMemoryFunc *gpt_read[] = {
|
1859 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_readb, |
1860 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_readw, |
1861 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_readl, |
1862 | 9c02f1a2 | j_mayer | }; |
1863 | 9c02f1a2 | j_mayer | |
1864 | 9c02f1a2 | j_mayer | static CPUWriteMemoryFunc *gpt_write[] = {
|
1865 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_writeb, |
1866 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_writew, |
1867 | 9c02f1a2 | j_mayer | &ppc4xx_gpt_writel, |
1868 | 9c02f1a2 | j_mayer | }; |
1869 | 9c02f1a2 | j_mayer | |
1870 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_cb (void *opaque) |
1871 | 9c02f1a2 | j_mayer | { |
1872 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
1873 | 9c02f1a2 | j_mayer | |
1874 | 9c02f1a2 | j_mayer | gpt = opaque; |
1875 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_irqs(gpt); |
1876 | 9c02f1a2 | j_mayer | ppc4xx_gpt_set_outputs(gpt); |
1877 | 9c02f1a2 | j_mayer | ppc4xx_gpt_compute_timer(gpt); |
1878 | 9c02f1a2 | j_mayer | } |
1879 | 9c02f1a2 | j_mayer | |
1880 | 9c02f1a2 | j_mayer | static void ppc4xx_gpt_reset (void *opaque) |
1881 | 9c02f1a2 | j_mayer | { |
1882 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
1883 | 9c02f1a2 | j_mayer | int i;
|
1884 | 9c02f1a2 | j_mayer | |
1885 | 9c02f1a2 | j_mayer | gpt = opaque; |
1886 | 9c02f1a2 | j_mayer | qemu_del_timer(gpt->timer); |
1887 | 9c02f1a2 | j_mayer | gpt->oe = 0x00000000;
|
1888 | 9c02f1a2 | j_mayer | gpt->ol = 0x00000000;
|
1889 | 9c02f1a2 | j_mayer | gpt->im = 0x00000000;
|
1890 | 9c02f1a2 | j_mayer | gpt->is = 0x00000000;
|
1891 | 9c02f1a2 | j_mayer | gpt->ie = 0x00000000;
|
1892 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) { |
1893 | 9c02f1a2 | j_mayer | gpt->comp[i] = 0x00000000;
|
1894 | 9c02f1a2 | j_mayer | gpt->mask[i] = 0x00000000;
|
1895 | 9c02f1a2 | j_mayer | } |
1896 | 9c02f1a2 | j_mayer | } |
1897 | 9c02f1a2 | j_mayer | |
1898 | 9c02f1a2 | j_mayer | void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
|
1899 | 9c02f1a2 | j_mayer | target_phys_addr_t offset, qemu_irq irqs[5])
|
1900 | 9c02f1a2 | j_mayer | { |
1901 | 9c02f1a2 | j_mayer | ppc4xx_gpt_t *gpt; |
1902 | 9c02f1a2 | j_mayer | int i;
|
1903 | 9c02f1a2 | j_mayer | |
1904 | 9c02f1a2 | j_mayer | gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
|
1905 | 9c02f1a2 | j_mayer | if (gpt != NULL) { |
1906 | 9c02f1a2 | j_mayer | gpt->base = offset; |
1907 | 9c02f1a2 | j_mayer | for (i = 0; i < 5; i++) |
1908 | 9c02f1a2 | j_mayer | gpt->irqs[i] = irqs[i]; |
1909 | 9c02f1a2 | j_mayer | gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); |
1910 | 9c02f1a2 | j_mayer | ppc4xx_gpt_reset(gpt); |
1911 | 9c02f1a2 | j_mayer | #ifdef DEBUG_GPT
|
1912 | 9c02f1a2 | j_mayer | printf("%s: offset=" PADDRX "\n", __func__, offset); |
1913 | 9c02f1a2 | j_mayer | #endif
|
1914 | 9c02f1a2 | j_mayer | ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
|
1915 | 9c02f1a2 | j_mayer | gpt_read, gpt_write, gpt); |
1916 | 9c02f1a2 | j_mayer | qemu_register_reset(ppc4xx_gpt_reset, gpt); |
1917 | 9c02f1a2 | j_mayer | } |
1918 | 9c02f1a2 | j_mayer | } |
1919 | 9c02f1a2 | j_mayer | |
1920 | 9c02f1a2 | j_mayer | /*****************************************************************************/
|
1921 | 9c02f1a2 | j_mayer | /* MAL */
|
1922 | 9c02f1a2 | j_mayer | enum {
|
1923 | 9c02f1a2 | j_mayer | MAL0_CFG = 0x180,
|
1924 | 9c02f1a2 | j_mayer | MAL0_ESR = 0x181,
|
1925 | 9c02f1a2 | j_mayer | MAL0_IER = 0x182,
|
1926 | 9c02f1a2 | j_mayer | MAL0_TXCASR = 0x184,
|
1927 | 9c02f1a2 | j_mayer | MAL0_TXCARR = 0x185,
|
1928 | 9c02f1a2 | j_mayer | MAL0_TXEOBISR = 0x186,
|
1929 | 9c02f1a2 | j_mayer | MAL0_TXDEIR = 0x187,
|
1930 | 9c02f1a2 | j_mayer | MAL0_RXCASR = 0x190,
|
1931 | 9c02f1a2 | j_mayer | MAL0_RXCARR = 0x191,
|
1932 | 9c02f1a2 | j_mayer | MAL0_RXEOBISR = 0x192,
|
1933 | 9c02f1a2 | j_mayer | MAL0_RXDEIR = 0x193,
|
1934 | 9c02f1a2 | j_mayer | MAL0_TXCTP0R = 0x1A0,
|
1935 | 9c02f1a2 | j_mayer | MAL0_TXCTP1R = 0x1A1,
|
1936 | 9c02f1a2 | j_mayer | MAL0_TXCTP2R = 0x1A2,
|
1937 | 9c02f1a2 | j_mayer | MAL0_TXCTP3R = 0x1A3,
|
1938 | 9c02f1a2 | j_mayer | MAL0_RXCTP0R = 0x1C0,
|
1939 | 9c02f1a2 | j_mayer | MAL0_RXCTP1R = 0x1C1,
|
1940 | 9c02f1a2 | j_mayer | MAL0_RCBS0 = 0x1E0,
|
1941 | 9c02f1a2 | j_mayer | MAL0_RCBS1 = 0x1E1,
|
1942 | 9c02f1a2 | j_mayer | }; |
1943 | 9c02f1a2 | j_mayer | |
1944 | 9c02f1a2 | j_mayer | typedef struct ppc40x_mal_t ppc40x_mal_t; |
1945 | 9c02f1a2 | j_mayer | struct ppc40x_mal_t {
|
1946 | 9c02f1a2 | j_mayer | qemu_irq irqs[4];
|
1947 | 9c02f1a2 | j_mayer | uint32_t cfg; |
1948 | 9c02f1a2 | j_mayer | uint32_t esr; |
1949 | 9c02f1a2 | j_mayer | uint32_t ier; |
1950 | 9c02f1a2 | j_mayer | uint32_t txcasr; |
1951 | 9c02f1a2 | j_mayer | uint32_t txcarr; |
1952 | 9c02f1a2 | j_mayer | uint32_t txeobisr; |
1953 | 9c02f1a2 | j_mayer | uint32_t txdeir; |
1954 | 9c02f1a2 | j_mayer | uint32_t rxcasr; |
1955 | 9c02f1a2 | j_mayer | uint32_t rxcarr; |
1956 | 9c02f1a2 | j_mayer | uint32_t rxeobisr; |
1957 | 9c02f1a2 | j_mayer | uint32_t rxdeir; |
1958 | 9c02f1a2 | j_mayer | uint32_t txctpr[4];
|
1959 | 9c02f1a2 | j_mayer | uint32_t rxctpr[2];
|
1960 | 9c02f1a2 | j_mayer | uint32_t rcbs[2];
|
1961 | 9c02f1a2 | j_mayer | }; |
1962 | 9c02f1a2 | j_mayer | |
1963 | 9c02f1a2 | j_mayer | static void ppc40x_mal_reset (void *opaque); |
1964 | 9c02f1a2 | j_mayer | |
1965 | 9c02f1a2 | j_mayer | static target_ulong dcr_read_mal (void *opaque, int dcrn) |
1966 | 9c02f1a2 | j_mayer | { |
1967 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
1968 | 9c02f1a2 | j_mayer | target_ulong ret; |
1969 | 9c02f1a2 | j_mayer | |
1970 | 9c02f1a2 | j_mayer | mal = opaque; |
1971 | 9c02f1a2 | j_mayer | switch (dcrn) {
|
1972 | 9c02f1a2 | j_mayer | case MAL0_CFG:
|
1973 | 9c02f1a2 | j_mayer | ret = mal->cfg; |
1974 | 9c02f1a2 | j_mayer | break;
|
1975 | 9c02f1a2 | j_mayer | case MAL0_ESR:
|
1976 | 9c02f1a2 | j_mayer | ret = mal->esr; |
1977 | 9c02f1a2 | j_mayer | break;
|
1978 | 9c02f1a2 | j_mayer | case MAL0_IER:
|
1979 | 9c02f1a2 | j_mayer | ret = mal->ier; |
1980 | 9c02f1a2 | j_mayer | break;
|
1981 | 9c02f1a2 | j_mayer | case MAL0_TXCASR:
|
1982 | 9c02f1a2 | j_mayer | ret = mal->txcasr; |
1983 | 9c02f1a2 | j_mayer | break;
|
1984 | 9c02f1a2 | j_mayer | case MAL0_TXCARR:
|
1985 | 9c02f1a2 | j_mayer | ret = mal->txcarr; |
1986 | 9c02f1a2 | j_mayer | break;
|
1987 | 9c02f1a2 | j_mayer | case MAL0_TXEOBISR:
|
1988 | 9c02f1a2 | j_mayer | ret = mal->txeobisr; |
1989 | 9c02f1a2 | j_mayer | break;
|
1990 | 9c02f1a2 | j_mayer | case MAL0_TXDEIR:
|
1991 | 9c02f1a2 | j_mayer | ret = mal->txdeir; |
1992 | 9c02f1a2 | j_mayer | break;
|
1993 | 9c02f1a2 | j_mayer | case MAL0_RXCASR:
|
1994 | 9c02f1a2 | j_mayer | ret = mal->rxcasr; |
1995 | 9c02f1a2 | j_mayer | break;
|
1996 | 9c02f1a2 | j_mayer | case MAL0_RXCARR:
|
1997 | 9c02f1a2 | j_mayer | ret = mal->rxcarr; |
1998 | 9c02f1a2 | j_mayer | break;
|
1999 | 9c02f1a2 | j_mayer | case MAL0_RXEOBISR:
|
2000 | 9c02f1a2 | j_mayer | ret = mal->rxeobisr; |
2001 | 9c02f1a2 | j_mayer | break;
|
2002 | 9c02f1a2 | j_mayer | case MAL0_RXDEIR:
|
2003 | 9c02f1a2 | j_mayer | ret = mal->rxdeir; |
2004 | 9c02f1a2 | j_mayer | break;
|
2005 | 9c02f1a2 | j_mayer | case MAL0_TXCTP0R:
|
2006 | 9c02f1a2 | j_mayer | ret = mal->txctpr[0];
|
2007 | 9c02f1a2 | j_mayer | break;
|
2008 | 9c02f1a2 | j_mayer | case MAL0_TXCTP1R:
|
2009 | 9c02f1a2 | j_mayer | ret = mal->txctpr[1];
|
2010 | 9c02f1a2 | j_mayer | break;
|
2011 | 9c02f1a2 | j_mayer | case MAL0_TXCTP2R:
|
2012 | 9c02f1a2 | j_mayer | ret = mal->txctpr[2];
|
2013 | 9c02f1a2 | j_mayer | break;
|
2014 | 9c02f1a2 | j_mayer | case MAL0_TXCTP3R:
|
2015 | 9c02f1a2 | j_mayer | ret = mal->txctpr[3];
|
2016 | 9c02f1a2 | j_mayer | break;
|
2017 | 9c02f1a2 | j_mayer | case MAL0_RXCTP0R:
|
2018 | 9c02f1a2 | j_mayer | ret = mal->rxctpr[0];
|
2019 | 9c02f1a2 | j_mayer | break;
|
2020 | 9c02f1a2 | j_mayer | case MAL0_RXCTP1R:
|
2021 | 9c02f1a2 | j_mayer | ret = mal->rxctpr[1];
|
2022 | 9c02f1a2 | j_mayer | break;
|
2023 | 9c02f1a2 | j_mayer | case MAL0_RCBS0:
|
2024 | 9c02f1a2 | j_mayer | ret = mal->rcbs[0];
|
2025 | 9c02f1a2 | j_mayer | break;
|
2026 | 9c02f1a2 | j_mayer | case MAL0_RCBS1:
|
2027 | 9c02f1a2 | j_mayer | ret = mal->rcbs[1];
|
2028 | 9c02f1a2 | j_mayer | break;
|
2029 | 9c02f1a2 | j_mayer | default:
|
2030 | 9c02f1a2 | j_mayer | ret = 0;
|
2031 | 9c02f1a2 | j_mayer | break;
|
2032 | 9c02f1a2 | j_mayer | } |
2033 | 9c02f1a2 | j_mayer | |
2034 | 9c02f1a2 | j_mayer | return ret;
|
2035 | 9c02f1a2 | j_mayer | } |
2036 | 9c02f1a2 | j_mayer | |
2037 | 9c02f1a2 | j_mayer | static void dcr_write_mal (void *opaque, int dcrn, target_ulong val) |
2038 | 9c02f1a2 | j_mayer | { |
2039 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
2040 | 9c02f1a2 | j_mayer | int idx;
|
2041 | 9c02f1a2 | j_mayer | |
2042 | 9c02f1a2 | j_mayer | mal = opaque; |
2043 | 9c02f1a2 | j_mayer | switch (dcrn) {
|
2044 | 9c02f1a2 | j_mayer | case MAL0_CFG:
|
2045 | 9c02f1a2 | j_mayer | if (val & 0x80000000) |
2046 | 9c02f1a2 | j_mayer | ppc40x_mal_reset(mal); |
2047 | 9c02f1a2 | j_mayer | mal->cfg = val & 0x00FFC087;
|
2048 | 9c02f1a2 | j_mayer | break;
|
2049 | 9c02f1a2 | j_mayer | case MAL0_ESR:
|
2050 | 9c02f1a2 | j_mayer | /* Read/clear */
|
2051 | 9c02f1a2 | j_mayer | mal->esr &= ~val; |
2052 | 9c02f1a2 | j_mayer | break;
|
2053 | 9c02f1a2 | j_mayer | case MAL0_IER:
|
2054 | 9c02f1a2 | j_mayer | mal->ier = val & 0x0000001F;
|
2055 | 9c02f1a2 | j_mayer | break;
|
2056 | 9c02f1a2 | j_mayer | case MAL0_TXCASR:
|
2057 | 9c02f1a2 | j_mayer | mal->txcasr = val & 0xF0000000;
|
2058 | 9c02f1a2 | j_mayer | break;
|
2059 | 9c02f1a2 | j_mayer | case MAL0_TXCARR:
|
2060 | 9c02f1a2 | j_mayer | mal->txcarr = val & 0xF0000000;
|
2061 | 9c02f1a2 | j_mayer | break;
|
2062 | 9c02f1a2 | j_mayer | case MAL0_TXEOBISR:
|
2063 | 9c02f1a2 | j_mayer | /* Read/clear */
|
2064 | 9c02f1a2 | j_mayer | mal->txeobisr &= ~val; |
2065 | 9c02f1a2 | j_mayer | break;
|
2066 | 9c02f1a2 | j_mayer | case MAL0_TXDEIR:
|
2067 | 9c02f1a2 | j_mayer | /* Read/clear */
|
2068 | 9c02f1a2 | j_mayer | mal->txdeir &= ~val; |
2069 | 9c02f1a2 | j_mayer | break;
|
2070 | 9c02f1a2 | j_mayer | case MAL0_RXCASR:
|
2071 | 9c02f1a2 | j_mayer | mal->rxcasr = val & 0xC0000000;
|
2072 | 9c02f1a2 | j_mayer | break;
|
2073 | 9c02f1a2 | j_mayer | case MAL0_RXCARR:
|
2074 | 9c02f1a2 | j_mayer | mal->rxcarr = val & 0xC0000000;
|
2075 | 9c02f1a2 | j_mayer | break;
|
2076 | 9c02f1a2 | j_mayer | case MAL0_RXEOBISR:
|
2077 | 9c02f1a2 | j_mayer | /* Read/clear */
|
2078 | 9c02f1a2 | j_mayer | mal->rxeobisr &= ~val; |
2079 | 9c02f1a2 | j_mayer | break;
|
2080 | 9c02f1a2 | j_mayer | case MAL0_RXDEIR:
|
2081 | 9c02f1a2 | j_mayer | /* Read/clear */
|
2082 | 9c02f1a2 | j_mayer | mal->rxdeir &= ~val; |
2083 | 9c02f1a2 | j_mayer | break;
|
2084 | 9c02f1a2 | j_mayer | case MAL0_TXCTP0R:
|
2085 | 9c02f1a2 | j_mayer | idx = 0;
|
2086 | 9c02f1a2 | j_mayer | goto update_tx_ptr;
|
2087 | 9c02f1a2 | j_mayer | case MAL0_TXCTP1R:
|
2088 | 9c02f1a2 | j_mayer | idx = 1;
|
2089 | 9c02f1a2 | j_mayer | goto update_tx_ptr;
|
2090 | 9c02f1a2 | j_mayer | case MAL0_TXCTP2R:
|
2091 | 9c02f1a2 | j_mayer | idx = 2;
|
2092 | 9c02f1a2 | j_mayer | goto update_tx_ptr;
|
2093 | 9c02f1a2 | j_mayer | case MAL0_TXCTP3R:
|
2094 | 9c02f1a2 | j_mayer | idx = 3;
|
2095 | 9c02f1a2 | j_mayer | update_tx_ptr:
|
2096 | 9c02f1a2 | j_mayer | mal->txctpr[idx] = val; |
2097 | 9c02f1a2 | j_mayer | break;
|
2098 | 9c02f1a2 | j_mayer | case MAL0_RXCTP0R:
|
2099 | 9c02f1a2 | j_mayer | idx = 0;
|
2100 | 9c02f1a2 | j_mayer | goto update_rx_ptr;
|
2101 | 9c02f1a2 | j_mayer | case MAL0_RXCTP1R:
|
2102 | 9c02f1a2 | j_mayer | idx = 1;
|
2103 | 9c02f1a2 | j_mayer | update_rx_ptr:
|
2104 | 9c02f1a2 | j_mayer | mal->rxctpr[idx] = val; |
2105 | 9c02f1a2 | j_mayer | break;
|
2106 | 9c02f1a2 | j_mayer | case MAL0_RCBS0:
|
2107 | 9c02f1a2 | j_mayer | idx = 0;
|
2108 | 9c02f1a2 | j_mayer | goto update_rx_size;
|
2109 | 9c02f1a2 | j_mayer | case MAL0_RCBS1:
|
2110 | 9c02f1a2 | j_mayer | idx = 1;
|
2111 | 9c02f1a2 | j_mayer | update_rx_size:
|
2112 | 9c02f1a2 | j_mayer | mal->rcbs[idx] = val & 0x000000FF;
|
2113 | 9c02f1a2 | j_mayer | break;
|
2114 | 9c02f1a2 | j_mayer | } |
2115 | 9c02f1a2 | j_mayer | } |
2116 | 9c02f1a2 | j_mayer | |
2117 | 9c02f1a2 | j_mayer | static void ppc40x_mal_reset (void *opaque) |
2118 | 9c02f1a2 | j_mayer | { |
2119 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
2120 | 9c02f1a2 | j_mayer | |
2121 | 9c02f1a2 | j_mayer | mal = opaque; |
2122 | 9c02f1a2 | j_mayer | mal->cfg = 0x0007C000;
|
2123 | 9c02f1a2 | j_mayer | mal->esr = 0x00000000;
|
2124 | 9c02f1a2 | j_mayer | mal->ier = 0x00000000;
|
2125 | 9c02f1a2 | j_mayer | mal->rxcasr = 0x00000000;
|
2126 | 9c02f1a2 | j_mayer | mal->rxdeir = 0x00000000;
|
2127 | 9c02f1a2 | j_mayer | mal->rxeobisr = 0x00000000;
|
2128 | 9c02f1a2 | j_mayer | mal->txcasr = 0x00000000;
|
2129 | 9c02f1a2 | j_mayer | mal->txdeir = 0x00000000;
|
2130 | 9c02f1a2 | j_mayer | mal->txeobisr = 0x00000000;
|
2131 | 9c02f1a2 | j_mayer | } |
2132 | 9c02f1a2 | j_mayer | |
2133 | 9c02f1a2 | j_mayer | void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]) |
2134 | 9c02f1a2 | j_mayer | { |
2135 | 9c02f1a2 | j_mayer | ppc40x_mal_t *mal; |
2136 | 9c02f1a2 | j_mayer | int i;
|
2137 | 9c02f1a2 | j_mayer | |
2138 | 9c02f1a2 | j_mayer | mal = qemu_mallocz(sizeof(ppc40x_mal_t));
|
2139 | 9c02f1a2 | j_mayer | if (mal != NULL) { |
2140 | 9c02f1a2 | j_mayer | for (i = 0; i < 4; i++) |
2141 | 9c02f1a2 | j_mayer | mal->irqs[i] = irqs[i]; |
2142 | 9c02f1a2 | j_mayer | ppc40x_mal_reset(mal); |
2143 | 9c02f1a2 | j_mayer | qemu_register_reset(&ppc40x_mal_reset, mal); |
2144 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_CFG, |
2145 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2146 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_ESR, |
2147 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2148 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_IER, |
2149 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2150 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCASR, |
2151 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2152 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCARR, |
2153 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2154 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXEOBISR, |
2155 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2156 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXDEIR, |
2157 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2158 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXCASR, |
2159 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2160 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXCARR, |
2161 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2162 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXEOBISR, |
2163 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2164 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXDEIR, |
2165 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2166 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCTP0R, |
2167 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2168 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCTP1R, |
2169 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2170 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCTP2R, |
2171 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2172 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_TXCTP3R, |
2173 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2174 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXCTP0R, |
2175 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2176 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RXCTP1R, |
2177 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2178 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RCBS0, |
2179 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2180 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, MAL0_RCBS1, |
2181 | 9c02f1a2 | j_mayer | mal, &dcr_read_mal, &dcr_write_mal); |
2182 | 9c02f1a2 | j_mayer | } |
2183 | 9c02f1a2 | j_mayer | } |
2184 | 9c02f1a2 | j_mayer | |
2185 | 9c02f1a2 | j_mayer | /*****************************************************************************/
|
2186 | 8ecc7913 | j_mayer | /* SPR */
|
2187 | 8ecc7913 | j_mayer | void ppc40x_core_reset (CPUState *env)
|
2188 | 8ecc7913 | j_mayer | { |
2189 | 8ecc7913 | j_mayer | target_ulong dbsr; |
2190 | 8ecc7913 | j_mayer | |
2191 | 8ecc7913 | j_mayer | printf("Reset PowerPC core\n");
|
2192 | 8ecc7913 | j_mayer | cpu_ppc_reset(env); |
2193 | 8ecc7913 | j_mayer | dbsr = env->spr[SPR_40x_DBSR]; |
2194 | 8ecc7913 | j_mayer | dbsr &= ~0x00000300;
|
2195 | 8ecc7913 | j_mayer | dbsr |= 0x00000100;
|
2196 | 8ecc7913 | j_mayer | env->spr[SPR_40x_DBSR] = dbsr; |
2197 | 8ecc7913 | j_mayer | cpu_loop_exit(); |
2198 | 8ecc7913 | j_mayer | } |
2199 | 8ecc7913 | j_mayer | |
2200 | 8ecc7913 | j_mayer | void ppc40x_chip_reset (CPUState *env)
|
2201 | 8ecc7913 | j_mayer | { |
2202 | 8ecc7913 | j_mayer | target_ulong dbsr; |
2203 | 8ecc7913 | j_mayer | |
2204 | 8ecc7913 | j_mayer | printf("Reset PowerPC chip\n");
|
2205 | 8ecc7913 | j_mayer | cpu_ppc_reset(env); |
2206 | 8ecc7913 | j_mayer | /* XXX: TODO reset all internal peripherals */
|
2207 | 8ecc7913 | j_mayer | dbsr = env->spr[SPR_40x_DBSR]; |
2208 | 8ecc7913 | j_mayer | dbsr &= ~0x00000300;
|
2209 | 04f20795 | j_mayer | dbsr |= 0x00000200;
|
2210 | 8ecc7913 | j_mayer | env->spr[SPR_40x_DBSR] = dbsr; |
2211 | 8ecc7913 | j_mayer | cpu_loop_exit(); |
2212 | 8ecc7913 | j_mayer | } |
2213 | 8ecc7913 | j_mayer | |
2214 | 8ecc7913 | j_mayer | void ppc40x_system_reset (CPUState *env)
|
2215 | 8ecc7913 | j_mayer | { |
2216 | 8ecc7913 | j_mayer | printf("Reset PowerPC system\n");
|
2217 | 8ecc7913 | j_mayer | qemu_system_reset_request(); |
2218 | 8ecc7913 | j_mayer | } |
2219 | 8ecc7913 | j_mayer | |
2220 | 8ecc7913 | j_mayer | void store_40x_dbcr0 (CPUState *env, uint32_t val)
|
2221 | 8ecc7913 | j_mayer | { |
2222 | 8ecc7913 | j_mayer | switch ((val >> 28) & 0x3) { |
2223 | 8ecc7913 | j_mayer | case 0x0: |
2224 | 8ecc7913 | j_mayer | /* No action */
|
2225 | 8ecc7913 | j_mayer | break;
|
2226 | 8ecc7913 | j_mayer | case 0x1: |
2227 | 8ecc7913 | j_mayer | /* Core reset */
|
2228 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
2229 | 8ecc7913 | j_mayer | break;
|
2230 | 8ecc7913 | j_mayer | case 0x2: |
2231 | 8ecc7913 | j_mayer | /* Chip reset */
|
2232 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
2233 | 8ecc7913 | j_mayer | break;
|
2234 | 8ecc7913 | j_mayer | case 0x3: |
2235 | 8ecc7913 | j_mayer | /* System reset */
|
2236 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
2237 | 8ecc7913 | j_mayer | break;
|
2238 | 8ecc7913 | j_mayer | } |
2239 | 8ecc7913 | j_mayer | } |
2240 | 8ecc7913 | j_mayer | |
2241 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
2242 | 8ecc7913 | j_mayer | /* PowerPC 405CR */
|
2243 | 8ecc7913 | j_mayer | enum {
|
2244 | 8ecc7913 | j_mayer | PPC405CR_CPC0_PLLMR = 0x0B0,
|
2245 | 8ecc7913 | j_mayer | PPC405CR_CPC0_CR0 = 0x0B1,
|
2246 | 8ecc7913 | j_mayer | PPC405CR_CPC0_CR1 = 0x0B2,
|
2247 | 8ecc7913 | j_mayer | PPC405CR_CPC0_PSR = 0x0B4,
|
2248 | 8ecc7913 | j_mayer | PPC405CR_CPC0_JTAGID = 0x0B5,
|
2249 | 8ecc7913 | j_mayer | PPC405CR_CPC0_ER = 0x0B9,
|
2250 | 8ecc7913 | j_mayer | PPC405CR_CPC0_FR = 0x0BA,
|
2251 | 8ecc7913 | j_mayer | PPC405CR_CPC0_SR = 0x0BB,
|
2252 | 8ecc7913 | j_mayer | }; |
2253 | 8ecc7913 | j_mayer | |
2254 | 04f20795 | j_mayer | enum {
|
2255 | 04f20795 | j_mayer | PPC405CR_CPU_CLK = 0,
|
2256 | 04f20795 | j_mayer | PPC405CR_TMR_CLK = 1,
|
2257 | 04f20795 | j_mayer | PPC405CR_PLB_CLK = 2,
|
2258 | 04f20795 | j_mayer | PPC405CR_SDRAM_CLK = 3,
|
2259 | 04f20795 | j_mayer | PPC405CR_OPB_CLK = 4,
|
2260 | 04f20795 | j_mayer | PPC405CR_EXT_CLK = 5,
|
2261 | 04f20795 | j_mayer | PPC405CR_UART_CLK = 6,
|
2262 | 04f20795 | j_mayer | PPC405CR_CLK_NB = 7,
|
2263 | 04f20795 | j_mayer | }; |
2264 | 04f20795 | j_mayer | |
2265 | 8ecc7913 | j_mayer | typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; |
2266 | 8ecc7913 | j_mayer | struct ppc405cr_cpc_t {
|
2267 | 04f20795 | j_mayer | clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
2268 | 8ecc7913 | j_mayer | uint32_t sysclk; |
2269 | 8ecc7913 | j_mayer | uint32_t psr; |
2270 | 8ecc7913 | j_mayer | uint32_t cr0; |
2271 | 8ecc7913 | j_mayer | uint32_t cr1; |
2272 | 8ecc7913 | j_mayer | uint32_t jtagid; |
2273 | 8ecc7913 | j_mayer | uint32_t pllmr; |
2274 | 8ecc7913 | j_mayer | uint32_t er; |
2275 | 8ecc7913 | j_mayer | uint32_t fr; |
2276 | 8ecc7913 | j_mayer | }; |
2277 | 8ecc7913 | j_mayer | |
2278 | 8ecc7913 | j_mayer | static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) |
2279 | 8ecc7913 | j_mayer | { |
2280 | 8ecc7913 | j_mayer | uint64_t VCO_out, PLL_out; |
2281 | 8ecc7913 | j_mayer | uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk; |
2282 | 8ecc7913 | j_mayer | int M, D0, D1, D2;
|
2283 | 8ecc7913 | j_mayer | |
2284 | 8ecc7913 | j_mayer | D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ |
2285 | 8ecc7913 | j_mayer | if (cpc->pllmr & 0x80000000) { |
2286 | 8ecc7913 | j_mayer | D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ |
2287 | 8ecc7913 | j_mayer | D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ |
2288 | 8ecc7913 | j_mayer | M = D0 * D1 * D2; |
2289 | 8ecc7913 | j_mayer | VCO_out = cpc->sysclk * M; |
2290 | 8ecc7913 | j_mayer | if (VCO_out < 400000000 || VCO_out > 800000000) { |
2291 | 8ecc7913 | j_mayer | /* PLL cannot lock */
|
2292 | 8ecc7913 | j_mayer | cpc->pllmr &= ~0x80000000;
|
2293 | 8ecc7913 | j_mayer | goto bypass_pll;
|
2294 | 8ecc7913 | j_mayer | } |
2295 | 8ecc7913 | j_mayer | PLL_out = VCO_out / D2; |
2296 | 8ecc7913 | j_mayer | } else {
|
2297 | 8ecc7913 | j_mayer | /* Bypass PLL */
|
2298 | 8ecc7913 | j_mayer | bypass_pll:
|
2299 | 8ecc7913 | j_mayer | M = D0; |
2300 | 8ecc7913 | j_mayer | PLL_out = cpc->sysclk * M; |
2301 | 8ecc7913 | j_mayer | } |
2302 | 8ecc7913 | j_mayer | CPU_clk = PLL_out; |
2303 | 8ecc7913 | j_mayer | if (cpc->cr1 & 0x00800000) |
2304 | 8ecc7913 | j_mayer | TMR_clk = cpc->sysclk; /* Should have a separate clock */
|
2305 | 8ecc7913 | j_mayer | else
|
2306 | 8ecc7913 | j_mayer | TMR_clk = CPU_clk; |
2307 | 8ecc7913 | j_mayer | PLB_clk = CPU_clk / D0; |
2308 | 8ecc7913 | j_mayer | SDRAM_clk = PLB_clk; |
2309 | 8ecc7913 | j_mayer | D0 = ((cpc->pllmr >> 10) & 0x3) + 1; |
2310 | 8ecc7913 | j_mayer | OPB_clk = PLB_clk / D0; |
2311 | 8ecc7913 | j_mayer | D0 = ((cpc->pllmr >> 24) & 0x3) + 2; |
2312 | 8ecc7913 | j_mayer | EXT_clk = PLB_clk / D0; |
2313 | 8ecc7913 | j_mayer | D0 = ((cpc->cr0 >> 1) & 0x1F) + 1; |
2314 | 8ecc7913 | j_mayer | UART_clk = CPU_clk / D0; |
2315 | 8ecc7913 | j_mayer | /* Setup CPU clocks */
|
2316 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); |
2317 | 8ecc7913 | j_mayer | /* Setup time-base clock */
|
2318 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); |
2319 | 8ecc7913 | j_mayer | /* Setup PLB clock */
|
2320 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); |
2321 | 8ecc7913 | j_mayer | /* Setup SDRAM clock */
|
2322 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); |
2323 | 8ecc7913 | j_mayer | /* Setup OPB clock */
|
2324 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); |
2325 | 8ecc7913 | j_mayer | /* Setup external clock */
|
2326 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); |
2327 | 8ecc7913 | j_mayer | /* Setup UART clock */
|
2328 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); |
2329 | 8ecc7913 | j_mayer | } |
2330 | 8ecc7913 | j_mayer | |
2331 | 8ecc7913 | j_mayer | static target_ulong dcr_read_crcpc (void *opaque, int dcrn) |
2332 | 8ecc7913 | j_mayer | { |
2333 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
2334 | 8ecc7913 | j_mayer | target_ulong ret; |
2335 | 8ecc7913 | j_mayer | |
2336 | 8ecc7913 | j_mayer | cpc = opaque; |
2337 | 8ecc7913 | j_mayer | switch (dcrn) {
|
2338 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PLLMR:
|
2339 | 8ecc7913 | j_mayer | ret = cpc->pllmr; |
2340 | 8ecc7913 | j_mayer | break;
|
2341 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR0:
|
2342 | 8ecc7913 | j_mayer | ret = cpc->cr0; |
2343 | 8ecc7913 | j_mayer | break;
|
2344 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR1:
|
2345 | 8ecc7913 | j_mayer | ret = cpc->cr1; |
2346 | 8ecc7913 | j_mayer | break;
|
2347 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PSR:
|
2348 | 8ecc7913 | j_mayer | ret = cpc->psr; |
2349 | 8ecc7913 | j_mayer | break;
|
2350 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_JTAGID:
|
2351 | 8ecc7913 | j_mayer | ret = cpc->jtagid; |
2352 | 8ecc7913 | j_mayer | break;
|
2353 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_ER:
|
2354 | 8ecc7913 | j_mayer | ret = cpc->er; |
2355 | 8ecc7913 | j_mayer | break;
|
2356 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_FR:
|
2357 | 8ecc7913 | j_mayer | ret = cpc->fr; |
2358 | 8ecc7913 | j_mayer | break;
|
2359 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_SR:
|
2360 | 8ecc7913 | j_mayer | ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
|
2361 | 8ecc7913 | j_mayer | break;
|
2362 | 8ecc7913 | j_mayer | default:
|
2363 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
|
2364 | 8ecc7913 | j_mayer | ret = 0;
|
2365 | 8ecc7913 | j_mayer | break;
|
2366 | 8ecc7913 | j_mayer | } |
2367 | 8ecc7913 | j_mayer | |
2368 | 8ecc7913 | j_mayer | return ret;
|
2369 | 8ecc7913 | j_mayer | } |
2370 | 8ecc7913 | j_mayer | |
2371 | 8ecc7913 | j_mayer | static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val) |
2372 | 8ecc7913 | j_mayer | { |
2373 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
2374 | 8ecc7913 | j_mayer | |
2375 | 8ecc7913 | j_mayer | cpc = opaque; |
2376 | 8ecc7913 | j_mayer | switch (dcrn) {
|
2377 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PLLMR:
|
2378 | 8ecc7913 | j_mayer | cpc->pllmr = val & 0xFFF77C3F;
|
2379 | 8ecc7913 | j_mayer | break;
|
2380 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR0:
|
2381 | 8ecc7913 | j_mayer | cpc->cr0 = val & 0x0FFFFFFE;
|
2382 | 8ecc7913 | j_mayer | break;
|
2383 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_CR1:
|
2384 | 8ecc7913 | j_mayer | cpc->cr1 = val & 0x00800000;
|
2385 | 8ecc7913 | j_mayer | break;
|
2386 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_PSR:
|
2387 | 8ecc7913 | j_mayer | /* Read-only */
|
2388 | 8ecc7913 | j_mayer | break;
|
2389 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_JTAGID:
|
2390 | 8ecc7913 | j_mayer | /* Read-only */
|
2391 | 8ecc7913 | j_mayer | break;
|
2392 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_ER:
|
2393 | 8ecc7913 | j_mayer | cpc->er = val & 0xBFFC0000;
|
2394 | 8ecc7913 | j_mayer | break;
|
2395 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_FR:
|
2396 | 8ecc7913 | j_mayer | cpc->fr = val & 0xBFFC0000;
|
2397 | 8ecc7913 | j_mayer | break;
|
2398 | 8ecc7913 | j_mayer | case PPC405CR_CPC0_SR:
|
2399 | 8ecc7913 | j_mayer | /* Read-only */
|
2400 | 8ecc7913 | j_mayer | break;
|
2401 | 8ecc7913 | j_mayer | } |
2402 | 8ecc7913 | j_mayer | } |
2403 | 8ecc7913 | j_mayer | |
2404 | 8ecc7913 | j_mayer | static void ppc405cr_cpc_reset (void *opaque) |
2405 | 8ecc7913 | j_mayer | { |
2406 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
2407 | 8ecc7913 | j_mayer | int D;
|
2408 | 8ecc7913 | j_mayer | |
2409 | 8ecc7913 | j_mayer | cpc = opaque; |
2410 | 8ecc7913 | j_mayer | /* Compute PLLMR value from PSR settings */
|
2411 | 8ecc7913 | j_mayer | cpc->pllmr = 0x80000000;
|
2412 | 8ecc7913 | j_mayer | /* PFWD */
|
2413 | 8ecc7913 | j_mayer | switch ((cpc->psr >> 30) & 3) { |
2414 | 8ecc7913 | j_mayer | case 0: |
2415 | 8ecc7913 | j_mayer | /* Bypass */
|
2416 | 8ecc7913 | j_mayer | cpc->pllmr &= ~0x80000000;
|
2417 | 8ecc7913 | j_mayer | break;
|
2418 | 8ecc7913 | j_mayer | case 1: |
2419 | 8ecc7913 | j_mayer | /* Divide by 3 */
|
2420 | 8ecc7913 | j_mayer | cpc->pllmr |= 5 << 16; |
2421 | 8ecc7913 | j_mayer | break;
|
2422 | 8ecc7913 | j_mayer | case 2: |
2423 | 8ecc7913 | j_mayer | /* Divide by 4 */
|
2424 | 8ecc7913 | j_mayer | cpc->pllmr |= 4 << 16; |
2425 | 8ecc7913 | j_mayer | break;
|
2426 | 8ecc7913 | j_mayer | case 3: |
2427 | 8ecc7913 | j_mayer | /* Divide by 6 */
|
2428 | 8ecc7913 | j_mayer | cpc->pllmr |= 2 << 16; |
2429 | 8ecc7913 | j_mayer | break;
|
2430 | 8ecc7913 | j_mayer | } |
2431 | 8ecc7913 | j_mayer | /* PFBD */
|
2432 | 8ecc7913 | j_mayer | D = (cpc->psr >> 28) & 3; |
2433 | 8ecc7913 | j_mayer | cpc->pllmr |= (D + 1) << 20; |
2434 | 8ecc7913 | j_mayer | /* PT */
|
2435 | 8ecc7913 | j_mayer | D = (cpc->psr >> 25) & 7; |
2436 | 8ecc7913 | j_mayer | switch (D) {
|
2437 | 8ecc7913 | j_mayer | case 0x2: |
2438 | 8ecc7913 | j_mayer | cpc->pllmr |= 0x13;
|
2439 | 8ecc7913 | j_mayer | break;
|
2440 | 8ecc7913 | j_mayer | case 0x4: |
2441 | 8ecc7913 | j_mayer | cpc->pllmr |= 0x15;
|
2442 | 8ecc7913 | j_mayer | break;
|
2443 | 8ecc7913 | j_mayer | case 0x5: |
2444 | 8ecc7913 | j_mayer | cpc->pllmr |= 0x16;
|
2445 | 8ecc7913 | j_mayer | break;
|
2446 | 8ecc7913 | j_mayer | default:
|
2447 | 8ecc7913 | j_mayer | break;
|
2448 | 8ecc7913 | j_mayer | } |
2449 | 8ecc7913 | j_mayer | /* PDC */
|
2450 | 8ecc7913 | j_mayer | D = (cpc->psr >> 23) & 3; |
2451 | 8ecc7913 | j_mayer | cpc->pllmr |= D << 26;
|
2452 | 8ecc7913 | j_mayer | /* ODP */
|
2453 | 8ecc7913 | j_mayer | D = (cpc->psr >> 21) & 3; |
2454 | 8ecc7913 | j_mayer | cpc->pllmr |= D << 10;
|
2455 | 8ecc7913 | j_mayer | /* EBPD */
|
2456 | 8ecc7913 | j_mayer | D = (cpc->psr >> 17) & 3; |
2457 | 8ecc7913 | j_mayer | cpc->pllmr |= D << 24;
|
2458 | 8ecc7913 | j_mayer | cpc->cr0 = 0x0000003C;
|
2459 | 8ecc7913 | j_mayer | cpc->cr1 = 0x2B0D8800;
|
2460 | 8ecc7913 | j_mayer | cpc->er = 0x00000000;
|
2461 | 8ecc7913 | j_mayer | cpc->fr = 0x00000000;
|
2462 | 8ecc7913 | j_mayer | ppc405cr_clk_setup(cpc); |
2463 | 8ecc7913 | j_mayer | } |
2464 | 8ecc7913 | j_mayer | |
2465 | 8ecc7913 | j_mayer | static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) |
2466 | 8ecc7913 | j_mayer | { |
2467 | 8ecc7913 | j_mayer | int D;
|
2468 | 8ecc7913 | j_mayer | |
2469 | 8ecc7913 | j_mayer | /* XXX: this should be read from IO pins */
|
2470 | 8ecc7913 | j_mayer | cpc->psr = 0x00000000; /* 8 bits ROM */ |
2471 | 8ecc7913 | j_mayer | /* PFWD */
|
2472 | 8ecc7913 | j_mayer | D = 0x2; /* Divide by 4 */ |
2473 | 8ecc7913 | j_mayer | cpc->psr |= D << 30;
|
2474 | 8ecc7913 | j_mayer | /* PFBD */
|
2475 | 8ecc7913 | j_mayer | D = 0x1; /* Divide by 2 */ |
2476 | 8ecc7913 | j_mayer | cpc->psr |= D << 28;
|
2477 | 8ecc7913 | j_mayer | /* PDC */
|
2478 | 8ecc7913 | j_mayer | D = 0x1; /* Divide by 2 */ |
2479 | 8ecc7913 | j_mayer | cpc->psr |= D << 23;
|
2480 | 8ecc7913 | j_mayer | /* PT */
|
2481 | 8ecc7913 | j_mayer | D = 0x5; /* M = 16 */ |
2482 | 8ecc7913 | j_mayer | cpc->psr |= D << 25;
|
2483 | 8ecc7913 | j_mayer | /* ODP */
|
2484 | 8ecc7913 | j_mayer | D = 0x1; /* Divide by 2 */ |
2485 | 8ecc7913 | j_mayer | cpc->psr |= D << 21;
|
2486 | 8ecc7913 | j_mayer | /* EBDP */
|
2487 | 8ecc7913 | j_mayer | D = 0x2; /* Divide by 4 */ |
2488 | 8ecc7913 | j_mayer | cpc->psr |= D << 17;
|
2489 | 8ecc7913 | j_mayer | } |
2490 | 8ecc7913 | j_mayer | |
2491 | 8ecc7913 | j_mayer | static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], |
2492 | 8ecc7913 | j_mayer | uint32_t sysclk) |
2493 | 8ecc7913 | j_mayer | { |
2494 | 8ecc7913 | j_mayer | ppc405cr_cpc_t *cpc; |
2495 | 8ecc7913 | j_mayer | |
2496 | 8ecc7913 | j_mayer | cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
|
2497 | 8ecc7913 | j_mayer | if (cpc != NULL) { |
2498 | 04f20795 | j_mayer | memcpy(cpc->clk_setup, clk_setup, |
2499 | 04f20795 | j_mayer | PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
2500 | 8ecc7913 | j_mayer | cpc->sysclk = sysclk; |
2501 | 8ecc7913 | j_mayer | cpc->jtagid = 0x42051049;
|
2502 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, |
2503 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
2504 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, |
2505 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
2506 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, |
2507 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
2508 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, |
2509 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
2510 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, |
2511 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
2512 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, |
2513 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
2514 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, |
2515 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
2516 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, |
2517 | 8ecc7913 | j_mayer | &dcr_read_crcpc, &dcr_write_crcpc); |
2518 | 8ecc7913 | j_mayer | ppc405cr_clk_init(cpc); |
2519 | 8ecc7913 | j_mayer | qemu_register_reset(ppc405cr_cpc_reset, cpc); |
2520 | 8ecc7913 | j_mayer | ppc405cr_cpc_reset(cpc); |
2521 | 8ecc7913 | j_mayer | } |
2522 | 8ecc7913 | j_mayer | } |
2523 | 8ecc7913 | j_mayer | |
2524 | 71db710f | blueswir1 | CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
|
2525 | 71db710f | blueswir1 | target_phys_addr_t ram_sizes[4],
|
2526 | 8ecc7913 | j_mayer | uint32_t sysclk, qemu_irq **picp, |
2527 | 04f20795 | j_mayer | ram_addr_t *offsetp, int do_init)
|
2528 | 8ecc7913 | j_mayer | { |
2529 | 04f20795 | j_mayer | clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
2530 | 8ecc7913 | j_mayer | qemu_irq dma_irqs[4];
|
2531 | 8ecc7913 | j_mayer | CPUState *env; |
2532 | 8ecc7913 | j_mayer | ppc4xx_mmio_t *mmio; |
2533 | 8ecc7913 | j_mayer | qemu_irq *pic, *irqs; |
2534 | 8ecc7913 | j_mayer | ram_addr_t offset; |
2535 | 8ecc7913 | j_mayer | int i;
|
2536 | 8ecc7913 | j_mayer | |
2537 | 8ecc7913 | j_mayer | memset(clk_setup, 0, sizeof(clk_setup)); |
2538 | 008ff9d7 | j_mayer | env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
2539 | 04f20795 | j_mayer | &clk_setup[PPC405CR_TMR_CLK], sysclk); |
2540 | 8ecc7913 | j_mayer | /* Memory mapped devices registers */
|
2541 | 8ecc7913 | j_mayer | mmio = ppc4xx_mmio_init(env, 0xEF600000);
|
2542 | 8ecc7913 | j_mayer | /* PLB arbitrer */
|
2543 | 8ecc7913 | j_mayer | ppc4xx_plb_init(env); |
2544 | 8ecc7913 | j_mayer | /* PLB to OPB bridge */
|
2545 | 8ecc7913 | j_mayer | ppc4xx_pob_init(env); |
2546 | 8ecc7913 | j_mayer | /* OBP arbitrer */
|
2547 | 8ecc7913 | j_mayer | ppc4xx_opba_init(env, mmio, 0x600);
|
2548 | 8ecc7913 | j_mayer | /* Universal interrupt controller */
|
2549 | 8ecc7913 | j_mayer | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
2550 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_INT] = |
2551 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
2552 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_CINT] = |
2553 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
2554 | 8ecc7913 | j_mayer | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
2555 | 8ecc7913 | j_mayer | *picp = pic; |
2556 | 8ecc7913 | j_mayer | /* SDRAM controller */
|
2557 | 04f20795 | j_mayer | ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
2558 | 8ecc7913 | j_mayer | offset = 0;
|
2559 | 8ecc7913 | j_mayer | for (i = 0; i < 4; i++) |
2560 | 8ecc7913 | j_mayer | offset += ram_sizes[i]; |
2561 | 8ecc7913 | j_mayer | /* External bus controller */
|
2562 | 8ecc7913 | j_mayer | ppc405_ebc_init(env); |
2563 | 8ecc7913 | j_mayer | /* DMA controller */
|
2564 | 04f20795 | j_mayer | dma_irqs[0] = pic[26]; |
2565 | 04f20795 | j_mayer | dma_irqs[1] = pic[25]; |
2566 | 04f20795 | j_mayer | dma_irqs[2] = pic[24]; |
2567 | 04f20795 | j_mayer | dma_irqs[3] = pic[23]; |
2568 | 8ecc7913 | j_mayer | ppc405_dma_init(env, dma_irqs); |
2569 | 8ecc7913 | j_mayer | /* Serial ports */
|
2570 | 8ecc7913 | j_mayer | if (serial_hds[0] != NULL) { |
2571 | 04f20795 | j_mayer | ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]); |
2572 | 8ecc7913 | j_mayer | } |
2573 | 8ecc7913 | j_mayer | if (serial_hds[1] != NULL) { |
2574 | 04f20795 | j_mayer | ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]); |
2575 | 8ecc7913 | j_mayer | } |
2576 | 8ecc7913 | j_mayer | /* IIC controller */
|
2577 | 9c02f1a2 | j_mayer | ppc405_i2c_init(env, mmio, 0x500, pic[29]); |
2578 | 8ecc7913 | j_mayer | /* GPIO */
|
2579 | 8ecc7913 | j_mayer | ppc405_gpio_init(env, mmio, 0x700);
|
2580 | 8ecc7913 | j_mayer | /* CPU control */
|
2581 | 8ecc7913 | j_mayer | ppc405cr_cpc_init(env, clk_setup, sysclk); |
2582 | 8ecc7913 | j_mayer | *offsetp = offset; |
2583 | 8ecc7913 | j_mayer | |
2584 | 8ecc7913 | j_mayer | return env;
|
2585 | 8ecc7913 | j_mayer | } |
2586 | 8ecc7913 | j_mayer | |
2587 | 8ecc7913 | j_mayer | /*****************************************************************************/
|
2588 | 8ecc7913 | j_mayer | /* PowerPC 405EP */
|
2589 | 8ecc7913 | j_mayer | /* CPU control */
|
2590 | 8ecc7913 | j_mayer | enum {
|
2591 | 8ecc7913 | j_mayer | PPC405EP_CPC0_PLLMR0 = 0x0F0,
|
2592 | 8ecc7913 | j_mayer | PPC405EP_CPC0_BOOT = 0x0F1,
|
2593 | 8ecc7913 | j_mayer | PPC405EP_CPC0_EPCTL = 0x0F3,
|
2594 | 8ecc7913 | j_mayer | PPC405EP_CPC0_PLLMR1 = 0x0F4,
|
2595 | 8ecc7913 | j_mayer | PPC405EP_CPC0_UCR = 0x0F5,
|
2596 | 8ecc7913 | j_mayer | PPC405EP_CPC0_SRR = 0x0F6,
|
2597 | 8ecc7913 | j_mayer | PPC405EP_CPC0_JTAGID = 0x0F7,
|
2598 | 8ecc7913 | j_mayer | PPC405EP_CPC0_PCI = 0x0F9,
|
2599 | 9c02f1a2 | j_mayer | #if 0
|
2600 | 9c02f1a2 | j_mayer | PPC405EP_CPC0_ER = xxx,
|
2601 | 9c02f1a2 | j_mayer | PPC405EP_CPC0_FR = xxx,
|
2602 | 9c02f1a2 | j_mayer | PPC405EP_CPC0_SR = xxx,
|
2603 | 9c02f1a2 | j_mayer | #endif
|
2604 | 8ecc7913 | j_mayer | }; |
2605 | 8ecc7913 | j_mayer | |
2606 | 04f20795 | j_mayer | enum {
|
2607 | 04f20795 | j_mayer | PPC405EP_CPU_CLK = 0,
|
2608 | 04f20795 | j_mayer | PPC405EP_PLB_CLK = 1,
|
2609 | 04f20795 | j_mayer | PPC405EP_OPB_CLK = 2,
|
2610 | 04f20795 | j_mayer | PPC405EP_EBC_CLK = 3,
|
2611 | 04f20795 | j_mayer | PPC405EP_MAL_CLK = 4,
|
2612 | 04f20795 | j_mayer | PPC405EP_PCI_CLK = 5,
|
2613 | 04f20795 | j_mayer | PPC405EP_UART0_CLK = 6,
|
2614 | 04f20795 | j_mayer | PPC405EP_UART1_CLK = 7,
|
2615 | 04f20795 | j_mayer | PPC405EP_CLK_NB = 8,
|
2616 | 04f20795 | j_mayer | }; |
2617 | 04f20795 | j_mayer | |
2618 | 8ecc7913 | j_mayer | typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; |
2619 | 8ecc7913 | j_mayer | struct ppc405ep_cpc_t {
|
2620 | 8ecc7913 | j_mayer | uint32_t sysclk; |
2621 | 04f20795 | j_mayer | clk_setup_t clk_setup[PPC405EP_CLK_NB]; |
2622 | 8ecc7913 | j_mayer | uint32_t boot; |
2623 | 8ecc7913 | j_mayer | uint32_t epctl; |
2624 | 8ecc7913 | j_mayer | uint32_t pllmr[2];
|
2625 | 8ecc7913 | j_mayer | uint32_t ucr; |
2626 | 8ecc7913 | j_mayer | uint32_t srr; |
2627 | 8ecc7913 | j_mayer | uint32_t jtagid; |
2628 | 8ecc7913 | j_mayer | uint32_t pci; |
2629 | 9c02f1a2 | j_mayer | /* Clock and power management */
|
2630 | 9c02f1a2 | j_mayer | uint32_t er; |
2631 | 9c02f1a2 | j_mayer | uint32_t fr; |
2632 | 9c02f1a2 | j_mayer | uint32_t sr; |
2633 | 8ecc7913 | j_mayer | }; |
2634 | 8ecc7913 | j_mayer | |
2635 | 8ecc7913 | j_mayer | static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) |
2636 | 8ecc7913 | j_mayer | { |
2637 | 8ecc7913 | j_mayer | uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; |
2638 | 8ecc7913 | j_mayer | uint32_t UART0_clk, UART1_clk; |
2639 | 8ecc7913 | j_mayer | uint64_t VCO_out, PLL_out; |
2640 | 8ecc7913 | j_mayer | int M, D;
|
2641 | 8ecc7913 | j_mayer | |
2642 | 8ecc7913 | j_mayer | VCO_out = 0;
|
2643 | 8ecc7913 | j_mayer | if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { |
2644 | 8ecc7913 | j_mayer | M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ |
2645 | 8ecc7913 | j_mayer | // printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
|
2646 | 8ecc7913 | j_mayer | D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ |
2647 | 8ecc7913 | j_mayer | // printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
|
2648 | 8ecc7913 | j_mayer | VCO_out = cpc->sysclk * M * D; |
2649 | 8ecc7913 | j_mayer | if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { |
2650 | 8ecc7913 | j_mayer | /* Error - unlock the PLL */
|
2651 | 8ecc7913 | j_mayer | printf("VCO out of range %" PRIu64 "\n", VCO_out); |
2652 | 8ecc7913 | j_mayer | #if 0
|
2653 | 8ecc7913 | j_mayer | cpc->pllmr[1] &= ~0x80000000;
|
2654 | 8ecc7913 | j_mayer | goto pll_bypass;
|
2655 | 8ecc7913 | j_mayer | #endif
|
2656 | 8ecc7913 | j_mayer | } |
2657 | 8ecc7913 | j_mayer | PLL_out = VCO_out / D; |
2658 | 9c02f1a2 | j_mayer | /* Pretend the PLL is locked */
|
2659 | 9c02f1a2 | j_mayer | cpc->boot |= 0x00000001;
|
2660 | 8ecc7913 | j_mayer | } else {
|
2661 | 8ecc7913 | j_mayer | #if 0
|
2662 | 8ecc7913 | j_mayer | pll_bypass:
|
2663 | 8ecc7913 | j_mayer | #endif
|
2664 | 8ecc7913 | j_mayer | PLL_out = cpc->sysclk; |
2665 | 9c02f1a2 | j_mayer | if (cpc->pllmr[1] & 0x40000000) { |
2666 | 9c02f1a2 | j_mayer | /* Pretend the PLL is not locked */
|
2667 | 9c02f1a2 | j_mayer | cpc->boot &= ~0x00000001;
|
2668 | 9c02f1a2 | j_mayer | } |
2669 | 8ecc7913 | j_mayer | } |
2670 | 8ecc7913 | j_mayer | /* Now, compute all other clocks */
|
2671 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ |
2672 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
2673 | 8ecc7913 | j_mayer | // printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
|
2674 | 8ecc7913 | j_mayer | #endif
|
2675 | 8ecc7913 | j_mayer | CPU_clk = PLL_out / D; |
2676 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ |
2677 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
2678 | 8ecc7913 | j_mayer | // printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
|
2679 | 8ecc7913 | j_mayer | #endif
|
2680 | 8ecc7913 | j_mayer | PLB_clk = CPU_clk / D; |
2681 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ |
2682 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
2683 | 8ecc7913 | j_mayer | // printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
|
2684 | 8ecc7913 | j_mayer | #endif
|
2685 | 8ecc7913 | j_mayer | OPB_clk = PLB_clk / D; |
2686 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ |
2687 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
2688 | 8ecc7913 | j_mayer | // printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
|
2689 | 8ecc7913 | j_mayer | #endif
|
2690 | 8ecc7913 | j_mayer | EBC_clk = PLB_clk / D; |
2691 | 8ecc7913 | j_mayer | D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ |
2692 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
2693 | 8ecc7913 | j_mayer | // printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
|
2694 | 8ecc7913 | j_mayer | #endif
|
2695 | 8ecc7913 | j_mayer | MAL_clk = PLB_clk / D; |
2696 | 8ecc7913 | j_mayer | D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ |
2697 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
2698 | 8ecc7913 | j_mayer | // printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D);
|
2699 | 8ecc7913 | j_mayer | #endif
|
2700 | 8ecc7913 | j_mayer | PCI_clk = PLB_clk / D; |
2701 | 8ecc7913 | j_mayer | D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ |
2702 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
2703 | 8ecc7913 | j_mayer | // printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D);
|
2704 | 8ecc7913 | j_mayer | #endif
|
2705 | 8ecc7913 | j_mayer | UART0_clk = PLL_out / D; |
2706 | 8ecc7913 | j_mayer | D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ |
2707 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
2708 | 8ecc7913 | j_mayer | // printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D);
|
2709 | 8ecc7913 | j_mayer | #endif
|
2710 | 8ecc7913 | j_mayer | UART1_clk = PLL_out / D; |
2711 | 8ecc7913 | j_mayer | #ifdef DEBUG_CLOCKS
|
2712 | 8ecc7913 | j_mayer | printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64
|
2713 | 8ecc7913 | j_mayer | " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); |
2714 | 8ecc7913 | j_mayer | printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n",
|
2715 | 8ecc7913 | j_mayer | CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, |
2716 | 8ecc7913 | j_mayer | UART0_clk, UART1_clk); |
2717 | 9c02f1a2 | j_mayer | printf("CB %p opaque %p\n", cpc->clk_setup[PPC405EP_CPU_CLK].cb,
|
2718 | 9c02f1a2 | j_mayer | cpc->clk_setup[PPC405EP_CPU_CLK].opaque); |
2719 | 8ecc7913 | j_mayer | #endif
|
2720 | 8ecc7913 | j_mayer | /* Setup CPU clocks */
|
2721 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); |
2722 | 8ecc7913 | j_mayer | /* Setup PLB clock */
|
2723 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); |
2724 | 8ecc7913 | j_mayer | /* Setup OPB clock */
|
2725 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); |
2726 | 8ecc7913 | j_mayer | /* Setup external clock */
|
2727 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); |
2728 | 8ecc7913 | j_mayer | /* Setup MAL clock */
|
2729 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); |
2730 | 8ecc7913 | j_mayer | /* Setup PCI clock */
|
2731 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); |
2732 | 8ecc7913 | j_mayer | /* Setup UART0 clock */
|
2733 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); |
2734 | 8ecc7913 | j_mayer | /* Setup UART1 clock */
|
2735 | 04f20795 | j_mayer | clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); |
2736 | 8ecc7913 | j_mayer | } |
2737 | 8ecc7913 | j_mayer | |
2738 | 8ecc7913 | j_mayer | static target_ulong dcr_read_epcpc (void *opaque, int dcrn) |
2739 | 8ecc7913 | j_mayer | { |
2740 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc; |
2741 | 8ecc7913 | j_mayer | target_ulong ret; |
2742 | 8ecc7913 | j_mayer | |
2743 | 8ecc7913 | j_mayer | cpc = opaque; |
2744 | 8ecc7913 | j_mayer | switch (dcrn) {
|
2745 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_BOOT:
|
2746 | 8ecc7913 | j_mayer | ret = cpc->boot; |
2747 | 8ecc7913 | j_mayer | break;
|
2748 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_EPCTL:
|
2749 | 8ecc7913 | j_mayer | ret = cpc->epctl; |
2750 | 8ecc7913 | j_mayer | break;
|
2751 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR0:
|
2752 | 8ecc7913 | j_mayer | ret = cpc->pllmr[0];
|
2753 | 8ecc7913 | j_mayer | break;
|
2754 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR1:
|
2755 | 8ecc7913 | j_mayer | ret = cpc->pllmr[1];
|
2756 | 8ecc7913 | j_mayer | break;
|
2757 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_UCR:
|
2758 | 8ecc7913 | j_mayer | ret = cpc->ucr; |
2759 | 8ecc7913 | j_mayer | break;
|
2760 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_SRR:
|
2761 | 8ecc7913 | j_mayer | ret = cpc->srr; |
2762 | 8ecc7913 | j_mayer | break;
|
2763 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_JTAGID:
|
2764 | 8ecc7913 | j_mayer | ret = cpc->jtagid; |
2765 | 8ecc7913 | j_mayer | break;
|
2766 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PCI:
|
2767 | 8ecc7913 | j_mayer | ret = cpc->pci; |
2768 | 8ecc7913 | j_mayer | break;
|
2769 | 8ecc7913 | j_mayer | default:
|
2770 | 8ecc7913 | j_mayer | /* Avoid gcc warning */
|
2771 | 8ecc7913 | j_mayer | ret = 0;
|
2772 | 8ecc7913 | j_mayer | break;
|
2773 | 8ecc7913 | j_mayer | } |
2774 | 8ecc7913 | j_mayer | |
2775 | 8ecc7913 | j_mayer | return ret;
|
2776 | 8ecc7913 | j_mayer | } |
2777 | 8ecc7913 | j_mayer | |
2778 | 8ecc7913 | j_mayer | static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val) |
2779 | 8ecc7913 | j_mayer | { |
2780 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc; |
2781 | 8ecc7913 | j_mayer | |
2782 | 8ecc7913 | j_mayer | cpc = opaque; |
2783 | 8ecc7913 | j_mayer | switch (dcrn) {
|
2784 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_BOOT:
|
2785 | 8ecc7913 | j_mayer | /* Read-only register */
|
2786 | 8ecc7913 | j_mayer | break;
|
2787 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_EPCTL:
|
2788 | 8ecc7913 | j_mayer | /* Don't care for now */
|
2789 | 8ecc7913 | j_mayer | cpc->epctl = val & 0xC00000F3;
|
2790 | 8ecc7913 | j_mayer | break;
|
2791 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR0:
|
2792 | 8ecc7913 | j_mayer | cpc->pllmr[0] = val & 0x00633333; |
2793 | 8ecc7913 | j_mayer | ppc405ep_compute_clocks(cpc); |
2794 | 8ecc7913 | j_mayer | break;
|
2795 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PLLMR1:
|
2796 | 8ecc7913 | j_mayer | cpc->pllmr[1] = val & 0xC0F73FFF; |
2797 | 8ecc7913 | j_mayer | ppc405ep_compute_clocks(cpc); |
2798 | 8ecc7913 | j_mayer | break;
|
2799 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_UCR:
|
2800 | 8ecc7913 | j_mayer | /* UART control - don't care for now */
|
2801 | 8ecc7913 | j_mayer | cpc->ucr = val & 0x003F7F7F;
|
2802 | 8ecc7913 | j_mayer | break;
|
2803 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_SRR:
|
2804 | 8ecc7913 | j_mayer | cpc->srr = val; |
2805 | 8ecc7913 | j_mayer | break;
|
2806 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_JTAGID:
|
2807 | 8ecc7913 | j_mayer | /* Read-only */
|
2808 | 8ecc7913 | j_mayer | break;
|
2809 | 8ecc7913 | j_mayer | case PPC405EP_CPC0_PCI:
|
2810 | 8ecc7913 | j_mayer | cpc->pci = val; |
2811 | 8ecc7913 | j_mayer | break;
|
2812 | 8ecc7913 | j_mayer | } |
2813 | 8ecc7913 | j_mayer | } |
2814 | 8ecc7913 | j_mayer | |
2815 | 8ecc7913 | j_mayer | static void ppc405ep_cpc_reset (void *opaque) |
2816 | 8ecc7913 | j_mayer | { |
2817 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc = opaque; |
2818 | 8ecc7913 | j_mayer | |
2819 | 8ecc7913 | j_mayer | cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ |
2820 | 8ecc7913 | j_mayer | cpc->epctl = 0x00000000;
|
2821 | 8ecc7913 | j_mayer | cpc->pllmr[0] = 0x00011010; |
2822 | 8ecc7913 | j_mayer | cpc->pllmr[1] = 0x40000000; |
2823 | 8ecc7913 | j_mayer | cpc->ucr = 0x00000000;
|
2824 | 8ecc7913 | j_mayer | cpc->srr = 0x00040000;
|
2825 | 8ecc7913 | j_mayer | cpc->pci = 0x00000000;
|
2826 | 9c02f1a2 | j_mayer | cpc->er = 0x00000000;
|
2827 | 9c02f1a2 | j_mayer | cpc->fr = 0x00000000;
|
2828 | 9c02f1a2 | j_mayer | cpc->sr = 0x00000000;
|
2829 | 8ecc7913 | j_mayer | ppc405ep_compute_clocks(cpc); |
2830 | 8ecc7913 | j_mayer | } |
2831 | 8ecc7913 | j_mayer | |
2832 | 8ecc7913 | j_mayer | /* XXX: sysclk should be between 25 and 100 MHz */
|
2833 | 8ecc7913 | j_mayer | static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], |
2834 | 8ecc7913 | j_mayer | uint32_t sysclk) |
2835 | 8ecc7913 | j_mayer | { |
2836 | 8ecc7913 | j_mayer | ppc405ep_cpc_t *cpc; |
2837 | 8ecc7913 | j_mayer | |
2838 | 8ecc7913 | j_mayer | cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
|
2839 | 8ecc7913 | j_mayer | if (cpc != NULL) { |
2840 | 04f20795 | j_mayer | memcpy(cpc->clk_setup, clk_setup, |
2841 | 04f20795 | j_mayer | PPC405EP_CLK_NB * sizeof(clk_setup_t));
|
2842 | 8ecc7913 | j_mayer | cpc->jtagid = 0x20267049;
|
2843 | 8ecc7913 | j_mayer | cpc->sysclk = sysclk; |
2844 | 8ecc7913 | j_mayer | ppc405ep_cpc_reset(cpc); |
2845 | 8ecc7913 | j_mayer | qemu_register_reset(&ppc405ep_cpc_reset, cpc); |
2846 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, |
2847 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
2848 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, |
2849 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
2850 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, |
2851 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
2852 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, |
2853 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
2854 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, |
2855 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
2856 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, |
2857 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
2858 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, |
2859 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
2860 | 8ecc7913 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, |
2861 | 8ecc7913 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc); |
2862 | 9c02f1a2 | j_mayer | #if 0
|
2863 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
|
2864 | 9c02f1a2 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc);
|
2865 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
|
2866 | 9c02f1a2 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc);
|
2867 | 9c02f1a2 | j_mayer | ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
|
2868 | 9c02f1a2 | j_mayer | &dcr_read_epcpc, &dcr_write_epcpc);
|
2869 | 9c02f1a2 | j_mayer | #endif
|
2870 | 8ecc7913 | j_mayer | } |
2871 | 8ecc7913 | j_mayer | } |
2872 | 8ecc7913 | j_mayer | |
2873 | 71db710f | blueswir1 | CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
|
2874 | 71db710f | blueswir1 | target_phys_addr_t ram_sizes[2],
|
2875 | 8ecc7913 | j_mayer | uint32_t sysclk, qemu_irq **picp, |
2876 | 04f20795 | j_mayer | ram_addr_t *offsetp, int do_init)
|
2877 | 8ecc7913 | j_mayer | { |
2878 | 9c02f1a2 | j_mayer | clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
2879 | 9c02f1a2 | j_mayer | qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
2880 | 8ecc7913 | j_mayer | CPUState *env; |
2881 | 8ecc7913 | j_mayer | ppc4xx_mmio_t *mmio; |
2882 | 8ecc7913 | j_mayer | qemu_irq *pic, *irqs; |
2883 | 8ecc7913 | j_mayer | ram_addr_t offset; |
2884 | 8ecc7913 | j_mayer | int i;
|
2885 | 8ecc7913 | j_mayer | |
2886 | 8ecc7913 | j_mayer | memset(clk_setup, 0, sizeof(clk_setup)); |
2887 | 8ecc7913 | j_mayer | /* init CPUs */
|
2888 | 008ff9d7 | j_mayer | env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
|
2889 | 9c02f1a2 | j_mayer | &tlb_clk_setup, sysclk); |
2890 | 9c02f1a2 | j_mayer | clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; |
2891 | 9c02f1a2 | j_mayer | clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; |
2892 | 8ecc7913 | j_mayer | /* Internal devices init */
|
2893 | 8ecc7913 | j_mayer | /* Memory mapped devices registers */
|
2894 | 8ecc7913 | j_mayer | mmio = ppc4xx_mmio_init(env, 0xEF600000);
|
2895 | 8ecc7913 | j_mayer | /* PLB arbitrer */
|
2896 | 8ecc7913 | j_mayer | ppc4xx_plb_init(env); |
2897 | 8ecc7913 | j_mayer | /* PLB to OPB bridge */
|
2898 | 8ecc7913 | j_mayer | ppc4xx_pob_init(env); |
2899 | 8ecc7913 | j_mayer | /* OBP arbitrer */
|
2900 | 8ecc7913 | j_mayer | ppc4xx_opba_init(env, mmio, 0x600);
|
2901 | 8ecc7913 | j_mayer | /* Universal interrupt controller */
|
2902 | 8ecc7913 | j_mayer | irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
2903 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_INT] = |
2904 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
2905 | 8ecc7913 | j_mayer | irqs[PPCUIC_OUTPUT_CINT] = |
2906 | b48d7d69 | j_mayer | ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
2907 | 8ecc7913 | j_mayer | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
2908 | 8ecc7913 | j_mayer | *picp = pic; |
2909 | 8ecc7913 | j_mayer | /* SDRAM controller */
|
2910 | 04f20795 | j_mayer | ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init); |
2911 | 8ecc7913 | j_mayer | offset = 0;
|
2912 | 8ecc7913 | j_mayer | for (i = 0; i < 2; i++) |
2913 | 8ecc7913 | j_mayer | offset += ram_sizes[i]; |
2914 | 8ecc7913 | j_mayer | /* External bus controller */
|
2915 | 8ecc7913 | j_mayer | ppc405_ebc_init(env); |
2916 | 8ecc7913 | j_mayer | /* DMA controller */
|
2917 | 04f20795 | j_mayer | dma_irqs[0] = pic[26]; |
2918 | 04f20795 | j_mayer | dma_irqs[1] = pic[25]; |
2919 | 04f20795 | j_mayer | dma_irqs[2] = pic[24]; |
2920 | 04f20795 | j_mayer | dma_irqs[3] = pic[23]; |
2921 | 8ecc7913 | j_mayer | ppc405_dma_init(env, dma_irqs); |
2922 | 8ecc7913 | j_mayer | /* IIC controller */
|
2923 | 9c02f1a2 | j_mayer | ppc405_i2c_init(env, mmio, 0x500, pic[29]); |
2924 | 8ecc7913 | j_mayer | /* GPIO */
|
2925 | 8ecc7913 | j_mayer | ppc405_gpio_init(env, mmio, 0x700);
|
2926 | 8ecc7913 | j_mayer | /* Serial ports */
|
2927 | 8ecc7913 | j_mayer | if (serial_hds[0] != NULL) { |
2928 | 04f20795 | j_mayer | ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]); |
2929 | 8ecc7913 | j_mayer | } |
2930 | 8ecc7913 | j_mayer | if (serial_hds[1] != NULL) { |
2931 | 04f20795 | j_mayer | ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]); |
2932 | 8ecc7913 | j_mayer | } |
2933 | 8ecc7913 | j_mayer | /* OCM */
|
2934 | 8ecc7913 | j_mayer | ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]); |
2935 | 8ecc7913 | j_mayer | offset += 4096;
|
2936 | 9c02f1a2 | j_mayer | /* GPT */
|
2937 | 9c02f1a2 | j_mayer | gpt_irqs[0] = pic[12]; |
2938 | 9c02f1a2 | j_mayer | gpt_irqs[1] = pic[11]; |
2939 | 9c02f1a2 | j_mayer | gpt_irqs[2] = pic[10]; |
2940 | 9c02f1a2 | j_mayer | gpt_irqs[3] = pic[9]; |
2941 | 9c02f1a2 | j_mayer | gpt_irqs[4] = pic[8]; |
2942 | 9c02f1a2 | j_mayer | ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
|
2943 | 8ecc7913 | j_mayer | /* PCI */
|
2944 | 9c02f1a2 | j_mayer | /* Uses pic[28], pic[15], pic[13] */
|
2945 | 9c02f1a2 | j_mayer | /* MAL */
|
2946 | 9c02f1a2 | j_mayer | mal_irqs[0] = pic[20]; |
2947 | 9c02f1a2 | j_mayer | mal_irqs[1] = pic[19]; |
2948 | 9c02f1a2 | j_mayer | mal_irqs[2] = pic[18]; |
2949 | 9c02f1a2 | j_mayer | mal_irqs[3] = pic[17]; |
2950 | 9c02f1a2 | j_mayer | ppc405_mal_init(env, mal_irqs); |
2951 | 9c02f1a2 | j_mayer | /* Ethernet */
|
2952 | 9c02f1a2 | j_mayer | /* Uses pic[22], pic[16], pic[14] */
|
2953 | 8ecc7913 | j_mayer | /* CPU control */
|
2954 | 8ecc7913 | j_mayer | ppc405ep_cpc_init(env, clk_setup, sysclk); |
2955 | 8ecc7913 | j_mayer | *offsetp = offset; |
2956 | 8ecc7913 | j_mayer | |
2957 | 8ecc7913 | j_mayer | return env;
|
2958 | 8ecc7913 | j_mayer | } |