Revision 008ff9d7 hw/ppc405.h

b/hw/ppc405.h
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#if !defined(PPC_405_H)
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#define PPC_405_H
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#include "ppc4xx.h"
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/* Bootinfo as set-up by u-boot */
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typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
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struct ppc4xx_bd_info_t {
......
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};
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/* PowerPC 405 core */
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CPUState *ppc405_init (const unsigned char *cpu_model,
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                       clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
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                       uint32_t sysclk);
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ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
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                                uint32_t flags);
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/* */
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typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
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int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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                          target_phys_addr_t offset, uint32_t len,
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                          CPUReadMemoryFunc **mem_read,
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                          CPUWriteMemoryFunc **mem_write, void *opaque);
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ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base);
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/* PowerPC 4xx peripheral local bus arbitrer */
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void ppc4xx_plb_init (CPUState *env);
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/* PLB to OPB bridge */
......
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/* OPB arbitrer */
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void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
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                       target_phys_addr_t offset);
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/* PowerPC 4xx universal interrupt controller */
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enum {
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    PPCUIC_OUTPUT_INT = 0,
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    PPCUIC_OUTPUT_CINT = 1,
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    PPCUIC_OUTPUT_NB,
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};
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qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
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                       uint32_t dcr_base, int has_ssr, int has_vr);
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/* SDRAM controller */
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void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
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                        target_phys_addr_t *ram_bases,

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