Revision 008ff9d7 hw/ppc405_uc.c
| b/hw/ppc405_uc.c | ||
|---|---|---|
| 27 | 27 |
extern int loglevel; |
| 28 | 28 |
extern FILE *logfile; |
| 29 | 29 |
|
| 30 |
//#define DEBUG_MMIO |
|
| 31 | 30 |
#define DEBUG_OPBA |
| 32 | 31 |
#define DEBUG_SDRAM |
| 33 | 32 |
#define DEBUG_GPIO |
| ... | ... | |
| 36 | 35 |
//#define DEBUG_I2C |
| 37 | 36 |
#define DEBUG_GPT |
| 38 | 37 |
#define DEBUG_MAL |
| 39 |
#define DEBUG_UIC |
|
| 40 | 38 |
#define DEBUG_CLOCKS |
| 41 | 39 |
//#define DEBUG_UNASSIGNED |
| 42 | 40 |
|
| 43 |
/*****************************************************************************/ |
|
| 44 |
/* Generic PowerPC 405 processor instanciation */ |
|
| 45 |
CPUState *ppc405_init (const unsigned char *cpu_model, |
|
| 46 |
clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
|
| 47 |
uint32_t sysclk) |
|
| 48 |
{
|
|
| 49 |
CPUState *env; |
|
| 50 |
ppc_def_t *def; |
|
| 51 |
|
|
| 52 |
/* init CPUs */ |
|
| 53 |
env = cpu_init(); |
|
| 54 |
ppc_find_by_name(cpu_model, &def); |
|
| 55 |
if (def == NULL) {
|
|
| 56 |
cpu_abort(env, "Unable to find PowerPC %s CPU definition\n", |
|
| 57 |
cpu_model); |
|
| 58 |
} |
|
| 59 |
cpu_ppc_register(env, def); |
|
| 60 |
cpu_ppc_reset(env); |
|
| 61 |
cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ |
|
| 62 |
cpu_clk->opaque = env; |
|
| 63 |
/* Set time-base frequency to sysclk */ |
|
| 64 |
tb_clk->cb = ppc_emb_timers_init(env, sysclk); |
|
| 65 |
tb_clk->opaque = env; |
|
| 66 |
ppc_dcr_init(env, NULL, NULL); |
|
| 67 |
/* Register Qemu callbacks */ |
|
| 68 |
qemu_register_reset(&cpu_ppc_reset, env); |
|
| 69 |
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
|
|
| 70 |
|
|
| 71 |
return env; |
|
| 72 |
} |
|
| 73 |
|
|
| 74 | 41 |
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
| 75 | 42 |
uint32_t flags) |
| 76 | 43 |
{
|
| ... | ... | |
| 124 | 91 |
/* Shared peripherals */ |
| 125 | 92 |
|
| 126 | 93 |
/*****************************************************************************/ |
| 127 |
/* Fake device used to map multiple devices in a single memory page */ |
|
| 128 |
#define MMIO_AREA_BITS 8 |
|
| 129 |
#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS) |
|
| 130 |
#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS)) |
|
| 131 |
#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1)) |
|
| 132 |
struct ppc4xx_mmio_t {
|
|
| 133 |
target_phys_addr_t base; |
|
| 134 |
CPUReadMemoryFunc **mem_read[MMIO_AREA_NB]; |
|
| 135 |
CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB]; |
|
| 136 |
void *opaque[MMIO_AREA_NB]; |
|
| 137 |
}; |
|
| 138 |
|
|
| 139 |
static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr) |
|
| 140 |
{
|
|
| 141 |
#ifdef DEBUG_UNASSIGNED |
|
| 142 |
ppc4xx_mmio_t *mmio; |
|
| 143 |
|
|
| 144 |
mmio = opaque; |
|
| 145 |
printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
|
|
| 146 |
addr, mmio->base); |
|
| 147 |
#endif |
|
| 148 |
|
|
| 149 |
return 0; |
|
| 150 |
} |
|
| 151 |
|
|
| 152 |
static void unassigned_mmio_writeb (void *opaque, |
|
| 153 |
target_phys_addr_t addr, uint32_t val) |
|
| 154 |
{
|
|
| 155 |
#ifdef DEBUG_UNASSIGNED |
|
| 156 |
ppc4xx_mmio_t *mmio; |
|
| 157 |
|
|
| 158 |
mmio = opaque; |
|
| 159 |
printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
|
|
| 160 |
addr, val, mmio->base); |
|
| 161 |
#endif |
|
| 162 |
} |
|
| 163 |
|
|
| 164 |
static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
|
|
| 165 |
unassigned_mmio_readb, |
|
| 166 |
unassigned_mmio_readb, |
|
| 167 |
unassigned_mmio_readb, |
|
| 168 |
}; |
|
| 169 |
|
|
| 170 |
static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
|
|
| 171 |
unassigned_mmio_writeb, |
|
| 172 |
unassigned_mmio_writeb, |
|
| 173 |
unassigned_mmio_writeb, |
|
| 174 |
}; |
|
| 175 |
|
|
| 176 |
static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio, |
|
| 177 |
target_phys_addr_t addr, int len) |
|
| 178 |
{
|
|
| 179 |
CPUReadMemoryFunc **mem_read; |
|
| 180 |
uint32_t ret; |
|
| 181 |
int idx; |
|
| 182 |
|
|
| 183 |
idx = MMIO_IDX(addr - mmio->base); |
|
| 184 |
#if defined(DEBUG_MMIO) |
|
| 185 |
printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
|
|
| 186 |
mmio, len, addr, idx); |
|
| 187 |
#endif |
|
| 188 |
mem_read = mmio->mem_read[idx]; |
|
| 189 |
ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base); |
|
| 190 |
|
|
| 191 |
return ret; |
|
| 192 |
} |
|
| 193 |
|
|
| 194 |
static void mmio_writelen (ppc4xx_mmio_t *mmio, |
|
| 195 |
target_phys_addr_t addr, uint32_t value, int len) |
|
| 196 |
{
|
|
| 197 |
CPUWriteMemoryFunc **mem_write; |
|
| 198 |
int idx; |
|
| 199 |
|
|
| 200 |
idx = MMIO_IDX(addr - mmio->base); |
|
| 201 |
#if defined(DEBUG_MMIO) |
|
| 202 |
printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,
|
|
| 203 |
mmio, len, addr, idx, value); |
|
| 204 |
#endif |
|
| 205 |
mem_write = mmio->mem_write[idx]; |
|
| 206 |
(*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value); |
|
| 207 |
} |
|
| 208 |
|
|
| 209 |
static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr) |
|
| 210 |
{
|
|
| 211 |
#if defined(DEBUG_MMIO) |
|
| 212 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
| 213 |
#endif |
|
| 214 |
|
|
| 215 |
return mmio_readlen(opaque, addr, 0); |
|
| 216 |
} |
|
| 217 |
|
|
| 218 |
static void mmio_writeb (void *opaque, |
|
| 219 |
target_phys_addr_t addr, uint32_t value) |
|
| 220 |
{
|
|
| 221 |
#if defined(DEBUG_MMIO) |
|
| 222 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
|
|
| 223 |
#endif |
|
| 224 |
mmio_writelen(opaque, addr, value, 0); |
|
| 225 |
} |
|
| 226 |
|
|
| 227 |
static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr) |
|
| 228 |
{
|
|
| 229 |
#if defined(DEBUG_MMIO) |
|
| 230 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
| 231 |
#endif |
|
| 232 |
|
|
| 233 |
return mmio_readlen(opaque, addr, 1); |
|
| 234 |
} |
|
| 235 |
|
|
| 236 |
static void mmio_writew (void *opaque, |
|
| 237 |
target_phys_addr_t addr, uint32_t value) |
|
| 238 |
{
|
|
| 239 |
#if defined(DEBUG_MMIO) |
|
| 240 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
|
|
| 241 |
#endif |
|
| 242 |
mmio_writelen(opaque, addr, value, 1); |
|
| 243 |
} |
|
| 244 |
|
|
| 245 |
static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr) |
|
| 246 |
{
|
|
| 247 |
#if defined(DEBUG_MMIO) |
|
| 248 |
printf("%s: addr " PADDRX "\n", __func__, addr);
|
|
| 249 |
#endif |
|
| 250 |
|
|
| 251 |
return mmio_readlen(opaque, addr, 2); |
|
| 252 |
} |
|
| 253 |
|
|
| 254 |
static void mmio_writel (void *opaque, |
|
| 255 |
target_phys_addr_t addr, uint32_t value) |
|
| 256 |
{
|
|
| 257 |
#if defined(DEBUG_MMIO) |
|
| 258 |
printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);
|
|
| 259 |
#endif |
|
| 260 |
mmio_writelen(opaque, addr, value, 2); |
|
| 261 |
} |
|
| 262 |
|
|
| 263 |
static CPUReadMemoryFunc *mmio_read[] = {
|
|
| 264 |
&mmio_readb, |
|
| 265 |
&mmio_readw, |
|
| 266 |
&mmio_readl, |
|
| 267 |
}; |
|
| 268 |
|
|
| 269 |
static CPUWriteMemoryFunc *mmio_write[] = {
|
|
| 270 |
&mmio_writeb, |
|
| 271 |
&mmio_writew, |
|
| 272 |
&mmio_writel, |
|
| 273 |
}; |
|
| 274 |
|
|
| 275 |
int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio, |
|
| 276 |
target_phys_addr_t offset, uint32_t len, |
|
| 277 |
CPUReadMemoryFunc **mem_read, |
|
| 278 |
CPUWriteMemoryFunc **mem_write, void *opaque) |
|
| 279 |
{
|
|
| 280 |
uint32_t end; |
|
| 281 |
int idx, eidx; |
|
| 282 |
|
|
| 283 |
if ((offset + len) > TARGET_PAGE_SIZE) |
|
| 284 |
return -1; |
|
| 285 |
idx = MMIO_IDX(offset); |
|
| 286 |
end = offset + len - 1; |
|
| 287 |
eidx = MMIO_IDX(end); |
|
| 288 |
#if defined(DEBUG_MMIO) |
|
| 289 |
printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,
|
|
| 290 |
end, idx, eidx); |
|
| 291 |
#endif |
|
| 292 |
for (; idx <= eidx; idx++) {
|
|
| 293 |
mmio->mem_read[idx] = mem_read; |
|
| 294 |
mmio->mem_write[idx] = mem_write; |
|
| 295 |
mmio->opaque[idx] = opaque; |
|
| 296 |
} |
|
| 297 |
|
|
| 298 |
return 0; |
|
| 299 |
} |
|
| 300 |
|
|
| 301 |
ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base) |
|
| 302 |
{
|
|
| 303 |
ppc4xx_mmio_t *mmio; |
|
| 304 |
int mmio_memory; |
|
| 305 |
|
|
| 306 |
mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t)); |
|
| 307 |
if (mmio != NULL) {
|
|
| 308 |
mmio->base = base; |
|
| 309 |
mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio); |
|
| 310 |
#if defined(DEBUG_MMIO) |
|
| 311 |
printf("%s: %p base %08x len %08x %d\n", __func__,
|
|
| 312 |
mmio, base, TARGET_PAGE_SIZE, mmio_memory); |
|
| 313 |
#endif |
|
| 314 |
cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory); |
|
| 315 |
ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE, |
|
| 316 |
unassigned_mmio_read, unassigned_mmio_write, |
|
| 317 |
mmio); |
|
| 318 |
} |
|
| 319 |
|
|
| 320 |
return mmio; |
|
| 321 |
} |
|
| 322 |
|
|
| 323 |
/*****************************************************************************/ |
|
| 324 | 94 |
/* Peripheral local bus arbitrer */ |
| 325 | 95 |
enum {
|
| 326 | 96 |
PLB0_BESR = 0x084, |
| ... | ... | |
| 625 | 395 |
} |
| 626 | 396 |
|
| 627 | 397 |
/*****************************************************************************/ |
| 628 |
/* "Universal" Interrupt controller */ |
|
| 629 |
enum {
|
|
| 630 |
DCR_UICSR = 0x000, |
|
| 631 |
DCR_UICSRS = 0x001, |
|
| 632 |
DCR_UICER = 0x002, |
|
| 633 |
DCR_UICCR = 0x003, |
|
| 634 |
DCR_UICPR = 0x004, |
|
| 635 |
DCR_UICTR = 0x005, |
|
| 636 |
DCR_UICMSR = 0x006, |
|
| 637 |
DCR_UICVR = 0x007, |
|
| 638 |
DCR_UICVCR = 0x008, |
|
| 639 |
DCR_UICMAX = 0x009, |
|
| 640 |
}; |
|
| 641 |
|
|
| 642 |
#define UIC_MAX_IRQ 32 |
|
| 643 |
typedef struct ppcuic_t ppcuic_t; |
|
| 644 |
struct ppcuic_t {
|
|
| 645 |
uint32_t dcr_base; |
|
| 646 |
int use_vectors; |
|
| 647 |
uint32_t uicsr; /* Status register */ |
|
| 648 |
uint32_t uicer; /* Enable register */ |
|
| 649 |
uint32_t uiccr; /* Critical register */ |
|
| 650 |
uint32_t uicpr; /* Polarity register */ |
|
| 651 |
uint32_t uictr; /* Triggering register */ |
|
| 652 |
uint32_t uicvcr; /* Vector configuration register */ |
|
| 653 |
uint32_t uicvr; |
|
| 654 |
qemu_irq *irqs; |
|
| 655 |
}; |
|
| 656 |
|
|
| 657 |
static void ppcuic_trigger_irq (ppcuic_t *uic) |
|
| 658 |
{
|
|
| 659 |
uint32_t ir, cr; |
|
| 660 |
int start, end, inc, i; |
|
| 661 |
|
|
| 662 |
/* Trigger interrupt if any is pending */ |
|
| 663 |
ir = uic->uicsr & uic->uicer & (~uic->uiccr); |
|
| 664 |
cr = uic->uicsr & uic->uicer & uic->uiccr; |
|
| 665 |
#ifdef DEBUG_UIC |
|
| 666 |
if (loglevel & CPU_LOG_INT) {
|
|
| 667 |
fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n" |
|
| 668 |
" %08x ir %08x cr %08x\n", __func__, |
|
| 669 |
uic->uicsr, uic->uicer, uic->uiccr, |
|
| 670 |
uic->uicsr & uic->uicer, ir, cr); |
|
| 671 |
} |
|
| 672 |
#endif |
|
| 673 |
if (ir != 0x0000000) {
|
|
| 674 |
#ifdef DEBUG_UIC |
|
| 675 |
if (loglevel & CPU_LOG_INT) {
|
|
| 676 |
fprintf(logfile, "Raise UIC interrupt\n"); |
|
| 677 |
} |
|
| 678 |
#endif |
|
| 679 |
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
|
| 680 |
} else {
|
|
| 681 |
#ifdef DEBUG_UIC |
|
| 682 |
if (loglevel & CPU_LOG_INT) {
|
|
| 683 |
fprintf(logfile, "Lower UIC interrupt\n"); |
|
| 684 |
} |
|
| 685 |
#endif |
|
| 686 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
|
| 687 |
} |
|
| 688 |
/* Trigger critical interrupt if any is pending and update vector */ |
|
| 689 |
if (cr != 0x0000000) {
|
|
| 690 |
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); |
|
| 691 |
if (uic->use_vectors) {
|
|
| 692 |
/* Compute critical IRQ vector */ |
|
| 693 |
if (uic->uicvcr & 1) {
|
|
| 694 |
start = 31; |
|
| 695 |
end = 0; |
|
| 696 |
inc = -1; |
|
| 697 |
} else {
|
|
| 698 |
start = 0; |
|
| 699 |
end = 31; |
|
| 700 |
inc = 1; |
|
| 701 |
} |
|
| 702 |
uic->uicvr = uic->uicvcr & 0xFFFFFFFC; |
|
| 703 |
for (i = start; i <= end; i += inc) {
|
|
| 704 |
if (cr & (1 << i)) {
|
|
| 705 |
uic->uicvr += (i - start) * 512 * inc; |
|
| 706 |
break; |
|
| 707 |
} |
|
| 708 |
} |
|
| 709 |
} |
|
| 710 |
#ifdef DEBUG_UIC |
|
| 711 |
if (loglevel & CPU_LOG_INT) {
|
|
| 712 |
fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n", |
|
| 713 |
uic->uicvr); |
|
| 714 |
} |
|
| 715 |
#endif |
|
| 716 |
} else {
|
|
| 717 |
#ifdef DEBUG_UIC |
|
| 718 |
if (loglevel & CPU_LOG_INT) {
|
|
| 719 |
fprintf(logfile, "Lower UIC critical interrupt\n"); |
|
| 720 |
} |
|
| 721 |
#endif |
|
| 722 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
|
| 723 |
uic->uicvr = 0x00000000; |
|
| 724 |
} |
|
| 725 |
} |
|
| 726 |
|
|
| 727 |
static void ppcuic_set_irq (void *opaque, int irq_num, int level) |
|
| 728 |
{
|
|
| 729 |
ppcuic_t *uic; |
|
| 730 |
uint32_t mask, sr; |
|
| 731 |
|
|
| 732 |
uic = opaque; |
|
| 733 |
mask = 1 << irq_num; |
|
| 734 |
#ifdef DEBUG_UIC |
|
| 735 |
if (loglevel & CPU_LOG_INT) {
|
|
| 736 |
fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x " |
|
| 737 |
"%08x\n", __func__, irq_num, level, |
|
| 738 |
uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
|
| 739 |
} |
|
| 740 |
#endif |
|
| 741 |
if (irq_num < 0 || irq_num > 31) |
|
| 742 |
return; |
|
| 743 |
sr = uic->uicsr; |
|
| 744 |
if (!(uic->uicpr & mask)) {
|
|
| 745 |
/* Negatively asserted IRQ */ |
|
| 746 |
level = level == 0 ? 1 : 0; |
|
| 747 |
} |
|
| 748 |
/* Update status register */ |
|
| 749 |
if (uic->uictr & mask) {
|
|
| 750 |
/* Edge sensitive interrupt */ |
|
| 751 |
if (level == 1) |
|
| 752 |
uic->uicsr |= mask; |
|
| 753 |
} else {
|
|
| 754 |
/* Level sensitive interrupt */ |
|
| 755 |
if (level == 1) |
|
| 756 |
uic->uicsr |= mask; |
|
| 757 |
else |
|
| 758 |
uic->uicsr &= ~mask; |
|
| 759 |
} |
|
| 760 |
#ifdef DEBUG_UIC |
|
| 761 |
if (loglevel & CPU_LOG_INT) {
|
|
| 762 |
fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__, |
|
| 763 |
irq_num, level, uic->uicsr, sr); |
|
| 764 |
} |
|
| 765 |
#endif |
|
| 766 |
if (sr != uic->uicsr) |
|
| 767 |
ppcuic_trigger_irq(uic); |
|
| 768 |
} |
|
| 769 |
|
|
| 770 |
static target_ulong dcr_read_uic (void *opaque, int dcrn) |
|
| 771 |
{
|
|
| 772 |
ppcuic_t *uic; |
|
| 773 |
target_ulong ret; |
|
| 774 |
|
|
| 775 |
uic = opaque; |
|
| 776 |
dcrn -= uic->dcr_base; |
|
| 777 |
switch (dcrn) {
|
|
| 778 |
case DCR_UICSR: |
|
| 779 |
case DCR_UICSRS: |
|
| 780 |
ret = uic->uicsr; |
|
| 781 |
break; |
|
| 782 |
case DCR_UICER: |
|
| 783 |
ret = uic->uicer; |
|
| 784 |
break; |
|
| 785 |
case DCR_UICCR: |
|
| 786 |
ret = uic->uiccr; |
|
| 787 |
break; |
|
| 788 |
case DCR_UICPR: |
|
| 789 |
ret = uic->uicpr; |
|
| 790 |
break; |
|
| 791 |
case DCR_UICTR: |
|
| 792 |
ret = uic->uictr; |
|
| 793 |
break; |
|
| 794 |
case DCR_UICMSR: |
|
| 795 |
ret = uic->uicsr & uic->uicer; |
|
| 796 |
break; |
|
| 797 |
case DCR_UICVR: |
|
| 798 |
if (!uic->use_vectors) |
|
| 799 |
goto no_read; |
|
| 800 |
ret = uic->uicvr; |
|
| 801 |
break; |
|
| 802 |
case DCR_UICVCR: |
|
| 803 |
if (!uic->use_vectors) |
|
| 804 |
goto no_read; |
|
| 805 |
ret = uic->uicvcr; |
|
| 806 |
break; |
|
| 807 |
default: |
|
| 808 |
no_read: |
|
| 809 |
ret = 0x00000000; |
|
| 810 |
break; |
|
| 811 |
} |
|
| 812 |
|
|
| 813 |
return ret; |
|
| 814 |
} |
|
| 815 |
|
|
| 816 |
static void dcr_write_uic (void *opaque, int dcrn, target_ulong val) |
|
| 817 |
{
|
|
| 818 |
ppcuic_t *uic; |
|
| 819 |
|
|
| 820 |
uic = opaque; |
|
| 821 |
dcrn -= uic->dcr_base; |
|
| 822 |
#ifdef DEBUG_UIC |
|
| 823 |
if (loglevel & CPU_LOG_INT) {
|
|
| 824 |
fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val); |
|
| 825 |
} |
|
| 826 |
#endif |
|
| 827 |
switch (dcrn) {
|
|
| 828 |
case DCR_UICSR: |
|
| 829 |
uic->uicsr &= ~val; |
|
| 830 |
ppcuic_trigger_irq(uic); |
|
| 831 |
break; |
|
| 832 |
case DCR_UICSRS: |
|
| 833 |
uic->uicsr |= val; |
|
| 834 |
ppcuic_trigger_irq(uic); |
|
| 835 |
break; |
|
| 836 |
case DCR_UICER: |
|
| 837 |
uic->uicer = val; |
|
| 838 |
ppcuic_trigger_irq(uic); |
|
| 839 |
break; |
|
| 840 |
case DCR_UICCR: |
|
| 841 |
uic->uiccr = val; |
|
| 842 |
ppcuic_trigger_irq(uic); |
|
| 843 |
break; |
|
| 844 |
case DCR_UICPR: |
|
| 845 |
uic->uicpr = val; |
|
| 846 |
ppcuic_trigger_irq(uic); |
|
| 847 |
break; |
|
| 848 |
case DCR_UICTR: |
|
| 849 |
uic->uictr = val; |
|
| 850 |
ppcuic_trigger_irq(uic); |
|
| 851 |
break; |
|
| 852 |
case DCR_UICMSR: |
|
| 853 |
break; |
|
| 854 |
case DCR_UICVR: |
|
| 855 |
break; |
|
| 856 |
case DCR_UICVCR: |
|
| 857 |
uic->uicvcr = val & 0xFFFFFFFD; |
|
| 858 |
ppcuic_trigger_irq(uic); |
|
| 859 |
break; |
|
| 860 |
} |
|
| 861 |
} |
|
| 862 |
|
|
| 863 |
static void ppcuic_reset (void *opaque) |
|
| 864 |
{
|
|
| 865 |
ppcuic_t *uic; |
|
| 866 |
|
|
| 867 |
uic = opaque; |
|
| 868 |
uic->uiccr = 0x00000000; |
|
| 869 |
uic->uicer = 0x00000000; |
|
| 870 |
uic->uicpr = 0x00000000; |
|
| 871 |
uic->uicsr = 0x00000000; |
|
| 872 |
uic->uictr = 0x00000000; |
|
| 873 |
if (uic->use_vectors) {
|
|
| 874 |
uic->uicvcr = 0x00000000; |
|
| 875 |
uic->uicvr = 0x0000000; |
|
| 876 |
} |
|
| 877 |
} |
|
| 878 |
|
|
| 879 |
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
|
| 880 |
uint32_t dcr_base, int has_ssr, int has_vr) |
|
| 881 |
{
|
|
| 882 |
ppcuic_t *uic; |
|
| 883 |
int i; |
|
| 884 |
|
|
| 885 |
uic = qemu_mallocz(sizeof(ppcuic_t)); |
|
| 886 |
if (uic != NULL) {
|
|
| 887 |
uic->dcr_base = dcr_base; |
|
| 888 |
uic->irqs = irqs; |
|
| 889 |
if (has_vr) |
|
| 890 |
uic->use_vectors = 1; |
|
| 891 |
for (i = 0; i < DCR_UICMAX; i++) {
|
|
| 892 |
ppc_dcr_register(env, dcr_base + i, uic, |
|
| 893 |
&dcr_read_uic, &dcr_write_uic); |
|
| 894 |
} |
|
| 895 |
qemu_register_reset(ppcuic_reset, uic); |
|
| 896 |
ppcuic_reset(uic); |
|
| 897 |
} |
|
| 898 |
|
|
| 899 |
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ); |
|
| 900 |
} |
|
| 901 |
|
|
| 902 |
/*****************************************************************************/ |
|
| 903 | 398 |
/* Code decompression controller */ |
| 904 | 399 |
/* XXX: TODO */ |
| 905 | 400 |
|
| ... | ... | |
| 3040 | 2535 |
int i; |
| 3041 | 2536 |
|
| 3042 | 2537 |
memset(clk_setup, 0, sizeof(clk_setup)); |
| 3043 |
env = ppc405_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
|
| 2538 |
env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
|
|
| 3044 | 2539 |
&clk_setup[PPC405CR_TMR_CLK], sysclk); |
| 3045 | 2540 |
/* Memory mapped devices registers */ |
| 3046 | 2541 |
mmio = ppc4xx_mmio_init(env, 0xEF600000); |
| ... | ... | |
| 3390 | 2885 |
|
| 3391 | 2886 |
memset(clk_setup, 0, sizeof(clk_setup)); |
| 3392 | 2887 |
/* init CPUs */ |
| 3393 |
env = ppc405_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
|
|
| 2888 |
env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
|
|
| 3394 | 2889 |
&tlb_clk_setup, sysclk); |
| 3395 | 2890 |
clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; |
| 3396 | 2891 |
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; |
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