Revision 01b1fa6d

b/target-sparc/translate.c
2920 2920 
                    if (insn & (1 << 12)) {
2921 2921 
                        tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2922 2922 
                    } else {
2923 
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2924 
                        tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2923 
                        tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f);
2925 2924 
                    }
2926 2925 
                } else {                /* register */
2927 2926 
                    rs2 = GET_FIELD(insn, 27, 31);
2928 2927 
                    gen_movl_reg_TN(rs2, cpu_src2);
2929 2928 
                    if (insn & (1 << 12)) {
2930 2929 
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2931 
                        tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2932 2930 
                    } else {
2933 2931 
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2934 
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2935 
                        tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2936 2932 
                    }
2933 
                    tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2937 2934 
                }
2938 2935 
                gen_movl_TN_reg(rd, cpu_dst);
2939 2936 
            } else if (xop == 0x26) { /* srl, V9 srlx */
......
2979 2976 
                    } else {
2980 2977 
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2981 2978 
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2979 
                        tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2982 2980 
                        tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2983 2981 
                    }
2984 2982 
                }

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