root / target-sparc / exec.h @ 01d6a890
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1 | 7a3f1944 | bellard | #ifndef EXEC_SPARC_H
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2 | 7a3f1944 | bellard | #define EXEC_SPARC_H 1 |
3 | 7a3f1944 | bellard | #include "dyngen-exec.h" |
4 | 3475187d | bellard | #include "config.h" |
5 | 7a3f1944 | bellard | |
6 | 01d6a890 | ths | #if defined(__sparc__)
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7 | 01d6a890 | ths | struct CPUSPARCState *env;
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8 | 01d6a890 | ths | #else
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9 | 7a3f1944 | bellard | register struct CPUSPARCState *env asm(AREG0); |
10 | 01d6a890 | ths | #endif
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11 | 01d6a890 | ths | |
12 | af7bf89b | bellard | #ifdef TARGET_SPARC64
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13 | af7bf89b | bellard | #define T0 (env->t0)
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14 | af7bf89b | bellard | #define T1 (env->t1)
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15 | af7bf89b | bellard | #define T2 (env->t2)
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16 | 3475187d | bellard | #define REGWPTR env->regwptr
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17 | af7bf89b | bellard | #else
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18 | 01d6a890 | ths | #if defined(__sparc__)
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19 | 01d6a890 | ths | register uint32_t T0 asm(AREG3); |
20 | 01d6a890 | ths | register uint32_t T1 asm(AREG2); |
21 | 01d6a890 | ths | #else
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22 | 7a3f1944 | bellard | register uint32_t T0 asm(AREG1); |
23 | 7a3f1944 | bellard | register uint32_t T1 asm(AREG2); |
24 | 01d6a890 | ths | #endif
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25 | 3475187d | bellard | |
26 | 3475187d | bellard | #undef REG_REGWPTR // Broken |
27 | 3475187d | bellard | #ifdef REG_REGWPTR
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28 | 01d6a890 | ths | #if defined(__sparc__)
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29 | 01d6a890 | ths | register uint32_t *REGWPTR asm(AREG4); |
30 | 01d6a890 | ths | #else
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31 | 3475187d | bellard | register uint32_t *REGWPTR asm(AREG3); |
32 | 01d6a890 | ths | #endif
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33 | 3475187d | bellard | #define reg_REGWPTR
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34 | 3475187d | bellard | |
35 | 3475187d | bellard | #ifdef AREG4
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36 | 01d6a890 | ths | #if defined(__sparc__)
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37 | 01d6a890 | ths | register uint32_t T2 asm(AREG0); |
38 | 01d6a890 | ths | #else
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39 | 3475187d | bellard | register uint32_t T2 asm(AREG4); |
40 | 01d6a890 | ths | #endif
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41 | 3475187d | bellard | #define reg_T2
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42 | 3475187d | bellard | #else
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43 | 3475187d | bellard | #define T2 (env->t2)
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44 | 3475187d | bellard | #endif
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45 | 3475187d | bellard | |
46 | 3475187d | bellard | #else
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47 | 3475187d | bellard | #define REGWPTR env->regwptr
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48 | 01d6a890 | ths | #if defined(__sparc__)
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49 | 01d6a890 | ths | register uint32_t T2 asm(AREG0); |
50 | 01d6a890 | ths | #else
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51 | 7a3f1944 | bellard | register uint32_t T2 asm(AREG3); |
52 | 01d6a890 | ths | #endif
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53 | 3475187d | bellard | #define reg_T2
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54 | 3475187d | bellard | #endif
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55 | af7bf89b | bellard | #endif
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56 | 3475187d | bellard | |
57 | e8af50a3 | bellard | #define FT0 (env->ft0)
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58 | e8af50a3 | bellard | #define FT1 (env->ft1)
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59 | e8af50a3 | bellard | #define DT0 (env->dt0)
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60 | e8af50a3 | bellard | #define DT1 (env->dt1)
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61 | 7a3f1944 | bellard | |
62 | 7a3f1944 | bellard | #include "cpu.h" |
63 | 7a3f1944 | bellard | #include "exec-all.h" |
64 | 7a3f1944 | bellard | |
65 | 7a3f1944 | bellard | void cpu_lock(void); |
66 | 7a3f1944 | bellard | void cpu_unlock(void); |
67 | 7a3f1944 | bellard | void cpu_loop_exit(void); |
68 | 658138bc | bellard | void helper_flush(target_ulong addr);
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69 | e8af50a3 | bellard | void helper_ld_asi(int asi, int size, int sign); |
70 | e8af50a3 | bellard | void helper_st_asi(int asi, int size, int sign); |
71 | e8af50a3 | bellard | void helper_rett(void); |
72 | 8d5f07fa | bellard | void helper_ldfsr(void); |
73 | e8af50a3 | bellard | void set_cwp(int new_cwp); |
74 | a0c4cb4a | bellard | void do_fitos(void); |
75 | a0c4cb4a | bellard | void do_fitod(void); |
76 | e8af50a3 | bellard | void do_fabss(void); |
77 | e8af50a3 | bellard | void do_fsqrts(void); |
78 | e8af50a3 | bellard | void do_fsqrtd(void); |
79 | e8af50a3 | bellard | void do_fcmps(void); |
80 | e8af50a3 | bellard | void do_fcmpd(void); |
81 | 3475187d | bellard | #ifdef TARGET_SPARC64
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82 | 3475187d | bellard | void do_fabsd(void); |
83 | 3475187d | bellard | void do_fcmps_fcc1(void); |
84 | 3475187d | bellard | void do_fcmpd_fcc1(void); |
85 | 3475187d | bellard | void do_fcmps_fcc2(void); |
86 | 3475187d | bellard | void do_fcmpd_fcc2(void); |
87 | 3475187d | bellard | void do_fcmps_fcc3(void); |
88 | 3475187d | bellard | void do_fcmpd_fcc3(void); |
89 | 3475187d | bellard | void do_popc();
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90 | 83469015 | bellard | void do_wrpstate();
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91 | 83469015 | bellard | void do_done();
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92 | 83469015 | bellard | void do_retry();
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93 | 3475187d | bellard | #endif
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94 | af7bf89b | bellard | void do_ldd_kernel(target_ulong addr);
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95 | af7bf89b | bellard | void do_ldd_user(target_ulong addr);
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96 | af7bf89b | bellard | void do_ldd_raw(target_ulong addr);
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97 | 878d3096 | bellard | void do_interrupt(int intno); |
98 | e8af50a3 | bellard | void raise_exception(int tt); |
99 | af7bf89b | bellard | void memcpy32(target_ulong *dst, const target_ulong *src); |
100 | ee5bbe38 | bellard | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev);
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101 | ee5bbe38 | bellard | void dump_mmu(CPUState *env);
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102 | e80cfcfc | bellard | void helper_debug();
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103 | af7bf89b | bellard | void do_wrpsr();
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104 | af7bf89b | bellard | void do_rdpsr();
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105 | e8af50a3 | bellard | |
106 | e8af50a3 | bellard | /* XXX: move that to a generic header */
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107 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
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108 | a9049a07 | bellard | #include "softmmu_exec.h" |
109 | e8af50a3 | bellard | #endif /* !defined(CONFIG_USER_ONLY) */ |
110 | 0d1a29f9 | bellard | |
111 | 0d1a29f9 | bellard | static inline void env_to_regs(void) |
112 | 0d1a29f9 | bellard | { |
113 | aea3ce4c | bellard | #if defined(reg_REGWPTR)
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114 | aea3ce4c | bellard | REGWPTR = env->regbase + (env->cwp * 16);
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115 | aea3ce4c | bellard | env->regwptr = REGWPTR; |
116 | aea3ce4c | bellard | #endif
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117 | 0d1a29f9 | bellard | } |
118 | 0d1a29f9 | bellard | |
119 | 0d1a29f9 | bellard | static inline void regs_to_env(void) |
120 | 0d1a29f9 | bellard | { |
121 | 0d1a29f9 | bellard | } |
122 | 0d1a29f9 | bellard | |
123 | 9d893301 | bellard | int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
124 | 9d893301 | bellard | int is_user, int is_softmmu); |
125 | 9d893301 | bellard | |
126 | 7a3f1944 | bellard | #endif |