Statistics
| Branch: | Revision:

root / target-mips / exec.h @ 01dbbdf1

History | View | Annotate | Download (2.6 kB)

1 6af0bf9c bellard
#if !defined(__QEMU_MIPS_EXEC_H__)
2 6af0bf9c bellard
#define __QEMU_MIPS_EXEC_H__
3 6af0bf9c bellard
4 01dbbdf1 bellard
//#define DEBUG_OP
5 6af0bf9c bellard
6 6af0bf9c bellard
#include "mips-defs.h"
7 6af0bf9c bellard
#include "dyngen-exec.h"
8 6af0bf9c bellard
9 6af0bf9c bellard
register struct CPUMIPSState *env asm(AREG0);
10 6af0bf9c bellard
11 6af0bf9c bellard
#if defined (USE_64BITS_REGS)
12 6af0bf9c bellard
typedef int64_t host_int_t;
13 6af0bf9c bellard
typedef uint64_t host_uint_t;
14 6af0bf9c bellard
#else
15 6af0bf9c bellard
typedef int32_t host_int_t;
16 6af0bf9c bellard
typedef uint32_t host_uint_t;
17 6af0bf9c bellard
#endif
18 6af0bf9c bellard
19 6af0bf9c bellard
register host_uint_t T0 asm(AREG1);
20 6af0bf9c bellard
register host_uint_t T1 asm(AREG2);
21 6af0bf9c bellard
register host_uint_t T2 asm(AREG3);
22 6af0bf9c bellard
23 6af0bf9c bellard
#if defined (USE_HOST_FLOAT_REGS)
24 6af0bf9c bellard
register double FT0 asm(FREG0);
25 6af0bf9c bellard
register double FT1 asm(FREG1);
26 6af0bf9c bellard
register double FT2 asm(FREG2);
27 6af0bf9c bellard
#else
28 6af0bf9c bellard
#define FT0 (env->ft0.d)
29 6af0bf9c bellard
#define FT1 (env->ft1.d)
30 6af0bf9c bellard
#define FT2 (env->ft2.d)
31 6af0bf9c bellard
#endif
32 6af0bf9c bellard
33 6af0bf9c bellard
#if defined (DEBUG_OP)
34 6af0bf9c bellard
#define RETURN() __asm__ __volatile__("nop");
35 6af0bf9c bellard
#else
36 6af0bf9c bellard
#define RETURN() __asm__ __volatile__("");
37 6af0bf9c bellard
#endif
38 6af0bf9c bellard
39 6af0bf9c bellard
#include "cpu.h"
40 6af0bf9c bellard
#include "exec-all.h"
41 6af0bf9c bellard
42 6af0bf9c bellard
#if !defined(CONFIG_USER_ONLY)
43 a9049a07 bellard
#include "softmmu_exec.h"
44 6af0bf9c bellard
#endif /* !defined(CONFIG_USER_ONLY) */
45 6af0bf9c bellard
46 6af0bf9c bellard
static inline void env_to_regs(void)
47 6af0bf9c bellard
{
48 6af0bf9c bellard
}
49 6af0bf9c bellard
50 6af0bf9c bellard
static inline void regs_to_env(void)
51 6af0bf9c bellard
{
52 6af0bf9c bellard
}
53 6af0bf9c bellard
54 6af0bf9c bellard
#if (HOST_LONG_BITS == 32)
55 6af0bf9c bellard
void do_mult (void);
56 6af0bf9c bellard
void do_multu (void);
57 6af0bf9c bellard
void do_madd (void);
58 6af0bf9c bellard
void do_maddu (void);
59 6af0bf9c bellard
void do_msub (void);
60 6af0bf9c bellard
void do_msubu (void);
61 6af0bf9c bellard
#endif
62 6af0bf9c bellard
void do_mfc0(int reg, int sel);
63 6af0bf9c bellard
void do_mtc0(int reg, int sel);
64 6af0bf9c bellard
void do_tlbwi (void);
65 6af0bf9c bellard
void do_tlbwr (void);
66 6af0bf9c bellard
void do_tlbp (void);
67 6af0bf9c bellard
void do_tlbr (void);
68 4ad40f36 bellard
void do_lwl_raw (uint32_t);
69 4ad40f36 bellard
void do_lwr_raw (uint32_t);
70 4ad40f36 bellard
uint32_t do_swl_raw (uint32_t);
71 4ad40f36 bellard
uint32_t do_swr_raw (uint32_t);
72 6af0bf9c bellard
#if !defined(CONFIG_USER_ONLY)
73 4ad40f36 bellard
void do_lwl_user (uint32_t);
74 4ad40f36 bellard
void do_lwl_kernel (uint32_t);
75 4ad40f36 bellard
void do_lwr_user (uint32_t);
76 4ad40f36 bellard
void do_lwr_kernel (uint32_t);
77 4ad40f36 bellard
uint32_t do_swl_user (uint32_t);
78 4ad40f36 bellard
uint32_t do_swl_kernel (uint32_t);
79 4ad40f36 bellard
uint32_t do_swr_user (uint32_t);
80 4ad40f36 bellard
uint32_t do_swr_kernel (uint32_t);
81 6af0bf9c bellard
#endif
82 6af0bf9c bellard
void do_pmon (int function);
83 6af0bf9c bellard
84 6af0bf9c bellard
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
85 6af0bf9c bellard
                               int is_user, int is_softmmu);
86 6af0bf9c bellard
void do_interrupt (CPUState *env);
87 6af0bf9c bellard
88 6af0bf9c bellard
void cpu_loop_exit(void);
89 6af0bf9c bellard
void do_raise_exception_err (uint32_t exception, int error_code);
90 6af0bf9c bellard
void do_raise_exception (uint32_t exception);
91 4ad40f36 bellard
void do_raise_exception_direct (uint32_t exception);
92 6af0bf9c bellard
93 6af0bf9c bellard
void cpu_dump_state(CPUState *env, FILE *f, 
94 6af0bf9c bellard
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
95 6af0bf9c bellard
                    int flags);
96 6af0bf9c bellard
void cpu_mips_irqctrl_init (void);
97 6af0bf9c bellard
uint32_t cpu_mips_get_random (CPUState *env);
98 6af0bf9c bellard
uint32_t cpu_mips_get_count (CPUState *env);
99 6af0bf9c bellard
void cpu_mips_store_count (CPUState *env, uint32_t value);
100 6af0bf9c bellard
void cpu_mips_store_compare (CPUState *env, uint32_t value);
101 6af0bf9c bellard
void cpu_mips_clock_init (CPUState *env);
102 6af0bf9c bellard
103 6af0bf9c bellard
#endif /* !defined(__QEMU_MIPS_EXEC_H__) */