root / hw / spapr.c @ 0201e2da
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1 | 9fdf0c29 | David Gibson | /*
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2 | 9fdf0c29 | David Gibson | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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3 | 9fdf0c29 | David Gibson | *
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4 | 9fdf0c29 | David Gibson | * Copyright (c) 2004-2007 Fabrice Bellard
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5 | 9fdf0c29 | David Gibson | * Copyright (c) 2007 Jocelyn Mayer
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6 | 9fdf0c29 | David Gibson | * Copyright (c) 2010 David Gibson, IBM Corporation.
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7 | 9fdf0c29 | David Gibson | *
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8 | 9fdf0c29 | David Gibson | * Permission is hereby granted, free of charge, to any person obtaining a copy
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9 | 9fdf0c29 | David Gibson | * of this software and associated documentation files (the "Software"), to deal
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10 | 9fdf0c29 | David Gibson | * in the Software without restriction, including without limitation the rights
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11 | 9fdf0c29 | David Gibson | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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12 | 9fdf0c29 | David Gibson | * copies of the Software, and to permit persons to whom the Software is
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13 | 9fdf0c29 | David Gibson | * furnished to do so, subject to the following conditions:
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14 | 9fdf0c29 | David Gibson | *
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15 | 9fdf0c29 | David Gibson | * The above copyright notice and this permission notice shall be included in
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16 | 9fdf0c29 | David Gibson | * all copies or substantial portions of the Software.
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17 | 9fdf0c29 | David Gibson | *
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18 | 9fdf0c29 | David Gibson | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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19 | 9fdf0c29 | David Gibson | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 | 9fdf0c29 | David Gibson | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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21 | 9fdf0c29 | David Gibson | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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22 | 9fdf0c29 | David Gibson | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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23 | 9fdf0c29 | David Gibson | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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24 | 9fdf0c29 | David Gibson | * THE SOFTWARE.
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25 | 9fdf0c29 | David Gibson | *
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26 | 9fdf0c29 | David Gibson | */
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27 | 9fdf0c29 | David Gibson | #include "sysemu.h" |
28 | 9fdf0c29 | David Gibson | #include "hw.h" |
29 | 9fdf0c29 | David Gibson | #include "elf.h" |
30 | 9fdf0c29 | David Gibson | |
31 | 9fdf0c29 | David Gibson | #include "hw/boards.h" |
32 | 9fdf0c29 | David Gibson | #include "hw/ppc.h" |
33 | 9fdf0c29 | David Gibson | #include "hw/loader.h" |
34 | 9fdf0c29 | David Gibson | |
35 | 9fdf0c29 | David Gibson | #include "hw/spapr.h" |
36 | 4040ab72 | David Gibson | #include "hw/spapr_vio.h" |
37 | b5cec4c5 | David Gibson | #include "hw/xics.h" |
38 | 9fdf0c29 | David Gibson | |
39 | 9fdf0c29 | David Gibson | #include <libfdt.h> |
40 | 9fdf0c29 | David Gibson | |
41 | 9fdf0c29 | David Gibson | #define KERNEL_LOAD_ADDR 0x00000000 |
42 | 9fdf0c29 | David Gibson | #define INITRD_LOAD_ADDR 0x02800000 |
43 | 9fdf0c29 | David Gibson | #define FDT_MAX_SIZE 0x10000 |
44 | 39ac8455 | David Gibson | #define RTAS_MAX_SIZE 0x10000 |
45 | 9fdf0c29 | David Gibson | |
46 | 9fdf0c29 | David Gibson | #define TIMEBASE_FREQ 512000000ULL |
47 | 9fdf0c29 | David Gibson | |
48 | 9fdf0c29 | David Gibson | #define MAX_CPUS 32 |
49 | b5cec4c5 | David Gibson | #define XICS_IRQS 1024 |
50 | 9fdf0c29 | David Gibson | |
51 | 9fdf0c29 | David Gibson | sPAPREnvironment *spapr; |
52 | 9fdf0c29 | David Gibson | |
53 | 9fdf0c29 | David Gibson | static void *spapr_create_fdt(int *fdt_size, ram_addr_t ramsize, |
54 | 9fdf0c29 | David Gibson | const char *cpu_model, CPUState *envs[], |
55 | 9fdf0c29 | David Gibson | sPAPREnvironment *spapr, |
56 | 9fdf0c29 | David Gibson | target_phys_addr_t initrd_base, |
57 | 9fdf0c29 | David Gibson | target_phys_addr_t initrd_size, |
58 | f43e3525 | David Gibson | const char *kernel_cmdline, |
59 | 39ac8455 | David Gibson | target_phys_addr_t rtas_addr, |
60 | 39ac8455 | David Gibson | target_phys_addr_t rtas_size, |
61 | f43e3525 | David Gibson | long hash_shift)
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62 | 9fdf0c29 | David Gibson | { |
63 | 9fdf0c29 | David Gibson | void *fdt;
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64 | 9fdf0c29 | David Gibson | uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
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65 | 9fdf0c29 | David Gibson | uint32_t start_prop = cpu_to_be32(initrd_base); |
66 | 9fdf0c29 | David Gibson | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); |
67 | f43e3525 | David Gibson | uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
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68 | 00dc738d | David Gibson | char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"; |
69 | b5cec4c5 | David Gibson | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
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70 | 9fdf0c29 | David Gibson | int i;
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71 | 9fdf0c29 | David Gibson | char *modelname;
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72 | 4040ab72 | David Gibson | int ret;
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73 | 9fdf0c29 | David Gibson | |
74 | 9fdf0c29 | David Gibson | #define _FDT(exp) \
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75 | 9fdf0c29 | David Gibson | do { \
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76 | 9fdf0c29 | David Gibson | int ret = (exp); \
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77 | 9fdf0c29 | David Gibson | if (ret < 0) { \ |
78 | 9fdf0c29 | David Gibson | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
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79 | 9fdf0c29 | David Gibson | #exp, fdt_strerror(ret)); \
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80 | 9fdf0c29 | David Gibson | exit(1); \
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81 | 9fdf0c29 | David Gibson | } \ |
82 | 9fdf0c29 | David Gibson | } while (0) |
83 | 9fdf0c29 | David Gibson | |
84 | 9fdf0c29 | David Gibson | fdt = qemu_mallocz(FDT_MAX_SIZE); |
85 | 9fdf0c29 | David Gibson | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
86 | 9fdf0c29 | David Gibson | |
87 | 9fdf0c29 | David Gibson | _FDT((fdt_finish_reservemap(fdt))); |
88 | 9fdf0c29 | David Gibson | |
89 | 9fdf0c29 | David Gibson | /* Root node */
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90 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "")));
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91 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); |
92 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR"))); |
93 | 9fdf0c29 | David Gibson | |
94 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); |
95 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); |
96 | 9fdf0c29 | David Gibson | |
97 | 9fdf0c29 | David Gibson | /* /chosen */
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98 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "chosen")));
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99 | 9fdf0c29 | David Gibson | |
100 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
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101 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "linux,initrd-start",
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102 | 9fdf0c29 | David Gibson | &start_prop, sizeof(start_prop))));
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103 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "linux,initrd-end",
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104 | 9fdf0c29 | David Gibson | &end_prop, sizeof(end_prop))));
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105 | 9fdf0c29 | David Gibson | |
106 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
107 | 9fdf0c29 | David Gibson | |
108 | 9fdf0c29 | David Gibson | /* memory node */
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109 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "memory@0")));
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110 | 9fdf0c29 | David Gibson | |
111 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "memory"))); |
112 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "reg",
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113 | 9fdf0c29 | David Gibson | mem_reg_property, sizeof(mem_reg_property))));
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114 | 9fdf0c29 | David Gibson | |
115 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
116 | 9fdf0c29 | David Gibson | |
117 | 9fdf0c29 | David Gibson | /* cpus */
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118 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, "cpus")));
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119 | 9fdf0c29 | David Gibson | |
120 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
121 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
122 | 9fdf0c29 | David Gibson | |
123 | 9fdf0c29 | David Gibson | modelname = qemu_strdup(cpu_model); |
124 | 9fdf0c29 | David Gibson | |
125 | 9fdf0c29 | David Gibson | for (i = 0; i < strlen(modelname); i++) { |
126 | 9fdf0c29 | David Gibson | modelname[i] = toupper(modelname[i]); |
127 | 9fdf0c29 | David Gibson | } |
128 | 9fdf0c29 | David Gibson | |
129 | 9fdf0c29 | David Gibson | for (i = 0; i < smp_cpus; i++) { |
130 | 9fdf0c29 | David Gibson | CPUState *env = envs[i]; |
131 | b5cec4c5 | David Gibson | uint32_t gserver_prop[] = {cpu_to_be32(i), 0}; /* HACK! */ |
132 | 9fdf0c29 | David Gibson | char *nodename;
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133 | 9fdf0c29 | David Gibson | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), |
134 | 9fdf0c29 | David Gibson | 0xffffffff, 0xffffffff}; |
135 | 9fdf0c29 | David Gibson | |
136 | 9fdf0c29 | David Gibson | if (asprintf(&nodename, "%s@%x", modelname, i) < 0) { |
137 | 9fdf0c29 | David Gibson | fprintf(stderr, "Allocation failure\n");
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138 | 9fdf0c29 | David Gibson | exit(1);
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139 | 9fdf0c29 | David Gibson | } |
140 | 9fdf0c29 | David Gibson | |
141 | 9fdf0c29 | David Gibson | _FDT((fdt_begin_node(fdt, nodename))); |
142 | 9fdf0c29 | David Gibson | |
143 | 9fdf0c29 | David Gibson | free(nodename); |
144 | 9fdf0c29 | David Gibson | |
145 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "reg", i)));
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146 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "cpu"))); |
147 | 9fdf0c29 | David Gibson | |
148 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
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149 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "dcache-block-size",
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150 | 9fdf0c29 | David Gibson | env->dcache_line_size))); |
151 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "icache-block-size",
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152 | 9fdf0c29 | David Gibson | env->icache_line_size))); |
153 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ)));
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154 | 9fdf0c29 | David Gibson | /* Hardcode CPU frequency for now. It's kind of arbitrary on
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155 | 9fdf0c29 | David Gibson | * full emu, for kvm we should copy it from the host */
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156 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000))); |
157 | 9fdf0c29 | David Gibson | _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
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158 | f43e3525 | David Gibson | _FDT((fdt_property(fdt, "ibm,pft-size",
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159 | f43e3525 | David Gibson | pft_size_prop, sizeof(pft_size_prop))));
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160 | 9fdf0c29 | David Gibson | _FDT((fdt_property_string(fdt, "status", "okay"))); |
161 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "64-bit", NULL, 0))); |
162 | b5cec4c5 | David Gibson | _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", i)));
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163 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
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164 | b5cec4c5 | David Gibson | gserver_prop, sizeof(gserver_prop))));
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165 | 9fdf0c29 | David Gibson | |
166 | 9fdf0c29 | David Gibson | if (envs[i]->mmu_model & POWERPC_MMU_1TSEG) {
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167 | 9fdf0c29 | David Gibson | _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
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168 | 9fdf0c29 | David Gibson | segs, sizeof(segs))));
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169 | 9fdf0c29 | David Gibson | } |
170 | 9fdf0c29 | David Gibson | |
171 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
172 | 9fdf0c29 | David Gibson | } |
173 | 9fdf0c29 | David Gibson | |
174 | 9fdf0c29 | David Gibson | qemu_free(modelname); |
175 | 9fdf0c29 | David Gibson | |
176 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); |
177 | 9fdf0c29 | David Gibson | |
178 | f43e3525 | David Gibson | /* RTAS */
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179 | f43e3525 | David Gibson | _FDT((fdt_begin_node(fdt, "rtas")));
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180 | f43e3525 | David Gibson | |
181 | f43e3525 | David Gibson | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
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182 | f43e3525 | David Gibson | sizeof(hypertas_prop))));
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183 | f43e3525 | David Gibson | |
184 | f43e3525 | David Gibson | _FDT((fdt_end_node(fdt))); |
185 | f43e3525 | David Gibson | |
186 | b5cec4c5 | David Gibson | /* interrupt controller */
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187 | b5cec4c5 | David Gibson | _FDT((fdt_begin_node(fdt, "interrupt-controller@0")));
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188 | b5cec4c5 | David Gibson | |
189 | b5cec4c5 | David Gibson | _FDT((fdt_property_string(fdt, "device_type",
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190 | b5cec4c5 | David Gibson | "PowerPC-External-Interrupt-Presentation")));
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191 | b5cec4c5 | David Gibson | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); |
192 | b5cec4c5 | David Gibson | _FDT((fdt_property_cell(fdt, "reg", 0))); |
193 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
194 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
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195 | b5cec4c5 | David Gibson | interrupt_server_ranges_prop, |
196 | b5cec4c5 | David Gibson | sizeof(interrupt_server_ranges_prop))));
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197 | b5cec4c5 | David Gibson | |
198 | b5cec4c5 | David Gibson | _FDT((fdt_end_node(fdt))); |
199 | b5cec4c5 | David Gibson | |
200 | 4040ab72 | David Gibson | /* vdevice */
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201 | 4040ab72 | David Gibson | _FDT((fdt_begin_node(fdt, "vdevice")));
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202 | 4040ab72 | David Gibson | |
203 | 4040ab72 | David Gibson | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); |
204 | 4040ab72 | David Gibson | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); |
205 | 4040ab72 | David Gibson | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); |
206 | 4040ab72 | David Gibson | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); |
207 | b5cec4c5 | David Gibson | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
208 | b5cec4c5 | David Gibson | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); |
209 | 4040ab72 | David Gibson | |
210 | 4040ab72 | David Gibson | _FDT((fdt_end_node(fdt))); |
211 | 4040ab72 | David Gibson | |
212 | 9fdf0c29 | David Gibson | _FDT((fdt_end_node(fdt))); /* close root node */
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213 | 9fdf0c29 | David Gibson | _FDT((fdt_finish(fdt))); |
214 | 9fdf0c29 | David Gibson | |
215 | 4040ab72 | David Gibson | /* re-expand to allow for further tweaks */
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216 | 4040ab72 | David Gibson | _FDT((fdt_open_into(fdt, fdt, FDT_MAX_SIZE))); |
217 | 4040ab72 | David Gibson | |
218 | 4040ab72 | David Gibson | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); |
219 | 4040ab72 | David Gibson | if (ret < 0) { |
220 | 4040ab72 | David Gibson | fprintf(stderr, "couldn't setup vio devices in fdt\n");
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221 | 4040ab72 | David Gibson | exit(1);
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222 | 4040ab72 | David Gibson | } |
223 | 4040ab72 | David Gibson | |
224 | 39ac8455 | David Gibson | /* RTAS */
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225 | 39ac8455 | David Gibson | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); |
226 | 39ac8455 | David Gibson | if (ret < 0) { |
227 | 39ac8455 | David Gibson | fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
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228 | 39ac8455 | David Gibson | } |
229 | 39ac8455 | David Gibson | |
230 | 4040ab72 | David Gibson | _FDT((fdt_pack(fdt))); |
231 | 4040ab72 | David Gibson | |
232 | 9fdf0c29 | David Gibson | *fdt_size = fdt_totalsize(fdt); |
233 | 9fdf0c29 | David Gibson | |
234 | 9fdf0c29 | David Gibson | return fdt;
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235 | 9fdf0c29 | David Gibson | } |
236 | 9fdf0c29 | David Gibson | |
237 | 9fdf0c29 | David Gibson | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
238 | 9fdf0c29 | David Gibson | { |
239 | 9fdf0c29 | David Gibson | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; |
240 | 9fdf0c29 | David Gibson | } |
241 | 9fdf0c29 | David Gibson | |
242 | 9fdf0c29 | David Gibson | static void emulate_spapr_hypercall(CPUState *env) |
243 | 9fdf0c29 | David Gibson | { |
244 | 9fdf0c29 | David Gibson | env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); |
245 | 9fdf0c29 | David Gibson | } |
246 | 9fdf0c29 | David Gibson | |
247 | 9fdf0c29 | David Gibson | /* pSeries LPAR / sPAPR hardware init */
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248 | 9fdf0c29 | David Gibson | static void ppc_spapr_init(ram_addr_t ram_size, |
249 | 9fdf0c29 | David Gibson | const char *boot_device, |
250 | 9fdf0c29 | David Gibson | const char *kernel_filename, |
251 | 9fdf0c29 | David Gibson | const char *kernel_cmdline, |
252 | 9fdf0c29 | David Gibson | const char *initrd_filename, |
253 | 9fdf0c29 | David Gibson | const char *cpu_model) |
254 | 9fdf0c29 | David Gibson | { |
255 | 9fdf0c29 | David Gibson | CPUState *envs[MAX_CPUS]; |
256 | f43e3525 | David Gibson | void *fdt, *htab;
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257 | 9fdf0c29 | David Gibson | int i;
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258 | 9fdf0c29 | David Gibson | ram_addr_t ram_offset; |
259 | 39ac8455 | David Gibson | target_phys_addr_t fdt_addr, rtas_addr; |
260 | 9fdf0c29 | David Gibson | uint32_t kernel_base, initrd_base; |
261 | 39ac8455 | David Gibson | long kernel_size, initrd_size, htab_size, rtas_size;
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262 | f43e3525 | David Gibson | long pteg_shift = 17; |
263 | 9fdf0c29 | David Gibson | int fdt_size;
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264 | 39ac8455 | David Gibson | char *filename;
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265 | 0201e2da | David Gibson | int irq = 16; |
266 | 9fdf0c29 | David Gibson | |
267 | 9fdf0c29 | David Gibson | spapr = qemu_malloc(sizeof(*spapr));
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268 | 9fdf0c29 | David Gibson | cpu_ppc_hypercall = emulate_spapr_hypercall; |
269 | 9fdf0c29 | David Gibson | |
270 | 9fdf0c29 | David Gibson | /* We place the device tree just below either the top of RAM, or
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271 | 9fdf0c29 | David Gibson | * 2GB, so that it can be processed with 32-bit code if
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272 | 9fdf0c29 | David Gibson | * necessary */
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273 | 9fdf0c29 | David Gibson | fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
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274 | 39ac8455 | David Gibson | /* RTAS goes just below that */
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275 | 39ac8455 | David Gibson | rtas_addr = fdt_addr - RTAS_MAX_SIZE; |
276 | 9fdf0c29 | David Gibson | |
277 | 9fdf0c29 | David Gibson | /* init CPUs */
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278 | 9fdf0c29 | David Gibson | if (cpu_model == NULL) { |
279 | 9fdf0c29 | David Gibson | cpu_model = "POWER7";
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280 | 9fdf0c29 | David Gibson | } |
281 | 9fdf0c29 | David Gibson | for (i = 0; i < smp_cpus; i++) { |
282 | 9fdf0c29 | David Gibson | CPUState *env = cpu_init(cpu_model); |
283 | 9fdf0c29 | David Gibson | |
284 | 9fdf0c29 | David Gibson | if (!env) {
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285 | 9fdf0c29 | David Gibson | fprintf(stderr, "Unable to find PowerPC CPU definition\n");
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286 | 9fdf0c29 | David Gibson | exit(1);
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287 | 9fdf0c29 | David Gibson | } |
288 | 9fdf0c29 | David Gibson | /* Set time-base frequency to 512 MHz */
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289 | 9fdf0c29 | David Gibson | cpu_ppc_tb_init(env, TIMEBASE_FREQ); |
290 | 9fdf0c29 | David Gibson | qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); |
291 | 9fdf0c29 | David Gibson | |
292 | 9fdf0c29 | David Gibson | env->hreset_vector = 0x60;
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293 | 9fdf0c29 | David Gibson | env->hreset_excp_prefix = 0;
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294 | 9fdf0c29 | David Gibson | env->gpr[3] = i;
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295 | 9fdf0c29 | David Gibson | |
296 | 9fdf0c29 | David Gibson | envs[i] = env; |
297 | 9fdf0c29 | David Gibson | } |
298 | 9fdf0c29 | David Gibson | |
299 | 9fdf0c29 | David Gibson | /* allocate RAM */
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300 | 9fdf0c29 | David Gibson | ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size); |
301 | 9fdf0c29 | David Gibson | cpu_register_physical_memory(0, ram_size, ram_offset);
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302 | 9fdf0c29 | David Gibson | |
303 | f43e3525 | David Gibson | /* allocate hash page table. For now we always make this 16mb,
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304 | f43e3525 | David Gibson | * later we should probably make it scale to the size of guest
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305 | f43e3525 | David Gibson | * RAM */
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306 | f43e3525 | David Gibson | htab_size = 1ULL << (pteg_shift + 7); |
307 | f43e3525 | David Gibson | htab = qemu_mallocz(htab_size); |
308 | f43e3525 | David Gibson | |
309 | f43e3525 | David Gibson | for (i = 0; i < smp_cpus; i++) { |
310 | f43e3525 | David Gibson | envs[i]->external_htab = htab; |
311 | f43e3525 | David Gibson | envs[i]->htab_base = -1;
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312 | f43e3525 | David Gibson | envs[i]->htab_mask = htab_size - 1;
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313 | f43e3525 | David Gibson | } |
314 | f43e3525 | David Gibson | |
315 | 39ac8455 | David Gibson | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
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316 | 39ac8455 | David Gibson | rtas_size = load_image_targphys(filename, rtas_addr, ram_size - rtas_addr); |
317 | 39ac8455 | David Gibson | if (rtas_size < 0) { |
318 | 39ac8455 | David Gibson | hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
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319 | 39ac8455 | David Gibson | exit(1);
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320 | 39ac8455 | David Gibson | } |
321 | 39ac8455 | David Gibson | qemu_free(filename); |
322 | 39ac8455 | David Gibson | |
323 | b5cec4c5 | David Gibson | /* Set up Interrupt Controller */
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324 | b5cec4c5 | David Gibson | spapr->icp = xics_system_init(smp_cpus, envs, XICS_IRQS); |
325 | b5cec4c5 | David Gibson | |
326 | b5cec4c5 | David Gibson | /* Set up VIO bus */
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327 | 4040ab72 | David Gibson | spapr->vio_bus = spapr_vio_bus_init(); |
328 | 4040ab72 | David Gibson | |
329 | 0201e2da | David Gibson | for (i = 0; i < MAX_SERIAL_PORTS; i++, irq++) { |
330 | 4040ab72 | David Gibson | if (serial_hds[i]) {
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331 | 0201e2da | David Gibson | spapr_vty_create(spapr->vio_bus, i, serial_hds[i], |
332 | 0201e2da | David Gibson | xics_find_qirq(spapr->icp, irq), irq); |
333 | 4040ab72 | David Gibson | } |
334 | 4040ab72 | David Gibson | } |
335 | 9fdf0c29 | David Gibson | |
336 | 9fdf0c29 | David Gibson | if (kernel_filename) {
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337 | 9fdf0c29 | David Gibson | uint64_t lowaddr = 0;
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338 | 9fdf0c29 | David Gibson | |
339 | 9fdf0c29 | David Gibson | kernel_base = KERNEL_LOAD_ADDR; |
340 | 9fdf0c29 | David Gibson | |
341 | 9fdf0c29 | David Gibson | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
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342 | 9fdf0c29 | David Gibson | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); |
343 | 9fdf0c29 | David Gibson | if (kernel_size < 0) { |
344 | 9fdf0c29 | David Gibson | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
345 | 9fdf0c29 | David Gibson | ram_size - kernel_base); |
346 | 9fdf0c29 | David Gibson | } |
347 | 9fdf0c29 | David Gibson | if (kernel_size < 0) { |
348 | 9fdf0c29 | David Gibson | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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349 | 9fdf0c29 | David Gibson | kernel_filename); |
350 | 9fdf0c29 | David Gibson | exit(1);
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351 | 9fdf0c29 | David Gibson | } |
352 | 9fdf0c29 | David Gibson | |
353 | 9fdf0c29 | David Gibson | /* load initrd */
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354 | 9fdf0c29 | David Gibson | if (initrd_filename) {
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355 | 9fdf0c29 | David Gibson | initrd_base = INITRD_LOAD_ADDR; |
356 | 9fdf0c29 | David Gibson | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
357 | 9fdf0c29 | David Gibson | ram_size - initrd_base); |
358 | 9fdf0c29 | David Gibson | if (initrd_size < 0) { |
359 | 9fdf0c29 | David Gibson | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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360 | 9fdf0c29 | David Gibson | initrd_filename); |
361 | 9fdf0c29 | David Gibson | exit(1);
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362 | 9fdf0c29 | David Gibson | } |
363 | 9fdf0c29 | David Gibson | } else {
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364 | 9fdf0c29 | David Gibson | initrd_base = 0;
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365 | 9fdf0c29 | David Gibson | initrd_size = 0;
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366 | 9fdf0c29 | David Gibson | } |
367 | 9fdf0c29 | David Gibson | } else {
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368 | 9fdf0c29 | David Gibson | fprintf(stderr, "pSeries machine needs -kernel for now");
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369 | 9fdf0c29 | David Gibson | exit(1);
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370 | 9fdf0c29 | David Gibson | } |
371 | 9fdf0c29 | David Gibson | |
372 | 9fdf0c29 | David Gibson | /* Prepare the device tree */
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373 | 9fdf0c29 | David Gibson | fdt = spapr_create_fdt(&fdt_size, ram_size, cpu_model, envs, spapr, |
374 | f43e3525 | David Gibson | initrd_base, initrd_size, kernel_cmdline, |
375 | 39ac8455 | David Gibson | rtas_addr, rtas_size, pteg_shift + 7);
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376 | 9fdf0c29 | David Gibson | assert(fdt != NULL);
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377 | 9fdf0c29 | David Gibson | |
378 | 9fdf0c29 | David Gibson | cpu_physical_memory_write(fdt_addr, fdt, fdt_size); |
379 | 9fdf0c29 | David Gibson | |
380 | 9fdf0c29 | David Gibson | qemu_free(fdt); |
381 | 9fdf0c29 | David Gibson | |
382 | 9fdf0c29 | David Gibson | envs[0]->gpr[3] = fdt_addr; |
383 | 9fdf0c29 | David Gibson | envs[0]->gpr[5] = 0; |
384 | 9fdf0c29 | David Gibson | envs[0]->hreset_vector = kernel_base;
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385 | 9fdf0c29 | David Gibson | } |
386 | 9fdf0c29 | David Gibson | |
387 | 9fdf0c29 | David Gibson | static QEMUMachine spapr_machine = {
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388 | 9fdf0c29 | David Gibson | .name = "pseries",
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389 | 9fdf0c29 | David Gibson | .desc = "pSeries Logical Partition (PAPR compliant)",
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390 | 9fdf0c29 | David Gibson | .init = ppc_spapr_init, |
391 | 9fdf0c29 | David Gibson | .max_cpus = MAX_CPUS, |
392 | 9fdf0c29 | David Gibson | .no_vga = 1,
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393 | 9fdf0c29 | David Gibson | .no_parallel = 1,
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394 | 9fdf0c29 | David Gibson | }; |
395 | 9fdf0c29 | David Gibson | |
396 | 9fdf0c29 | David Gibson | static void spapr_machine_init(void) |
397 | 9fdf0c29 | David Gibson | { |
398 | 9fdf0c29 | David Gibson | qemu_register_machine(&spapr_machine); |
399 | 9fdf0c29 | David Gibson | } |
400 | 9fdf0c29 | David Gibson | |
401 | 9fdf0c29 | David Gibson | machine_init(spapr_machine_init); |