Revision 0208def1

b/hw/pci_bridge.c
151 151
    }
152 152
}
153 153

  
154
void pci_bridge_disable_base_limit(PCIDevice *dev)
155
{
156
    uint8_t *conf = dev->config;
157

  
158
    pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
159
                               PCI_IO_RANGE_MASK & 0xff);
160
    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
161
                                 PCI_IO_RANGE_MASK & 0xff);
162
    pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
163
                               PCI_MEMORY_RANGE_MASK & 0xffff);
164
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
165
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
166
    pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
167
                               PCI_PREF_RANGE_MASK & 0xffff);
168
    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
169
                                 PCI_PREF_RANGE_MASK & 0xffff);
170
    pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
171
    pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
172
}
173

  
154 174
/* reset bridge specific configuration registers */
155 175
void pci_bridge_reset_reg(PCIDevice *dev)
156 176
{
......
161 181
    conf[PCI_SUBORDINATE_BUS] = 0;
162 182
    conf[PCI_SEC_LATENCY_TIMER] = 0;
163 183

  
164
    conf[PCI_IO_BASE] = 0;
165
    conf[PCI_IO_LIMIT] = 0;
166
    pci_set_word(conf + PCI_MEMORY_BASE, 0);
167
    pci_set_word(conf + PCI_MEMORY_LIMIT, 0);
168
    pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0);
169
    pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0);
184
    /*
185
     * the default values for base/limit registers aren't specified
186
     * in the PCI-to-PCI-bridge spec. So we don't thouch them here.
187
     * Each implementation can override it.
188
     * typical implementation does
189
     * zero base/limit registers or
190
     * disable forwarding: pci_bridge_disable_base_limit()
191
     * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
192
     * after this function.
193
     */
194
    pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
195
                                 PCI_IO_RANGE_MASK & 0xff);
196
    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
197
                                 PCI_IO_RANGE_MASK & 0xff);
198
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
199
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
200
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
201
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
202
    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
203
                                 PCI_PREF_RANGE_MASK & 0xffff);
204
    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
205
                                 PCI_PREF_RANGE_MASK & 0xffff);
170 206
    pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
171 207
    pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
172 208

  
b/hw/pci_bridge.h
39 39

  
40 40
void pci_bridge_write_config(PCIDevice *d,
41 41
                             uint32_t address, uint32_t val, int len);
42
void pci_bridge_disable_base_limit(PCIDevice *dev);
42 43
void pci_bridge_reset_reg(PCIDevice *dev);
43 44
void pci_bridge_reset(DeviceState *qdev);
44 45

  

Also available in: Unified diff