Revision 02d74341

b/Makefile.target
268 268
obj-arm-y += pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
269 269
obj-arm-y += gumstix.o
270 270
obj-arm-y += zaurus.o ide/microdrive.o spitz.o tosa.o tc6393xb.o
271
obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o omap_gpio.o omap_intc.o
271
obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o \
272
		omap_gpio.o omap_intc.o omap_uart.o
272 273
obj-arm-y += omap2.o omap_dss.o soc_dma.o omap_gptimer.o omap_synctimer.o \
273 274
		omap_gpmc.o omap_sdrc.o omap_spi.o omap_tap.o omap_l4.o
274 275
obj-arm-y += omap_sx1.o palm.o tsc210x.o
b/hw/omap1.c
1378 1378
    cpu_register_physical_memory(base, 0x100, iomemtype);
1379 1379
}
1380 1380

  
1381
/* UARTs */
1382
struct omap_uart_s {
1383
    target_phys_addr_t base;
1384
    SerialState *serial; /* TODO */
1385
    struct omap_target_agent_s *ta;
1386
    omap_clk fclk;
1387
    qemu_irq irq;
1388

  
1389
    uint8_t eblr;
1390
    uint8_t syscontrol;
1391
    uint8_t wkup;
1392
    uint8_t cfps;
1393
    uint8_t mdr[2];
1394
    uint8_t scr;
1395
    uint8_t clksel;
1396
};
1397

  
1398
void omap_uart_reset(struct omap_uart_s *s)
1399
{
1400
    s->eblr = 0x00;
1401
    s->syscontrol = 0;
1402
    s->wkup = 0x3f;
1403
    s->cfps = 0x69;
1404
    s->clksel = 0;
1405
}
1406

  
1407
struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
1408
                qemu_irq irq, omap_clk fclk, omap_clk iclk,
1409
                qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
1410
{
1411
    struct omap_uart_s *s = (struct omap_uart_s *)
1412
            qemu_mallocz(sizeof(struct omap_uart_s));
1413

  
1414
    s->base = base;
1415
    s->fclk = fclk;
1416
    s->irq = irq;
1417
#ifdef TARGET_WORDS_BIGENDIAN
1418
    s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
1419
                               chr ?: qemu_chr_open("null", "null", NULL), 1,
1420
                               1);
1421
#else
1422
    s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
1423
                               chr ?: qemu_chr_open("null", "null", NULL), 1,
1424
                               0);
1425
#endif
1426
    return s;
1427
}
1428

  
1429
static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
1430
{
1431
    struct omap_uart_s *s = (struct omap_uart_s *) opaque;
1432

  
1433
    addr &= 0xff;
1434
    switch (addr) {
1435
    case 0x20:	/* MDR1 */
1436
        return s->mdr[0];
1437
    case 0x24:	/* MDR2 */
1438
        return s->mdr[1];
1439
    case 0x40:	/* SCR */
1440
        return s->scr;
1441
    case 0x44:	/* SSR */
1442
        return 0x0;
1443
    case 0x48:	/* EBLR (OMAP2) */
1444
        return s->eblr;
1445
    case 0x4C:	/* OSC_12M_SEL (OMAP1) */
1446
        return s->clksel;
1447
    case 0x50:	/* MVR */
1448
        return 0x30;
1449
    case 0x54:	/* SYSC (OMAP2) */
1450
        return s->syscontrol;
1451
    case 0x58:	/* SYSS (OMAP2) */
1452
        return 1;
1453
    case 0x5c:	/* WER (OMAP2) */
1454
        return s->wkup;
1455
    case 0x60:	/* CFPS (OMAP2) */
1456
        return s->cfps;
1457
    }
1458

  
1459
    OMAP_BAD_REG(addr);
1460
    return 0;
1461
}
1462

  
1463
static void omap_uart_write(void *opaque, target_phys_addr_t addr,
1464
                uint32_t value)
1465
{
1466
    struct omap_uart_s *s = (struct omap_uart_s *) opaque;
1467

  
1468
    addr &= 0xff;
1469
    switch (addr) {
1470
    case 0x20:	/* MDR1 */
1471
        s->mdr[0] = value & 0x7f;
1472
        break;
1473
    case 0x24:	/* MDR2 */
1474
        s->mdr[1] = value & 0xff;
1475
        break;
1476
    case 0x40:	/* SCR */
1477
        s->scr = value & 0xff;
1478
        break;
1479
    case 0x48:	/* EBLR (OMAP2) */
1480
        s->eblr = value & 0xff;
1481
        break;
1482
    case 0x4C:	/* OSC_12M_SEL (OMAP1) */
1483
        s->clksel = value & 1;
1484
        break;
1485
    case 0x44:	/* SSR */
1486
    case 0x50:	/* MVR */
1487
    case 0x58:	/* SYSS (OMAP2) */
1488
        OMAP_RO_REG(addr);
1489
        break;
1490
    case 0x54:	/* SYSC (OMAP2) */
1491
        s->syscontrol = value & 0x1d;
1492
        if (value & 2)
1493
            omap_uart_reset(s);
1494
        break;
1495
    case 0x5c:	/* WER (OMAP2) */
1496
        s->wkup = value & 0x7f;
1497
        break;
1498
    case 0x60:	/* CFPS (OMAP2) */
1499
        s->cfps = value & 0xff;
1500
        break;
1501
    default:
1502
        OMAP_BAD_REG(addr);
1503
    }
1504
}
1505

  
1506
static CPUReadMemoryFunc * const omap_uart_readfn[] = {
1507
    omap_uart_read,
1508
    omap_uart_read,
1509
    omap_badwidth_read8,
1510
};
1511

  
1512
static CPUWriteMemoryFunc * const omap_uart_writefn[] = {
1513
    omap_uart_write,
1514
    omap_uart_write,
1515
    omap_badwidth_write8,
1516
};
1517

  
1518
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
1519
                qemu_irq irq, omap_clk fclk, omap_clk iclk,
1520
                qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
1521
{
1522
    target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
1523
    struct omap_uart_s *s = omap_uart_init(base, irq,
1524
                    fclk, iclk, txdma, rxdma, chr);
1525
    int iomemtype = cpu_register_io_memory(omap_uart_readfn,
1526
                    omap_uart_writefn, s);
1527

  
1528
    s->ta = ta;
1529

  
1530
    cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
1531

  
1532
    return s;
1533
}
1534

  
1535
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
1536
{
1537
    /* TODO: Should reuse or destroy current s->serial */
1538
#ifdef TARGET_WORDS_BIGENDIAN
1539
    s->serial = serial_mm_init(s->base, 2, s->irq,
1540
                               omap_clk_getrate(s->fclk) / 16,
1541
                               chr ?: qemu_chr_open("null", "null", NULL), 1,
1542
                               1);
1543
#else
1544
    s->serial = serial_mm_init(s->base, 2, s->irq,
1545
                               omap_clk_getrate(s->fclk) / 16,
1546
                               chr ?: qemu_chr_open("null", "null", NULL), 1,
1547
                               0);
1548
#endif
1549
}
1550

  
1551 1381
/* MPU Clock/Reset/Power Mode Control */
1552 1382
static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
1553 1383
{
b/hw/omap_uart.c
1
/*
2
 * TI OMAP processors UART emulation.
3
 *
4
 * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
5
 * Copyright (C) 2007-2009 Nokia Corporation
6
 *
7
 * This program is free software; you can redistribute it and/or
8
 * modify it under the terms of the GNU General Public License as
9
 * published by the Free Software Foundation; either version 2 or
10
 * (at your option) version 3 of the License.
11
 *
12
 * This program is distributed in the hope that it will be useful,
13
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
 * GNU General Public License for more details.
16
 *
17
 * You should have received a copy of the GNU General Public License along
18
 * with this program; if not, see <http://www.gnu.org/licenses/>.
19
 */
20
#include "qemu-char.h"
21
#include "hw.h"
22
#include "omap.h"
23
/* We use pc-style serial ports.  */
24
#include "pc.h"
25

  
26
/* UARTs */
27
struct omap_uart_s {
28
    target_phys_addr_t base;
29
    SerialState *serial; /* TODO */
30
    struct omap_target_agent_s *ta;
31
    omap_clk fclk;
32
    qemu_irq irq;
33

  
34
    uint8_t eblr;
35
    uint8_t syscontrol;
36
    uint8_t wkup;
37
    uint8_t cfps;
38
    uint8_t mdr[2];
39
    uint8_t scr;
40
    uint8_t clksel;
41
};
42

  
43
void omap_uart_reset(struct omap_uart_s *s)
44
{
45
    s->eblr = 0x00;
46
    s->syscontrol = 0;
47
    s->wkup = 0x3f;
48
    s->cfps = 0x69;
49
    s->clksel = 0;
50
}
51

  
52
struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
53
                qemu_irq irq, omap_clk fclk, omap_clk iclk,
54
                qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
55
{
56
    struct omap_uart_s *s = (struct omap_uart_s *)
57
            qemu_mallocz(sizeof(struct omap_uart_s));
58

  
59
    s->base = base;
60
    s->fclk = fclk;
61
    s->irq = irq;
62
#ifdef TARGET_WORDS_BIGENDIAN
63
    s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
64
                               chr ?: qemu_chr_open("null", "null", NULL), 1,
65
                               1);
66
#else
67
    s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
68
                               chr ?: qemu_chr_open("null", "null", NULL), 1,
69
                               0);
70
#endif
71
    return s;
72
}
73

  
74
static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
75
{
76
    struct omap_uart_s *s = (struct omap_uart_s *) opaque;
77

  
78
    addr &= 0xff;
79
    switch (addr) {
80
    case 0x20:	/* MDR1 */
81
        return s->mdr[0];
82
    case 0x24:	/* MDR2 */
83
        return s->mdr[1];
84
    case 0x40:	/* SCR */
85
        return s->scr;
86
    case 0x44:	/* SSR */
87
        return 0x0;
88
    case 0x48:	/* EBLR (OMAP2) */
89
        return s->eblr;
90
    case 0x4C:	/* OSC_12M_SEL (OMAP1) */
91
        return s->clksel;
92
    case 0x50:	/* MVR */
93
        return 0x30;
94
    case 0x54:	/* SYSC (OMAP2) */
95
        return s->syscontrol;
96
    case 0x58:	/* SYSS (OMAP2) */
97
        return 1;
98
    case 0x5c:	/* WER (OMAP2) */
99
        return s->wkup;
100
    case 0x60:	/* CFPS (OMAP2) */
101
        return s->cfps;
102
    }
103

  
104
    OMAP_BAD_REG(addr);
105
    return 0;
106
}
107

  
108
static void omap_uart_write(void *opaque, target_phys_addr_t addr,
109
                uint32_t value)
110
{
111
    struct omap_uart_s *s = (struct omap_uart_s *) opaque;
112

  
113
    addr &= 0xff;
114
    switch (addr) {
115
    case 0x20:	/* MDR1 */
116
        s->mdr[0] = value & 0x7f;
117
        break;
118
    case 0x24:	/* MDR2 */
119
        s->mdr[1] = value & 0xff;
120
        break;
121
    case 0x40:	/* SCR */
122
        s->scr = value & 0xff;
123
        break;
124
    case 0x48:	/* EBLR (OMAP2) */
125
        s->eblr = value & 0xff;
126
        break;
127
    case 0x4C:	/* OSC_12M_SEL (OMAP1) */
128
        s->clksel = value & 1;
129
        break;
130
    case 0x44:	/* SSR */
131
    case 0x50:	/* MVR */
132
    case 0x58:	/* SYSS (OMAP2) */
133
        OMAP_RO_REG(addr);
134
        break;
135
    case 0x54:	/* SYSC (OMAP2) */
136
        s->syscontrol = value & 0x1d;
137
        if (value & 2)
138
            omap_uart_reset(s);
139
        break;
140
    case 0x5c:	/* WER (OMAP2) */
141
        s->wkup = value & 0x7f;
142
        break;
143
    case 0x60:	/* CFPS (OMAP2) */
144
        s->cfps = value & 0xff;
145
        break;
146
    default:
147
        OMAP_BAD_REG(addr);
148
    }
149
}
150

  
151
static CPUReadMemoryFunc * const omap_uart_readfn[] = {
152
    omap_uart_read,
153
    omap_uart_read,
154
    omap_badwidth_read8,
155
};
156

  
157
static CPUWriteMemoryFunc * const omap_uart_writefn[] = {
158
    omap_uart_write,
159
    omap_uart_write,
160
    omap_badwidth_write8,
161
};
162

  
163
struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
164
                qemu_irq irq, omap_clk fclk, omap_clk iclk,
165
                qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
166
{
167
    target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
168
    struct omap_uart_s *s = omap_uart_init(base, irq,
169
                    fclk, iclk, txdma, rxdma, chr);
170
    int iomemtype = cpu_register_io_memory(omap_uart_readfn,
171
                    omap_uart_writefn, s);
172

  
173
    s->ta = ta;
174

  
175
    cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
176

  
177
    return s;
178
}
179

  
180
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
181
{
182
    /* TODO: Should reuse or destroy current s->serial */
183
#ifdef TARGET_WORDS_BIGENDIAN
184
    s->serial = serial_mm_init(s->base, 2, s->irq,
185
                               omap_clk_getrate(s->fclk) / 16,
186
                               chr ?: qemu_chr_open("null", "null", NULL), 1,
187
                               1);
188
#else
189
    s->serial = serial_mm_init(s->base, 2, s->irq,
190
                               omap_clk_getrate(s->fclk) / 16,
191
                               chr ?: qemu_chr_open("null", "null", NULL), 1,
192
                               0);
193
#endif
194
}

Also available in: Unified diff