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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | d4e8164f | bellard | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | b346ff46 | bellard | #define DEBUG_DISAS
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23 | b346ff46 | bellard | |
24 | 33417e70 | bellard | #ifndef glue
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25 | 33417e70 | bellard | #define xglue(x, y) x ## y |
26 | 33417e70 | bellard | #define glue(x, y) xglue(x, y)
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27 | 33417e70 | bellard | #define stringify(s) tostring(s)
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28 | 33417e70 | bellard | #define tostring(s) #s |
29 | 33417e70 | bellard | #endif
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30 | 33417e70 | bellard | |
31 | 33417e70 | bellard | #if GCC_MAJOR < 3 |
32 | 33417e70 | bellard | #define __builtin_expect(x, n) (x)
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33 | 33417e70 | bellard | #endif
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34 | 33417e70 | bellard | |
35 | e2222c39 | bellard | #ifdef __i386__
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36 | e2222c39 | bellard | #define REGPARM(n) __attribute((regparm(n)))
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37 | e2222c39 | bellard | #else
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38 | e2222c39 | bellard | #define REGPARM(n)
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39 | e2222c39 | bellard | #endif
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40 | e2222c39 | bellard | |
41 | b346ff46 | bellard | /* is_jmp field values */
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42 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
43 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
44 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
45 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
46 | b346ff46 | bellard | |
47 | b346ff46 | bellard | struct TranslationBlock;
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48 | b346ff46 | bellard | |
49 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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50 | b346ff46 | bellard | #define MAX_OP_PER_INSTR 32 |
51 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
52 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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53 | b346ff46 | bellard | |
54 | b346ff46 | bellard | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
55 | b346ff46 | bellard | |
56 | b346ff46 | bellard | extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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57 | b346ff46 | bellard | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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58 | b346ff46 | bellard | extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
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59 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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60 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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61 | b346ff46 | bellard | |
62 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
63 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
64 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
65 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
66 | 9886cc16 | bellard | |
67 | b346ff46 | bellard | #if defined(TARGET_I386)
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68 | b346ff46 | bellard | |
69 | 33417e70 | bellard | void optimize_flags_init(void); |
70 | d4e8164f | bellard | |
71 | b346ff46 | bellard | #endif
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72 | b346ff46 | bellard | |
73 | b346ff46 | bellard | extern FILE *logfile;
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74 | b346ff46 | bellard | extern int loglevel; |
75 | b346ff46 | bellard | |
76 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
77 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
78 | b346ff46 | bellard | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
79 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
80 | b346ff46 | bellard | int max_code_size, int *gen_code_size_ptr); |
81 | 66e85a21 | bellard | int cpu_restore_state(struct TranslationBlock *tb, |
82 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
83 | 58fe2f10 | bellard | void *puc);
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84 | 58fe2f10 | bellard | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
85 | 58fe2f10 | bellard | int max_code_size, int *gen_code_size_ptr); |
86 | 58fe2f10 | bellard | int cpu_restore_state_copy(struct TranslationBlock *tb, |
87 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
88 | 58fe2f10 | bellard | void *puc);
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89 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
90 | b346ff46 | bellard | void cpu_exec_init(void); |
91 | 2e12669a | bellard | int page_unprotect(unsigned long address, unsigned long pc, void *puc); |
92 | 2e12669a | bellard | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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93 | 2e12669a | bellard | int is_cpu_write_access);
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94 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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95 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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96 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
97 | 2e12669a | bellard | int tlb_set_page(CPUState *env, target_ulong vaddr,
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98 | 2e12669a | bellard | target_phys_addr_t paddr, int prot,
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99 | 4390df51 | bellard | int is_user, int is_softmmu); |
100 | d4e8164f | bellard | |
101 | d4e8164f | bellard | #define CODE_GEN_MAX_SIZE 65536 |
102 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
103 | d4e8164f | bellard | |
104 | d4e8164f | bellard | #define CODE_GEN_HASH_BITS 15 |
105 | d4e8164f | bellard | #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) |
106 | d4e8164f | bellard | |
107 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
108 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
109 | 4390df51 | bellard | |
110 | d4e8164f | bellard | /* maximum total translate dcode allocated */
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111 | 4390df51 | bellard | |
112 | 4390df51 | bellard | /* NOTE: the translated code area cannot be too big because on some
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113 | c4c7e3e6 | bellard | archs the range of "fast" function calls is limited. Here is a
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114 | 4390df51 | bellard | summary of the ranges:
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115 | 4390df51 | bellard | |
116 | 4390df51 | bellard | i386 : signed 32 bits
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117 | 4390df51 | bellard | arm : signed 26 bits
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118 | 4390df51 | bellard | ppc : signed 24 bits
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119 | 4390df51 | bellard | sparc : signed 32 bits
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120 | 4390df51 | bellard | alpha : signed 23 bits
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121 | 4390df51 | bellard | */
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122 | 4390df51 | bellard | |
123 | 4390df51 | bellard | #if defined(__alpha__)
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124 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
125 | 4390df51 | bellard | #elif defined(__powerpc__)
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126 | c4c7e3e6 | bellard | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
127 | 4390df51 | bellard | #else
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128 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024) |
129 | 4390df51 | bellard | #endif
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130 | 4390df51 | bellard | |
131 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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132 | d4e8164f | bellard | |
133 | 4390df51 | bellard | /* estimated block size for TB allocation */
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134 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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135 | 4390df51 | bellard | according to the host CPU */
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136 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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137 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
138 | 4390df51 | bellard | #else
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139 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
140 | 4390df51 | bellard | #endif
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141 | 4390df51 | bellard | |
142 | 4390df51 | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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143 | 4390df51 | bellard | |
144 | 4390df51 | bellard | #if defined(__powerpc__)
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145 | 4390df51 | bellard | #define USE_DIRECT_JUMP
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146 | 4390df51 | bellard | #endif
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147 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
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148 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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149 | d4e8164f | bellard | #endif
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150 | d4e8164f | bellard | |
151 | d4e8164f | bellard | typedef struct TranslationBlock { |
152 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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153 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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154 | d4e8164f | bellard | unsigned int flags; /* flags defining in which context the code was generated */ |
155 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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156 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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157 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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158 | bf088061 | bellard | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
159 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
160 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
161 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
162 | 58fe2f10 | bellard | |
163 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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164 | 4390df51 | bellard | struct TranslationBlock *hash_next; /* next matching tb for virtual address */ |
165 | 4390df51 | bellard | /* next matching tb for physical address. */
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166 | 4390df51 | bellard | struct TranslationBlock *phys_hash_next;
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167 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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168 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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169 | 4390df51 | bellard | struct TranslationBlock *page_next[2]; |
170 | 4390df51 | bellard | target_ulong page_addr[2];
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171 | 4390df51 | bellard | |
172 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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173 | d4e8164f | bellard | the code of this one. */
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174 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
175 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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176 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
177 | d4e8164f | bellard | #else
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178 | 95f7652d | bellard | uint32_t tb_next[2]; /* address of jump generated code */ |
179 | d4e8164f | bellard | #endif
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180 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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181 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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182 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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183 | d4e8164f | bellard | jmp_first */
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184 | d4e8164f | bellard | struct TranslationBlock *jmp_next[2]; |
185 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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186 | d4e8164f | bellard | } TranslationBlock; |
187 | d4e8164f | bellard | |
188 | d4e8164f | bellard | static inline unsigned int tb_hash_func(unsigned long pc) |
189 | d4e8164f | bellard | { |
190 | d4e8164f | bellard | return pc & (CODE_GEN_HASH_SIZE - 1); |
191 | d4e8164f | bellard | } |
192 | d4e8164f | bellard | |
193 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
194 | 4390df51 | bellard | { |
195 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
196 | 4390df51 | bellard | } |
197 | 4390df51 | bellard | |
198 | d4e8164f | bellard | TranslationBlock *tb_alloc(unsigned long pc); |
199 | 0124311e | bellard | void tb_flush(CPUState *env);
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200 | d4e8164f | bellard | void tb_link(TranslationBlock *tb);
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201 | 4390df51 | bellard | void tb_link_phys(TranslationBlock *tb,
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202 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
203 | d4e8164f | bellard | |
204 | d4e8164f | bellard | extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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205 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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206 | d4e8164f | bellard | |
207 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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208 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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209 | d4e8164f | bellard | |
210 | d4e8164f | bellard | /* find a translation block in the translation cache. If not found,
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211 | d4e8164f | bellard | return NULL and the pointer to the last element of the list in pptb */
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212 | d4e8164f | bellard | static inline TranslationBlock *tb_find(TranslationBlock ***pptb, |
213 | 2e12669a | bellard | target_ulong pc, |
214 | 2e12669a | bellard | target_ulong cs_base, |
215 | d4e8164f | bellard | unsigned int flags) |
216 | d4e8164f | bellard | { |
217 | d4e8164f | bellard | TranslationBlock **ptb, *tb; |
218 | d4e8164f | bellard | unsigned int h; |
219 | d4e8164f | bellard | |
220 | d4e8164f | bellard | h = tb_hash_func(pc); |
221 | d4e8164f | bellard | ptb = &tb_hash[h]; |
222 | d4e8164f | bellard | for(;;) {
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223 | d4e8164f | bellard | tb = *ptb; |
224 | d4e8164f | bellard | if (!tb)
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225 | d4e8164f | bellard | break;
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226 | d4e8164f | bellard | if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
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227 | d4e8164f | bellard | return tb;
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228 | d4e8164f | bellard | ptb = &tb->hash_next; |
229 | d4e8164f | bellard | } |
230 | d4e8164f | bellard | *pptb = ptb; |
231 | d4e8164f | bellard | return NULL; |
232 | d4e8164f | bellard | } |
233 | d4e8164f | bellard | |
234 | d4e8164f | bellard | |
235 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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236 | 4390df51 | bellard | |
237 | 4390df51 | bellard | #if defined(__powerpc__)
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238 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
239 | d4e8164f | bellard | { |
240 | d4e8164f | bellard | uint32_t val, *ptr; |
241 | d4e8164f | bellard | |
242 | d4e8164f | bellard | /* patch the branch destination */
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243 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
244 | d4e8164f | bellard | val = *ptr; |
245 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
246 | d4e8164f | bellard | *ptr = val; |
247 | d4e8164f | bellard | /* flush icache */
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248 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
249 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
250 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
251 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
252 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
253 | d4e8164f | bellard | } |
254 | 4390df51 | bellard | #elif defined(__i386__)
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255 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
256 | 4390df51 | bellard | { |
257 | 4390df51 | bellard | /* patch the branch destination */
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258 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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259 | 4390df51 | bellard | /* no need to flush icache explicitely */
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260 | 4390df51 | bellard | } |
261 | 4390df51 | bellard | #endif
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262 | d4e8164f | bellard | |
263 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
264 | 4cbb86e1 | bellard | int n, unsigned long addr) |
265 | 4cbb86e1 | bellard | { |
266 | 4cbb86e1 | bellard | unsigned long offset; |
267 | 4cbb86e1 | bellard | |
268 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
269 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
270 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
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271 | 4cbb86e1 | bellard | if (offset != 0xffff) |
272 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
273 | 4cbb86e1 | bellard | } |
274 | 4cbb86e1 | bellard | |
275 | d4e8164f | bellard | #else
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276 | d4e8164f | bellard | |
277 | d4e8164f | bellard | /* set the jump target */
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278 | d4e8164f | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
279 | d4e8164f | bellard | int n, unsigned long addr) |
280 | d4e8164f | bellard | { |
281 | 95f7652d | bellard | tb->tb_next[n] = addr; |
282 | d4e8164f | bellard | } |
283 | d4e8164f | bellard | |
284 | d4e8164f | bellard | #endif
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285 | d4e8164f | bellard | |
286 | d4e8164f | bellard | static inline void tb_add_jump(TranslationBlock *tb, int n, |
287 | d4e8164f | bellard | TranslationBlock *tb_next) |
288 | d4e8164f | bellard | { |
289 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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290 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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291 | cf25629d | bellard | /* patch the native jump address */
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292 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
293 | cf25629d | bellard | |
294 | cf25629d | bellard | /* add in TB jmp circular list */
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295 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
296 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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297 | cf25629d | bellard | } |
298 | d4e8164f | bellard | } |
299 | d4e8164f | bellard | |
300 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
301 | a513fe19 | bellard | |
302 | d4e8164f | bellard | #ifndef offsetof
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303 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
304 | d4e8164f | bellard | #endif
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305 | d4e8164f | bellard | |
306 | d549f7d9 | bellard | #if defined(_WIN32)
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307 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
308 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
309 | d549f7d9 | bellard | #elif defined(__APPLE__)
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310 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
311 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
312 | d549f7d9 | bellard | #define ASM_NAME(x) "_" #x |
313 | d549f7d9 | bellard | #else
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314 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
315 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
316 | d549f7d9 | bellard | #define ASM_NAME(x) stringify(x)
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317 | d549f7d9 | bellard | #endif
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318 | d549f7d9 | bellard | |
319 | b346ff46 | bellard | #if defined(__powerpc__)
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320 | b346ff46 | bellard | |
321 | 4390df51 | bellard | /* we patch the jump instruction directly */
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322 | 9257a9e4 | bellard | #define JUMP_TB(opname, tbparam, n, eip)\
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323 | b346ff46 | bellard | do {\
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324 | d549f7d9 | bellard | asm volatile (ASM_DATA_SECTION\ |
325 | d549f7d9 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\ |
326 | 9257a9e4 | bellard | ".long 1f\n"\
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327 | d549f7d9 | bellard | ASM_PREVIOUS_SECTION \ |
328 | d549f7d9 | bellard | "b " ASM_NAME(__op_jmp) #n "\n"\ |
329 | 9257a9e4 | bellard | "1:\n");\
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330 | b346ff46 | bellard | T0 = (long)(tbparam) + (n);\
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331 | b346ff46 | bellard | EIP = eip;\ |
332 | 31e8f3c8 | bellard | EXIT_TB();\ |
333 | b346ff46 | bellard | } while (0) |
334 | b346ff46 | bellard | |
335 | 4cbb86e1 | bellard | #define JUMP_TB2(opname, tbparam, n)\
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336 | 4cbb86e1 | bellard | do {\
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337 | d549f7d9 | bellard | asm volatile ("b " ASM_NAME(__op_jmp) #n "\n");\ |
338 | 4390df51 | bellard | } while (0) |
339 | 4390df51 | bellard | |
340 | 4390df51 | bellard | #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
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341 | 4390df51 | bellard | |
342 | 4390df51 | bellard | /* we patch the jump instruction directly */
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343 | 4390df51 | bellard | #define JUMP_TB(opname, tbparam, n, eip)\
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344 | 4390df51 | bellard | do {\
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345 | 67b915a5 | bellard | asm volatile (".section .data\n"\ |
346 | d549f7d9 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\ |
347 | 4390df51 | bellard | ".long 1f\n"\
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348 | 67b915a5 | bellard | ASM_PREVIOUS_SECTION \ |
349 | d549f7d9 | bellard | "jmp " ASM_NAME(__op_jmp) #n "\n"\ |
350 | 4390df51 | bellard | "1:\n");\
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351 | 4390df51 | bellard | T0 = (long)(tbparam) + (n);\
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352 | 4390df51 | bellard | EIP = eip;\ |
353 | 4390df51 | bellard | EXIT_TB();\ |
354 | 4390df51 | bellard | } while (0) |
355 | 4390df51 | bellard | |
356 | 4390df51 | bellard | #define JUMP_TB2(opname, tbparam, n)\
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357 | 4390df51 | bellard | do {\
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358 | d549f7d9 | bellard | asm volatile ("jmp " ASM_NAME(__op_jmp) #n "\n");\ |
359 | 4cbb86e1 | bellard | } while (0) |
360 | 4cbb86e1 | bellard | |
361 | b346ff46 | bellard | #else
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362 | b346ff46 | bellard | |
363 | b346ff46 | bellard | /* jump to next block operations (more portable code, does not need
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364 | b346ff46 | bellard | cache flushing, but slower because of indirect jump) */
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365 | 9257a9e4 | bellard | #define JUMP_TB(opname, tbparam, n, eip)\
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366 | b346ff46 | bellard | do {\
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367 | b346ff46 | bellard | static void __attribute__((unused)) *__op_label ## n = &&label ## n;\ |
368 | 2f62b397 | bellard | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ |
369 | b346ff46 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
370 | b346ff46 | bellard | label ## n:\ |
371 | b346ff46 | bellard | T0 = (long)(tbparam) + (n);\
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372 | b346ff46 | bellard | EIP = eip;\ |
373 | 2f62b397 | bellard | dummy_label ## n:\ |
374 | 9621339d | bellard | EXIT_TB();\ |
375 | b346ff46 | bellard | } while (0) |
376 | b346ff46 | bellard | |
377 | 4cbb86e1 | bellard | /* second jump to same destination 'n' */
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378 | 4cbb86e1 | bellard | #define JUMP_TB2(opname, tbparam, n)\
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379 | 4cbb86e1 | bellard | do {\
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380 | 4390df51 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\ |
381 | 4cbb86e1 | bellard | } while (0) |
382 | 4cbb86e1 | bellard | |
383 | b346ff46 | bellard | #endif
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384 | b346ff46 | bellard | |
385 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
386 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
387 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
388 | 33417e70 | bellard | |
389 | d4e8164f | bellard | #ifdef __powerpc__
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390 | d4e8164f | bellard | static inline int testandset (int *p) |
391 | d4e8164f | bellard | { |
392 | d4e8164f | bellard | int ret;
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393 | d4e8164f | bellard | __asm__ __volatile__ ( |
394 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
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395 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
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396 | 02e1ec9b | bellard | " bne 1f\n"
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397 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
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398 | 02e1ec9b | bellard | " bne- 0b\n"
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399 | d4e8164f | bellard | "1: "
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400 | d4e8164f | bellard | : "=&r" (ret)
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401 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
402 | d4e8164f | bellard | : "cr0", "memory"); |
403 | d4e8164f | bellard | return ret;
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404 | d4e8164f | bellard | } |
405 | d4e8164f | bellard | #endif
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406 | d4e8164f | bellard | |
407 | d4e8164f | bellard | #ifdef __i386__
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408 | d4e8164f | bellard | static inline int testandset (int *p) |
409 | d4e8164f | bellard | { |
410 | d4e8164f | bellard | char ret;
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411 | d4e8164f | bellard | long int readval; |
412 | d4e8164f | bellard | |
413 | d4e8164f | bellard | __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
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414 | d4e8164f | bellard | : "=q" (ret), "=m" (*p), "=a" (readval) |
415 | d4e8164f | bellard | : "r" (1), "m" (*p), "a" (0) |
416 | d4e8164f | bellard | : "memory");
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417 | d4e8164f | bellard | return ret;
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418 | d4e8164f | bellard | } |
419 | d4e8164f | bellard | #endif
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420 | d4e8164f | bellard | |
421 | bc51c5c9 | bellard | #ifdef __x86_64__
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422 | bc51c5c9 | bellard | static inline int testandset (int *p) |
423 | bc51c5c9 | bellard | { |
424 | bc51c5c9 | bellard | char ret;
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425 | bc51c5c9 | bellard | int readval;
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426 | bc51c5c9 | bellard | |
427 | bc51c5c9 | bellard | __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
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428 | bc51c5c9 | bellard | : "=q" (ret), "=m" (*p), "=a" (readval) |
429 | bc51c5c9 | bellard | : "r" (1), "m" (*p), "a" (0) |
430 | bc51c5c9 | bellard | : "memory");
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431 | bc51c5c9 | bellard | return ret;
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432 | bc51c5c9 | bellard | } |
433 | bc51c5c9 | bellard | #endif
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434 | bc51c5c9 | bellard | |
435 | d4e8164f | bellard | #ifdef __s390__
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436 | d4e8164f | bellard | static inline int testandset (int *p) |
437 | d4e8164f | bellard | { |
438 | d4e8164f | bellard | int ret;
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439 | d4e8164f | bellard | |
440 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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441 | d4e8164f | bellard | " jl 0b"
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442 | d4e8164f | bellard | : "=&d" (ret)
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443 | d4e8164f | bellard | : "r" (1), "a" (p), "0" (*p) |
444 | d4e8164f | bellard | : "cc", "memory" ); |
445 | d4e8164f | bellard | return ret;
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446 | d4e8164f | bellard | } |
447 | d4e8164f | bellard | #endif
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448 | d4e8164f | bellard | |
449 | d4e8164f | bellard | #ifdef __alpha__
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450 | 2f87c607 | bellard | static inline int testandset (int *p) |
451 | d4e8164f | bellard | { |
452 | d4e8164f | bellard | int ret;
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453 | d4e8164f | bellard | unsigned long one; |
454 | d4e8164f | bellard | |
455 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
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456 | d4e8164f | bellard | " ldl_l %0,%1\n"
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457 | d4e8164f | bellard | " stl_c %2,%1\n"
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458 | d4e8164f | bellard | " beq %2,1f\n"
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459 | d4e8164f | bellard | ".subsection 2\n"
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460 | d4e8164f | bellard | "1: br 0b\n"
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461 | d4e8164f | bellard | ".previous"
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462 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
463 | d4e8164f | bellard | : "m" (*p));
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464 | d4e8164f | bellard | return ret;
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465 | d4e8164f | bellard | } |
466 | d4e8164f | bellard | #endif
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467 | d4e8164f | bellard | |
468 | d4e8164f | bellard | #ifdef __sparc__
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469 | d4e8164f | bellard | static inline int testandset (int *p) |
470 | d4e8164f | bellard | { |
471 | d4e8164f | bellard | int ret;
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472 | d4e8164f | bellard | |
473 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
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474 | d4e8164f | bellard | : "=r" (ret)
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475 | d4e8164f | bellard | : "r" (p)
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476 | d4e8164f | bellard | : "memory");
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477 | d4e8164f | bellard | |
478 | d4e8164f | bellard | return (ret ? 1 : 0); |
479 | d4e8164f | bellard | } |
480 | d4e8164f | bellard | #endif
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481 | d4e8164f | bellard | |
482 | a95c6790 | bellard | #ifdef __arm__
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483 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
484 | a95c6790 | bellard | { |
485 | a95c6790 | bellard | register unsigned int ret; |
486 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
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487 | a95c6790 | bellard | : "=r"(ret)
|
488 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
489 | a95c6790 | bellard | |
490 | a95c6790 | bellard | return ret;
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491 | a95c6790 | bellard | } |
492 | a95c6790 | bellard | #endif
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493 | a95c6790 | bellard | |
494 | 38e584a0 | bellard | #ifdef __mc68000
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495 | 38e584a0 | bellard | static inline int testandset (int *p) |
496 | 38e584a0 | bellard | { |
497 | 38e584a0 | bellard | char ret;
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498 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
|
499 | 38e584a0 | bellard | : "=r" (ret)
|
500 | 38e584a0 | bellard | : "m" (p)
|
501 | 38e584a0 | bellard | : "cc","memory"); |
502 | 38e584a0 | bellard | return ret == 0; |
503 | 38e584a0 | bellard | } |
504 | 38e584a0 | bellard | #endif
|
505 | 38e584a0 | bellard | |
506 | d4e8164f | bellard | typedef int spinlock_t; |
507 | d4e8164f | bellard | |
508 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
509 | d4e8164f | bellard | |
510 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
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511 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
512 | d4e8164f | bellard | { |
513 | d4e8164f | bellard | while (testandset(lock));
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514 | d4e8164f | bellard | } |
515 | d4e8164f | bellard | |
516 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
517 | d4e8164f | bellard | { |
518 | d4e8164f | bellard | *lock = 0;
|
519 | d4e8164f | bellard | } |
520 | d4e8164f | bellard | |
521 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
522 | d4e8164f | bellard | { |
523 | d4e8164f | bellard | return !testandset(lock);
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524 | d4e8164f | bellard | } |
525 | 3c1cf9fa | bellard | #else
|
526 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
527 | 3c1cf9fa | bellard | { |
528 | 3c1cf9fa | bellard | } |
529 | 3c1cf9fa | bellard | |
530 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
531 | 3c1cf9fa | bellard | { |
532 | 3c1cf9fa | bellard | } |
533 | 3c1cf9fa | bellard | |
534 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
535 | 3c1cf9fa | bellard | { |
536 | 3c1cf9fa | bellard | return 1; |
537 | 3c1cf9fa | bellard | } |
538 | 3c1cf9fa | bellard | #endif
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539 | d4e8164f | bellard | |
540 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
541 | d4e8164f | bellard | |
542 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
543 | 6e59c1db | bellard | |
544 | 9886cc16 | bellard | #if (defined(TARGET_I386) || defined(TARGET_PPC)) && \
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545 | 9886cc16 | bellard | !defined(CONFIG_USER_ONLY) |
546 | 6e59c1db | bellard | |
547 | 6e59c1db | bellard | void tlb_fill(unsigned long addr, int is_write, int is_user, |
548 | 6e59c1db | bellard | void *retaddr);
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549 | 6e59c1db | bellard | |
550 | 6e59c1db | bellard | #define ACCESS_TYPE 3 |
551 | 6e59c1db | bellard | #define MEMSUFFIX _code
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552 | 6e59c1db | bellard | #define env cpu_single_env
|
553 | 6e59c1db | bellard | |
554 | 6e59c1db | bellard | #define DATA_SIZE 1 |
555 | 6e59c1db | bellard | #include "softmmu_header.h" |
556 | 6e59c1db | bellard | |
557 | 6e59c1db | bellard | #define DATA_SIZE 2 |
558 | 6e59c1db | bellard | #include "softmmu_header.h" |
559 | 6e59c1db | bellard | |
560 | 6e59c1db | bellard | #define DATA_SIZE 4 |
561 | 6e59c1db | bellard | #include "softmmu_header.h" |
562 | 6e59c1db | bellard | |
563 | 6e59c1db | bellard | #undef ACCESS_TYPE
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564 | 6e59c1db | bellard | #undef MEMSUFFIX
|
565 | 6e59c1db | bellard | #undef env
|
566 | 6e59c1db | bellard | |
567 | 6e59c1db | bellard | #endif
|
568 | 4390df51 | bellard | |
569 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
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570 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
571 | 4390df51 | bellard | { |
572 | 4390df51 | bellard | return addr;
|
573 | 4390df51 | bellard | } |
574 | 4390df51 | bellard | #else
|
575 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
576 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
577 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
578 | 4390df51 | bellard | /* XXX: i386 target specific */
|
579 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
580 | 4390df51 | bellard | { |
581 | 4390df51 | bellard | int is_user, index;
|
582 | 4390df51 | bellard | |
583 | 4390df51 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
584 | 3f5dcc34 | bellard | #if defined(TARGET_I386)
|
585 | 4390df51 | bellard | is_user = ((env->hflags & HF_CPL_MASK) == 3);
|
586 | 3f5dcc34 | bellard | #elif defined (TARGET_PPC)
|
587 | 3f5dcc34 | bellard | is_user = msr_pr; |
588 | 3f5dcc34 | bellard | #else
|
589 | 3f5dcc34 | bellard | #error "Unimplemented !" |
590 | 3f5dcc34 | bellard | #endif
|
591 | 4390df51 | bellard | if (__builtin_expect(env->tlb_read[is_user][index].address !=
|
592 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
593 | a541f297 | bellard | #if defined (TARGET_PPC)
|
594 | a541f297 | bellard | env->access_type = ACCESS_CODE; |
595 | a541f297 | bellard | ldub_code((void *)addr);
|
596 | a541f297 | bellard | env->access_type = ACCESS_INT; |
597 | a541f297 | bellard | #else
|
598 | 4390df51 | bellard | ldub_code((void *)addr);
|
599 | a541f297 | bellard | #endif
|
600 | 4390df51 | bellard | } |
601 | 4390df51 | bellard | return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base; |
602 | 4390df51 | bellard | } |
603 | 4390df51 | bellard | #endif |