Archipelago » qemu

    register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);

    s->irq = sci_irq;

    qemu_register_reset(piix4_reset, 0, s);

    s = qemu_mallocz(sizeof(APBState));

    /* Ultrasparc PBM main bus */

    pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,

                                            pci_apb_config_write, s);

    int pci_mem_config, pci_mem_data;

    s = qemu_mallocz(sizeof(GrackleState));

                              pic, 0, 4);

    pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,

    s = qemu_mallocz(sizeof(GT64120State));

    s->pci = qemu_mallocz(sizeof(GT64120PCIState));

                                   pic, 144, 4);

    s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s);

    d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),

struct i2c_bus

{

    i2c_slave *current_dev;

    i2c_slave *dev;

    int saved_address;

}

/* Create a new I2C bus.  */

{

    i2c_bus *bus;

    register_savevm("i2c_bus", -1, 1, i2c_bus_save, i2c_bus_load, bus);

    return bus;

}

/* TODO: Make this handle multiple masters.  */

int i2c_start_transfer(i2c_bus *bus, int address, int recv)

{

            break;

    }

        return 1;

    /* If the bus is already busy, assume this is a repeated

       start condition.  */

    return 0;

}

void i2c_slave_load(QEMUFile *f, i2c_slave *dev)

{

    i2c_bus *bus;

    dev->address = qemu_get_byte(f);

    if (bus->saved_address == dev->address) {

        bus->current_dev = dev;

    }

}

{

    i2c_slave *s = I2C_SLAVE_FROM_QDEV(dev);

    s->info = info;

    s->address = qdev_get_prop_int(dev, "address", 0);

    info->init(s);

}

void i2c_register_slave(const char *name, int size, I2CSlaveInfo *info)

{

    assert(size >= sizeof(i2c_slave));

}

DeviceState *i2c_create_slave(i2c_bus *bus, const char *name, int addr)

{

    DeviceState *dev;

    qdev_set_prop_int(dev, "address", addr);

    qdev_init(dev);

    return dev;

typedef void (*i2c_slave_initfn)(i2c_slave *dev);

typedef struct {

    /* Callbacks provided by the device.  */

    i2c_slave_initfn init;

    i2c_event_cb event;

    /* Remaining fields for internal use by the I2C code.  */

    int address;

};

void i2c_set_slave_address(i2c_slave *dev, int address);

int i2c_bus_busy(i2c_bus *bus);

int i2c_start_transfer(i2c_bus *bus, int address, int recv);

    for (i = 0; i < 8; i++) {

        /* TODO: Populate SPD eeprom data.  */

        DeviceState *eeprom;

        qdev_set_prop_int(eeprom, "address", 0x50 + i);

        qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256));

        qdev_init(eeprom);

    s->irq = irq;

    i2c = qemu_mallocz(sizeof(i2c_interface));

    i2c->current_addr = -1;

    s->wm = i2c_create_slave(i2c->bus, "wm8750", MP_WM_ADDR);

    s->irq = irq;

    s->drq[0] = dma[0];

    s->drq[1] = dma[1];

    omap_i2c_reset(s);

    iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,

    s->irq = irq;

    s->drq[0] = dma[0];

    s->drq[1] = dma[1];

    omap_i2c_reset(s);

    iomemtype = l4_register_io_memory(0, omap_i2c_readfn,

        smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);

        for (i = 0; i < 8; i++) {

            DeviceState *eeprom;

            qdev_set_prop_int(eeprom, "address", 0x50 + i);

            qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256));

            qdev_init(eeprom);

//#define DEBUG_PCI

struct PCIBus {

    int bus_num;

    int devfn_min;

    pci_set_irq_fn set_irq;

    return 0;

}

                         qemu_irq *pic, int devfn_min, int nirq)

{

    PCIBus *bus;

    static int nbus = 0;

    bus->set_irq = set_irq;

    bus->map_irq = map_irq;

    bus->irq_opaque = pic;

    qemu_free_irqs(pci_dev->irq);

    pci_irq_index--;

    pci_dev->bus->devices[pci_dev->devfn] = NULL;

    return 0;

}

    for (i = 0; pci_nic_models[i]; i++) {

        if (strcmp(nd->model, pci_nic_models[i]) == 0) {

            qdev_set_prop_int(dev, "devfn", devfn);

            qdev_set_netdev(dev, nd);

            qdev_init(dev);

    return s->bus;

}

{

    PCIDevice *pci_dev = (PCIDevice *)qdev;

    PCIBus *bus;

    int devfn;

    devfn = qdev_get_prop_int(qdev, "devfn", -1);

    pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,

                                     NULL, NULL);//FIXME:config_read, config_write);

    assert(pci_dev);

}

void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)

{

}

PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)

{

    DeviceState *dev;

    qdev_set_prop_int(dev, "devfn", devfn);

    qdev_init(dev);

typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);

typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);

                         qemu_irq *pic, int devfn_min, int nirq);

PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,

    I440FXState *s;

    s = qemu_mallocz(sizeof(I440FXState));

    s->bus = b;

    register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);

                                       pl022_writefn, s);

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    sysbus_init_irq(dev, &s->irq);

    pl022_reset(s);

    register_savevm("pl022_ssp", -1, 1, pl022_save, pl022_load, s);

}

    controller = qemu_mallocz(sizeof(PPC4xxPCIState));

                                                 ppc4xx_pci_map_irq,

                                                 pci_irqs, 0, 4);

    controller = qemu_mallocz(sizeof(PPCE500PCIState));

                                                 mpc85xx_pci_map_irq,

                                                 pci_irqs, 0x88, 4);

    d = pci_register_device(controller->pci_state.bus,

    int PPC_io_memory;

    s = qemu_mallocz(sizeof(PREPPCIState));

    register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);

    register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);

    register_savevm("pxa2xx_ssp", -1, 0,

                    pxa2xx_ssp_save, pxa2xx_ssp_load, s);

}

/* Real-Time Clock */

    PXA2xxI2CState *s = qemu_mallocz(sizeof(PXA2xxI2CState));

    /* FIXME: Should the slave device really be on a separate bus?  */

    s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));

    s->slave->host = s;

    s->irq = irq;

    s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK);

    iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,

        DeviceState *dev;

        dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,

                                   s->pic[pxa27x_ssp[i].irqn]);

    }

    if (usb_enabled) {

        DeviceState *dev;

        dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,

                                   s->pic[pxa255_ssp[i].irqn]);

    }

    if (usb_enabled) {

struct DeviceType {

    const char *name;

    int size;

    DeviceType *next;

};

static DeviceType *device_type_list;

/* Register a new device type.  */

{

    DeviceType *t;

    device_type_list = t;

    t->name = qemu_strdup(name);

    t->size = size;

}

/* Create a new device.  This only initializes the device state structure

   and allows properties to be set.  qdev_init should be called to

   initialize the actual device emulation.  */

{

    DeviceType *t;

    DeviceState *dev;

        }

    }

    if (!t) {

    }

    dev = qemu_mallocz(t->size);

    dev->name = name;

    dev->type = t;

    return dev;

}

   calling this function.  */

void qdev_init(DeviceState *dev)

{

}

static DeviceProperty *create_prop(DeviceState *dev, const char *name)

    }

}

{

}

static DeviceProperty *find_prop(DeviceState *dev, const char *name)

    return drives_table[index].bdrv;

}

{

        if (strcmp(name, bus->name) == 0) {

        }

    }

    return NULL;

}

static int next_scsi_bus;

/* Create a scsi bus, and attach devices to it.  */

       attach(host, drives_table[index].bdrv, unit);

   }

}

#define QDEV_H

#include "hw.h"

typedef struct DeviceType DeviceType;

typedef struct DeviceProperty DeviceProperty;

/* This structure should not be accessed directly.  We declare it here

   so that it can be embedded in individual device state structures.  */

    const char *name;

    DeviceType *type;

    DeviceProperty *props;

    int num_irq_sink;

    qemu_irq *irq_sink;

    qemu_irq *gpio_out;

    int num_gpio_in;

    qemu_irq *gpio_in;

    NICInfo *nd;

};

/*** Board API.  This should go away once we have a machine config file.  ***/

void qdev_init(DeviceState *dev);

/* Set properties between creation and init.  */

void qdev_set_prop_int(DeviceState *dev, const char *name, uint64_t value);

qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);

void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin);

/*** Device API.  ***/

typedef void (*SCSIAttachFn)(DeviceState *host, BlockDriverState *bdrv,

              int unit);

/* Register device properties.  */

void qdev_init_irq_sink(DeviceState *dev, qemu_irq_handler handler, int nirq);

void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n);

void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n);

void scsi_bus_new(DeviceState *host, SCSIAttachFn attach);

CharDriverState *qdev_init_chardev(DeviceState *dev);

uint64_t qdev_get_prop_int(DeviceState *dev, const char *name, uint64_t def);

void *qdev_get_prop_ptr(DeviceState *dev, const char *name);

#define DO_UPCAST(type, field, dev) container_of(dev, type, field)

#endif

#endif

    dev = sysbus_create_varargs("realview_pci", 0x60000000,

                                pic[48], pic[49], pic[50], pic[51], NULL);

    if (usb_enabled) {

        usb_ohci_init_pci(pci_bus, 3, -1);

    }

    int mem, reg, iop;

    p = qemu_mallocz(sizeof(SHPCIC));

    p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),

                                 -1, NULL, NULL);

    CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);

    qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3);

    register_savevm("spitz_ssp", -1, 1, spitz_ssp_save, spitz_ssp_load, s);

}

#include "ssi.h"

struct SSIBus {

};

{

    SSISlave *s = SSI_SLAVE_FROM_QDEV(dev);

    s->info = info;

    info->init(s);

}

void ssi_register_slave(const char *name, int size, SSISlaveInfo *info)

{

    assert(size >= sizeof(SSISlave));

}

DeviceState *ssi_create_slave(SSIBus *bus, const char *name)

{

    DeviceState *dev;

    qdev_init(dev);

    return dev;

}

{

}

uint32_t ssi_transfer(SSIBus *bus, uint32_t val)

{

        return 0;

    }

}

/* Slave devices.  */

typedef struct {

    void (*init)(SSISlave *dev);

    uint32_t (*transfer)(SSISlave *dev, uint32_t val);

} SSISlaveInfo;

DeviceState *ssi_create_slave(SSIBus *bus, const char *name);

/* Master interface.  */

uint32_t ssi_transfer(SSIBus *bus, uint32_t val);

static void stellaris_i2c_init(SysBusDevice * dev)

{

    stellaris_i2c_state *s = FROM_SYSBUS(stellaris_i2c_state, dev);

    int iomemtype;

    sysbus_init_irq(dev, &s->irq);

    s->bus = bus;

    iomemtype = cpu_register_io_memory(0, stellaris_i2c_readfn,

{

    stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);

    qdev_init_gpio_in(&dev->qdev, stellaris_ssi_bus_select, 1);

    register_savevm("stellaris_ssi_bus", -1, 1,

    if (board->dc2 & (1 << 12)) {

        DeviceState *dev;

        dev = sysbus_create_simple("stellaris-i2c", 0x40020000, pic[8]);

        if (board->peripherals & BP_OLED_I2C) {

            i2c_create_slave(i2c, "ssd0303", 0x3d);

        }

#include "sysbus.h"

#include "sysemu.h"

void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq)

{

    assert(n >= 0 && n < dev->num_irq);

    dev->mmio[n].cb = cb;

}

{

}

void sysbus_register_dev(const char *name, size_t size, sysbus_initfn init)

{

    assert(size >= sizeof(SysBusDevice));

}

DeviceState *sysbus_create_varargs(const char *name,

    /* Use values found on a real PowerMac */

    /* Uninorth main bus */

    s = qemu_mallocz(sizeof(UNINState));

                              pic, 11 << 3, 4);

    pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,

    for (i = 0; i < 4; i++) {

        sysbus_init_irq(dev, &s->irq[i]);

    }

                           11 << 3, 4);

    /* ??? Register memory space.  */

    dev = sysbus_create_varargs("versatile_pci", 0x40000000,

                                sic[27], sic[28], sic[29], sic[30], NULL);

    /* The Versatile PCI bridge does not provide access to PCI IO space,

       so many of the qemu PCI devices are not useable.  */