Revision 02f4f6c2 target-ppc/translate.c
| b/target-ppc/translate.c | ||
|---|---|---|
| 80 | 80 |
static uint16_t **gen_fprf_ptr; |
| 81 | 81 |
#endif |
| 82 | 82 |
|
| 83 |
static always_inline void gen_set_T0 (target_ulong val) |
|
| 84 |
{
|
|
| 85 |
#if defined(TARGET_PPC64) |
|
| 86 |
if (val >> 32) |
|
| 87 |
gen_op_set_T0_64(val >> 32, val); |
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| 88 |
else |
|
| 89 |
#endif |
|
| 90 |
gen_op_set_T0(val); |
|
| 91 |
} |
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| 92 |
|
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| 93 |
static always_inline void gen_set_T1 (target_ulong val) |
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{
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| 95 |
#if defined(TARGET_PPC64) |
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if (val >> 32) |
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gen_op_set_T1_64(val >> 32, val); |
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else |
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#endif |
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gen_op_set_T1(val); |
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} |
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| 102 |
|
|
| 103 | 83 |
#define GEN8(func, NAME) \ |
| 104 | 84 |
static GenOpFunc *NAME ## _table [8] = { \
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| 105 | 85 |
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
| ... | ... | |
| 1004 | 984 |
|
| 1005 | 985 |
if (rA(ctx->opcode) == 0) {
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| 1006 | 986 |
/* li case */ |
| 1007 |
gen_set_T0(simm);
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|
| 987 |
tcg_gen_movi_tl(cpu_T[0], simm);
|
|
| 1008 | 988 |
} else {
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| 1009 | 989 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 1010 | 990 |
if (likely(simm != 0)) |
| ... | ... | |
| 1060 | 1040 |
|
| 1061 | 1041 |
if (rA(ctx->opcode) == 0) {
|
| 1062 | 1042 |
/* lis case */ |
| 1063 |
gen_set_T0(simm << 16);
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| 1043 |
tcg_gen_movi_tl(cpu_T[0], simm << 16);
|
|
| 1064 | 1044 |
} else {
|
| 1065 | 1045 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 1066 | 1046 |
if (likely(simm != 0)) |
| ... | ... | |
| 1161 | 1141 |
uint32_t mask; |
| 1162 | 1142 |
|
| 1163 | 1143 |
if (rA(ctx->opcode) == 0) {
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| 1164 |
gen_set_T0(0);
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| 1144 |
tcg_gen_movi_tl(cpu_T[0], 0);
|
|
| 1165 | 1145 |
} else {
|
| 1166 | 1146 |
gen_op_load_gpr_T1(rA(ctx->opcode)); |
| 1167 | 1147 |
} |
| ... | ... | |
| 2100 | 2080 |
|
| 2101 | 2081 |
simm &= ~maskl; |
| 2102 | 2082 |
if (rA(ctx->opcode) == 0) {
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| 2103 |
gen_set_T0(simm);
|
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| 2083 |
tcg_gen_movi_tl(cpu_T[0], simm);
|
|
| 2104 | 2084 |
} else {
|
| 2105 | 2085 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 2106 | 2086 |
if (likely(simm != 0)) |
| ... | ... | |
| 2823 | 2803 |
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
| 2824 | 2804 |
likely(!ctx->singlestep_enabled)) {
|
| 2825 | 2805 |
tcg_gen_goto_tb(n); |
| 2826 |
gen_set_T1(dest);
|
|
| 2806 |
tcg_gen_movi_tl(cpu_T[1], dest);
|
|
| 2827 | 2807 |
#if defined(TARGET_PPC64) |
| 2828 | 2808 |
if (ctx->sf_mode) |
| 2829 | 2809 |
gen_op_b_T1_64(); |
| ... | ... | |
| 2832 | 2812 |
gen_op_b_T1(); |
| 2833 | 2813 |
tcg_gen_exit_tb((long)tb + n); |
| 2834 | 2814 |
} else {
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gen_set_T1(dest);
|
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| 2815 |
tcg_gen_movi_tl(cpu_T[1], dest);
|
|
| 2836 | 2816 |
#if defined(TARGET_PPC64) |
| 2837 | 2817 |
if (ctx->sf_mode) |
| 2838 | 2818 |
gen_op_b_T1_64(); |
| ... | ... | |
| 3185 | 3165 |
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) |
| 3186 | 3166 |
{
|
| 3187 | 3167 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 3188 |
gen_set_T1(SIMM(ctx->opcode));
|
|
| 3168 |
tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
|
|
| 3189 | 3169 |
/* Update the nip since this might generate a trap exception */ |
| 3190 | 3170 |
gen_update_nip(ctx, ctx->nip); |
| 3191 | 3171 |
gen_op_tw(TO(ctx->opcode)); |
| ... | ... | |
| 3206 | 3186 |
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) |
| 3207 | 3187 |
{
|
| 3208 | 3188 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 3209 |
gen_set_T1(SIMM(ctx->opcode));
|
|
| 3189 |
tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
|
|
| 3210 | 3190 |
/* Update the nip since this might generate a trap exception */ |
| 3211 | 3191 |
gen_update_nip(ctx, ctx->nip); |
| 3212 | 3192 |
gen_op_td(TO(ctx->opcode)); |
| ... | ... | |
| 5335 | 5315 |
target_long simm = rB(ctx->opcode); |
| 5336 | 5316 |
|
| 5337 | 5317 |
if (rA(ctx->opcode) == 0) {
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| 5338 |
gen_set_T0(simm << sh);
|
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| 5318 |
tcg_gen_movi_tl(cpu_T[0], simm << sh);
|
|
| 5339 | 5319 |
} else {
|
| 5340 | 5320 |
gen_op_load_gpr_T0(rA(ctx->opcode)); |
| 5341 | 5321 |
if (likely(simm != 0)) |
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