Archipelago » qemu

/* page related stuff */

#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)

#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)

int cpu_inl(CPUState *env, int addr);

#endif

/* memory API */

extern int phys_ram_fd;

extern uint8_t *phys_ram_base;

extern uint8_t *phys_ram_dirty;

/* physical memory access */

#define TLB_INVALID_MASK   (1 << 3)

typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);

void cpu_register_physical_memory(target_phys_addr_t start_addr,

void qemu_ram_free(ram_addr_t addr);

int cpu_register_io_memory(int io_index,

                           CPUReadMemoryFunc **mem_read,

#error TARGET_PHYS_ADDR_BITS undefined

#endif

#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)

#define EXCP_INTERRUPT 	0x10000 /* async interruption */

void cpu_resume_from_signal(CPUState *env1, void *puc);

void cpu_exec_init(CPUState *env);

int page_unprotect(target_ulong address, unsigned long pc, void *puc);

                                   int is_cpu_write_access);

void tb_invalidate_page_range(target_ulong start, target_ulong end);

void tlb_flush_page(CPUState *env, target_ulong addr);

#define TARGET_VIRT_ADDR_SPACE_BITS 42

#elif defined(TARGET_PPC64)

#define TARGET_PHYS_ADDR_SPACE_BITS 42

#else

/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */

#define TARGET_PHYS_ADDR_SPACE_BITS 32

uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE] __attribute__((aligned (32)));

uint8_t *code_gen_ptr;

int phys_ram_fd;

uint8_t *phys_ram_base;

uint8_t *phys_ram_dirty;

typedef struct PhysPageDesc {

    /* offset in host memory of the page + io_index in the low 12 bits */

} PhysPageDesc;

#define L2_BITS 10

 */

#define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)

#else

#endif

#define L1_SIZE (1 << L1_BITS)

#define L2_SIZE (1 << L2_BITS)

#endif

}

{

    PageDesc **lp, *p;

    return p + (index & (L2_SIZE - 1));

}

{

    PageDesc *p;

    PhysPageDesc *pd;

    p = (void **)l1_phys_map;

#if TARGET_PHYS_ADDR_SPACE_BITS > 32

#if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)

        *lp = p;

    }

#endif

    lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));

    pd = *lp;

    if (!pd) {

    tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));

}

{

    CPUState *env;

    PageDesc *p;

    unsigned int h, n1;

    TranslationBlock *tb1, *tb2;

    /* remove the TB from the hash list */

   the same physical page. 'is_cpu_write_access' should be true if called

   from a real cpu write access: the virtual CPU will exit the current

   TB if code is modified inside this TB. */

                                   int is_cpu_write_access)

{

    int n, current_tb_modified, current_tb_not_found, current_flags;

}

/* len must be <= 8 and start must be a multiple of len */

{

    PageDesc *p;

    int offset, b;

}

#if !defined(CONFIG_SOFTMMU)

                                    unsigned long pc, void *puc)

{

    int n, current_flags, current_tb_modified;

static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,

                             int memory);

                           int orig_memory);

#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \

                      need_subpage)                                     \

   page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an

   io memory page */

void cpu_register_physical_memory(target_phys_addr_t start_addr,

{

    target_phys_addr_t addr, end_addr;

    PhysPageDesc *p;

    CPUState *env;

    void *subpage;

    size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;

    for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {

        p = phys_page_find(addr >> TARGET_PAGE_BITS);

        if (p && p->phys_offset != IO_MEM_UNASSIGNED) {

            target_phys_addr_t start_addr2, end_addr2;

            int need_subpage = 0;

}

/* XXX: temporary until new memory mapping API */

{

    PhysPageDesc *p;

}

/* XXX: better than nothing */

{

    ram_addr_t addr;

    if ((phys_ram_alloc_offset + size) >= phys_ram_size) {

        abort();

    }

    addr = phys_ram_alloc_offset;

    return 0;

}

                           int orig_memory)

{

    subpage_t *mmio;

/* Board init.  */

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

#ifndef HW_BOARDS_H

#define HW_BOARDS_H

                                 const char *boot_device, DisplayState *ds,

                                 const char *kernel_filename,

                                 const char *kernel_cmdline,

/* Board init.  */

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

void etraxfs_ser_init(CPUState *env, qemu_irq *irqs, target_phys_addr_t base);

static

                       const char *boot_device, DisplayState *ds,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

static const int sector_len = 128 * 1024;

                const char *boot_device, DisplayState *ds,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

                    pxa2xx_gpio_in_get(cpu->gpio)[36]);

}

                const char *boot_device, DisplayState *ds,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

    .board_id = 0x113,

};

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

    .ram_size = 0x04000000,

};

                DisplayState *ds, const char *kernel_filename,

                const char *kernel_cmdline, const char *initrd_filename,

                const char *cpu_model, enum mainstone_model_e model, int arm_id)

    arm_load_kernel(cpu->env, &mainstone_binfo);

}

                const char *boot_device, DisplayState *ds,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

    }

}

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)

static

                     DisplayState *ds, const char *cpu_model,

                     enum jazz_model_e jazz_model)

{

}

static

                       const char *boot_device, DisplayState *ds,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

}

static

                       const char *boot_device, DisplayState *ds,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

}

static

                      const char *boot_device, DisplayState *ds,

                      const char *kernel_filename, const char *kernel_cmdline,

                      const char *initrd_filename, const char *cpu_model)

}

static void

                   const char *boot_device, DisplayState *ds,

                   const char *kernel_filename, const char *kernel_cmdline,

                   const char *initrd_filename, const char *cpu_model)

static const int sector_len = 32 * 1024;

static

                    const char *boot_device, DisplayState *ds,

                    const char *kernel_filename, const char *kernel_cmdline,

                    const char *initrd_filename, const char *cpu_model)

    .atag_board = n800_atag_setup,

};

                const char *boot_device, DisplayState *ds,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

    .board_id = 0x331,

};

                const char *boot_device, DisplayState *ds,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

}

/* hd_table must contain 4 block drivers */

{

    RTCState *s = rtc_state;

    int nbds, bds[3] = { 0, };

    rtc_set_memory(s, 0x30, val);

    rtc_set_memory(s, 0x31, val >> 8);

    if (ram_size > (16 * 1024 * 1024))

        val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);

    else

}

/* PC hardware initialisation */

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename,

    char buf[1024];

    int ret, linux_boot, i;

    ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;

    int bios_size, isa_bios_size, vga_bios_size;

    PCIBus *pci_bus;

    int piix3_devfn = -1;

    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];

    BlockDriverState *fd[MAX_FD];

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */

    /* allocate RAM */

    ram_addr = qemu_ram_alloc(ram_size);

    /* allocate VGA RAM */

    vga_ram_addr = qemu_ram_alloc(vga_ram_size);

    }

    floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);

    if (pci_enabled && usb_enabled) {

        usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);

    }

}

                        const char *boot_device, DisplayState *ds,

                        const char *kernel_filename,

                        const char *kernel_cmdline,

             initrd_filename, 1, cpu_model);

}

                        const char *boot_device, DisplayState *ds,

                        const char *kernel_filename,

                        const char *kernel_cmdline,

    return (irq_num + slot_addend) & 3;

}

static uint8_t smm_enabled;

static int pci_irq_levels[4];

    }

}

                           const char *boot_device, DisplayState *ds,

                           const char *kernel_filename,

                           const char *kernel_cmdline,

    }

}

                             const char *boot_device, DisplayState *ds,

                             const char *kernel_filename,

                             const char *kernel_cmdline,

};

/* PowerPC Mac99 hardware initialisation */

                             const char *boot_device, DisplayState *ds,

                             const char *kernel_filename,

                             const char *kernel_cmdline,

    return 1; /* osi_call handled */

}

                               const char *boot_device, DisplayState *ds,

                               const char *kernel_filename,

                               const char *kernel_cmdline,

#define NVRAM_SIZE        0x2000

/* PowerPC PREP hardware initialisation */

                           const char *boot_device, DisplayState *ds,

                           const char *kernel_filename,

                           const char *kernel_cmdline,

#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */

#define SDRAM_SIZE 0x04000000

              const char *boot_device, DisplayState * ds,

	      const char *kernel_filename, const char *kernel_cmdline,

	      const char *initrd_filename, const char *cpu_model)

    .board_id = 0x33b,

};

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

    /* XXXXX */

}

               const char *boot_device, DisplayState * ds,

	       const char *kernel_filename, const char *kernel_cmdline,

	       const char *initrd_filename, const char *cpu_model)

    .ram_size = 0x04000000,

};

                DisplayState *ds, const char *kernel_filename,

                const char *kernel_cmdline, const char *initrd_filename,

                const char *cpu_model, enum spitz_model_e model, int arm_id)

    sl_bootparam_write(SL_PXA_PARAM_BASE - PXA2XX_SDRAM_BASE);

}

                const char *boot_device, DisplayState *ds,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

                kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);

}

                const char *boot_device, DisplayState *ds,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

                kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);

}

                const char *boot_device, DisplayState *ds,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

                kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);

}

                const char *boot_device, DisplayState *ds,

                const char *kernel_filename, const char *kernel_cmdline,

                const char *initrd_filename, const char *cpu_model)

}

/* FIXME: Figure out how to generate these from stellaris_boards.  */

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

    stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[0]);

}

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

};

/* SPARCstation 5 hardware initialisation */

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

}

/* SPARCstation 10 hardware initialisation */

                      const char *boot_device, DisplayState *ds,

                      const char *kernel_filename, const char *kernel_cmdline,

                      const char *initrd_filename, const char *cpu_model)

}

/* SPARCserver 600MP hardware initialisation */

                         const char *boot_device, DisplayState *ds,

                         const char *kernel_filename, const char *kernel_cmdline,

                         const char *initrd_filename, const char *cpu_model)

}

/* SPARCstation 20 hardware initialisation */

                      const char *boot_device, DisplayState *ds,

                      const char *kernel_filename, const char *kernel_cmdline,

                      const char *initrd_filename, const char *cpu_model)

}

/* SPARCstation 2 hardware initialisation */

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

}

/* SPARCserver 1000 hardware initialisation */

                        const char *boot_device, DisplayState *ds,

                        const char *kernel_filename, const char *kernel_cmdline,

                        const char *initrd_filename, const char *cpu_model)

}

/* SPARCcenter 2000 hardware initialisation */

                        const char *boot_device, DisplayState *ds,

                        const char *kernel_filename, const char *kernel_cmdline,

                        const char *initrd_filename, const char *cpu_model)

static fdctrl_t *floppy_controller;

/* Sun4u hardware initialisation */

                       const char *boot_devices, DisplayState *ds,

                       const char *kernel_filename, const char *kernel_cmdline,

                       const char *initrd_filename, const char *cpu_model)

static struct arm_boot_info versatile_binfo;

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model,

    arm_load_kernel(env, &versatile_binfo);

}

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

                   initrd_filename, cpu_model, 0x183);

}

                     const char *boot_device, DisplayState *ds,

                     const char *kernel_filename, const char *kernel_cmdline,

                     const char *initrd_filename, const char *cpu_model)

            int64_t free_space;

            int ram_mb;

            free_space = (int64_t)stfs.f_bavail * stfs.f_bsize;

            if ((ram_size + 8192 * 1024) >= free_space) {

                ram_mb = (ram_size / (1024 * 1024));

be needed to boot from old floppy disks.

@item -m @var{megs}

@item -smp @var{n}

Simulate an SMP system with @var{n} CPUs. On the PC target, up to 255

/* SLIRP */

void do_info_slirp(void);

extern int bios_size;

extern int cirrus_vga_enabled;

extern int vmsvga_enabled;

//#define DEBUG_UNUSED_IOPORT

//#define DEBUG_IOPORT

#ifdef TARGET_PPC

#define DEFAULT_RAM_SIZE 144

#else

int curses;

const char* keyboard_layout = NULL;

int64_t ticks_per_sec;

int pit_min_timer_count = 0;

int nb_nics;

NICInfo nd_table[MAX_NICS];

static int ram_load_v1(QEMUFile *f, void *opaque)

{

    if (qemu_get_be32(f) != phys_ram_size)

        return -EINVAL;

static void ram_save(QEMUFile *f, void *opaque)

{

    RamCompressState s1, *s = &s1;

    uint8_t buf[10];

{

    RamDecompressState s1, *s = &s1;

    uint8_t buf[10];

    if (version_id == 1)

        return ram_load_v1(f, opaque);

        }

        if (buf[0] == 0) {

            if (ram_decompress_buf(s, phys_ram_base + i, BDRV_HASH_BLOCK_SIZE) < 0) {

                goto error;

            }

        } else

            case QEMU_OPTION_h:

                help(0);

                break;

                    exit(1);

                }

                break;

            case QEMU_OPTION_d:

                {

                    int mask;