Revision 03c7a6a8

b/Makefile.objs
244 244
hw-obj-$(CONFIG_IDE_MACIO) += ide/macio.o
245 245
hw-obj-$(CONFIG_IDE_VIA) += ide/via.o
246 246
hw-obj-$(CONFIG_AHCI) += ide/ahci.o
247
hw-obj-$(CONFIG_AHCI) += ide/ich.o
247 248

  
248 249
# SCSI layer
249 250
hw-obj-$(CONFIG_LSI_SCSI_PCI) += lsi53c895a.o
b/hw/ide/ahci.c
72 72
#include "cpu-common.h"
73 73
#include "internal.h"
74 74
#include <hw/ide/pci.h>
75
#include <hw/ide/ahci.h>
75 76

  
76 77
/* #define DEBUG_AHCI */
77 78

  
......
83 84
#define DPRINTF(port, fmt, ...) do {} while(0)
84 85
#endif
85 86

  
86
#define AHCI_PCI_BAR              5
87
#define AHCI_MAX_PORTS            32
88
#define AHCI_MAX_SG               168 /* hardware max is 64K */
89
#define AHCI_DMA_BOUNDARY         0xffffffff
90
#define AHCI_USE_CLUSTERING       0
91
#define AHCI_MAX_CMDS             32
92
#define AHCI_CMD_SZ               32
93
#define AHCI_CMD_SLOT_SZ          (AHCI_MAX_CMDS * AHCI_CMD_SZ)
94
#define AHCI_RX_FIS_SZ            256
95
#define AHCI_CMD_TBL_CDB          0x40
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#define AHCI_CMD_TBL_HDR_SZ       0x80
97
#define AHCI_CMD_TBL_SZ           (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16))
98
#define AHCI_CMD_TBL_AR_SZ        (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS)
99
#define AHCI_PORT_PRIV_DMA_SZ     (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
100
                                   AHCI_RX_FIS_SZ)
101

  
102
#define AHCI_IRQ_ON_SG            (1 << 31)
103
#define AHCI_CMD_ATAPI            (1 << 5)
104
#define AHCI_CMD_WRITE            (1 << 6)
105
#define AHCI_CMD_PREFETCH         (1 << 7)
106
#define AHCI_CMD_RESET            (1 << 8)
107
#define AHCI_CMD_CLR_BUSY         (1 << 10)
108

  
109
#define RX_FIS_D2H_REG            0x40 /* offset of D2H Register FIS data */
110
#define RX_FIS_SDB                0x58 /* offset of SDB FIS data */
111
#define RX_FIS_UNK                0x60 /* offset of Unknown FIS data */
112

  
113
/* global controller registers */
114
#define HOST_CAP                  0x00 /* host capabilities */
115
#define HOST_CTL                  0x04 /* global host control */
116
#define HOST_IRQ_STAT             0x08 /* interrupt status */
117
#define HOST_PORTS_IMPL           0x0c /* bitmap of implemented ports */
118
#define HOST_VERSION              0x10 /* AHCI spec. version compliancy */
119

  
120
/* HOST_CTL bits */
121
#define HOST_CTL_RESET            (1 << 0)  /* reset controller; self-clear */
122
#define HOST_CTL_IRQ_EN           (1 << 1)  /* global IRQ enable */
123
#define HOST_CTL_AHCI_EN          (1 << 31) /* AHCI enabled */
124

  
125
/* HOST_CAP bits */
126
#define HOST_CAP_SSC              (1 << 14) /* Slumber capable */
127
#define HOST_CAP_AHCI             (1 << 18) /* AHCI only */
128
#define HOST_CAP_CLO              (1 << 24) /* Command List Override support */
129
#define HOST_CAP_SSS              (1 << 27) /* Staggered Spin-up */
130
#define HOST_CAP_NCQ              (1 << 30) /* Native Command Queueing */
131
#define HOST_CAP_64               (1 << 31) /* PCI DAC (64-bit DMA) support */
132

  
133
/* registers for each SATA port */
134
#define PORT_LST_ADDR             0x00 /* command list DMA addr */
135
#define PORT_LST_ADDR_HI          0x04 /* command list DMA addr hi */
136
#define PORT_FIS_ADDR             0x08 /* FIS rx buf addr */
137
#define PORT_FIS_ADDR_HI          0x0c /* FIS rx buf addr hi */
138
#define PORT_IRQ_STAT             0x10 /* interrupt status */
139
#define PORT_IRQ_MASK             0x14 /* interrupt enable/disable mask */
140
#define PORT_CMD                  0x18 /* port command */
141
#define PORT_TFDATA               0x20 /* taskfile data */
142
#define PORT_SIG                  0x24 /* device TF signature */
143
#define PORT_SCR_STAT             0x28 /* SATA phy register: SStatus */
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#define PORT_SCR_CTL              0x2c /* SATA phy register: SControl */
145
#define PORT_SCR_ERR              0x30 /* SATA phy register: SError */
146
#define PORT_SCR_ACT              0x34 /* SATA phy register: SActive */
147
#define PORT_CMD_ISSUE            0x38 /* command issue */
148
#define PORT_RESERVED             0x3c /* reserved */
149

  
150
/* PORT_IRQ_{STAT,MASK} bits */
151
#define PORT_IRQ_COLD_PRES        (1 << 31) /* cold presence detect */
152
#define PORT_IRQ_TF_ERR           (1 << 30) /* task file error */
153
#define PORT_IRQ_HBUS_ERR         (1 << 29) /* host bus fatal error */
154
#define PORT_IRQ_HBUS_DATA_ERR    (1 << 28) /* host bus data error */
155
#define PORT_IRQ_IF_ERR           (1 << 27) /* interface fatal error */
156
#define PORT_IRQ_IF_NONFATAL      (1 << 26) /* interface non-fatal error */
157
#define PORT_IRQ_OVERFLOW         (1 << 24) /* xfer exhausted available S/G */
158
#define PORT_IRQ_BAD_PMP          (1 << 23) /* incorrect port multiplier */
159

  
160
#define PORT_IRQ_PHYRDY           (1 << 22) /* PhyRdy changed */
161
#define PORT_IRQ_DEV_ILCK         (1 << 7) /* device interlock */
162
#define PORT_IRQ_CONNECT          (1 << 6) /* port connect change status */
163
#define PORT_IRQ_SG_DONE          (1 << 5) /* descriptor processed */
164
#define PORT_IRQ_UNK_FIS          (1 << 4) /* unknown FIS rx'd */
165
#define PORT_IRQ_SDB_FIS          (1 << 3) /* Set Device Bits FIS rx'd */
166
#define PORT_IRQ_DMAS_FIS         (1 << 2) /* DMA Setup FIS rx'd */
167
#define PORT_IRQ_PIOS_FIS         (1 << 1) /* PIO Setup FIS rx'd */
168
#define PORT_IRQ_D2H_REG_FIS      (1 << 0) /* D2H Register FIS rx'd */
169

  
170
#define PORT_IRQ_FREEZE           (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR |   \
171
                                   PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY |    \
172
                                   PORT_IRQ_UNK_FIS)
173
#define PORT_IRQ_ERROR            (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR |     \
174
                                   PORT_IRQ_HBUS_DATA_ERR)
175
#define DEF_PORT_IRQ              (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |     \
176
                                   PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |  \
177
                                   PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
178

  
179
/* PORT_CMD bits */
180
#define PORT_CMD_ATAPI            (1 << 24) /* Device is ATAPI */
181
#define PORT_CMD_LIST_ON          (1 << 15) /* cmd list DMA engine running */
182
#define PORT_CMD_FIS_ON           (1 << 14) /* FIS DMA engine running */
183
#define PORT_CMD_FIS_RX           (1 << 4) /* Enable FIS receive DMA engine */
184
#define PORT_CMD_CLO              (1 << 3) /* Command list override */
185
#define PORT_CMD_POWER_ON         (1 << 2) /* Power up device */
186
#define PORT_CMD_SPIN_UP          (1 << 1) /* Spin up device */
187
#define PORT_CMD_START            (1 << 0) /* Enable port DMA engine */
188

  
189
#define PORT_CMD_ICC_MASK         (0xf << 28) /* i/f ICC state mask */
190
#define PORT_CMD_ICC_ACTIVE       (0x1 << 28) /* Put i/f in active state */
191
#define PORT_CMD_ICC_PARTIAL      (0x2 << 28) /* Put i/f in partial state */
192
#define PORT_CMD_ICC_SLUMBER      (0x6 << 28) /* Put i/f in slumber state */
193

  
194
#define PORT_IRQ_STAT_DHRS        (1 << 0) /* Device to Host Register FIS */
195
#define PORT_IRQ_STAT_PSS         (1 << 1) /* PIO Setup FIS */
196
#define PORT_IRQ_STAT_DSS         (1 << 2) /* DMA Setup FIS */
197
#define PORT_IRQ_STAT_SDBS        (1 << 3) /* Set Device Bits */
198
#define PORT_IRQ_STAT_UFS         (1 << 4) /* Unknown FIS */
199
#define PORT_IRQ_STAT_DPS         (1 << 5) /* Descriptor Processed */
200
#define PORT_IRQ_STAT_PCS         (1 << 6) /* Port Connect Change Status */
201
#define PORT_IRQ_STAT_DMPS        (1 << 7) /* Device Mechanical Presence
202
                                              Status */
203
#define PORT_IRQ_STAT_PRCS        (1 << 22) /* File Ready Status */
204
#define PORT_IRQ_STAT_IPMS        (1 << 23) /* Incorrect Port Multiplier
205
                                               Status */
206
#define PORT_IRQ_STAT_OFS         (1 << 24) /* Overflow Status */
207
#define PORT_IRQ_STAT_INFS        (1 << 26) /* Interface Non-Fatal Error
208
                                               Status */
209
#define PORT_IRQ_STAT_IFS         (1 << 27) /* Interface Fatal Error */
210
#define PORT_IRQ_STAT_HBDS        (1 << 28) /* Host Bus Data Error Status */
211
#define PORT_IRQ_STAT_HBFS        (1 << 29) /* Host Bus Fatal Error Status */
212
#define PORT_IRQ_STAT_TFES        (1 << 30) /* Task File Error Status */
213
#define PORT_IRQ_STAT_CPDS        (1 << 31) /* Code Port Detect Status */
214

  
215
/* ap->flags bits */
216
#define AHCI_FLAG_NO_NCQ                  (1 << 24)
217
#define AHCI_FLAG_IGN_IRQ_IF_ERR          (1 << 25) /* ignore IRQ_IF_ERR */
218
#define AHCI_FLAG_HONOR_PI                (1 << 26) /* honor PORTS_IMPL */
219
#define AHCI_FLAG_IGN_SERR_INTERNAL       (1 << 27) /* ignore SERR_INTERNAL */
220
#define AHCI_FLAG_32BIT_ONLY              (1 << 28) /* force 32bit */
221

  
222
#define ATA_SRST                          (1 << 2)  /* software reset */
223

  
224
#define STATE_RUN                         0
225
#define STATE_RESET                       1
226

  
227
#define SATA_SCR_SSTATUS_DET_NODEV        0x0
228
#define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3
229

  
230
#define SATA_SCR_SSTATUS_SPD_NODEV        0x00
231
#define SATA_SCR_SSTATUS_SPD_GEN1         0x10
232

  
233
#define SATA_SCR_SSTATUS_IPM_NODEV        0x000
234
#define SATA_SCR_SSTATUS_IPM_ACTIVE       0X100
235

  
236
#define AHCI_SCR_SCTL_DET                 0xf
237

  
238
#define SATA_FIS_TYPE_REGISTER_H2D        0x27
239
#define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80
240

  
241
#define AHCI_CMD_HDR_CMD_FIS_LEN           0x1f
242
#define AHCI_CMD_HDR_PRDT_LEN              16
243

  
244
#define SATA_SIGNATURE_CDROM               0xeb140000
245
#define SATA_SIGNATURE_DISK                0x00000101
246

  
247
#define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x20
248
                                            /* Shouldn't this be 0x2c? */
249

  
250
#define SATA_PORTS                         4
251

  
252
#define AHCI_PORT_REGS_START_ADDR          0x100
253
#define AHCI_PORT_REGS_END_ADDR (AHCI_PORT_REGS_START_ADDR + SATA_PORTS * 0x80)
254
#define AHCI_PORT_ADDR_OFFSET_MASK         0x7f
255

  
256
#define AHCI_NUM_COMMAND_SLOTS             31
257
#define AHCI_SUPPORTED_SPEED               20
258
#define AHCI_SUPPORTED_SPEED_GEN1          1
259
#define AHCI_VERSION_1_0                   0x10000
260

  
261
#define AHCI_PROGMODE_MAJOR_REV_1          1
262

  
263
#define AHCI_COMMAND_TABLE_ACMD            0x40
264

  
265
#define IDE_FEATURE_DMA                    1
266

  
267
#define READ_FPDMA_QUEUED                  0x60
268
#define WRITE_FPDMA_QUEUED                 0x61
269

  
270
#define RES_FIS_DSFIS                      0x00
271
#define RES_FIS_PSFIS                      0x20
272
#define RES_FIS_RFIS                       0x40
273
#define RES_FIS_SDBFIS                     0x58
274
#define RES_FIS_UFIS                       0x60
275

  
276
typedef struct AHCIControlRegs {
277
    uint32_t    cap;
278
    uint32_t    ghc;
279
    uint32_t    irqstatus;
280
    uint32_t    impl;
281
    uint32_t    version;
282
} AHCIControlRegs;
283

  
284
typedef struct AHCIPortRegs {
285
    uint32_t    lst_addr;
286
    uint32_t    lst_addr_hi;
287
    uint32_t    fis_addr;
288
    uint32_t    fis_addr_hi;
289
    uint32_t    irq_stat;
290
    uint32_t    irq_mask;
291
    uint32_t    cmd;
292
    uint32_t    unused0;
293
    uint32_t    tfdata;
294
    uint32_t    sig;
295
    uint32_t    scr_stat;
296
    uint32_t    scr_ctl;
297
    uint32_t    scr_err;
298
    uint32_t    scr_act;
299
    uint32_t    cmd_issue;
300
    uint32_t    reserved;
301
} AHCIPortRegs;
302

  
303
typedef struct AHCICmdHdr {
304
    uint32_t    opts;
305
    uint32_t    status;
306
    uint64_t    tbl_addr;
307
    uint32_t    reserved[4];
308
} __attribute__ ((packed)) AHCICmdHdr;
309

  
310
typedef struct AHCI_SG {
311
    uint64_t    addr;
312
    uint32_t    reserved;
313
    uint32_t    flags_size;
314
} __attribute__ ((packed)) AHCI_SG;
315

  
316
typedef struct AHCIDevice AHCIDevice;
317

  
318
typedef struct NCQTransferState {
319
    AHCIDevice *drive;
320
    BlockDriverAIOCB *aiocb;
321
    QEMUSGList sglist;
322
    int is_read;
323
    uint16_t sector_count;
324
    uint64_t lba;
325
    uint8_t tag;
326
    int slot;
327
    int used;
328
} NCQTransferState;
329

  
330
struct AHCIDevice {
331
    IDEDMA dma;
332
    IDEBus port;
333
    int port_no;
334
    uint32_t port_state;
335
    uint32_t finished;
336
    AHCIPortRegs port_regs;
337
    struct AHCIState *hba;
338
    QEMUBH *check_bh;
339
    uint8_t *lst;
340
    uint8_t *res_fis;
341
    int dma_status;
342
    int done_atapi_packet;
343
    int busy_slot;
344
    BlockDriverCompletionFunc *dma_cb;
345
    AHCICmdHdr *cur_cmd;
346
    NCQTransferState ncq_tfs[AHCI_MAX_CMDS];
347
};
348

  
349
typedef struct AHCIState {
350
    AHCIDevice dev[SATA_PORTS];
351
    AHCIControlRegs control_regs;
352
    int mem;
353
    qemu_irq irq;
354
} AHCIState;
355

  
356
typedef struct AHCIPCIState {
357
    PCIDevice card;
358
    AHCIState ahci;
359
} AHCIPCIState;
360

  
361
typedef struct NCQFrame {
362
    uint8_t fis_type;
363
    uint8_t c;
364
    uint8_t command;
365
    uint8_t sector_count_low;
366
    uint8_t lba0;
367
    uint8_t lba1;
368
    uint8_t lba2;
369
    uint8_t fua;
370
    uint8_t lba3;
371
    uint8_t lba4;
372
    uint8_t lba5;
373
    uint8_t sector_count_high;
374
    uint8_t tag;
375
    uint8_t reserved5;
376
    uint8_t reserved6;
377
    uint8_t control;
378
    uint8_t reserved7;
379
    uint8_t reserved8;
380
    uint8_t reserved9;
381
    uint8_t reserved10;
382
} __attribute__ ((packed)) NCQFrame;
383

  
384 87
static void check_cmd(AHCIState *s, int port);
385 88
static int handle_cmd(AHCIState *s,int port,int slot);
386 89
static void ahci_reset_port(AHCIState *s, int port);
......
1410 1113
    .reset = ahci_dma_reset,
1411 1114
};
1412 1115

  
1413
static void ahci_init(AHCIState *s, DeviceState *qdev)
1116
void ahci_init(AHCIState *s, DeviceState *qdev)
1414 1117
{
1415 1118
    qemu_irq *irqs;
1416 1119
    int i;
......
1434 1137
    }
1435 1138
}
1436 1139

  
1437
static void ahci_pci_map(PCIDevice *pci_dev, int region_num,
1140
void ahci_pci_map(PCIDevice *pci_dev, int region_num,
1438 1141
        pcibus_t addr, pcibus_t size, int type)
1439 1142
{
1440 1143
    struct AHCIPCIState *d = (struct AHCIPCIState *)pci_dev;
......
1443 1146
    cpu_register_physical_memory(addr, size, s->mem);
1444 1147
}
1445 1148

  
1446
static void ahci_reset(void *opaque)
1149
void ahci_reset(void *opaque)
1447 1150
{
1448 1151
    struct AHCIPCIState *d = opaque;
1449 1152
    int i;
b/hw/ide/ahci.h
1
#ifndef HW_IDE_AHCI_H
2
#define HW_IDE_AHCI_H
3

  
4
#define AHCI_PCI_BAR              5
5
#define AHCI_MAX_PORTS            32
6
#define AHCI_MAX_SG               168 /* hardware max is 64K */
7
#define AHCI_DMA_BOUNDARY         0xffffffff
8
#define AHCI_USE_CLUSTERING       0
9
#define AHCI_MAX_CMDS             32
10
#define AHCI_CMD_SZ               32
11
#define AHCI_CMD_SLOT_SZ          (AHCI_MAX_CMDS * AHCI_CMD_SZ)
12
#define AHCI_RX_FIS_SZ            256
13
#define AHCI_CMD_TBL_CDB          0x40
14
#define AHCI_CMD_TBL_HDR_SZ       0x80
15
#define AHCI_CMD_TBL_SZ           (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16))
16
#define AHCI_CMD_TBL_AR_SZ        (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS)
17
#define AHCI_PORT_PRIV_DMA_SZ     (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
18
                                   AHCI_RX_FIS_SZ)
19

  
20
#define AHCI_IRQ_ON_SG            (1 << 31)
21
#define AHCI_CMD_ATAPI            (1 << 5)
22
#define AHCI_CMD_WRITE            (1 << 6)
23
#define AHCI_CMD_PREFETCH         (1 << 7)
24
#define AHCI_CMD_RESET            (1 << 8)
25
#define AHCI_CMD_CLR_BUSY         (1 << 10)
26

  
27
#define RX_FIS_D2H_REG            0x40 /* offset of D2H Register FIS data */
28
#define RX_FIS_SDB                0x58 /* offset of SDB FIS data */
29
#define RX_FIS_UNK                0x60 /* offset of Unknown FIS data */
30

  
31
/* global controller registers */
32
#define HOST_CAP                  0x00 /* host capabilities */
33
#define HOST_CTL                  0x04 /* global host control */
34
#define HOST_IRQ_STAT             0x08 /* interrupt status */
35
#define HOST_PORTS_IMPL           0x0c /* bitmap of implemented ports */
36
#define HOST_VERSION              0x10 /* AHCI spec. version compliancy */
37

  
38
/* HOST_CTL bits */
39
#define HOST_CTL_RESET            (1 << 0)  /* reset controller; self-clear */
40
#define HOST_CTL_IRQ_EN           (1 << 1)  /* global IRQ enable */
41
#define HOST_CTL_AHCI_EN          (1 << 31) /* AHCI enabled */
42

  
43
/* HOST_CAP bits */
44
#define HOST_CAP_SSC              (1 << 14) /* Slumber capable */
45
#define HOST_CAP_AHCI             (1 << 18) /* AHCI only */
46
#define HOST_CAP_CLO              (1 << 24) /* Command List Override support */
47
#define HOST_CAP_SSS              (1 << 27) /* Staggered Spin-up */
48
#define HOST_CAP_NCQ              (1 << 30) /* Native Command Queueing */
49
#define HOST_CAP_64               (1 << 31) /* PCI DAC (64-bit DMA) support */
50

  
51
/* registers for each SATA port */
52
#define PORT_LST_ADDR             0x00 /* command list DMA addr */
53
#define PORT_LST_ADDR_HI          0x04 /* command list DMA addr hi */
54
#define PORT_FIS_ADDR             0x08 /* FIS rx buf addr */
55
#define PORT_FIS_ADDR_HI          0x0c /* FIS rx buf addr hi */
56
#define PORT_IRQ_STAT             0x10 /* interrupt status */
57
#define PORT_IRQ_MASK             0x14 /* interrupt enable/disable mask */
58
#define PORT_CMD                  0x18 /* port command */
59
#define PORT_TFDATA               0x20 /* taskfile data */
60
#define PORT_SIG                  0x24 /* device TF signature */
61
#define PORT_SCR_STAT             0x28 /* SATA phy register: SStatus */
62
#define PORT_SCR_CTL              0x2c /* SATA phy register: SControl */
63
#define PORT_SCR_ERR              0x30 /* SATA phy register: SError */
64
#define PORT_SCR_ACT              0x34 /* SATA phy register: SActive */
65
#define PORT_CMD_ISSUE            0x38 /* command issue */
66
#define PORT_RESERVED             0x3c /* reserved */
67

  
68
/* PORT_IRQ_{STAT,MASK} bits */
69
#define PORT_IRQ_COLD_PRES        (1 << 31) /* cold presence detect */
70
#define PORT_IRQ_TF_ERR           (1 << 30) /* task file error */
71
#define PORT_IRQ_HBUS_ERR         (1 << 29) /* host bus fatal error */
72
#define PORT_IRQ_HBUS_DATA_ERR    (1 << 28) /* host bus data error */
73
#define PORT_IRQ_IF_ERR           (1 << 27) /* interface fatal error */
74
#define PORT_IRQ_IF_NONFATAL      (1 << 26) /* interface non-fatal error */
75
#define PORT_IRQ_OVERFLOW         (1 << 24) /* xfer exhausted available S/G */
76
#define PORT_IRQ_BAD_PMP          (1 << 23) /* incorrect port multiplier */
77

  
78
#define PORT_IRQ_PHYRDY           (1 << 22) /* PhyRdy changed */
79
#define PORT_IRQ_DEV_ILCK         (1 << 7) /* device interlock */
80
#define PORT_IRQ_CONNECT          (1 << 6) /* port connect change status */
81
#define PORT_IRQ_SG_DONE          (1 << 5) /* descriptor processed */
82
#define PORT_IRQ_UNK_FIS          (1 << 4) /* unknown FIS rx'd */
83
#define PORT_IRQ_SDB_FIS          (1 << 3) /* Set Device Bits FIS rx'd */
84
#define PORT_IRQ_DMAS_FIS         (1 << 2) /* DMA Setup FIS rx'd */
85
#define PORT_IRQ_PIOS_FIS         (1 << 1) /* PIO Setup FIS rx'd */
86
#define PORT_IRQ_D2H_REG_FIS      (1 << 0) /* D2H Register FIS rx'd */
87

  
88
#define PORT_IRQ_FREEZE           (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR |   \
89
                                   PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY |    \
90
                                   PORT_IRQ_UNK_FIS)
91
#define PORT_IRQ_ERROR            (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR |     \
92
                                   PORT_IRQ_HBUS_DATA_ERR)
93
#define DEF_PORT_IRQ              (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |     \
94
                                   PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |  \
95
                                   PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
96

  
97
/* PORT_CMD bits */
98
#define PORT_CMD_ATAPI            (1 << 24) /* Device is ATAPI */
99
#define PORT_CMD_LIST_ON          (1 << 15) /* cmd list DMA engine running */
100
#define PORT_CMD_FIS_ON           (1 << 14) /* FIS DMA engine running */
101
#define PORT_CMD_FIS_RX           (1 << 4) /* Enable FIS receive DMA engine */
102
#define PORT_CMD_CLO              (1 << 3) /* Command list override */
103
#define PORT_CMD_POWER_ON         (1 << 2) /* Power up device */
104
#define PORT_CMD_SPIN_UP          (1 << 1) /* Spin up device */
105
#define PORT_CMD_START            (1 << 0) /* Enable port DMA engine */
106

  
107
#define PORT_CMD_ICC_MASK         (0xf << 28) /* i/f ICC state mask */
108
#define PORT_CMD_ICC_ACTIVE       (0x1 << 28) /* Put i/f in active state */
109
#define PORT_CMD_ICC_PARTIAL      (0x2 << 28) /* Put i/f in partial state */
110
#define PORT_CMD_ICC_SLUMBER      (0x6 << 28) /* Put i/f in slumber state */
111

  
112
#define PORT_IRQ_STAT_DHRS        (1 << 0) /* Device to Host Register FIS */
113
#define PORT_IRQ_STAT_PSS         (1 << 1) /* PIO Setup FIS */
114
#define PORT_IRQ_STAT_DSS         (1 << 2) /* DMA Setup FIS */
115
#define PORT_IRQ_STAT_SDBS        (1 << 3) /* Set Device Bits */
116
#define PORT_IRQ_STAT_UFS         (1 << 4) /* Unknown FIS */
117
#define PORT_IRQ_STAT_DPS         (1 << 5) /* Descriptor Processed */
118
#define PORT_IRQ_STAT_PCS         (1 << 6) /* Port Connect Change Status */
119
#define PORT_IRQ_STAT_DMPS        (1 << 7) /* Device Mechanical Presence
120
                                              Status */
121
#define PORT_IRQ_STAT_PRCS        (1 << 22) /* File Ready Status */
122
#define PORT_IRQ_STAT_IPMS        (1 << 23) /* Incorrect Port Multiplier
123
                                               Status */
124
#define PORT_IRQ_STAT_OFS         (1 << 24) /* Overflow Status */
125
#define PORT_IRQ_STAT_INFS        (1 << 26) /* Interface Non-Fatal Error
126
                                               Status */
127
#define PORT_IRQ_STAT_IFS         (1 << 27) /* Interface Fatal Error */
128
#define PORT_IRQ_STAT_HBDS        (1 << 28) /* Host Bus Data Error Status */
129
#define PORT_IRQ_STAT_HBFS        (1 << 29) /* Host Bus Fatal Error Status */
130
#define PORT_IRQ_STAT_TFES        (1 << 30) /* Task File Error Status */
131
#define PORT_IRQ_STAT_CPDS        (1 << 31) /* Code Port Detect Status */
132

  
133
/* ap->flags bits */
134
#define AHCI_FLAG_NO_NCQ                  (1 << 24)
135
#define AHCI_FLAG_IGN_IRQ_IF_ERR          (1 << 25) /* ignore IRQ_IF_ERR */
136
#define AHCI_FLAG_HONOR_PI                (1 << 26) /* honor PORTS_IMPL */
137
#define AHCI_FLAG_IGN_SERR_INTERNAL       (1 << 27) /* ignore SERR_INTERNAL */
138
#define AHCI_FLAG_32BIT_ONLY              (1 << 28) /* force 32bit */
139

  
140
#define ATA_SRST                          (1 << 2)  /* software reset */
141

  
142
#define STATE_RUN                         0
143
#define STATE_RESET                       1
144

  
145
#define SATA_SCR_SSTATUS_DET_NODEV        0x0
146
#define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3
147

  
148
#define SATA_SCR_SSTATUS_SPD_NODEV        0x00
149
#define SATA_SCR_SSTATUS_SPD_GEN1         0x10
150

  
151
#define SATA_SCR_SSTATUS_IPM_NODEV        0x000
152
#define SATA_SCR_SSTATUS_IPM_ACTIVE       0X100
153

  
154
#define AHCI_SCR_SCTL_DET                 0xf
155

  
156
#define SATA_FIS_TYPE_REGISTER_H2D        0x27
157
#define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80
158

  
159
#define AHCI_CMD_HDR_CMD_FIS_LEN           0x1f
160
#define AHCI_CMD_HDR_PRDT_LEN              16
161

  
162
#define SATA_SIGNATURE_CDROM               0xeb140000
163
#define SATA_SIGNATURE_DISK                0x00000101
164

  
165
#define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x20
166
                                            /* Shouldn't this be 0x2c? */
167

  
168
#define SATA_PORTS                         4
169

  
170
#define AHCI_PORT_REGS_START_ADDR          0x100
171
#define AHCI_PORT_REGS_END_ADDR (AHCI_PORT_REGS_START_ADDR + SATA_PORTS * 0x80)
172
#define AHCI_PORT_ADDR_OFFSET_MASK         0x7f
173

  
174
#define AHCI_NUM_COMMAND_SLOTS             31
175
#define AHCI_SUPPORTED_SPEED               20
176
#define AHCI_SUPPORTED_SPEED_GEN1          1
177
#define AHCI_VERSION_1_0                   0x10000
178

  
179
#define AHCI_PROGMODE_MAJOR_REV_1          1
180

  
181
#define AHCI_COMMAND_TABLE_ACMD            0x40
182

  
183
#define IDE_FEATURE_DMA                    1
184

  
185
#define READ_FPDMA_QUEUED                  0x60
186
#define WRITE_FPDMA_QUEUED                 0x61
187

  
188
#define RES_FIS_DSFIS                      0x00
189
#define RES_FIS_PSFIS                      0x20
190
#define RES_FIS_RFIS                       0x40
191
#define RES_FIS_SDBFIS                     0x58
192
#define RES_FIS_UFIS                       0x60
193

  
194
typedef struct AHCIControlRegs {
195
    uint32_t    cap;
196
    uint32_t    ghc;
197
    uint32_t    irqstatus;
198
    uint32_t    impl;
199
    uint32_t    version;
200
} AHCIControlRegs;
201

  
202
typedef struct AHCIPortRegs {
203
    uint32_t    lst_addr;
204
    uint32_t    lst_addr_hi;
205
    uint32_t    fis_addr;
206
    uint32_t    fis_addr_hi;
207
    uint32_t    irq_stat;
208
    uint32_t    irq_mask;
209
    uint32_t    cmd;
210
    uint32_t    unused0;
211
    uint32_t    tfdata;
212
    uint32_t    sig;
213
    uint32_t    scr_stat;
214
    uint32_t    scr_ctl;
215
    uint32_t    scr_err;
216
    uint32_t    scr_act;
217
    uint32_t    cmd_issue;
218
    uint32_t    reserved;
219
} AHCIPortRegs;
220

  
221
typedef struct AHCICmdHdr {
222
    uint32_t    opts;
223
    uint32_t    status;
224
    uint64_t    tbl_addr;
225
    uint32_t    reserved[4];
226
} __attribute__ ((packed)) AHCICmdHdr;
227

  
228
typedef struct AHCI_SG {
229
    uint64_t    addr;
230
    uint32_t    reserved;
231
    uint32_t    flags_size;
232
} __attribute__ ((packed)) AHCI_SG;
233

  
234
typedef struct AHCIDevice AHCIDevice;
235

  
236
typedef struct NCQTransferState {
237
    AHCIDevice *drive;
238
    BlockDriverAIOCB *aiocb;
239
    QEMUSGList sglist;
240
    int is_read;
241
    uint16_t sector_count;
242
    uint64_t lba;
243
    uint8_t tag;
244
    int slot;
245
    int used;
246
} NCQTransferState;
247

  
248
struct AHCIDevice {
249
    IDEDMA dma;
250
    IDEBus port;
251
    int port_no;
252
    uint32_t port_state;
253
    uint32_t finished;
254
    AHCIPortRegs port_regs;
255
    struct AHCIState *hba;
256
    QEMUBH *check_bh;
257
    uint8_t *lst;
258
    uint8_t *res_fis;
259
    int dma_status;
260
    int done_atapi_packet;
261
    int busy_slot;
262
    BlockDriverCompletionFunc *dma_cb;
263
    AHCICmdHdr *cur_cmd;
264
    NCQTransferState ncq_tfs[AHCI_MAX_CMDS];
265
};
266

  
267
typedef struct AHCIState {
268
    AHCIDevice dev[SATA_PORTS];
269
    AHCIControlRegs control_regs;
270
    int mem;
271
    qemu_irq irq;
272
} AHCIState;
273

  
274
typedef struct AHCIPCIState {
275
    PCIDevice card;
276
    AHCIState ahci;
277
} AHCIPCIState;
278

  
279
typedef struct NCQFrame {
280
    uint8_t fis_type;
281
    uint8_t c;
282
    uint8_t command;
283
    uint8_t sector_count_low;
284
    uint8_t lba0;
285
    uint8_t lba1;
286
    uint8_t lba2;
287
    uint8_t fua;
288
    uint8_t lba3;
289
    uint8_t lba4;
290
    uint8_t lba5;
291
    uint8_t sector_count_high;
292
    uint8_t tag;
293
    uint8_t reserved5;
294
    uint8_t reserved6;
295
    uint8_t control;
296
    uint8_t reserved7;
297
    uint8_t reserved8;
298
    uint8_t reserved9;
299
    uint8_t reserved10;
300
} __attribute__ ((packed)) NCQFrame;
301

  
302
void ahci_init(AHCIState *s, DeviceState *qdev);
303

  
304
void ahci_pci_map(PCIDevice *pci_dev, int region_num,
305
        pcibus_t addr, pcibus_t size, int type);
306

  
307
void ahci_reset(void *opaque);
308

  
309
#endif /* HW_IDE_AHCI_H */
b/hw/ide/ich.c
1
#include <hw/hw.h>
2
#include <hw/msi.h>
3
#include <hw/pc.h>
4
#include <hw/pci.h>
5
#include <hw/isa.h>
6
#include "block.h"
7
#include "block_int.h"
8
#include "sysemu.h"
9
#include "dma.h"
10

  
11
#include <hw/ide/pci.h>
12
#include <hw/ide/ahci.h>
13

  
14
static int pci_ich9_ahci_initfn(PCIDevice *dev)
15
{
16
    struct AHCIPCIState *d;
17
    d = DO_UPCAST(struct AHCIPCIState, card, dev);
18

  
19
    pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL);
20
    pci_config_set_device_id(d->card.config, PCI_DEVICE_ID_INTEL_82801IR);
21

  
22
    pci_config_set_class(d->card.config, PCI_CLASS_STORAGE_SATA);
23
    pci_config_set_revision(d->card.config, 0x02);
24
    pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
25

  
26
    d->card.config[PCI_CACHE_LINE_SIZE] = 0x08;  /* Cache line size */
27
    d->card.config[PCI_LATENCY_TIMER]   = 0x00;  /* Latency timer */
28
    pci_config_set_interrupt_pin(d->card.config, 1);
29

  
30
    /* XXX Software should program this register */
31
    d->card.config[0x90]   = 1 << 6; /* Address Map Register - AHCI mode */
32

  
33
    qemu_register_reset(ahci_reset, d);
34

  
35
    /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
36
    pci_register_bar(&d->card, 5, 0x1000, PCI_BASE_ADDRESS_SPACE_MEMORY,
37
                     ahci_pci_map);
38

  
39
    msi_init(dev, 0x50, 1, true, false);
40

  
41
    ahci_init(&d->ahci, &dev->qdev);
42
    d->ahci.irq = d->card.irq[0];
43

  
44
    return 0;
45
}
46

  
47
static PCIDeviceInfo ich_ahci_info[] = {
48
    {
49
        .qdev.name    = "ich9-ahci",
50
        .qdev.size    = sizeof(AHCIPCIState),
51
        .init         = pci_ich9_ahci_initfn,
52
    },{
53
        /* end of list */
54
    }
55
};
56

  
57
static void ich_ahci_register(void)
58
{
59
    pci_qdev_register_many(ich_ahci_info);
60
}
61
device_init(ich_ahci_register);

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