root / target-sh4 / helper.c @ 03e3b61e
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/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "hw/sh_intc.h" |
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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{ |
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env->exception_index = -1;
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} |
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int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu) |
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{ |
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env->tea = address; |
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env->exception_index = 0;
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switch (rw) {
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case 0: |
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env->exception_index = 0x0a0;
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break;
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case 1: |
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env->exception_index = 0x0c0;
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break;
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case 2: |
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env->exception_index = 0x0a0;
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break;
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} |
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return 1; |
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} |
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
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{ |
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return addr;
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} |
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int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
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{ |
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/* For user mode, only U0 area is cachable. */
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return !(addr & 0x80000000); |
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} |
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#else /* !CONFIG_USER_ONLY */ |
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#define MMU_OK 0 |
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#define MMU_ITLB_MISS (-1) |
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#define MMU_ITLB_MULTIPLE (-2) |
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#define MMU_ITLB_VIOLATION (-3) |
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#define MMU_DTLB_MISS_READ (-4) |
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#define MMU_DTLB_MISS_WRITE (-5) |
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#define MMU_DTLB_INITIAL_WRITE (-6) |
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#define MMU_DTLB_VIOLATION_READ (-7) |
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#define MMU_DTLB_VIOLATION_WRITE (-8) |
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#define MMU_DTLB_MULTIPLE (-9) |
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#define MMU_DTLB_MISS (-10) |
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#define MMU_IADDR_ERROR (-11) |
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#define MMU_DADDR_ERROR_READ (-12) |
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#define MMU_DADDR_ERROR_WRITE (-13) |
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void do_interrupt(CPUState * env)
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{ |
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int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
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int do_exp, irq_vector = env->exception_index;
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/* prioritize exceptions over interrupts */
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do_exp = env->exception_index != -1;
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do_irq = do_irq && (env->exception_index == -1);
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if (env->sr & SR_BL) {
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if (do_exp && env->exception_index != 0x1e0) { |
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env->exception_index = 0x000; /* masked exception -> reset */ |
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} |
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if (do_irq && !env->intr_at_halt) {
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return; /* masked */ |
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} |
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env->intr_at_halt = 0;
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} |
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if (do_irq) {
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irq_vector = sh_intc_get_pending_vector(env->intc_handle, |
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(env->sr >> 4) & 0xf); |
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if (irq_vector == -1) { |
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return; /* masked */ |
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} |
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} |
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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const char *expname; |
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switch (env->exception_index) {
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case 0x0e0: |
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expname = "addr_error";
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break;
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case 0x040: |
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expname = "tlb_miss";
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break;
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case 0x0a0: |
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expname = "tlb_violation";
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break;
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case 0x180: |
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expname = "illegal_instruction";
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break;
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case 0x1a0: |
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expname = "slot_illegal_instruction";
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break;
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case 0x800: |
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expname = "fpu_disable";
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break;
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case 0x820: |
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expname = "slot_fpu";
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break;
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case 0x100: |
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expname = "data_write";
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break;
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case 0x060: |
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expname = "dtlb_miss_write";
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break;
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case 0x0c0: |
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expname = "dtlb_violation_write";
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break;
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case 0x120: |
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expname = "fpu_exception";
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break;
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case 0x080: |
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expname = "initial_page_write";
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break;
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case 0x160: |
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expname = "trapa";
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break;
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default:
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expname = do_irq ? "interrupt" : "???"; |
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break;
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} |
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qemu_log("exception 0x%03x [%s] raised\n",
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irq_vector, expname); |
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log_cpu_state(env, 0);
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} |
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env->ssr = env->sr; |
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env->spc = env->pc; |
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env->sgr = env->gregs[15];
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env->sr |= SR_BL | SR_MD | SR_RB; |
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if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
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/* Branch instruction should be executed again before delay slot. */
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env->spc -= 2;
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/* Clear flags for exception/interrupt routine. */
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env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE); |
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} |
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if (env->flags & DELAY_SLOT_CLEARME)
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env->flags = 0;
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if (do_exp) {
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env->expevt = env->exception_index; |
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switch (env->exception_index) {
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case 0x000: |
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case 0x020: |
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case 0x140: |
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env->sr &= ~SR_FD; |
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env->sr |= 0xf << 4; /* IMASK */ |
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env->pc = 0xa0000000;
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break;
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case 0x040: |
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case 0x060: |
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env->pc = env->vbr + 0x400;
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break;
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case 0x160: |
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env->spc += 2; /* special case for TRAPA */ |
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/* fall through */
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default:
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env->pc = env->vbr + 0x100;
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break;
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} |
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return;
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} |
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if (do_irq) {
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env->intevt = irq_vector; |
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env->pc = env->vbr + 0x600;
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return;
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} |
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} |
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static void update_itlb_use(CPUState * env, int itlbnb) |
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{ |
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uint8_t or_mask = 0, and_mask = (uint8_t) - 1; |
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switch (itlbnb) {
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case 0: |
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and_mask = 0x1f;
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break;
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case 1: |
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and_mask = 0xe7;
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or_mask = 0x80;
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break;
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case 2: |
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and_mask = 0xfb;
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or_mask = 0x50;
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break;
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case 3: |
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or_mask = 0x2c;
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break;
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} |
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env->mmucr &= (and_mask << 24) | 0x00ffffff; |
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env->mmucr |= (or_mask << 24);
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} |
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static int itlb_replacement(CPUState * env) |
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{ |
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if ((env->mmucr & 0xe0000000) == 0xe0000000) |
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return 0; |
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if ((env->mmucr & 0x98000000) == 0x18000000) |
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return 1; |
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if ((env->mmucr & 0x54000000) == 0x04000000) |
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return 2; |
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if ((env->mmucr & 0x2c000000) == 0x00000000) |
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return 3; |
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assert(0);
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} |
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/* Find the corresponding entry in the right TLB
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Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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*/
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static int find_tlb_entry(CPUState * env, target_ulong address, |
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tlb_t * entries, uint8_t nbtlb, int use_asid)
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{ |
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int match = MMU_DTLB_MISS;
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uint32_t start, end; |
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uint8_t asid; |
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int i;
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asid = env->pteh & 0xff;
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for (i = 0; i < nbtlb; i++) { |
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if (!entries[i].v)
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continue; /* Invalid entry */ |
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if (!entries[i].sh && use_asid && entries[i].asid != asid)
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continue; /* Bad ASID */ |
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start = (entries[i].vpn << 10) & ~(entries[i].size - 1); |
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end = start + entries[i].size - 1;
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if (address >= start && address <= end) { /* Match */ |
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if (match != MMU_DTLB_MISS)
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return MMU_DTLB_MULTIPLE; /* Multiple match */ |
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match = i; |
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} |
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} |
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return match;
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} |
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static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb, |
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const tlb_t * needle)
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{ |
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int i;
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for (i = 0; i < nbtlb; i++) |
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if (!memcmp(&haystack[i], needle, sizeof(tlb_t))) |
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return 1; |
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return 0; |
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} |
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static void increment_urc(CPUState * env) |
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{ |
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uint8_t urb, urc; |
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/* Increment URC */
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urb = ((env->mmucr) >> 18) & 0x3f; |
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urc = ((env->mmucr) >> 10) & 0x3f; |
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urc++; |
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if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1)) |
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urc = 0;
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env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); |
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} |
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/* Find itlb entry - update itlb from utlb if necessary and asked for
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Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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Update the itlb from utlb if update is not 0
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*/
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static int find_itlb_entry(CPUState * env, target_ulong address, |
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int use_asid, int update) |
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{ |
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int e, n;
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e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); |
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if (e == MMU_DTLB_MULTIPLE)
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e = MMU_ITLB_MULTIPLE; |
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else if (e == MMU_DTLB_MISS && update) { |
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e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); |
312 |
if (e >= 0) { |
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tlb_t * ientry; |
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n = itlb_replacement(env); |
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ientry = &env->itlb[n]; |
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if (ientry->v) {
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if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
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tlb_flush_page(env, ientry->vpn << 10);
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} |
320 |
*ientry = env->utlb[e]; |
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e = n; |
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} else if (e == MMU_DTLB_MISS) |
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e = MMU_ITLB_MISS; |
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} else if (e == MMU_DTLB_MISS) |
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e = MMU_ITLB_MISS; |
326 |
if (e >= 0) |
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update_itlb_use(env, e); |
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return e;
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} |
330 |
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/* Find utlb entry
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Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
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static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) |
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{ |
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/* per utlb access */
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increment_urc(env); |
337 |
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/* Return entry */
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return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
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} |
341 |
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342 |
/* Match address against MMU
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343 |
Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
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MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
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MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
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MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
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MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
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*/
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349 |
static int get_mmu_address(CPUState * env, target_ulong * physical, |
350 |
int *prot, target_ulong address,
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int rw, int access_type) |
352 |
{ |
353 |
int use_asid, n;
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tlb_t *matching = NULL;
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|
356 |
use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; |
357 |
|
358 |
if (rw == 2) { |
359 |
n = find_itlb_entry(env, address, use_asid, 1);
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360 |
if (n >= 0) { |
361 |
matching = &env->itlb[n]; |
362 |
if (!(env->sr & SR_MD) && !(matching->pr & 2)) |
363 |
n = MMU_ITLB_VIOLATION; |
364 |
else
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365 |
*prot = PAGE_READ; |
366 |
} |
367 |
} else {
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368 |
n = find_utlb_entry(env, address, use_asid); |
369 |
if (n >= 0) { |
370 |
matching = &env->utlb[n]; |
371 |
if (!(env->sr & SR_MD) && !(matching->pr & 2)) { |
372 |
n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
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MMU_DTLB_VIOLATION_READ; |
374 |
} else if ((rw == 1) && !(matching->pr & 1)) { |
375 |
n = MMU_DTLB_VIOLATION_WRITE; |
376 |
} else if ((rw == 1) & !matching->d) { |
377 |
n = MMU_DTLB_INITIAL_WRITE; |
378 |
} else {
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379 |
*prot = PAGE_READ; |
380 |
if ((matching->pr & 1) && matching->d) { |
381 |
*prot |= PAGE_WRITE; |
382 |
} |
383 |
} |
384 |
} else if (n == MMU_DTLB_MISS) { |
385 |
n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
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386 |
MMU_DTLB_MISS_READ; |
387 |
} |
388 |
} |
389 |
if (n >= 0) { |
390 |
n = MMU_OK; |
391 |
*physical = ((matching->ppn << 10) & ~(matching->size - 1)) | |
392 |
(address & (matching->size - 1));
|
393 |
} |
394 |
return n;
|
395 |
} |
396 |
|
397 |
static int get_physical_address(CPUState * env, target_ulong * physical, |
398 |
int *prot, target_ulong address,
|
399 |
int rw, int access_type) |
400 |
{ |
401 |
/* P1, P2 and P4 areas do not use translation */
|
402 |
if ((address >= 0x80000000 && address < 0xc0000000) || |
403 |
address >= 0xe0000000) {
|
404 |
if (!(env->sr & SR_MD)
|
405 |
&& (address < 0xe0000000 || address >= 0xe4000000)) { |
406 |
/* Unauthorized access in user mode (only store queues are available) */
|
407 |
fprintf(stderr, "Unauthorized access\n");
|
408 |
if (rw == 0) |
409 |
return MMU_DADDR_ERROR_READ;
|
410 |
else if (rw == 1) |
411 |
return MMU_DADDR_ERROR_WRITE;
|
412 |
else
|
413 |
return MMU_IADDR_ERROR;
|
414 |
} |
415 |
if (address >= 0x80000000 && address < 0xc0000000) { |
416 |
/* Mask upper 3 bits for P1 and P2 areas */
|
417 |
*physical = address & 0x1fffffff;
|
418 |
} else {
|
419 |
*physical = address; |
420 |
} |
421 |
*prot = PAGE_READ | PAGE_WRITE; |
422 |
return MMU_OK;
|
423 |
} |
424 |
|
425 |
/* If MMU is disabled, return the corresponding physical page */
|
426 |
if (!env->mmucr & MMUCR_AT) {
|
427 |
*physical = address & 0x1FFFFFFF;
|
428 |
*prot = PAGE_READ | PAGE_WRITE; |
429 |
return MMU_OK;
|
430 |
} |
431 |
|
432 |
/* We need to resort to the MMU */
|
433 |
return get_mmu_address(env, physical, prot, address, rw, access_type);
|
434 |
} |
435 |
|
436 |
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
437 |
int mmu_idx, int is_softmmu) |
438 |
{ |
439 |
target_ulong physical; |
440 |
int prot, ret, access_type;
|
441 |
|
442 |
access_type = ACCESS_INT; |
443 |
ret = |
444 |
get_physical_address(env, &physical, &prot, address, rw, |
445 |
access_type); |
446 |
|
447 |
if (ret != MMU_OK) {
|
448 |
env->tea = address; |
449 |
switch (ret) {
|
450 |
case MMU_ITLB_MISS:
|
451 |
case MMU_DTLB_MISS_READ:
|
452 |
env->exception_index = 0x040;
|
453 |
break;
|
454 |
case MMU_DTLB_MULTIPLE:
|
455 |
case MMU_ITLB_MULTIPLE:
|
456 |
env->exception_index = 0x140;
|
457 |
break;
|
458 |
case MMU_ITLB_VIOLATION:
|
459 |
env->exception_index = 0x0a0;
|
460 |
break;
|
461 |
case MMU_DTLB_MISS_WRITE:
|
462 |
env->exception_index = 0x060;
|
463 |
break;
|
464 |
case MMU_DTLB_INITIAL_WRITE:
|
465 |
env->exception_index = 0x080;
|
466 |
break;
|
467 |
case MMU_DTLB_VIOLATION_READ:
|
468 |
env->exception_index = 0x0a0;
|
469 |
break;
|
470 |
case MMU_DTLB_VIOLATION_WRITE:
|
471 |
env->exception_index = 0x0c0;
|
472 |
break;
|
473 |
case MMU_IADDR_ERROR:
|
474 |
case MMU_DADDR_ERROR_READ:
|
475 |
env->exception_index = 0x0c0;
|
476 |
break;
|
477 |
case MMU_DADDR_ERROR_WRITE:
|
478 |
env->exception_index = 0x100;
|
479 |
break;
|
480 |
default:
|
481 |
assert(0);
|
482 |
} |
483 |
return 1; |
484 |
} |
485 |
|
486 |
address &= TARGET_PAGE_MASK; |
487 |
physical &= TARGET_PAGE_MASK; |
488 |
|
489 |
return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
|
490 |
} |
491 |
|
492 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
493 |
{ |
494 |
target_ulong physical; |
495 |
int prot;
|
496 |
|
497 |
get_physical_address(env, &physical, &prot, addr, 0, 0); |
498 |
return physical;
|
499 |
} |
500 |
|
501 |
void cpu_load_tlb(CPUSH4State * env)
|
502 |
{ |
503 |
int n = cpu_mmucr_urc(env->mmucr);
|
504 |
tlb_t * entry = &env->utlb[n]; |
505 |
|
506 |
if (entry->v) {
|
507 |
/* Overwriting valid entry in utlb. */
|
508 |
target_ulong address = entry->vpn << 10;
|
509 |
if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
|
510 |
tlb_flush_page(env, address); |
511 |
} |
512 |
} |
513 |
|
514 |
/* Take values into cpu status from registers. */
|
515 |
entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); |
516 |
entry->vpn = cpu_pteh_vpn(env->pteh); |
517 |
entry->v = (uint8_t)cpu_ptel_v(env->ptel); |
518 |
entry->ppn = cpu_ptel_ppn(env->ptel); |
519 |
entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); |
520 |
switch (entry->sz) {
|
521 |
case 0: /* 00 */ |
522 |
entry->size = 1024; /* 1K */ |
523 |
break;
|
524 |
case 1: /* 01 */ |
525 |
entry->size = 1024 * 4; /* 4K */ |
526 |
break;
|
527 |
case 2: /* 10 */ |
528 |
entry->size = 1024 * 64; /* 64K */ |
529 |
break;
|
530 |
case 3: /* 11 */ |
531 |
entry->size = 1024 * 1024; /* 1M */ |
532 |
break;
|
533 |
default:
|
534 |
assert(0);
|
535 |
break;
|
536 |
} |
537 |
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); |
538 |
entry->c = (uint8_t)cpu_ptel_c(env->ptel); |
539 |
entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); |
540 |
entry->d = (uint8_t)cpu_ptel_d(env->ptel); |
541 |
entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); |
542 |
entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); |
543 |
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); |
544 |
} |
545 |
|
546 |
void cpu_sh4_invalidate_tlb(CPUSH4State *s)
|
547 |
{ |
548 |
int i;
|
549 |
|
550 |
/* UTLB */
|
551 |
for (i = 0; i < UTLB_SIZE; i++) { |
552 |
tlb_t * entry = &s->utlb[i]; |
553 |
entry->v = 0;
|
554 |
} |
555 |
/* ITLB */
|
556 |
for (i = 0; i < UTLB_SIZE; i++) { |
557 |
tlb_t * entry = &s->utlb[i]; |
558 |
entry->v = 0;
|
559 |
} |
560 |
|
561 |
tlb_flush(s, 1);
|
562 |
} |
563 |
|
564 |
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
|
565 |
uint32_t mem_value) |
566 |
{ |
567 |
int associate = addr & 0x0000080; |
568 |
uint32_t vpn = (mem_value & 0xfffffc00) >> 10; |
569 |
uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9); |
570 |
uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); |
571 |
uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
572 |
int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0; |
573 |
|
574 |
if (associate) {
|
575 |
int i;
|
576 |
tlb_t * utlb_match_entry = NULL;
|
577 |
int needs_tlb_flush = 0; |
578 |
|
579 |
/* search UTLB */
|
580 |
for (i = 0; i < UTLB_SIZE; i++) { |
581 |
tlb_t * entry = &s->utlb[i]; |
582 |
if (!entry->v)
|
583 |
continue;
|
584 |
|
585 |
if (entry->vpn == vpn
|
586 |
&& (!use_asid || entry->asid == asid || entry->sh)) { |
587 |
if (utlb_match_entry) {
|
588 |
/* Multiple TLB Exception */
|
589 |
s->exception_index = 0x140;
|
590 |
s->tea = addr; |
591 |
break;
|
592 |
} |
593 |
if (entry->v && !v)
|
594 |
needs_tlb_flush = 1;
|
595 |
entry->v = v; |
596 |
entry->d = d; |
597 |
utlb_match_entry = entry; |
598 |
} |
599 |
increment_urc(s); /* per utlb access */
|
600 |
} |
601 |
|
602 |
/* search ITLB */
|
603 |
for (i = 0; i < ITLB_SIZE; i++) { |
604 |
tlb_t * entry = &s->itlb[i]; |
605 |
if (entry->vpn == vpn
|
606 |
&& (!use_asid || entry->asid == asid || entry->sh)) { |
607 |
if (entry->v && !v)
|
608 |
needs_tlb_flush = 1;
|
609 |
if (utlb_match_entry)
|
610 |
*entry = *utlb_match_entry; |
611 |
else
|
612 |
entry->v = v; |
613 |
break;
|
614 |
} |
615 |
} |
616 |
|
617 |
if (needs_tlb_flush)
|
618 |
tlb_flush_page(s, vpn << 10);
|
619 |
|
620 |
} else {
|
621 |
int index = (addr & 0x00003f00) >> 8; |
622 |
tlb_t * entry = &s->utlb[index]; |
623 |
if (entry->v) {
|
624 |
/* Overwriting valid entry in utlb. */
|
625 |
target_ulong address = entry->vpn << 10;
|
626 |
if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
|
627 |
tlb_flush_page(s, address); |
628 |
} |
629 |
} |
630 |
entry->asid = asid; |
631 |
entry->vpn = vpn; |
632 |
entry->d = d; |
633 |
entry->v = v; |
634 |
increment_urc(s); |
635 |
} |
636 |
} |
637 |
|
638 |
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
|
639 |
{ |
640 |
int n;
|
641 |
int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; |
642 |
|
643 |
/* check area */
|
644 |
if (env->sr & SR_MD) {
|
645 |
/* For previledged mode, P2 and P4 area is not cachable. */
|
646 |
if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr) |
647 |
return 0; |
648 |
} else {
|
649 |
/* For user mode, only U0 area is cachable. */
|
650 |
if (0x80000000 <= addr) |
651 |
return 0; |
652 |
} |
653 |
|
654 |
/*
|
655 |
* TODO : Evaluate CCR and check if the cache is on or off.
|
656 |
* Now CCR is not in CPUSH4State, but in SH7750State.
|
657 |
* When you move the ccr inot CPUSH4State, the code will be
|
658 |
* as follows.
|
659 |
*/
|
660 |
#if 0
|
661 |
/* check if operand cache is enabled or not. */
|
662 |
if (!(env->ccr & 1))
|
663 |
return 0;
|
664 |
#endif
|
665 |
|
666 |
/* if MMU is off, no check for TLB. */
|
667 |
if (env->mmucr & MMUCR_AT)
|
668 |
return 1; |
669 |
|
670 |
/* check TLB */
|
671 |
n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid); |
672 |
if (n >= 0) |
673 |
return env->itlb[n].c;
|
674 |
|
675 |
n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid); |
676 |
if (n >= 0) |
677 |
return env->utlb[n].c;
|
678 |
|
679 |
return 0; |
680 |
} |
681 |
|
682 |
#endif
|