Revision 0411a972 target-ppc/cpu.h

b/target-ppc/cpu.h
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#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
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#define MSR_FE1  8  /* Floating point exception mode 1                hflags */
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#define MSR_AL   7  /* AL bit on POWER                                       */
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#define MSR_EP   3  /* Exception prefix on 601                               */
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#define MSR_EP   6  /* Exception prefix on 601                               */
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#define MSR_IR   5  /* Instruction relocate                                  */
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#define MSR_DR   4  /* Data relocate                                         */
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#define MSR_PE   3  /* Protection enable on 403                              */
......
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#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
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#define MSR_RI   1  /* Recoverable interrupt                        1        */
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#define MSR_LE   0  /* Little-endian mode                           1 hflags */
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#define msr_sf   env->msr[MSR_SF]
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#define msr_isf  env->msr[MSR_ISF]
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#define msr_hv   env->msr[MSR_HV]
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#define msr_cm   env->msr[MSR_CM]
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#define msr_icm  env->msr[MSR_ICM]
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#define msr_ucle env->msr[MSR_UCLE]
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#define msr_vr   env->msr[MSR_VR]
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#define msr_spe  env->msr[MSR_SPE]
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#define msr_ap   env->msr[MSR_AP]
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#define msr_sa   env->msr[MSR_SA]
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#define msr_key  env->msr[MSR_KEY]
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#define msr_pow  env->msr[MSR_POW]
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#define msr_tgpr env->msr[MSR_TGPR]
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#define msr_ce   env->msr[MSR_CE]
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#define msr_ile  env->msr[MSR_ILE]
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#define msr_ee   env->msr[MSR_EE]
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#define msr_pr   env->msr[MSR_PR]
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#define msr_fp   env->msr[MSR_FP]
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#define msr_me   env->msr[MSR_ME]
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#define msr_fe0  env->msr[MSR_FE0]
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#define msr_se   env->msr[MSR_SE]
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#define msr_dwe  env->msr[MSR_DWE]
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#define msr_uble env->msr[MSR_UBLE]
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#define msr_be   env->msr[MSR_BE]
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#define msr_de   env->msr[MSR_DE]
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#define msr_fe1  env->msr[MSR_FE1]
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#define msr_al   env->msr[MSR_AL]
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#define msr_ir   env->msr[MSR_IR]
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#define msr_dr   env->msr[MSR_DR]
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#define msr_pe   env->msr[MSR_PE]
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#define msr_ep   env->msr[MSR_EP]
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#define msr_px   env->msr[MSR_PX]
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#define msr_pmm  env->msr[MSR_PMM]
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#define msr_ri   env->msr[MSR_RI]
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#define msr_le   env->msr[MSR_LE]
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#define msr_sf   ((env->msr >> MSR_SF)   & 1)


  		





  
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#define msr_isf  ((env->msr >> MSR_ISF)  & 1)


  		





  
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#define msr_hv   ((env->msr >> MSR_HV)   & 1)


  		





  
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#define msr_cm   ((env->msr >> MSR_CM)   & 1)


  		





  
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#define msr_icm  ((env->msr >> MSR_ICM)  & 1)


  		





  
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#define msr_ucle ((env->msr >> MSR_UCLE) & 1)


  		





  
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#define msr_vr   ((env->msr >> MSR_VR)   & 1)


  		





  
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#define msr_spe  ((env->msr >> MSR_SE)   & 1)


  		





  
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#define msr_ap   ((env->msr >> MSR_AP)   & 1)


  		





  
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#define msr_sa   ((env->msr >> MSR_SA)   & 1)


  		





  
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#define msr_key  ((env->msr >> MSR_KEY)  & 1)


  		





  
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#define msr_pow  ((env->msr >> MSR_POW)  & 1)


  		





  
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#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)


  		





  
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#define msr_ce   ((env->msr >> MSR_CE)   & 1)


  		





  
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#define msr_ile  ((env->msr >> MSR_ILE)  & 1)


  		





  
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#define msr_ee   ((env->msr >> MSR_EE)   & 1)


  		





  
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#define msr_pr   ((env->msr >> MSR_PR)   & 1)


  		





  
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#define msr_fp   ((env->msr >> MSR_FP)   & 1)


  		





  
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#define msr_me   ((env->msr >> MSR_ME)   & 1)


  		





  
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#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)


  		





  
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#define msr_se   ((env->msr >> MSR_SE)   & 1)


  		





  
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#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)


  		





  
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#define msr_uble ((env->msr >> MSR_UBLE) & 1)


  		





  
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#define msr_be   ((env->msr >> MSR_BE)   & 1)


  		





  
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#define msr_de   ((env->msr >> MSR_DE)   & 1)


  		





  
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#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)


  		





  
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#define msr_al   ((env->msr >> MSR_AL)   & 1)


  		





  
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#define msr_ep   ((env->msr >> MSR_EP)   & 1)


  		





  
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#define msr_ir   ((env->msr >> MSR_IR)   & 1)


  		





  
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#define msr_dr   ((env->msr >> MSR_DR)   & 1)


  		





  
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#define msr_pe   ((env->msr >> MSR_PE)   & 1)


  		





  
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#define msr_px   ((env->msr >> MSR_PX)   & 1)


  		





  
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#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)


  		





  
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#define msr_ri   ((env->msr >> MSR_RI)   & 1)


  		





  
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#define msr_le   ((env->msr >> MSR_LE)   & 1)


  		





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enum {


  		





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    POWERPC_FLAG_NONE = 0x00000000,


  		





  ......




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    /* Those ones are used in supervisor mode only */


  		





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    /* machine state register */


  		





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    uint8_t msr[64];


  		





  
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    target_ulong msr;


  		





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    /* temporary general purpose registers */


  		





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    ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */


  		





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  ......




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#endif /* !defined(CONFIG_USER_ONLY) */


  		





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target_ulong ppc_load_xer (CPUPPCState *env);


  		





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void ppc_store_xer (CPUPPCState *env, target_ulong value);


  		





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target_ulong do_load_msr (CPUPPCState *env);


  		





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int do_store_msr (CPUPPCState *env, target_ulong value);


  		





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#if defined(TARGET_PPC64)


  		





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int ppc_store_msr_32 (CPUPPCState *env, uint32_t value);


  		





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#endif


  		





  
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void ppc_store_msr (CPUPPCState *env, target_ulong value);


  		





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void do_compute_hflags (CPUPPCState *env);


  		





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void cpu_ppc_reset (void *opaque);


  		





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CPUPPCState *cpu_ppc_init (void);


  		





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void cpu_ppc_close(CPUPPCState *env);


  		












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