Revision 0411a972 target-ppc/op_helper.c
| b/target-ppc/op_helper.c | ||
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*/ |
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#include "exec.h" |
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#include "helper_regs.h" |
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#include "op_helper.h" |
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|
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#define MEMSUFFIX _raw |
| ... | ... | |
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} |
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} |
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void do_load_xer (void) |
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{
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T0 = (xer_so << XER_SO) | |
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(xer_ov << XER_OV) | |
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(xer_ca << XER_CA) | |
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(xer_bc << XER_BC) | |
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(xer_cmp << XER_CMP); |
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} |
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|
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void do_store_xer (void) |
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{
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xer_so = (T0 >> XER_SO) & 0x01; |
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xer_ov = (T0 >> XER_OV) & 0x01; |
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xer_ca = (T0 >> XER_CA) & 0x01; |
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xer_cmp = (T0 >> XER_CMP) & 0xFF; |
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xer_bc = (T0 >> XER_BC) & 0x7F; |
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} |
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#if defined(TARGET_PPC64) |
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void do_store_pri (int prio) |
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{
|
| ... | ... | |
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#if !defined (CONFIG_USER_ONLY) |
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void cpu_dump_rfi (target_ulong RA, target_ulong msr); |
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void do_rfi (void) |
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void do_store_msr (void) |
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{
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T0 = hreg_store_msr(env, T0); |
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if (T0 != 0) {
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env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
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do_raise_exception(T0); |
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} |
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} |
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static always_inline void __do_rfi (target_ulong nip, target_ulong msr, |
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target_ulong msrm, int keep_msrh) |
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{
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#if defined(TARGET_PPC64) |
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if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
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env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
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do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
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if (msr & (1ULL << MSR_SF)) {
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nip = (uint64_t)nip;
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msr &= (uint64_t)msrm;
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} else {
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env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003); |
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ppc_store_msr_32(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); |
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nip = (uint32_t)nip; |
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msr = (uint32_t)(msr & msrm); |
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if (keep_msrh) |
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msr |= env->msr & ~((uint64_t)0xFFFFFFFF); |
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} |
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#else |
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env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
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do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
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nip = (uint32_t)nip;
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msr &= (uint32_t)msrm;
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#endif |
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/* XXX: beware: this is false if VLE is supported */ |
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env->nip = nip & ~((target_ulong)0x00000003); |
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hreg_store_msr(env, msr); |
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#if defined (DEBUG_OP) |
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cpu_dump_rfi(env->nip, do_load_msr(env));
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cpu_dump_rfi(env->nip, env->msr);
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#endif |
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/* No need to raise an exception here, |
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* as rfi is always the last insn of a TB |
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*/ |
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env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
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} |
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void do_rfi (void) |
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{
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__do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1], |
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~((target_ulong)0xFFFF0000), 1); |
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} |
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#if defined(TARGET_PPC64) |
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void do_rfid (void) |
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{
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if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
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env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003); |
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do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); |
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} else {
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env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003); |
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do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); |
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} |
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#if defined (DEBUG_OP) |
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cpu_dump_rfi(env->nip, do_load_msr(env)); |
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#endif |
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env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
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__do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1], |
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~((target_ulong)0xFFFF0000), 0); |
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} |
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#endif |
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#if defined(TARGET_PPC64H) |
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void do_hrfid (void) |
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{
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if (env->spr[SPR_HSRR1] & (1ULL << MSR_SF)) {
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env->nip = (uint64_t)(env->spr[SPR_HSRR0] & ~0x00000003); |
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do_store_msr(env, (uint64_t)(env->spr[SPR_HSRR1] & ~0xFFFF0000UL)); |
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} else {
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env->nip = (uint32_t)(env->spr[SPR_HSRR0] & ~0x00000003); |
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do_store_msr(env, (uint32_t)(env->spr[SPR_HSRR1] & ~0xFFFF0000UL)); |
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} |
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#if defined (DEBUG_OP) |
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cpu_dump_rfi(env->nip, do_load_msr(env)); |
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#endif |
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env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
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__do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1], |
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~((target_ulong)0xFFFF0000), 0); |
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} |
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#endif |
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#endif |
| ... | ... | |
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void do_POWER_rfsvc (void) |
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{
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env->nip = env->lr & ~0x00000003UL; |
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T0 = env->ctr & 0x0000FFFFUL; |
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do_store_msr(env, T0); |
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#if defined (DEBUG_OP) |
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cpu_dump_rfi(env->nip, do_load_msr(env)); |
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#endif |
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env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
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__do_rfi(env->lr, env->ctr, 0x0000FFFF, 0); |
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} |
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/* PowerPC 601 BAT management helper */ |
| ... | ... | |
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#if !defined(CONFIG_USER_ONLY) |
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void do_40x_rfci (void) |
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{
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env->nip = env->spr[SPR_40x_SRR2]; |
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do_store_msr(env, env->spr[SPR_40x_SRR3] & ~0xFFFF0000); |
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#if defined (DEBUG_OP) |
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cpu_dump_rfi(env->nip, do_load_msr(env)); |
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#endif |
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env->interrupt_request = CPU_INTERRUPT_EXITTB; |
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__do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3], |
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~((target_ulong)0xFFFF0000), 0); |
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} |
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void do_rfci (void) |
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{
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#if defined(TARGET_PPC64) |
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if (env->spr[SPR_BOOKE_CSRR1] & (1 << MSR_CM)) {
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env->nip = (uint64_t)env->spr[SPR_BOOKE_CSRR0]; |
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} else |
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#endif |
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{
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env->nip = (uint32_t)env->spr[SPR_BOOKE_CSRR0]; |
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} |
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do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_CSRR1] & ~0x3FFF0000); |
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#if defined (DEBUG_OP) |
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cpu_dump_rfi(env->nip, do_load_msr(env)); |
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#endif |
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env->interrupt_request = CPU_INTERRUPT_EXITTB; |
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__do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1, |
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~((target_ulong)0x3FFF0000), 0); |
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} |
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void do_rfdi (void) |
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{
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#if defined(TARGET_PPC64) |
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if (env->spr[SPR_BOOKE_DSRR1] & (1 << MSR_CM)) {
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env->nip = (uint64_t)env->spr[SPR_BOOKE_DSRR0]; |
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} else |
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#endif |
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{
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env->nip = (uint32_t)env->spr[SPR_BOOKE_DSRR0]; |
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} |
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do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_DSRR1] & ~0x3FFF0000); |
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#if defined (DEBUG_OP) |
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cpu_dump_rfi(env->nip, do_load_msr(env)); |
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#endif |
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env->interrupt_request = CPU_INTERRUPT_EXITTB; |
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__do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1, |
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~((target_ulong)0x3FFF0000), 0); |
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} |
| 1376 | 1334 |
|
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void do_rfmci (void) |
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{
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#if defined(TARGET_PPC64) |
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if (env->spr[SPR_BOOKE_MCSRR1] & (1 << MSR_CM)) {
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env->nip = (uint64_t)env->spr[SPR_BOOKE_MCSRR0]; |
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} else |
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#endif |
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{
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env->nip = (uint32_t)env->spr[SPR_BOOKE_MCSRR0]; |
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} |
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do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_MCSRR1] & ~0x3FFF0000); |
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#if defined (DEBUG_OP) |
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cpu_dump_rfi(env->nip, do_load_msr(env)); |
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#endif |
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env->interrupt_request = CPU_INTERRUPT_EXITTB; |
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__do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1, |
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| 1338 |
~((target_ulong)0x3FFF0000), 0); |
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| 1392 | 1339 |
} |
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| 1394 | 1341 |
void do_load_403_pb (int num) |
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