root / hw / pci.h @ 0428527c
History | View | Annotate | Download (13.9 kB)
1 |
#ifndef QEMU_PCI_H
|
---|---|
2 |
#define QEMU_PCI_H
|
3 |
|
4 |
#include "qemu-common.h" |
5 |
#include "qobject.h" |
6 |
|
7 |
#include "qdev.h" |
8 |
|
9 |
/* PCI includes legacy ISA access. */
|
10 |
#include "isa.h" |
11 |
|
12 |
#include "pcie.h" |
13 |
|
14 |
/* PCI bus */
|
15 |
|
16 |
#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
17 |
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
18 |
#define PCI_FUNC(devfn) ((devfn) & 0x07) |
19 |
#define PCI_FUNC_MAX 8 |
20 |
|
21 |
/* Class, Vendor and Device IDs from Linux's pci_ids.h */
|
22 |
#include "pci_ids.h" |
23 |
|
24 |
/* QEMU-specific Vendor and Device ID definitions */
|
25 |
|
26 |
/* IBM (0x1014) */
|
27 |
#define PCI_DEVICE_ID_IBM_440GX 0x027f |
28 |
#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
29 |
|
30 |
/* Hitachi (0x1054) */
|
31 |
#define PCI_VENDOR_ID_HITACHI 0x1054 |
32 |
#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
33 |
|
34 |
/* Apple (0x106b) */
|
35 |
#define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
36 |
#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e |
37 |
#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f |
38 |
#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
39 |
#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
40 |
|
41 |
/* Realtek (0x10ec) */
|
42 |
#define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
43 |
|
44 |
/* Xilinx (0x10ee) */
|
45 |
#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 |
46 |
|
47 |
/* Marvell (0x11ab) */
|
48 |
#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 |
49 |
|
50 |
/* QEMU/Bochs VGA (0x1234) */
|
51 |
#define PCI_VENDOR_ID_QEMU 0x1234 |
52 |
#define PCI_DEVICE_ID_QEMU_VGA 0x1111 |
53 |
|
54 |
/* VMWare (0x15ad) */
|
55 |
#define PCI_VENDOR_ID_VMWARE 0x15ad |
56 |
#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
57 |
#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
58 |
#define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
59 |
#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
60 |
#define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
61 |
|
62 |
/* Intel (0x8086) */
|
63 |
#define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
64 |
#define PCI_DEVICE_ID_INTEL_82557 0x1229 |
65 |
|
66 |
/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
|
67 |
#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
68 |
#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
69 |
#define PCI_SUBDEVICE_ID_QEMU 0x1100 |
70 |
|
71 |
#define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
72 |
#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
73 |
#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
74 |
#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
75 |
|
76 |
#define FMT_PCIBUS PRIx64
|
77 |
|
78 |
typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
79 |
uint32_t address, uint32_t data, int len);
|
80 |
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
|
81 |
uint32_t address, int len);
|
82 |
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
83 |
pcibus_t addr, pcibus_t size, int type);
|
84 |
typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
85 |
|
86 |
typedef struct PCIIORegion { |
87 |
pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
|
88 |
#define PCI_BAR_UNMAPPED (~(pcibus_t)0) |
89 |
pcibus_t size; |
90 |
pcibus_t filtered_size; |
91 |
uint8_t type; |
92 |
PCIMapIORegionFunc *map_func; |
93 |
} PCIIORegion; |
94 |
|
95 |
#define PCI_ROM_SLOT 6 |
96 |
#define PCI_NUM_REGIONS 7 |
97 |
|
98 |
#include "pci_regs.h" |
99 |
|
100 |
/* PCI HEADER_TYPE */
|
101 |
#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
102 |
|
103 |
/* Size of the standard PCI config header */
|
104 |
#define PCI_CONFIG_HEADER_SIZE 0x40 |
105 |
/* Size of the standard PCI config space */
|
106 |
#define PCI_CONFIG_SPACE_SIZE 0x100 |
107 |
/* Size of the standart PCIe config space: 4KB */
|
108 |
#define PCIE_CONFIG_SPACE_SIZE 0x1000 |
109 |
|
110 |
#define PCI_NUM_PINS 4 /* A-D */ |
111 |
|
112 |
/* Bits in cap_present field. */
|
113 |
enum {
|
114 |
QEMU_PCI_CAP_MSI = 0x1,
|
115 |
QEMU_PCI_CAP_MSIX = 0x2,
|
116 |
QEMU_PCI_CAP_EXPRESS = 0x4,
|
117 |
|
118 |
/* multifunction capable device */
|
119 |
#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
120 |
QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
|
121 |
}; |
122 |
|
123 |
struct PCIDevice {
|
124 |
DeviceState qdev; |
125 |
/* PCI config space */
|
126 |
uint8_t *config; |
127 |
|
128 |
/* Used to enable config checks on load. Note that writeable bits are
|
129 |
* never checked even if set in cmask. */
|
130 |
uint8_t *cmask; |
131 |
|
132 |
/* Used to implement R/W bytes */
|
133 |
uint8_t *wmask; |
134 |
|
135 |
/* Used to implement RW1C(Write 1 to Clear) bytes */
|
136 |
uint8_t *w1cmask; |
137 |
|
138 |
/* Used to allocate config space for capabilities. */
|
139 |
uint8_t *used; |
140 |
|
141 |
/* the following fields are read only */
|
142 |
PCIBus *bus; |
143 |
uint32_t devfn; |
144 |
char name[64]; |
145 |
PCIIORegion io_regions[PCI_NUM_REGIONS]; |
146 |
|
147 |
/* do not access the following fields */
|
148 |
PCIConfigReadFunc *config_read; |
149 |
PCIConfigWriteFunc *config_write; |
150 |
|
151 |
/* IRQ objects for the INTA-INTD pins. */
|
152 |
qemu_irq *irq; |
153 |
|
154 |
/* Current IRQ levels. Used internally by the generic PCI code. */
|
155 |
uint8_t irq_state; |
156 |
|
157 |
/* Capability bits */
|
158 |
uint32_t cap_present; |
159 |
|
160 |
/* Offset of MSI-X capability in config space */
|
161 |
uint8_t msix_cap; |
162 |
|
163 |
/* MSI-X entries */
|
164 |
int msix_entries_nr;
|
165 |
|
166 |
/* Space to store MSIX table */
|
167 |
uint8_t *msix_table_page; |
168 |
/* MMIO index used to map MSIX table and pending bit entries. */
|
169 |
int msix_mmio_index;
|
170 |
/* Reference-count for entries actually in use by driver. */
|
171 |
unsigned *msix_entry_used;
|
172 |
/* Region including the MSI-X table */
|
173 |
uint32_t msix_bar_size; |
174 |
/* Version id needed for VMState */
|
175 |
int32_t version_id; |
176 |
|
177 |
/* Offset of MSI capability in config space */
|
178 |
uint8_t msi_cap; |
179 |
|
180 |
/* PCI Express */
|
181 |
PCIExpressDevice exp; |
182 |
|
183 |
/* Location of option rom */
|
184 |
char *romfile;
|
185 |
ram_addr_t rom_offset; |
186 |
uint32_t rom_bar; |
187 |
}; |
188 |
|
189 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
190 |
int instance_size, int devfn, |
191 |
PCIConfigReadFunc *config_read, |
192 |
PCIConfigWriteFunc *config_write); |
193 |
|
194 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
195 |
pcibus_t size, uint8_t type, |
196 |
PCIMapIORegionFunc *map_func); |
197 |
|
198 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
|
199 |
uint8_t offset, uint8_t size); |
200 |
|
201 |
void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
|
202 |
|
203 |
void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
|
204 |
|
205 |
uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
206 |
|
207 |
|
208 |
uint32_t pci_default_read_config(PCIDevice *d, |
209 |
uint32_t address, int len);
|
210 |
void pci_default_write_config(PCIDevice *d,
|
211 |
uint32_t address, uint32_t val, int len);
|
212 |
void pci_device_save(PCIDevice *s, QEMUFile *f);
|
213 |
int pci_device_load(PCIDevice *s, QEMUFile *f);
|
214 |
|
215 |
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
216 |
typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
217 |
typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state); |
218 |
void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
|
219 |
const char *name, int devfn_min); |
220 |
PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min); |
221 |
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
|
222 |
void *irq_opaque, int nirq); |
223 |
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
|
224 |
PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
225 |
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
226 |
void *irq_opaque, int devfn_min, int nirq); |
227 |
|
228 |
void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
|
229 |
|
230 |
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
231 |
const char *default_devaddr); |
232 |
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
233 |
const char *default_devaddr); |
234 |
int pci_bus_num(PCIBus *s);
|
235 |
void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d)); |
236 |
PCIBus *pci_find_root_bus(int domain);
|
237 |
int pci_find_domain(const PCIBus *bus); |
238 |
PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
|
239 |
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function); |
240 |
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
241 |
|
242 |
int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
243 |
unsigned int *slotp, unsigned int *funcp); |
244 |
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
245 |
unsigned *slotp);
|
246 |
|
247 |
void do_pci_info_print(Monitor *mon, const QObject *data); |
248 |
void do_pci_info(Monitor *mon, QObject **ret_data);
|
249 |
void pci_bridge_update_mappings(PCIBus *b);
|
250 |
|
251 |
bool pci_msi_enabled(PCIDevice *dev);
|
252 |
void pci_msi_notify(PCIDevice *dev, unsigned int vector); |
253 |
|
254 |
static inline void |
255 |
pci_set_byte(uint8_t *config, uint8_t val) |
256 |
{ |
257 |
*config = val; |
258 |
} |
259 |
|
260 |
static inline uint8_t |
261 |
pci_get_byte(const uint8_t *config)
|
262 |
{ |
263 |
return *config;
|
264 |
} |
265 |
|
266 |
static inline void |
267 |
pci_set_word(uint8_t *config, uint16_t val) |
268 |
{ |
269 |
cpu_to_le16wu((uint16_t *)config, val); |
270 |
} |
271 |
|
272 |
static inline uint16_t |
273 |
pci_get_word(const uint8_t *config)
|
274 |
{ |
275 |
return le16_to_cpupu((const uint16_t *)config); |
276 |
} |
277 |
|
278 |
static inline void |
279 |
pci_set_long(uint8_t *config, uint32_t val) |
280 |
{ |
281 |
cpu_to_le32wu((uint32_t *)config, val); |
282 |
} |
283 |
|
284 |
static inline uint32_t |
285 |
pci_get_long(const uint8_t *config)
|
286 |
{ |
287 |
return le32_to_cpupu((const uint32_t *)config); |
288 |
} |
289 |
|
290 |
static inline void |
291 |
pci_set_quad(uint8_t *config, uint64_t val) |
292 |
{ |
293 |
cpu_to_le64w((uint64_t *)config, val); |
294 |
} |
295 |
|
296 |
static inline uint64_t |
297 |
pci_get_quad(const uint8_t *config)
|
298 |
{ |
299 |
return le64_to_cpup((const uint64_t *)config); |
300 |
} |
301 |
|
302 |
static inline void |
303 |
pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
304 |
{ |
305 |
pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
306 |
} |
307 |
|
308 |
static inline void |
309 |
pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
310 |
{ |
311 |
pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
312 |
} |
313 |
|
314 |
static inline void |
315 |
pci_config_set_revision(uint8_t *pci_config, uint8_t val) |
316 |
{ |
317 |
pci_set_byte(&pci_config[PCI_REVISION_ID], val); |
318 |
} |
319 |
|
320 |
static inline void |
321 |
pci_config_set_class(uint8_t *pci_config, uint16_t val) |
322 |
{ |
323 |
pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
324 |
} |
325 |
|
326 |
static inline void |
327 |
pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) |
328 |
{ |
329 |
pci_set_byte(&pci_config[PCI_CLASS_PROG], val); |
330 |
} |
331 |
|
332 |
static inline void |
333 |
pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) |
334 |
{ |
335 |
pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); |
336 |
} |
337 |
|
338 |
/*
|
339 |
* helper functions to do bit mask operation on configuration space.
|
340 |
* Just to set bit, use test-and-set and discard returned value.
|
341 |
* Just to clear bit, use test-and-clear and discard returned value.
|
342 |
* NOTE: They aren't atomic.
|
343 |
*/
|
344 |
static inline uint8_t |
345 |
pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) |
346 |
{ |
347 |
uint8_t val = pci_get_byte(config); |
348 |
pci_set_byte(config, val & ~mask); |
349 |
return val & mask;
|
350 |
} |
351 |
|
352 |
static inline uint8_t |
353 |
pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) |
354 |
{ |
355 |
uint8_t val = pci_get_byte(config); |
356 |
pci_set_byte(config, val | mask); |
357 |
return val & mask;
|
358 |
} |
359 |
|
360 |
static inline uint16_t |
361 |
pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) |
362 |
{ |
363 |
uint16_t val = pci_get_word(config); |
364 |
pci_set_word(config, val & ~mask); |
365 |
return val & mask;
|
366 |
} |
367 |
|
368 |
static inline uint16_t |
369 |
pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) |
370 |
{ |
371 |
uint16_t val = pci_get_word(config); |
372 |
pci_set_word(config, val | mask); |
373 |
return val & mask;
|
374 |
} |
375 |
|
376 |
static inline uint32_t |
377 |
pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) |
378 |
{ |
379 |
uint32_t val = pci_get_long(config); |
380 |
pci_set_long(config, val & ~mask); |
381 |
return val & mask;
|
382 |
} |
383 |
|
384 |
static inline uint32_t |
385 |
pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) |
386 |
{ |
387 |
uint32_t val = pci_get_long(config); |
388 |
pci_set_long(config, val | mask); |
389 |
return val & mask;
|
390 |
} |
391 |
|
392 |
static inline uint64_t |
393 |
pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) |
394 |
{ |
395 |
uint64_t val = pci_get_quad(config); |
396 |
pci_set_quad(config, val & ~mask); |
397 |
return val & mask;
|
398 |
} |
399 |
|
400 |
static inline uint64_t |
401 |
pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) |
402 |
{ |
403 |
uint64_t val = pci_get_quad(config); |
404 |
pci_set_quad(config, val | mask); |
405 |
return val & mask;
|
406 |
} |
407 |
|
408 |
typedef int (*pci_qdev_initfn)(PCIDevice *dev); |
409 |
typedef struct { |
410 |
DeviceInfo qdev; |
411 |
pci_qdev_initfn init; |
412 |
PCIUnregisterFunc *exit; |
413 |
PCIConfigReadFunc *config_read; |
414 |
PCIConfigWriteFunc *config_write; |
415 |
|
416 |
/*
|
417 |
* pci-to-pci bridge or normal device.
|
418 |
* This doesn't mean pci host switch.
|
419 |
* When card bus bridge is supported, this would be enhanced.
|
420 |
*/
|
421 |
int is_bridge;
|
422 |
|
423 |
/* pcie stuff */
|
424 |
int is_express; /* is this device pci express? */ |
425 |
|
426 |
/* rom bar */
|
427 |
const char *romfile; |
428 |
} PCIDeviceInfo; |
429 |
|
430 |
void pci_qdev_register(PCIDeviceInfo *info);
|
431 |
void pci_qdev_register_many(PCIDeviceInfo *info);
|
432 |
|
433 |
PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
434 |
const char *name); |
435 |
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
|
436 |
bool multifunction,
|
437 |
const char *name); |
438 |
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
439 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
440 |
|
441 |
static inline int pci_is_express(const PCIDevice *d) |
442 |
{ |
443 |
return d->cap_present & QEMU_PCI_CAP_EXPRESS;
|
444 |
} |
445 |
|
446 |
static inline uint32_t pci_config_size(const PCIDevice *d) |
447 |
{ |
448 |
return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
|
449 |
} |
450 |
|
451 |
/* These are not pci specific. Should move into a separate header.
|
452 |
* Only pci.c uses them, so keep them here for now.
|
453 |
*/
|
454 |
|
455 |
/* Get last byte of a range from offset + length.
|
456 |
* Undefined for ranges that wrap around 0. */
|
457 |
static inline uint64_t range_get_last(uint64_t offset, uint64_t len) |
458 |
{ |
459 |
return offset + len - 1; |
460 |
} |
461 |
|
462 |
/* Check whether a given range covers a given byte. */
|
463 |
static inline int range_covers_byte(uint64_t offset, uint64_t len, |
464 |
uint64_t byte) |
465 |
{ |
466 |
return offset <= byte && byte <= range_get_last(offset, len);
|
467 |
} |
468 |
|
469 |
/* Check whether 2 given ranges overlap.
|
470 |
* Undefined if ranges that wrap around 0. */
|
471 |
static inline int ranges_overlap(uint64_t first1, uint64_t len1, |
472 |
uint64_t first2, uint64_t len2) |
473 |
{ |
474 |
uint64_t last1 = range_get_last(first1, len1); |
475 |
uint64_t last2 = range_get_last(first2, len2); |
476 |
|
477 |
return !(last2 < first1 || last1 < first2);
|
478 |
} |
479 |
|
480 |
#endif
|