Revision 0434e30a
b/default-configs/arm-softmmu.mak | ||
---|---|---|
34 | 34 |
CONFIG_MICRODRIVE=y |
35 | 35 |
CONFIG_USB_MUSB=y |
36 | 36 |
|
37 |
CONFIG_ARM5MPCORE=y |
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38 |
CONFIG_ARM9MPCORE=y |
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39 |
CONFIG_ARM15MPCORE=y |
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40 |
|
|
37 | 41 |
CONFIG_ARM_GIC=y |
38 | 42 |
CONFIG_ARM_GIC_KVM=$(CONFIG_KVM) |
39 | 43 |
CONFIG_ARM_TIMER=y |
/dev/null | ||
---|---|---|
1 |
/* |
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2 |
* Cortex-A15MPCore internal peripheral emulation. |
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3 |
* |
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4 |
* Copyright (c) 2012 Linaro Limited. |
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5 |
* Written by Peter Maydell. |
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6 |
* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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9 |
* the Free Software Foundation; either version 2 of the License, or |
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10 |
* (at your option) any later version. |
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11 |
* |
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12 |
* This program is distributed in the hope that it will be useful, |
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13 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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16 |
* |
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17 |
* You should have received a copy of the GNU General Public License along |
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18 |
* with this program; if not, see <http://www.gnu.org/licenses/>. |
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19 |
*/ |
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20 |
|
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21 |
#include "hw/sysbus.h" |
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22 |
#include "sysemu/kvm.h" |
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23 |
|
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24 |
/* A15MP private memory region. */ |
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25 |
|
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26 |
typedef struct A15MPPrivState { |
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27 |
SysBusDevice busdev; |
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28 |
uint32_t num_cpu; |
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29 |
uint32_t num_irq; |
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30 |
MemoryRegion container; |
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31 |
DeviceState *gic; |
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32 |
} A15MPPrivState; |
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33 |
|
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34 |
static void a15mp_priv_set_irq(void *opaque, int irq, int level) |
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35 |
{ |
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36 |
A15MPPrivState *s = (A15MPPrivState *)opaque; |
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37 |
qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
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38 |
} |
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39 |
|
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40 |
static int a15mp_priv_init(SysBusDevice *dev) |
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41 |
{ |
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42 |
A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev); |
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43 |
SysBusDevice *busdev; |
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44 |
const char *gictype = "arm_gic"; |
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45 |
|
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46 |
if (kvm_irqchip_in_kernel()) { |
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47 |
gictype = "kvm-arm-gic"; |
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48 |
} |
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49 |
|
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50 |
s->gic = qdev_create(NULL, gictype); |
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51 |
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); |
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52 |
qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); |
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53 |
qdev_prop_set_uint32(s->gic, "revision", 2); |
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54 |
qdev_init_nofail(s->gic); |
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55 |
busdev = SYS_BUS_DEVICE(s->gic); |
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56 |
|
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57 |
/* Pass through outbound IRQ lines from the GIC */ |
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58 |
sysbus_pass_irq(dev, busdev); |
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59 |
|
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60 |
/* Pass through inbound GPIO lines to the GIC */ |
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61 |
qdev_init_gpio_in(&s->busdev.qdev, a15mp_priv_set_irq, s->num_irq - 32); |
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62 |
|
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63 |
/* Memory map (addresses are offsets from PERIPHBASE): |
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* 0x0000-0x0fff -- reserved |
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* 0x1000-0x1fff -- GIC Distributor |
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66 |
* 0x2000-0x2fff -- GIC CPU interface |
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67 |
* 0x4000-0x4fff -- GIC virtual interface control (not modelled) |
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68 |
* 0x5000-0x5fff -- GIC virtual interface control (not modelled) |
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* 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) |
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70 |
*/ |
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71 |
memory_region_init(&s->container, "a15mp-priv-container", 0x8000); |
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72 |
memory_region_add_subregion(&s->container, 0x1000, |
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73 |
sysbus_mmio_get_region(busdev, 0)); |
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74 |
memory_region_add_subregion(&s->container, 0x2000, |
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75 |
sysbus_mmio_get_region(busdev, 1)); |
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76 |
|
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sysbus_init_mmio(dev, &s->container); |
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return 0; |
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79 |
} |
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80 |
|
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81 |
static Property a15mp_priv_properties[] = { |
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82 |
DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), |
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83 |
/* The Cortex-A15MP may have anything from 0 to 224 external interrupt |
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84 |
* IRQ lines (with another 32 internal). We default to 64+32, which |
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85 |
* is the number provided by the Cortex-A15MP test chip in the |
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86 |
* Versatile Express A15 development board. |
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87 |
* Other boards may differ and should set this property appropriately. |
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88 |
*/ |
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DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 96), |
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90 |
DEFINE_PROP_END_OF_LIST(), |
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91 |
}; |
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92 |
|
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93 |
static void a15mp_priv_class_init(ObjectClass *klass, void *data) |
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94 |
{ |
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95 |
DeviceClass *dc = DEVICE_CLASS(klass); |
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96 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
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97 |
k->init = a15mp_priv_init; |
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98 |
dc->props = a15mp_priv_properties; |
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99 |
/* We currently have no savable state */ |
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100 |
} |
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101 |
|
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102 |
static const TypeInfo a15mp_priv_info = { |
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103 |
.name = "a15mpcore_priv", |
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104 |
.parent = TYPE_SYS_BUS_DEVICE, |
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105 |
.instance_size = sizeof(A15MPPrivState), |
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106 |
.class_init = a15mp_priv_class_init, |
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107 |
}; |
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108 |
|
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109 |
static void a15mp_register_types(void) |
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110 |
{ |
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111 |
type_register_static(&a15mp_priv_info); |
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112 |
} |
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113 |
|
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114 |
type_init(a15mp_register_types) |
/dev/null | ||
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1 |
/* |
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2 |
* Cortex-A9MPCore internal peripheral emulation. |
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3 |
* |
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4 |
* Copyright (c) 2009 CodeSourcery. |
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5 |
* Copyright (c) 2011 Linaro Limited. |
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6 |
* Written by Paul Brook, Peter Maydell. |
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7 |
* |
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8 |
* This code is licensed under the GPL. |
|
9 |
*/ |
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10 |
|
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11 |
#include "hw/sysbus.h" |
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12 |
|
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13 |
typedef struct A9MPPrivState { |
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14 |
SysBusDevice busdev; |
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15 |
uint32_t num_cpu; |
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16 |
MemoryRegion container; |
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17 |
DeviceState *mptimer; |
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18 |
DeviceState *wdt; |
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19 |
DeviceState *gic; |
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20 |
DeviceState *scu; |
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21 |
uint32_t num_irq; |
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22 |
} A9MPPrivState; |
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23 |
|
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24 |
static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
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25 |
{ |
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26 |
A9MPPrivState *s = (A9MPPrivState *)opaque; |
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27 |
qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
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28 |
} |
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29 |
|
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30 |
static int a9mp_priv_init(SysBusDevice *dev) |
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31 |
{ |
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32 |
A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, dev); |
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33 |
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; |
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34 |
int i; |
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35 |
|
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36 |
s->gic = qdev_create(NULL, "arm_gic"); |
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37 |
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); |
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38 |
qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); |
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39 |
qdev_init_nofail(s->gic); |
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40 |
gicbusdev = SYS_BUS_DEVICE(s->gic); |
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41 |
|
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42 |
/* Pass through outbound IRQ lines from the GIC */ |
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43 |
sysbus_pass_irq(dev, gicbusdev); |
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44 |
|
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45 |
/* Pass through inbound GPIO lines to the GIC */ |
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46 |
qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32); |
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47 |
|
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48 |
s->scu = qdev_create(NULL, "a9-scu"); |
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49 |
qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu); |
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50 |
qdev_init_nofail(s->scu); |
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51 |
scubusdev = SYS_BUS_DEVICE(s->scu); |
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52 |
|
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53 |
s->mptimer = qdev_create(NULL, "arm_mptimer"); |
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54 |
qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); |
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55 |
qdev_init_nofail(s->mptimer); |
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56 |
timerbusdev = SYS_BUS_DEVICE(s->mptimer); |
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57 |
|
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58 |
s->wdt = qdev_create(NULL, "arm_mptimer"); |
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59 |
qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu); |
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60 |
qdev_init_nofail(s->wdt); |
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61 |
wdtbusdev = SYS_BUS_DEVICE(s->wdt); |
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62 |
|
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63 |
/* Memory map (addresses are offsets from PERIPHBASE): |
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64 |
* 0x0000-0x00ff -- Snoop Control Unit |
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65 |
* 0x0100-0x01ff -- GIC CPU interface |
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66 |
* 0x0200-0x02ff -- Global Timer |
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67 |
* 0x0300-0x05ff -- nothing |
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68 |
* 0x0600-0x06ff -- private timers and watchdogs |
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69 |
* 0x0700-0x0fff -- nothing |
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70 |
* 0x1000-0x1fff -- GIC Distributor |
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71 |
* |
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72 |
* We should implement the global timer but don't currently do so. |
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73 |
*/ |
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74 |
memory_region_init(&s->container, "a9mp-priv-container", 0x2000); |
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75 |
memory_region_add_subregion(&s->container, 0, |
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76 |
sysbus_mmio_get_region(scubusdev, 0)); |
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77 |
/* GIC CPU interface */ |
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78 |
memory_region_add_subregion(&s->container, 0x100, |
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sysbus_mmio_get_region(gicbusdev, 1)); |
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80 |
/* Note that the A9 exposes only the "timer/watchdog for this core" |
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81 |
* memory region, not the "timer/watchdog for core X" ones 11MPcore has. |
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*/ |
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memory_region_add_subregion(&s->container, 0x600, |
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sysbus_mmio_get_region(timerbusdev, 0)); |
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85 |
memory_region_add_subregion(&s->container, 0x620, |
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sysbus_mmio_get_region(wdtbusdev, 0)); |
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memory_region_add_subregion(&s->container, 0x1000, |
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sysbus_mmio_get_region(gicbusdev, 0)); |
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89 |
|
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90 |
sysbus_init_mmio(dev, &s->container); |
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91 |
|
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92 |
/* Wire up the interrupt from each watchdog and timer. |
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* For each core the timer is PPI 29 and the watchdog PPI 30. |
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*/ |
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95 |
for (i = 0; i < s->num_cpu; i++) { |
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96 |
int ppibase = (s->num_irq - 32) + i * 32; |
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97 |
sysbus_connect_irq(timerbusdev, i, |
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98 |
qdev_get_gpio_in(s->gic, ppibase + 29)); |
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sysbus_connect_irq(wdtbusdev, i, |
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qdev_get_gpio_in(s->gic, ppibase + 30)); |
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} |
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return 0; |
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} |
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104 |
|
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105 |
static Property a9mp_priv_properties[] = { |
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106 |
DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), |
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/* The Cortex-A9MP may have anything from 0 to 224 external interrupt |
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108 |
* IRQ lines (with another 32 internal). We default to 64+32, which |
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109 |
* is the number provided by the Cortex-A9MP test chip in the |
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110 |
* Realview PBX-A9 and Versatile Express A9 development boards. |
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111 |
* Other boards may differ and should set this property appropriately. |
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112 |
*/ |
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DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), |
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DEFINE_PROP_END_OF_LIST(), |
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}; |
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116 |
|
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117 |
static void a9mp_priv_class_init(ObjectClass *klass, void *data) |
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118 |
{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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120 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
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121 |
|
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122 |
k->init = a9mp_priv_init; |
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dc->props = a9mp_priv_properties; |
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124 |
} |
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125 |
|
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126 |
static const TypeInfo a9mp_priv_info = { |
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127 |
.name = "a9mpcore_priv", |
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128 |
.parent = TYPE_SYS_BUS_DEVICE, |
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129 |
.instance_size = sizeof(A9MPPrivState), |
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130 |
.class_init = a9mp_priv_class_init, |
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131 |
}; |
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132 |
|
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133 |
static void a9mp_register_types(void) |
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134 |
{ |
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135 |
type_register_static(&a9mp_priv_info); |
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136 |
} |
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137 |
|
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138 |
type_init(a9mp_register_types) |
b/hw/arm/Makefile.objs | ||
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1 |
obj-y += arm11mpcore.o a9mpcore.o |
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obj-y += a15mpcore.o |
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3 | 1 |
obj-y += strongarm.o |
4 | 2 |
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5 | 3 |
obj-y := $(addprefix ../,$(obj-y)) |
/dev/null | ||
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1 |
/* |
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2 |
* ARM11MPCore internal peripheral emulation. |
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3 |
* |
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4 |
* Copyright (c) 2006-2007 CodeSourcery. |
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5 |
* Written by Paul Brook |
|
6 |
* |
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7 |
* This code is licensed under the GPL. |
|
8 |
*/ |
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9 |
|
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10 |
#include "hw/sysbus.h" |
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11 |
#include "qemu/timer.h" |
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12 |
|
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13 |
/* MPCore private memory region. */ |
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14 |
|
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15 |
typedef struct ARM11MPCorePriveState { |
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16 |
SysBusDevice busdev; |
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17 |
uint32_t scu_control; |
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18 |
int iomemtype; |
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19 |
uint32_t old_timer_status[8]; |
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20 |
uint32_t num_cpu; |
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21 |
MemoryRegion iomem; |
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22 |
MemoryRegion container; |
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23 |
DeviceState *mptimer; |
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24 |
DeviceState *wdtimer; |
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25 |
DeviceState *gic; |
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26 |
uint32_t num_irq; |
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27 |
} ARM11MPCorePriveState; |
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28 |
|
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29 |
/* Per-CPU private memory mapped IO. */ |
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30 |
|
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31 |
static uint64_t mpcore_scu_read(void *opaque, hwaddr offset, |
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32 |
unsigned size) |
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33 |
{ |
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34 |
ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
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35 |
int id; |
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36 |
/* SCU */ |
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37 |
switch (offset) { |
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38 |
case 0x00: /* Control. */ |
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39 |
return s->scu_control; |
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40 |
case 0x04: /* Configuration. */ |
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41 |
id = ((1 << s->num_cpu) - 1) << 4; |
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42 |
return id | (s->num_cpu - 1); |
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43 |
case 0x08: /* CPU status. */ |
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44 |
return 0; |
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45 |
case 0x0c: /* Invalidate all. */ |
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46 |
return 0; |
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47 |
default: |
|
48 |
qemu_log_mask(LOG_GUEST_ERROR, |
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49 |
"mpcore_priv_read: Bad offset %x\n", (int)offset); |
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50 |
return 0; |
|
51 |
} |
|
52 |
} |
|
53 |
|
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54 |
static void mpcore_scu_write(void *opaque, hwaddr offset, |
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55 |
uint64_t value, unsigned size) |
|
56 |
{ |
|
57 |
ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
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58 |
/* SCU */ |
|
59 |
switch (offset) { |
|
60 |
case 0: /* Control register. */ |
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61 |
s->scu_control = value & 1; |
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62 |
break; |
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63 |
case 0x0c: /* Invalidate all. */ |
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64 |
/* This is a no-op as cache is not emulated. */ |
|
65 |
break; |
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66 |
default: |
|
67 |
qemu_log_mask(LOG_GUEST_ERROR, |
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68 |
"mpcore_priv_read: Bad offset %x\n", (int)offset); |
|
69 |
} |
|
70 |
} |
|
71 |
|
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72 |
static const MemoryRegionOps mpcore_scu_ops = { |
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73 |
.read = mpcore_scu_read, |
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74 |
.write = mpcore_scu_write, |
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75 |
.endianness = DEVICE_NATIVE_ENDIAN, |
|
76 |
}; |
|
77 |
|
|
78 |
static void mpcore_priv_set_irq(void *opaque, int irq, int level) |
|
79 |
{ |
|
80 |
ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
|
81 |
qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
|
82 |
} |
|
83 |
|
|
84 |
static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) |
|
85 |
{ |
|
86 |
int i; |
|
87 |
SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic); |
|
88 |
SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer); |
|
89 |
SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer); |
|
90 |
memory_region_init(&s->container, "mpcode-priv-container", 0x2000); |
|
91 |
memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100); |
|
92 |
memory_region_add_subregion(&s->container, 0, &s->iomem); |
|
93 |
/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs |
|
94 |
* at 0x200, 0x300... |
|
95 |
*/ |
|
96 |
for (i = 0; i < (s->num_cpu + 1); i++) { |
|
97 |
hwaddr offset = 0x100 + (i * 0x100); |
|
98 |
memory_region_add_subregion(&s->container, offset, |
|
99 |
sysbus_mmio_get_region(gicbusdev, i + 1)); |
|
100 |
} |
|
101 |
/* Add the regions for timer and watchdog for "current CPU" and |
|
102 |
* for each specific CPU. |
|
103 |
*/ |
|
104 |
for (i = 0; i < (s->num_cpu + 1); i++) { |
|
105 |
/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ |
|
106 |
hwaddr offset = 0x600 + i * 0x100; |
|
107 |
memory_region_add_subregion(&s->container, offset, |
|
108 |
sysbus_mmio_get_region(timerbusdev, i)); |
|
109 |
memory_region_add_subregion(&s->container, offset + 0x20, |
|
110 |
sysbus_mmio_get_region(wdtbusdev, i)); |
|
111 |
} |
|
112 |
memory_region_add_subregion(&s->container, 0x1000, |
|
113 |
sysbus_mmio_get_region(gicbusdev, 0)); |
|
114 |
/* Wire up the interrupt from each watchdog and timer. |
|
115 |
* For each core the timer is PPI 29 and the watchdog PPI 30. |
|
116 |
*/ |
|
117 |
for (i = 0; i < s->num_cpu; i++) { |
|
118 |
int ppibase = (s->num_irq - 32) + i * 32; |
|
119 |
sysbus_connect_irq(timerbusdev, i, |
|
120 |
qdev_get_gpio_in(s->gic, ppibase + 29)); |
|
121 |
sysbus_connect_irq(wdtbusdev, i, |
|
122 |
qdev_get_gpio_in(s->gic, ppibase + 30)); |
|
123 |
} |
|
124 |
} |
|
125 |
|
|
126 |
static int mpcore_priv_init(SysBusDevice *dev) |
|
127 |
{ |
|
128 |
ARM11MPCorePriveState *s = FROM_SYSBUS(ARM11MPCorePriveState, dev); |
|
129 |
|
|
130 |
s->gic = qdev_create(NULL, "arm_gic"); |
|
131 |
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); |
|
132 |
qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); |
|
133 |
/* Request the legacy 11MPCore GIC behaviour: */ |
|
134 |
qdev_prop_set_uint32(s->gic, "revision", 0); |
|
135 |
qdev_init_nofail(s->gic); |
|
136 |
|
|
137 |
/* Pass through outbound IRQ lines from the GIC */ |
|
138 |
sysbus_pass_irq(dev, SYS_BUS_DEVICE(s->gic)); |
|
139 |
|
|
140 |
/* Pass through inbound GPIO lines to the GIC */ |
|
141 |
qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32); |
|
142 |
|
|
143 |
s->mptimer = qdev_create(NULL, "arm_mptimer"); |
|
144 |
qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); |
|
145 |
qdev_init_nofail(s->mptimer); |
|
146 |
|
|
147 |
s->wdtimer = qdev_create(NULL, "arm_mptimer"); |
|
148 |
qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu); |
|
149 |
qdev_init_nofail(s->wdtimer); |
|
150 |
|
|
151 |
mpcore_priv_map_setup(s); |
|
152 |
sysbus_init_mmio(dev, &s->container); |
|
153 |
return 0; |
|
154 |
} |
|
155 |
|
|
156 |
/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ |
|
157 |
controllers. The output of these, plus some of the raw input lines |
|
158 |
are fed into a single SMP-aware interrupt controller on the CPU. */ |
|
159 |
typedef struct { |
|
160 |
SysBusDevice busdev; |
|
161 |
SysBusDevice *priv; |
|
162 |
qemu_irq cpuic[32]; |
|
163 |
qemu_irq rvic[4][64]; |
|
164 |
uint32_t num_cpu; |
|
165 |
} mpcore_rirq_state; |
|
166 |
|
|
167 |
/* Map baseboard IRQs onto CPU IRQ lines. */ |
|
168 |
static const int mpcore_irq_map[32] = { |
|
169 |
-1, -1, -1, -1, 1, 2, -1, -1, |
|
170 |
-1, -1, 6, -1, 4, 5, -1, -1, |
|
171 |
-1, 14, 15, 0, 7, 8, -1, -1, |
|
172 |
-1, -1, -1, -1, 9, 3, -1, -1, |
|
173 |
}; |
|
174 |
|
|
175 |
static void mpcore_rirq_set_irq(void *opaque, int irq, int level) |
|
176 |
{ |
|
177 |
mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; |
|
178 |
int i; |
|
179 |
|
|
180 |
for (i = 0; i < 4; i++) { |
|
181 |
qemu_set_irq(s->rvic[i][irq], level); |
|
182 |
} |
|
183 |
if (irq < 32) { |
|
184 |
irq = mpcore_irq_map[irq]; |
|
185 |
if (irq >= 0) { |
|
186 |
qemu_set_irq(s->cpuic[irq], level); |
|
187 |
} |
|
188 |
} |
|
189 |
} |
|
190 |
|
|
191 |
static int realview_mpcore_init(SysBusDevice *dev) |
|
192 |
{ |
|
193 |
mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev); |
|
194 |
DeviceState *gic; |
|
195 |
DeviceState *priv; |
|
196 |
int n; |
|
197 |
int i; |
|
198 |
|
|
199 |
priv = qdev_create(NULL, "arm11mpcore_priv"); |
|
200 |
qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); |
|
201 |
qdev_init_nofail(priv); |
|
202 |
s->priv = SYS_BUS_DEVICE(priv); |
|
203 |
sysbus_pass_irq(dev, s->priv); |
|
204 |
for (i = 0; i < 32; i++) { |
|
205 |
s->cpuic[i] = qdev_get_gpio_in(priv, i); |
|
206 |
} |
|
207 |
/* ??? IRQ routing is hardcoded to "normal" mode. */ |
|
208 |
for (n = 0; n < 4; n++) { |
|
209 |
gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000, |
|
210 |
s->cpuic[10 + n]); |
|
211 |
for (i = 0; i < 64; i++) { |
|
212 |
s->rvic[n][i] = qdev_get_gpio_in(gic, i); |
|
213 |
} |
|
214 |
} |
|
215 |
qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64); |
|
216 |
sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0)); |
|
217 |
return 0; |
|
218 |
} |
|
219 |
|
|
220 |
static Property mpcore_rirq_properties[] = { |
|
221 |
DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), |
|
222 |
DEFINE_PROP_END_OF_LIST(), |
|
223 |
}; |
|
224 |
|
|
225 |
static void mpcore_rirq_class_init(ObjectClass *klass, void *data) |
|
226 |
{ |
|
227 |
DeviceClass *dc = DEVICE_CLASS(klass); |
|
228 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
|
229 |
|
|
230 |
k->init = realview_mpcore_init; |
|
231 |
dc->props = mpcore_rirq_properties; |
|
232 |
} |
|
233 |
|
|
234 |
static const TypeInfo mpcore_rirq_info = { |
|
235 |
.name = "realview_mpcore", |
|
236 |
.parent = TYPE_SYS_BUS_DEVICE, |
|
237 |
.instance_size = sizeof(mpcore_rirq_state), |
|
238 |
.class_init = mpcore_rirq_class_init, |
|
239 |
}; |
|
240 |
|
|
241 |
static Property mpcore_priv_properties[] = { |
|
242 |
DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), |
|
243 |
/* The ARM11 MPCORE TRM says the on-chip controller may have |
|
244 |
* anything from 0 to 224 external interrupt IRQ lines (with another |
|
245 |
* 32 internal). We default to 32+32, which is the number provided by |
|
246 |
* the ARM11 MPCore test chip in the Realview Versatile Express |
|
247 |
* coretile. Other boards may differ and should set this property |
|
248 |
* appropriately. Some Linux kernels may not boot if the hardware |
|
249 |
* has more IRQ lines than the kernel expects. |
|
250 |
*/ |
|
251 |
DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), |
|
252 |
DEFINE_PROP_END_OF_LIST(), |
|
253 |
}; |
|
254 |
|
|
255 |
static void mpcore_priv_class_init(ObjectClass *klass, void *data) |
|
256 |
{ |
|
257 |
DeviceClass *dc = DEVICE_CLASS(klass); |
|
258 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
|
259 |
|
|
260 |
k->init = mpcore_priv_init; |
|
261 |
dc->props = mpcore_priv_properties; |
|
262 |
} |
|
263 |
|
|
264 |
static const TypeInfo mpcore_priv_info = { |
|
265 |
.name = "arm11mpcore_priv", |
|
266 |
.parent = TYPE_SYS_BUS_DEVICE, |
|
267 |
.instance_size = sizeof(ARM11MPCorePriveState), |
|
268 |
.class_init = mpcore_priv_class_init, |
|
269 |
}; |
|
270 |
|
|
271 |
static void arm11mpcore_register_types(void) |
|
272 |
{ |
|
273 |
type_register_static(&mpcore_rirq_info); |
|
274 |
type_register_static(&mpcore_priv_info); |
|
275 |
} |
|
276 |
|
|
277 |
type_init(arm11mpcore_register_types) |
b/hw/cpu/Makefile.objs | ||
---|---|---|
1 |
obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o |
|
2 |
obj-$(CONFIG_ARM9MPCORE) += a9mpcore.o |
|
3 |
obj-$(CONFIG_ARM15MPCORE) += a15mpcore.o |
|
4 |
|
b/hw/cpu/a15mpcore.c | ||
---|---|---|
1 |
/* |
|
2 |
* Cortex-A15MPCore internal peripheral emulation. |
|
3 |
* |
|
4 |
* Copyright (c) 2012 Linaro Limited. |
|
5 |
* Written by Peter Maydell. |
|
6 |
* |
|
7 |
* This program is free software; you can redistribute it and/or modify |
|
8 |
* it under the terms of the GNU General Public License as published by |
|
9 |
* the Free Software Foundation; either version 2 of the License, or |
|
10 |
* (at your option) any later version. |
|
11 |
* |
|
12 |
* This program is distributed in the hope that it will be useful, |
|
13 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
14 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
15 |
* GNU General Public License for more details. |
|
16 |
* |
|
17 |
* You should have received a copy of the GNU General Public License along |
|
18 |
* with this program; if not, see <http://www.gnu.org/licenses/>. |
|
19 |
*/ |
|
20 |
|
|
21 |
#include "hw/sysbus.h" |
|
22 |
#include "sysemu/kvm.h" |
|
23 |
|
|
24 |
/* A15MP private memory region. */ |
|
25 |
|
|
26 |
typedef struct A15MPPrivState { |
|
27 |
SysBusDevice busdev; |
|
28 |
uint32_t num_cpu; |
|
29 |
uint32_t num_irq; |
|
30 |
MemoryRegion container; |
|
31 |
DeviceState *gic; |
|
32 |
} A15MPPrivState; |
|
33 |
|
|
34 |
static void a15mp_priv_set_irq(void *opaque, int irq, int level) |
|
35 |
{ |
|
36 |
A15MPPrivState *s = (A15MPPrivState *)opaque; |
|
37 |
qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
|
38 |
} |
|
39 |
|
|
40 |
static int a15mp_priv_init(SysBusDevice *dev) |
|
41 |
{ |
|
42 |
A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev); |
|
43 |
SysBusDevice *busdev; |
|
44 |
const char *gictype = "arm_gic"; |
|
45 |
|
|
46 |
if (kvm_irqchip_in_kernel()) { |
|
47 |
gictype = "kvm-arm-gic"; |
|
48 |
} |
|
49 |
|
|
50 |
s->gic = qdev_create(NULL, gictype); |
|
51 |
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); |
|
52 |
qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); |
|
53 |
qdev_prop_set_uint32(s->gic, "revision", 2); |
|
54 |
qdev_init_nofail(s->gic); |
|
55 |
busdev = SYS_BUS_DEVICE(s->gic); |
|
56 |
|
|
57 |
/* Pass through outbound IRQ lines from the GIC */ |
|
58 |
sysbus_pass_irq(dev, busdev); |
|
59 |
|
|
60 |
/* Pass through inbound GPIO lines to the GIC */ |
|
61 |
qdev_init_gpio_in(&s->busdev.qdev, a15mp_priv_set_irq, s->num_irq - 32); |
|
62 |
|
|
63 |
/* Memory map (addresses are offsets from PERIPHBASE): |
|
64 |
* 0x0000-0x0fff -- reserved |
|
65 |
* 0x1000-0x1fff -- GIC Distributor |
|
66 |
* 0x2000-0x2fff -- GIC CPU interface |
|
67 |
* 0x4000-0x4fff -- GIC virtual interface control (not modelled) |
|
68 |
* 0x5000-0x5fff -- GIC virtual interface control (not modelled) |
|
69 |
* 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) |
|
70 |
*/ |
|
71 |
memory_region_init(&s->container, "a15mp-priv-container", 0x8000); |
|
72 |
memory_region_add_subregion(&s->container, 0x1000, |
|
73 |
sysbus_mmio_get_region(busdev, 0)); |
|
74 |
memory_region_add_subregion(&s->container, 0x2000, |
|
75 |
sysbus_mmio_get_region(busdev, 1)); |
|
76 |
|
|
77 |
sysbus_init_mmio(dev, &s->container); |
|
78 |
return 0; |
|
79 |
} |
|
80 |
|
|
81 |
static Property a15mp_priv_properties[] = { |
|
82 |
DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), |
|
83 |
/* The Cortex-A15MP may have anything from 0 to 224 external interrupt |
|
84 |
* IRQ lines (with another 32 internal). We default to 64+32, which |
|
85 |
* is the number provided by the Cortex-A15MP test chip in the |
|
86 |
* Versatile Express A15 development board. |
|
87 |
* Other boards may differ and should set this property appropriately. |
|
88 |
*/ |
|
89 |
DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 96), |
|
90 |
DEFINE_PROP_END_OF_LIST(), |
|
91 |
}; |
|
92 |
|
|
93 |
static void a15mp_priv_class_init(ObjectClass *klass, void *data) |
|
94 |
{ |
|
95 |
DeviceClass *dc = DEVICE_CLASS(klass); |
|
96 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
|
97 |
k->init = a15mp_priv_init; |
|
98 |
dc->props = a15mp_priv_properties; |
|
99 |
/* We currently have no savable state */ |
|
100 |
} |
|
101 |
|
|
102 |
static const TypeInfo a15mp_priv_info = { |
|
103 |
.name = "a15mpcore_priv", |
|
104 |
.parent = TYPE_SYS_BUS_DEVICE, |
|
105 |
.instance_size = sizeof(A15MPPrivState), |
|
106 |
.class_init = a15mp_priv_class_init, |
|
107 |
}; |
|
108 |
|
|
109 |
static void a15mp_register_types(void) |
|
110 |
{ |
|
111 |
type_register_static(&a15mp_priv_info); |
|
112 |
} |
|
113 |
|
|
114 |
type_init(a15mp_register_types) |
b/hw/cpu/a9mpcore.c | ||
---|---|---|
1 |
/* |
|
2 |
* Cortex-A9MPCore internal peripheral emulation. |
|
3 |
* |
|
4 |
* Copyright (c) 2009 CodeSourcery. |
|
5 |
* Copyright (c) 2011 Linaro Limited. |
|
6 |
* Written by Paul Brook, Peter Maydell. |
|
7 |
* |
|
8 |
* This code is licensed under the GPL. |
|
9 |
*/ |
|
10 |
|
|
11 |
#include "hw/sysbus.h" |
|
12 |
|
|
13 |
typedef struct A9MPPrivState { |
|
14 |
SysBusDevice busdev; |
|
15 |
uint32_t num_cpu; |
|
16 |
MemoryRegion container; |
|
17 |
DeviceState *mptimer; |
|
18 |
DeviceState *wdt; |
|
19 |
DeviceState *gic; |
|
20 |
DeviceState *scu; |
|
21 |
uint32_t num_irq; |
|
22 |
} A9MPPrivState; |
|
23 |
|
|
24 |
static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
|
25 |
{ |
|
26 |
A9MPPrivState *s = (A9MPPrivState *)opaque; |
|
27 |
qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
|
28 |
} |
|
29 |
|
|
30 |
static int a9mp_priv_init(SysBusDevice *dev) |
|
31 |
{ |
|
32 |
A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, dev); |
|
33 |
SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; |
|
34 |
int i; |
|
35 |
|
|
36 |
s->gic = qdev_create(NULL, "arm_gic"); |
|
37 |
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); |
|
38 |
qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); |
|
39 |
qdev_init_nofail(s->gic); |
|
40 |
gicbusdev = SYS_BUS_DEVICE(s->gic); |
|
41 |
|
|
42 |
/* Pass through outbound IRQ lines from the GIC */ |
|
43 |
sysbus_pass_irq(dev, gicbusdev); |
|
44 |
|
|
45 |
/* Pass through inbound GPIO lines to the GIC */ |
|
46 |
qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32); |
|
47 |
|
|
48 |
s->scu = qdev_create(NULL, "a9-scu"); |
|
49 |
qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu); |
|
50 |
qdev_init_nofail(s->scu); |
|
51 |
scubusdev = SYS_BUS_DEVICE(s->scu); |
|
52 |
|
|
53 |
s->mptimer = qdev_create(NULL, "arm_mptimer"); |
|
54 |
qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); |
|
55 |
qdev_init_nofail(s->mptimer); |
|
56 |
timerbusdev = SYS_BUS_DEVICE(s->mptimer); |
|
57 |
|
|
58 |
s->wdt = qdev_create(NULL, "arm_mptimer"); |
|
59 |
qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu); |
|
60 |
qdev_init_nofail(s->wdt); |
|
61 |
wdtbusdev = SYS_BUS_DEVICE(s->wdt); |
|
62 |
|
|
63 |
/* Memory map (addresses are offsets from PERIPHBASE): |
|
64 |
* 0x0000-0x00ff -- Snoop Control Unit |
|
65 |
* 0x0100-0x01ff -- GIC CPU interface |
|
66 |
* 0x0200-0x02ff -- Global Timer |
|
67 |
* 0x0300-0x05ff -- nothing |
|
68 |
* 0x0600-0x06ff -- private timers and watchdogs |
|
69 |
* 0x0700-0x0fff -- nothing |
|
70 |
* 0x1000-0x1fff -- GIC Distributor |
|
71 |
* |
|
72 |
* We should implement the global timer but don't currently do so. |
|
73 |
*/ |
|
74 |
memory_region_init(&s->container, "a9mp-priv-container", 0x2000); |
|
75 |
memory_region_add_subregion(&s->container, 0, |
|
76 |
sysbus_mmio_get_region(scubusdev, 0)); |
|
77 |
/* GIC CPU interface */ |
|
78 |
memory_region_add_subregion(&s->container, 0x100, |
|
79 |
sysbus_mmio_get_region(gicbusdev, 1)); |
|
80 |
/* Note that the A9 exposes only the "timer/watchdog for this core" |
|
81 |
* memory region, not the "timer/watchdog for core X" ones 11MPcore has. |
|
82 |
*/ |
|
83 |
memory_region_add_subregion(&s->container, 0x600, |
|
84 |
sysbus_mmio_get_region(timerbusdev, 0)); |
|
85 |
memory_region_add_subregion(&s->container, 0x620, |
|
86 |
sysbus_mmio_get_region(wdtbusdev, 0)); |
|
87 |
memory_region_add_subregion(&s->container, 0x1000, |
|
88 |
sysbus_mmio_get_region(gicbusdev, 0)); |
|
89 |
|
|
90 |
sysbus_init_mmio(dev, &s->container); |
|
91 |
|
|
92 |
/* Wire up the interrupt from each watchdog and timer. |
|
93 |
* For each core the timer is PPI 29 and the watchdog PPI 30. |
|
94 |
*/ |
|
95 |
for (i = 0; i < s->num_cpu; i++) { |
|
96 |
int ppibase = (s->num_irq - 32) + i * 32; |
|
97 |
sysbus_connect_irq(timerbusdev, i, |
|
98 |
qdev_get_gpio_in(s->gic, ppibase + 29)); |
|
99 |
sysbus_connect_irq(wdtbusdev, i, |
|
100 |
qdev_get_gpio_in(s->gic, ppibase + 30)); |
|
101 |
} |
|
102 |
return 0; |
|
103 |
} |
|
104 |
|
|
105 |
static Property a9mp_priv_properties[] = { |
|
106 |
DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), |
|
107 |
/* The Cortex-A9MP may have anything from 0 to 224 external interrupt |
|
108 |
* IRQ lines (with another 32 internal). We default to 64+32, which |
|
109 |
* is the number provided by the Cortex-A9MP test chip in the |
|
110 |
* Realview PBX-A9 and Versatile Express A9 development boards. |
|
111 |
* Other boards may differ and should set this property appropriately. |
|
112 |
*/ |
|
113 |
DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), |
|
114 |
DEFINE_PROP_END_OF_LIST(), |
|
115 |
}; |
|
116 |
|
|
117 |
static void a9mp_priv_class_init(ObjectClass *klass, void *data) |
|
118 |
{ |
|
119 |
DeviceClass *dc = DEVICE_CLASS(klass); |
|
120 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
|
121 |
|
|
122 |
k->init = a9mp_priv_init; |
|
123 |
dc->props = a9mp_priv_properties; |
|
124 |
} |
|
125 |
|
|
126 |
static const TypeInfo a9mp_priv_info = { |
|
127 |
.name = "a9mpcore_priv", |
|
128 |
.parent = TYPE_SYS_BUS_DEVICE, |
|
129 |
.instance_size = sizeof(A9MPPrivState), |
|
130 |
.class_init = a9mp_priv_class_init, |
|
131 |
}; |
|
132 |
|
|
133 |
static void a9mp_register_types(void) |
|
134 |
{ |
|
135 |
type_register_static(&a9mp_priv_info); |
|
136 |
} |
|
137 |
|
|
138 |
type_init(a9mp_register_types) |
b/hw/cpu/arm11mpcore.c | ||
---|---|---|
1 |
/* |
|
2 |
* ARM11MPCore internal peripheral emulation. |
|
3 |
* |
|
4 |
* Copyright (c) 2006-2007 CodeSourcery. |
|
5 |
* Written by Paul Brook |
|
6 |
* |
|
7 |
* This code is licensed under the GPL. |
|
8 |
*/ |
|
9 |
|
|
10 |
#include "hw/sysbus.h" |
|
11 |
#include "qemu/timer.h" |
|
12 |
|
|
13 |
/* MPCore private memory region. */ |
|
14 |
|
|
15 |
typedef struct ARM11MPCorePriveState { |
|
16 |
SysBusDevice busdev; |
|
17 |
uint32_t scu_control; |
|
18 |
int iomemtype; |
|
19 |
uint32_t old_timer_status[8]; |
|
20 |
uint32_t num_cpu; |
|
21 |
MemoryRegion iomem; |
|
22 |
MemoryRegion container; |
|
23 |
DeviceState *mptimer; |
|
24 |
DeviceState *wdtimer; |
|
25 |
DeviceState *gic; |
|
26 |
uint32_t num_irq; |
|
27 |
} ARM11MPCorePriveState; |
|
28 |
|
|
29 |
/* Per-CPU private memory mapped IO. */ |
|
30 |
|
|
31 |
static uint64_t mpcore_scu_read(void *opaque, hwaddr offset, |
|
32 |
unsigned size) |
|
33 |
{ |
|
34 |
ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
|
35 |
int id; |
|
36 |
/* SCU */ |
|
37 |
switch (offset) { |
|
38 |
case 0x00: /* Control. */ |
|
39 |
return s->scu_control; |
|
40 |
case 0x04: /* Configuration. */ |
|
41 |
id = ((1 << s->num_cpu) - 1) << 4; |
|
42 |
return id | (s->num_cpu - 1); |
|
43 |
case 0x08: /* CPU status. */ |
|
44 |
return 0; |
|
45 |
case 0x0c: /* Invalidate all. */ |
|
46 |
return 0; |
|
47 |
default: |
|
48 |
qemu_log_mask(LOG_GUEST_ERROR, |
|
49 |
"mpcore_priv_read: Bad offset %x\n", (int)offset); |
|
50 |
return 0; |
|
51 |
} |
|
52 |
} |
|
53 |
|
|
54 |
static void mpcore_scu_write(void *opaque, hwaddr offset, |
|
55 |
uint64_t value, unsigned size) |
|
56 |
{ |
|
57 |
ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
|
58 |
/* SCU */ |
|
59 |
switch (offset) { |
|
60 |
case 0: /* Control register. */ |
|
61 |
s->scu_control = value & 1; |
|
62 |
break; |
|
63 |
case 0x0c: /* Invalidate all. */ |
|
64 |
/* This is a no-op as cache is not emulated. */ |
|
65 |
break; |
|
66 |
default: |
|
67 |
qemu_log_mask(LOG_GUEST_ERROR, |
|
68 |
"mpcore_priv_read: Bad offset %x\n", (int)offset); |
|
69 |
} |
|
70 |
} |
|
71 |
|
|
72 |
static const MemoryRegionOps mpcore_scu_ops = { |
|
73 |
.read = mpcore_scu_read, |
|
74 |
.write = mpcore_scu_write, |
|
75 |
.endianness = DEVICE_NATIVE_ENDIAN, |
|
76 |
}; |
|
77 |
|
|
78 |
static void mpcore_priv_set_irq(void *opaque, int irq, int level) |
|
79 |
{ |
|
80 |
ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
|
81 |
qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
|
82 |
} |
|
83 |
|
|
84 |
static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) |
|
85 |
{ |
|
86 |
int i; |
|
87 |
SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic); |
|
88 |
SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer); |
|
89 |
SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer); |
|
90 |
memory_region_init(&s->container, "mpcode-priv-container", 0x2000); |
|
91 |
memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100); |
|
92 |
memory_region_add_subregion(&s->container, 0, &s->iomem); |
|
93 |
/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs |
|
94 |
* at 0x200, 0x300... |
|
95 |
*/ |
|
96 |
for (i = 0; i < (s->num_cpu + 1); i++) { |
|
97 |
hwaddr offset = 0x100 + (i * 0x100); |
|
98 |
memory_region_add_subregion(&s->container, offset, |
|
99 |
sysbus_mmio_get_region(gicbusdev, i + 1)); |
|
100 |
} |
|
101 |
/* Add the regions for timer and watchdog for "current CPU" and |
|
102 |
* for each specific CPU. |
|
103 |
*/ |
|
104 |
for (i = 0; i < (s->num_cpu + 1); i++) { |
|
105 |
/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ |
|
106 |
hwaddr offset = 0x600 + i * 0x100; |
|
107 |
memory_region_add_subregion(&s->container, offset, |
|
108 |
sysbus_mmio_get_region(timerbusdev, i)); |
|
109 |
memory_region_add_subregion(&s->container, offset + 0x20, |
|
110 |
sysbus_mmio_get_region(wdtbusdev, i)); |
|
111 |
} |
|
112 |
memory_region_add_subregion(&s->container, 0x1000, |
|
113 |
sysbus_mmio_get_region(gicbusdev, 0)); |
|
114 |
/* Wire up the interrupt from each watchdog and timer. |
|
115 |
* For each core the timer is PPI 29 and the watchdog PPI 30. |
|
116 |
*/ |
|
117 |
for (i = 0; i < s->num_cpu; i++) { |
|
118 |
int ppibase = (s->num_irq - 32) + i * 32; |
|
119 |
sysbus_connect_irq(timerbusdev, i, |
|
120 |
qdev_get_gpio_in(s->gic, ppibase + 29)); |
|
121 |
sysbus_connect_irq(wdtbusdev, i, |
|
122 |
qdev_get_gpio_in(s->gic, ppibase + 30)); |
|
123 |
} |
|
124 |
} |
|
125 |
|
|
126 |
static int mpcore_priv_init(SysBusDevice *dev) |
|
127 |
{ |
|
128 |
ARM11MPCorePriveState *s = FROM_SYSBUS(ARM11MPCorePriveState, dev); |
|
129 |
|
|
130 |
s->gic = qdev_create(NULL, "arm_gic"); |
|
131 |
qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); |
|
132 |
qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); |
|
133 |
/* Request the legacy 11MPCore GIC behaviour: */ |
|
134 |
qdev_prop_set_uint32(s->gic, "revision", 0); |
|
135 |
qdev_init_nofail(s->gic); |
|
136 |
|
|
137 |
/* Pass through outbound IRQ lines from the GIC */ |
|
138 |
sysbus_pass_irq(dev, SYS_BUS_DEVICE(s->gic)); |
|
139 |
|
|
140 |
/* Pass through inbound GPIO lines to the GIC */ |
|
141 |
qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32); |
|
142 |
|
|
143 |
s->mptimer = qdev_create(NULL, "arm_mptimer"); |
|
144 |
qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); |
|
145 |
qdev_init_nofail(s->mptimer); |
|
146 |
|
|
147 |
s->wdtimer = qdev_create(NULL, "arm_mptimer"); |
|
148 |
qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu); |
|
149 |
qdev_init_nofail(s->wdtimer); |
|
150 |
|
|
151 |
mpcore_priv_map_setup(s); |
|
152 |
sysbus_init_mmio(dev, &s->container); |
|
153 |
return 0; |
|
154 |
} |
|
155 |
|
|
156 |
/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ |
|
157 |
controllers. The output of these, plus some of the raw input lines |
|
158 |
are fed into a single SMP-aware interrupt controller on the CPU. */ |
|
159 |
typedef struct { |
|
160 |
SysBusDevice busdev; |
|
161 |
SysBusDevice *priv; |
|
162 |
qemu_irq cpuic[32]; |
|
163 |
qemu_irq rvic[4][64]; |
|
164 |
uint32_t num_cpu; |
|
165 |
} mpcore_rirq_state; |
|
166 |
|
|
167 |
/* Map baseboard IRQs onto CPU IRQ lines. */ |
|
168 |
static const int mpcore_irq_map[32] = { |
|
169 |
-1, -1, -1, -1, 1, 2, -1, -1, |
|
170 |
-1, -1, 6, -1, 4, 5, -1, -1, |
|
171 |
-1, 14, 15, 0, 7, 8, -1, -1, |
|
172 |
-1, -1, -1, -1, 9, 3, -1, -1, |
|
173 |
}; |
|
174 |
|
|
175 |
static void mpcore_rirq_set_irq(void *opaque, int irq, int level) |
|
176 |
{ |
|
177 |
mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; |
|
178 |
int i; |
|
179 |
|
|
180 |
for (i = 0; i < 4; i++) { |
|
181 |
qemu_set_irq(s->rvic[i][irq], level); |
|
182 |
} |
|
183 |
if (irq < 32) { |
|
184 |
irq = mpcore_irq_map[irq]; |
|
185 |
if (irq >= 0) { |
|
186 |
qemu_set_irq(s->cpuic[irq], level); |
|
187 |
} |
|
188 |
} |
|
189 |
} |
|
190 |
|
|
191 |
static int realview_mpcore_init(SysBusDevice *dev) |
|
192 |
{ |
|
193 |
mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev); |
|
194 |
DeviceState *gic; |
|
195 |
DeviceState *priv; |
|
196 |
int n; |
|
197 |
int i; |
|
198 |
|
|
199 |
priv = qdev_create(NULL, "arm11mpcore_priv"); |
|
200 |
qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); |
|
201 |
qdev_init_nofail(priv); |
|
202 |
s->priv = SYS_BUS_DEVICE(priv); |
|
203 |
sysbus_pass_irq(dev, s->priv); |
|
204 |
for (i = 0; i < 32; i++) { |
|
205 |
s->cpuic[i] = qdev_get_gpio_in(priv, i); |
|
206 |
} |
|
207 |
/* ??? IRQ routing is hardcoded to "normal" mode. */ |
|
208 |
for (n = 0; n < 4; n++) { |
|
209 |
gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000, |
|
210 |
s->cpuic[10 + n]); |
|
211 |
for (i = 0; i < 64; i++) { |
|
212 |
s->rvic[n][i] = qdev_get_gpio_in(gic, i); |
|
213 |
} |
|
214 |
} |
|
215 |
qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64); |
|
216 |
sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0)); |
|
217 |
return 0; |
|
218 |
} |
|
219 |
|
|
220 |
static Property mpcore_rirq_properties[] = { |
|
221 |
DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), |
|
222 |
DEFINE_PROP_END_OF_LIST(), |
|
223 |
}; |
|
224 |
|
|
225 |
static void mpcore_rirq_class_init(ObjectClass *klass, void *data) |
|
226 |
{ |
|
227 |
DeviceClass *dc = DEVICE_CLASS(klass); |
|
228 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
|
229 |
|
|
230 |
k->init = realview_mpcore_init; |
|
231 |
dc->props = mpcore_rirq_properties; |
|
232 |
} |
|
233 |
|
|
234 |
static const TypeInfo mpcore_rirq_info = { |
|
235 |
.name = "realview_mpcore", |
|
236 |
.parent = TYPE_SYS_BUS_DEVICE, |
|
237 |
.instance_size = sizeof(mpcore_rirq_state), |
|
238 |
.class_init = mpcore_rirq_class_init, |
|
239 |
}; |
|
240 |
|
|
241 |
static Property mpcore_priv_properties[] = { |
|
242 |
DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), |
|
243 |
/* The ARM11 MPCORE TRM says the on-chip controller may have |
|
244 |
* anything from 0 to 224 external interrupt IRQ lines (with another |
|
245 |
* 32 internal). We default to 32+32, which is the number provided by |
|
246 |
* the ARM11 MPCore test chip in the Realview Versatile Express |
|
247 |
* coretile. Other boards may differ and should set this property |
|
248 |
* appropriately. Some Linux kernels may not boot if the hardware |
|
249 |
* has more IRQ lines than the kernel expects. |
|
250 |
*/ |
|
251 |
DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), |
|
252 |
DEFINE_PROP_END_OF_LIST(), |
|
253 |
}; |
|
254 |
|
|
255 |
static void mpcore_priv_class_init(ObjectClass *klass, void *data) |
|
256 |
{ |
|
257 |
DeviceClass *dc = DEVICE_CLASS(klass); |
|
258 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
|
259 |
|
|
260 |
k->init = mpcore_priv_init; |
|
261 |
dc->props = mpcore_priv_properties; |
|
262 |
} |
|
263 |
|
|
264 |
static const TypeInfo mpcore_priv_info = { |
|
265 |
.name = "arm11mpcore_priv", |
|
266 |
.parent = TYPE_SYS_BUS_DEVICE, |
|
267 |
.instance_size = sizeof(ARM11MPCorePriveState), |
|
268 |
.class_init = mpcore_priv_class_init, |
|
269 |
}; |
|
270 |
|
|
271 |
static void arm11mpcore_register_types(void) |
|
272 |
{ |
|
273 |
type_register_static(&mpcore_rirq_info); |
|
274 |
type_register_static(&mpcore_priv_info); |
|
275 |
} |
|
276 |
|
|
277 |
type_init(arm11mpcore_register_types) |
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