Revision 04762841 hw/acpi.c
b/hw/acpi.c | ||
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*/ |
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#include "hw.h" |
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#include "pc.h" |
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#include "apm.h" |
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#include "pm_smbus.h" |
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#include "pci.h" |
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#include "qemu-timer.h" |
... | ... | |
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uint16_t pmsts; |
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uint16_t pmen; |
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uint16_t pmcntrl; |
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uint8_t apmc; |
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uint8_t apms; |
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APMState apm; |
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QEMUTimer *tmr_timer; |
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int64_t tmr_overflow_time; |
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... | ... | |
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return val; |
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} |
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static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
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static void apm_ctrl_changed(uint32_t val, void *arg)
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 1; |
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#ifdef DEBUG |
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printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val); |
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#endif |
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if (addr == 0) { |
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s->apmc = val; |
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/* ACPI specs 3.0, 4.7.2.5 */ |
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if (val == ACPI_ENABLE) { |
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s->pmcntrl |= SCI_EN; |
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} else if (val == ACPI_DISABLE) { |
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s->pmcntrl &= ~SCI_EN; |
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} |
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PIIX4PMState *s = arg; |
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if (s->dev.config[0x5b] & (1 << 1)) { |
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if (s->smi_irq) { |
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qemu_irq_raise(s->smi_irq); |
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} |
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} |
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} else { |
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s->apms = val; |
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/* ACPI specs 3.0, 4.7.2.5 */ |
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if (val == ACPI_ENABLE) { |
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s->pmcntrl |= SCI_EN; |
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} else if (val == ACPI_DISABLE) { |
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s->pmcntrl &= ~SCI_EN; |
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} |
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} |
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static uint32_t pm_smi_readb(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 1; |
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if (addr == 0) { |
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val = s->apmc; |
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} else { |
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val = s->apms; |
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if (s->dev.config[0x5b] & (1 << 1)) { |
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if (s->smi_irq) { |
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qemu_irq_raise(s->smi_irq); |
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} |
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} |
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#ifdef DEBUG |
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printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val); |
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#endif |
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return val; |
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} |
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
... | ... | |
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VMSTATE_UINT16(pmsts, PIIX4PMState), |
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VMSTATE_UINT16(pmen, PIIX4PMState), |
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VMSTATE_UINT16(pmcntrl, PIIX4PMState), |
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VMSTATE_UINT8(apmc, PIIX4PMState), |
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VMSTATE_UINT8(apms, PIIX4PMState), |
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VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState), |
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VMSTATE_TIMER(tmr_timer, PIIX4PMState), |
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VMSTATE_INT64(tmr_overflow_time, PIIX4PMState), |
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VMSTATE_END_OF_LIST() |
... | ... | |
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pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
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register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
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register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
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/* APM */
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apm_init(&s->apm, apm_ctrl_changed, s);
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register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
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