/ - Diff - qemu - Greek Research and Technology Network's projects

Revision 0487d6a8

     #if defined (TARGET_PPC64)
     typedef uint64_t ppc_gpr_t;
     #define TARGET_LONG_BITS 64
     #define TARGET_GPR_BITS  64
     #define REGX "%016" PRIx64
     #elif defined(TARGET_E500)
     /* We can safely use PowerPC SPE extension when compiling PowerPC 64 */
     #define TARGET_PPCSPE
     #elif defined(TARGET_PPCSPE)
     /* GPR are 64 bits: used by vector extension */
     typedef uint64_t ppc_gpr_t;
     #define TARGET_LONG_BITS 32
     #define TARGET_GPR_BITS  64
     #define REGX "%08" PRIx32
     #else
     typedef uint32_t ppc_gpr_t;
     #define TARGET_LONG_BITS 32
     #define TARGET_GPR_BITS  32
     #define REGX "%08" PRIx32
     #endif
-...
         /* ld/st with reservation instructions         */
         /* cache control instructions                  */
         /* spr/msr access instructions                 */
         PPC_INSNS_BASE  = 0x00000001,
         PPC_INSNS_BASE  = 0x0000000000000001ULL,
     #define PPC_INTEGER PPC_INSNS_BASE
     #define PPC_FLOW    PPC_INSNS_BASE
     #define PPC_MEM     PPC_INSNS_BASE
-...
     #define PPC_CACHE   PPC_INSNS_BASE
     #define PPC_MISC    PPC_INSNS_BASE
         /* floating point operations instructions      */
         PPC_FLOAT       = 0x00000002,
         PPC_FLOAT       = 0x0000000000000002ULL,
         /* more floating point operations instructions */
         PPC_FLOAT_EXT   = 0x00000004,
         PPC_FLOAT_EXT   = 0x0000000000000004ULL,
         /* external control instructions               */
         PPC_EXTERN      = 0x00000008,
         PPC_EXTERN      = 0x0000000000000008ULL,
         /* segment register access instructions        */
         PPC_SEGMENT     = 0x00000010,
         PPC_SEGMENT     = 0x0000000000000010ULL,
         /* Optional cache control instructions         */
         PPC_CACHE_OPT   = 0x00000020,
         PPC_CACHE_OPT   = 0x0000000000000020ULL,
         /* Optional floating point op instructions     */
         PPC_FLOAT_OPT   = 0x00000040,
         PPC_FLOAT_OPT   = 0x0000000000000040ULL,
         /* Optional memory control instructions        */
         PPC_MEM_TLBIA   = 0x00000080,
         PPC_MEM_TLBIE   = 0x00000100,
         PPC_MEM_TLBSYNC = 0x00000200,
         PPC_MEM_TLBIA   = 0x0000000000000080ULL,
         PPC_MEM_TLBIE   = 0x0000000000000100ULL,
         PPC_MEM_TLBSYNC = 0x0000000000000200ULL,
         /* eieio & sync                                */
         PPC_MEM_SYNC    = 0x00000400,
         PPC_MEM_SYNC    = 0x0000000000000400ULL,
         /* PowerPC 6xx TLB management instructions     */
         PPC_6xx_TLB     = 0x00000800,
         PPC_6xx_TLB     = 0x0000000000000800ULL,
         /* Altivec support                             */
         PPC_ALTIVEC     = 0x00001000,
         PPC_ALTIVEC     = 0x0000000000001000ULL,
         /* Time base support                           */
         PPC_TB          = 0x00002000,
         PPC_TB          = 0x0000000000002000ULL,
         /* Embedded PowerPC dedicated instructions     */
         PPC_EMB_COMMON  = 0x00004000,
         PPC_EMB_COMMON  = 0x0000000000004000ULL,
         /* PowerPC 40x exception model                 */
         PPC_40x_EXCP    = 0x00008000,
         PPC_40x_EXCP    = 0x0000000000008000ULL,
         /* PowerPC 40x specific instructions           */
         PPC_40x_SPEC    = 0x00010000,
         PPC_40x_SPEC    = 0x0000000000010000ULL,
         /* PowerPC 405 Mac instructions                */
         PPC_405_MAC     = 0x00020000,
         PPC_405_MAC     = 0x0000000000020000ULL,
         /* PowerPC 440 specific instructions           */
         PPC_440_SPEC    = 0x00040000,
         PPC_440_SPEC    = 0x0000000000040000ULL,
         /* Specific extensions */
         /* Power-to-PowerPC bridge (601)               */
         PPC_POWER_BR    = 0x00080000,
         PPC_POWER_BR    = 0x0000000000080000ULL,
         /* PowerPC 602 specific */
         PPC_602_SPEC    = 0x00100000,
         PPC_602_SPEC    = 0x0000000000100000ULL,
         /* Deprecated instructions                     */
         /* Original POWER instruction set              */
         PPC_POWER       = 0x00200000,
         PPC_POWER       = 0x0000000000200000ULL,
         /* POWER2 instruction set extension            */
         PPC_POWER2      = 0x00400000,
         PPC_POWER2      = 0x0000000000400000ULL,
         /* Power RTC support */
         PPC_POWER_RTC   = 0x00800000,
         PPC_POWER_RTC   = 0x0000000000800000ULL,
         /* 64 bits PowerPC instructions                */
         /* 64 bits PowerPC instruction set             */
         PPC_64B         = 0x01000000,
         PPC_64B         = 0x0000000001000000ULL,
         /* 64 bits hypervisor extensions               */
         PPC_64H         = 0x02000000,
         PPC_64H         = 0x0000000002000000ULL,
         /* 64 bits PowerPC "bridge" features           */
         PPC_64_BRIDGE   = 0x04000000,
         PPC_64_BRIDGE   = 0x0000000004000000ULL,
         /* BookE (embedded) PowerPC specification      */
         PPC_BOOKE       = 0x08000000,
         PPC_BOOKE       = 0x0000000008000000ULL,
         /* eieio */
         PPC_MEM_EIEIO   = 0x10000000,
         PPC_MEM_EIEIO   = 0x0000000010000000ULL,
         /* e500 vector instructions */
         PPC_E500_VECTOR = 0x20000000,
         PPC_E500_VECTOR = 0x0000000020000000ULL,
         /* PowerPC 4xx dedicated instructions     */
         PPC_4xx_COMMON  = 0x40000000,
         PPC_4xx_COMMON  = 0x0000000040000000ULL,
         /* PowerPC 2.03 specification extensions */
         PPC_203         = 0x80000000,
         PPC_203         = 0x0000000080000000ULL,
         /* PowerPC 2.03 SPE extension */
         PPC_SPE         = 0x0000000100000000ULL,
         /* PowerPC 2.03 SPE floating-point extension */
         PPC_SPEFPU      = 0x0000000200000000ULL,
     };
     /* CPU run-time flags (MMU and exception model) */
-...
         /* First are the most commonly used resources
          * during translated code execution
          */
     #if TARGET_LONG_BITS > HOST_LONG_BITS
     #if TARGET_GPR_BITS > HOST_LONG_BITS
         /* temporary fixed-point registers
          * used to emulate 64 bits target on 32 bits hosts
          */
          */
         target_ulong t0, t1, t2;
     #endif
         ppc_avr_t t0_avr, t1_avr, t2_avr;
-...
         uint32_t vscr;
         /* SPE registers */
         ppc_gpr_t spe_acc;
         float_status spe_status;
         uint32_t spe_fscr;
         /* Internal devices resources */
-...
     #define EXCP_970_MAINT     0x1600 /* Maintenance exception                   */
     #define EXCP_970_THRM      0x1800 /* Thermal exception                       */
     #define EXCP_970_VPUA      0x1700 /* VPU assist exception                    */
     /* SPE related exceptions                                                    */
     #define EXCP_NO_SPE        0x0F20 /* SPE unavailable exception               */
     /* End of exception vectors area                                             */
     #define EXCP_PPC_MAX       0x4000
     /* Qemu exceptions: special cases we want to stop translation                */

     register unsigned long T2 asm(AREG3);
     #endif
     /* We may, sometime, need 64 bits registers on 32 bits target */
     #if defined(TARGET_PPC64) || (HOST_LONG_BITS == 64)
     #if defined(TARGET_PPC64) || defined(TARGET_PPCSPE) || (HOST_LONG_BITS == 64)
     #define T0_64 T0
     #define T1_64 T0
     #define T2_64 T0
     #define T1_64 T1
     #define T2_64 T2
     #else
     /* no registers can be used */
     #define T0_64 (env->t0)

     /* count leading zero */
     void OPPROTO op_cntlzw (void)
+    {
         int cnt;
         cnt = 0;
         if (!(T0 & 0xFFFF0000UL)) {
             cnt += 16;
             T0 <<= 16;
+        }
         if (!(T0 & 0xFF000000UL)) {
             cnt += 8;
             T0 <<= 8;
+        }
         if (!(T0 & 0xF0000000UL)) {
             cnt += 4;
             T0 <<= 4;
+        }
         if (!(T0 & 0xC0000000UL)) {
             cnt += 2;
             T0 <<= 2;
+        }
         if (!(T0 & 0x80000000UL)) {
             cnt++;
             T0 <<= 1;
+        }
         if (!(T0 & 0x80000000UL)) {
             cnt++;
+        }
         T0 = cnt;
         T0 = _do_cntlzw(T0);
         RETURN();
+    }
     #if defined(TARGET_PPC64)
     void OPPROTO op_cntlzd (void)
+    {
     #if HOST_LONG_BITS == 64
         int cnt;
         cnt = 0;
         if (!(T0 & 0xFFFFFFFF00000000ULL)) {
             cnt += 32;
             T0 <<= 32;
+        }
         if (!(T0 & 0xFFFF000000000000ULL)) {
             cnt += 16;
             T0 <<= 16;
+        }
         if (!(T0 & 0xFF00000000000000ULL)) {
             cnt += 8;
             T0 <<= 8;
+        }
         if (!(T0 & 0xF000000000000000ULL)) {
             cnt += 4;
             T0 <<= 4;
+        }
         if (!(T0 & 0xC000000000000000ULL)) {
             cnt += 2;
             T0 <<= 2;
+        }
         if (!(T0 & 0x8000000000000000ULL)) {
             cnt++;
             T0 <<= 1;
+        }
         if (!(T0 & 0x8000000000000000ULL)) {
             cnt++;
+        }
         T0 = cnt;
     #else
         uint32_t tmp;
         /* Make it easier on 32 bits host machines */
         if (!(T0 >> 32)) {
             tmp = T0;
             T0 = 32;
         } else {
             tmp = T0 >> 32;
             T0 = 0;
+        }
         if (!(tmp & 0xFFFF0000UL)) {
             T0 += 16;
             tmp <<= 16;
+        }
         if (!(tmp & 0xFF000000UL)) {
             T0 += 8;
             tmp <<= 8;
+        }
         if (!(tmp & 0xF0000000UL)) {
             T0 += 4;
             tmp <<= 4;
+        }
         if (!(tmp & 0xC0000000UL)) {
             T0 += 2;
             tmp <<= 2;
+        }
         if (!(tmp & 0x80000000UL)) {
             T0++;
             tmp <<= 1;
+        }
         if (!(tmp & 0x80000000UL)) {
             T0++;
+        }
     #endif
         T0 = _do_cntlzd(T0);
         RETURN();
+    }
     #endif
-...
         store_booke_tsr(env, T0);
         RETURN();
+    }
     #endif /* !defined(CONFIG_USER_ONLY) */
     #if defined(TARGET_PPCSPE)
     /* SPE extension */
     void OPPROTO op_splatw_T1_64 (void)
+    {
         T1_64 = (T1_64 << 32) | (T1_64 & 0x00000000FFFFFFFFULL);
+    }
     void OPPROTO op_splatwi_T0_64 (void)
+    {
         uint64_t tmp = PARAM1;
         T0_64 = (tmp << 32) | tmp;
+    }
     void OPPROTO op_splatwi_T1_64 (void)
+    {
         uint64_t tmp = PARAM1;
         T1_64 = (tmp << 32) | tmp;
+    }
     void OPPROTO op_extsh_T1_64 (void)
+    {
         T1_64 = (int32_t)((int16_t)T1_64);
         RETURN();
+    }
     void OPPROTO op_sli16_T1_64 (void)
+    {
         T1_64 = T1_64 << 16;
         RETURN();
+    }
     void OPPROTO op_sli32_T1_64 (void)
+    {
         T1_64 = T1_64 << 32;
         RETURN();
+    }
     void OPPROTO op_srli32_T1_64 (void)
+    {
         T1_64 = T1_64 >> 32;
         RETURN();
+    }
     void OPPROTO op_evsel (void)
+    {
         do_evsel();
         RETURN();
+    }
     void OPPROTO op_evaddw (void)
+    {
         do_evaddw();
         RETURN();
+    }
     void OPPROTO op_evsubfw (void)
+    {
         do_evsubfw();
         RETURN();
+    }
     void OPPROTO op_evneg (void)
+    {
         do_evneg();
         RETURN();
+    }
     void OPPROTO op_evabs (void)
+    {
         do_evabs();
         RETURN();
+    }
     void OPPROTO op_evextsh (void)
+    {
         T0_64 = ((uint64_t)((int32_t)(int16_t)(T0_64 >> 32)) << 32) |
             (uint64_t)((int32_t)(int16_t)T0_64);
         RETURN();
+    }
     void OPPROTO op_evextsb (void)
+    {
         T0_64 = ((uint64_t)((int32_t)(int8_t)(T0_64 >> 32)) << 32) |
             (uint64_t)((int32_t)(int8_t)T0_64);
         RETURN();
+    }
     void OPPROTO op_evcntlzw (void)
+    {
         do_evcntlzw();
         RETURN();
+    }
     void OPPROTO op_evrndw (void)
+    {
         do_evrndw();
         RETURN();
+    }
     void OPPROTO op_brinc (void)
+    {
         do_brinc();
         RETURN();
+    }
     void OPPROTO op_evcntlsw (void)
+    {
         do_evcntlsw();
         RETURN();
+    }
     void OPPROTO op_evand (void)
+    {
         T0_64 &= T1_64;
         RETURN();
+    }
     void OPPROTO op_evandc (void)
+    {
         T0_64 &= ~T1_64;
         RETURN();
+    }
     void OPPROTO op_evor (void)
+    {
         T0_64 |= T1_64;
         RETURN();
+    }
     void OPPROTO op_evxor (void)
+    {
         T0_64 ^= T1_64;
         RETURN();
+    }
     void OPPROTO op_eveqv (void)
+    {
         T0_64 = ~(T0_64 ^ T1_64);
         RETURN();
+    }
     void OPPROTO op_evnor (void)
+    {
         T0_64 = ~(T0_64 | T1_64);
         RETURN();
+    }
     void OPPROTO op_evorc (void)
+    {
         T0_64 |= ~T1_64;
         RETURN();
+    }
     void OPPROTO op_evnand (void)
+    {
         T0_64 = ~(T0_64 & T1_64);
         RETURN();
+    }
     void OPPROTO op_evsrws (void)
+    {
         do_evsrws();
         RETURN();
+    }
     void OPPROTO op_evsrwu (void)
+    {
         do_evsrwu();
         RETURN();
+    }
     void OPPROTO op_evslw (void)
+    {
         do_evslw();
         RETURN();
+    }
     void OPPROTO op_evrlw (void)
+    {
         do_evrlw();
         RETURN();
+    }
     void OPPROTO op_evmergelo (void)
+    {
         T0_64 = (T0_64 << 32) | (T1_64 & 0x00000000FFFFFFFFULL);
         RETURN();
+    }
     void OPPROTO op_evmergehi (void)
+    {
         T0_64 = (T0_64 & 0xFFFFFFFF00000000ULL) | (T1_64 >> 32);
         RETURN();
+    }
     void OPPROTO op_evmergelohi (void)
+    {
         T0_64 = (T0_64 << 32) | (T1_64 >> 32);
         RETURN();
+    }
     void OPPROTO op_evmergehilo (void)
+    {
         T0_64 = (T0_64 & 0xFFFFFFFF00000000ULL) | (T1_64 & 0x00000000FFFFFFFFULL);
         RETURN();
+    }
     void OPPROTO op_evcmpgts (void)
+    {
         do_evcmpgts();
         RETURN();
+    }
     void OPPROTO op_evcmpgtu (void)
+    {
         do_evcmpgtu();
         RETURN();
+    }
     void OPPROTO op_evcmplts (void)
+    {
         do_evcmplts();
         RETURN();
+    }
     void OPPROTO op_evcmpltu (void)
+    {
         do_evcmpltu();
         RETURN();
+    }
     void OPPROTO op_evcmpeq (void)
+    {
         do_evcmpeq();
         RETURN();
+    }
     void OPPROTO op_evfssub (void)
+    {
         do_evfssub();
         RETURN();
+    }
     void OPPROTO op_evfsadd (void)
+    {
         do_evfsadd();
         RETURN();
+    }
     void OPPROTO op_evfsnabs (void)
+    {
         do_evfsnabs();
         RETURN();
+    }
     void OPPROTO op_evfsabs (void)
+    {
         do_evfsabs();
         RETURN();
+    }
     void OPPROTO op_evfsneg (void)
+    {
         do_evfsneg();
         RETURN();
+    }
     void OPPROTO op_evfsdiv (void)
+    {
         do_evfsdiv();
         RETURN();
+    }
     void OPPROTO op_evfsmul (void)
+    {
         do_evfsmul();
         RETURN();
+    }
     void OPPROTO op_evfscmplt (void)
+    {
         do_evfscmplt();
         RETURN();
+    }
     void OPPROTO op_evfscmpgt (void)
+    {
         do_evfscmpgt();
         RETURN();
+    }
     void OPPROTO op_evfscmpeq (void)
+    {
         do_evfscmpeq();
         RETURN();
+    }
     void OPPROTO op_evfscfsi (void)
+    {
         do_evfscfsi();
         RETURN();
+    }
     void OPPROTO op_evfscfui (void)
+    {
         do_evfscfui();
         RETURN();
+    }
     void OPPROTO op_evfscfsf (void)
+    {
         do_evfscfsf();
         RETURN();
+    }
     void OPPROTO op_evfscfuf (void)
+    {
         do_evfscfuf();
         RETURN();
+    }
     void OPPROTO op_evfsctsi (void)
+    {
         do_evfsctsi();
         RETURN();
+    }
     void OPPROTO op_evfsctui (void)
+    {
         do_evfsctui();
         RETURN();
+    }
     void OPPROTO op_evfsctsf (void)
+    {
         do_evfsctsf();
         RETURN();
+    }
     void OPPROTO op_evfsctuf (void)
+    {
         do_evfsctuf();
         RETURN();
+    }
     void OPPROTO op_evfsctuiz (void)
+    {
         do_evfsctuiz();
         RETURN();
+    }
     void OPPROTO op_evfsctsiz (void)
+    {
         do_evfsctsiz();
         RETURN();
+    }
     void OPPROTO op_evfststlt (void)
+    {
         do_evfststlt();
         RETURN();
+    }
     void OPPROTO op_evfststgt (void)
+    {
         do_evfststgt();
         RETURN();
+    }
     void OPPROTO op_evfststeq (void)
+    {
         do_evfststeq();
         RETURN();
+    }
     void OPPROTO op_efssub (void)
+    {
         T0_64 = _do_efssub(T0_64, T1_64);
         RETURN();
+    }
     void OPPROTO op_efsadd (void)
+    {
         T0_64 = _do_efsadd(T0_64, T1_64);
         RETURN();
+    }
     void OPPROTO op_efsnabs (void)
+    {
         T0_64 = _do_efsnabs(T0_64);
         RETURN();
+    }
     void OPPROTO op_efsabs (void)
+    {
         T0_64 = _do_efsabs(T0_64);
         RETURN();
+    }
     void OPPROTO op_efsneg (void)
+    {
         T0_64 = _do_efsneg(T0_64);
         RETURN();
+    }
     void OPPROTO op_efsdiv (void)
+    {
         T0_64 = _do_efsdiv(T0_64, T1_64);
         RETURN();
+    }
     void OPPROTO op_efsmul (void)
+    {
         T0_64 = _do_efsmul(T0_64, T1_64);
         RETURN();
+    }
     void OPPROTO op_efscmplt (void)
+    {
         do_efscmplt();
         RETURN();
+    }
     void OPPROTO op_efscmpgt (void)
+    {
         do_efscmpgt();
         RETURN();
+    }
     void OPPROTO op_efscfd (void)
+    {
         do_efscfd();
         RETURN();
+    }
     void OPPROTO op_efscmpeq (void)
+    {
         do_efscmpeq();
         RETURN();
+    }
     void OPPROTO op_efscfsi (void)
+    {
         do_efscfsi();
         RETURN();
+    }
     void OPPROTO op_efscfui (void)
+    {
         do_efscfui();
         RETURN();
+    }
     void OPPROTO op_efscfsf (void)
+    {
         do_efscfsf();
         RETURN();
+    }
     void OPPROTO op_efscfuf (void)
+    {
         do_efscfuf();
         RETURN();
+    }
     void OPPROTO op_efsctsi (void)
+    {
         do_efsctsi();
         RETURN();
+    }
     void OPPROTO op_efsctui (void)
+    {
         do_efsctui();
         RETURN();
+    }
     void OPPROTO op_efsctsf (void)
+    {
         do_efsctsf();
         RETURN();
+    }
     void OPPROTO op_efsctuf (void)
+    {
         do_efsctuf();
         RETURN();
+    }
     void OPPROTO op_efsctsiz (void)
+    {
         do_efsctsiz();
         RETURN();
+    }
     void OPPROTO op_efsctuiz (void)
+    {
         do_efsctuiz();
         RETURN();
+    }
     void OPPROTO op_efststlt (void)
+    {
         T0 = _do_efststlt(T0_64, T1_64);
         RETURN();
+    }
     void OPPROTO op_efststgt (void)
+    {
         T0 = _do_efststgt(T0_64, T1_64);
         RETURN();
+    }
     void OPPROTO op_efststeq (void)
+    {
         T0 = _do_efststeq(T0_64, T1_64);
         RETURN();
+    }
     void OPPROTO op_efdsub (void)
+    {
         union {
             uint64_t u;
             float64 f;
         } u1, u2;
         u1.u = T0_64;
         u2.u = T1_64;
         u1.f = float64_sub(u1.f, u2.f, &env->spe_status);
         T0_64 = u1.u;
         RETURN();
+    }
     void OPPROTO op_efdadd (void)
+    {
         union {
             uint64_t u;
             float64 f;
         } u1, u2;
         u1.u = T0_64;
         u2.u = T1_64;
         u1.f = float64_add(u1.f, u2.f, &env->spe_status);
         T0_64 = u1.u;
         RETURN();
+    }
     void OPPROTO op_efdcfsid (void)
+    {
         do_efdcfsi();
         RETURN();
+    }
     void OPPROTO op_efdcfuid (void)
+    {
         do_efdcfui();
         RETURN();
+    }
     void OPPROTO op_efdnabs (void)
+    {
         T0_64 |= 0x8000000000000000ULL;
         RETURN();
+    }
     void OPPROTO op_efdabs (void)
+    {
         T0_64 &= ~0x8000000000000000ULL;
         RETURN();
+    }
     void OPPROTO op_efdneg (void)
+    {
         T0_64 ^= 0x8000000000000000ULL;
         RETURN();
+    }
     void OPPROTO op_efddiv (void)
+    {
         union {
             uint64_t u;
             float64 f;
         } u1, u2;
         u1.u = T0_64;
         u2.u = T1_64;
         u1.f = float64_div(u1.f, u2.f, &env->spe_status);
         T0_64 = u1.u;
         RETURN();
+    }
     void OPPROTO op_efdmul (void)
+    {
         union {
             uint64_t u;
             float64 f;
         } u1, u2;
         u1.u = T0_64;
         u2.u = T1_64;
         u1.f = float64_mul(u1.f, u2.f, &env->spe_status);
         T0_64 = u1.u;
         RETURN();
+    }
     void OPPROTO op_efdctsidz (void)
+    {
         do_efdctsiz();
         RETURN();
+    }
     void OPPROTO op_efdctuidz (void)
+    {
         do_efdctuiz();
         RETURN();
+    }
     void OPPROTO op_efdcmplt (void)
+    {
         do_efdcmplt();
         RETURN();
+    }
     void OPPROTO op_efdcmpgt (void)
+    {
         do_efdcmpgt();
         RETURN();
+    }
     void OPPROTO op_efdcfs (void)
+    {
         do_efdcfs();
         RETURN();
+    }
     void OPPROTO op_efdcmpeq (void)
+    {
         do_efdcmpeq();
         RETURN();
+    }
     void OPPROTO op_efdcfsi (void)
+    {
         do_efdcfsi();
         RETURN();
+    }
     void OPPROTO op_efdcfui (void)
+    {
         do_efdcfui();
         RETURN();
+    }
     void OPPROTO op_efdcfsf (void)
+    {
         do_efdcfsf();
         RETURN();
+    }
     void OPPROTO op_efdcfuf (void)
+    {
         do_efdcfuf();
         RETURN();
+    }
     void OPPROTO op_efdctsi (void)
+    {
         do_efdctsi();
         RETURN();
+    }
     void OPPROTO op_efdctui (void)
+    {
         do_efdctui();
         RETURN();
+    }
     void OPPROTO op_efdctsf (void)
+    {
         do_efdctsf();
         RETURN();
+    }
     void OPPROTO op_efdctuf (void)
+    {
         do_efdctuf();
         RETURN();
+    }
     void OPPROTO op_efdctuiz (void)
+    {
         do_efdctuiz();
         RETURN();
+    }
     void OPPROTO op_efdctsiz (void)
+    {
         do_efdctsiz();
         RETURN();
+    }
     void OPPROTO op_efdtstlt (void)
+    {
         T0 = _do_efdtstlt(T0_64, T1_64);
         RETURN();
+    }
     void OPPROTO op_efdtstgt (void)
+    {
         T0 = _do_efdtstgt(T0_64, T1_64);
         RETURN();
+    }
     void OPPROTO op_efdtsteq (void)
+    {
         T0 = _do_efdtsteq(T0_64, T1_64);
         RETURN();
+    }
     #endif /* defined(TARGET_PPCSPE) */

      */
     #include "exec.h"
     #include "op_helper.h"
     #define MEMSUFFIX _raw
     #include "op_helper.h"
     #include "op_helper_mem.h"
     #if !defined(CONFIG_USER_ONLY)
     #define MEMSUFFIX _user
     #include "op_helper.h"
     #include "op_helper_mem.h"
     #define MEMSUFFIX _kernel
     #include "op_helper.h"
     #include "op_helper_mem.h"
     #endif
-...
         mul64(plow, phigh, T0, T1);
+    }
     static void imul64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
     static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
+    {
         int sa, sb;
         sa = (a < 0);
-...
         T0 = i;
+    }
     #if defined(TARGET_PPCSPE)
     /* SPE extension helpers */
     /* Use a table to make this quicker */
     static uint8_t hbrev[16] = {
 x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
 x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
     };
     static inline uint8_t byte_reverse (uint8_t val)
+    {
         return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
+    }
     static inline uint32_t word_reverse (uint32_t val)
+    {
         return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
             (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
+    }
     #define MASKBITS 16 // Random value - to be fixed
     void do_brinc (void)
+    {
         uint32_t a, b, d, mask;
         mask = (uint32_t)(-1UL) >> MASKBITS;
         b = T1_64 & mask;
         a = T0_64 & mask;
         d = word_reverse(1 + word_reverse(a | ~mask));
         T0_64 = (T0_64 & ~mask) | (d & mask);
+    }
     #define DO_SPE_OP2(name)                                                      \
     void do_ev##name (void)                                                       \
     {                                                                             \
         T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) |         \
             (uint64_t)_do_e##name(T0_64, T1_64);                                  \
+    }
     #define DO_SPE_OP1(name)                                                      \
     void do_ev##name (void)                                                       \
     {                                                                             \
         T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) |                      \
             (uint64_t)_do_e##name(T0_64);                                         \
+    }
     /* Fixed-point vector arithmetic */
     static inline uint32_t _do_eabs (uint32_t val)
+    {
         if (val != 0x80000000)
             val &= ~0x80000000;
         return val;
+    }
     static inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
+    {
         return op1 + op2;
+    }
     static inline int _do_ecntlsw (uint32_t val)
+    {
         if (val & 0x80000000)
             return _do_cntlzw(~val);
         else
             return _do_cntlzw(val);
+    }
     static inline int _do_ecntlzw (uint32_t val)
+    {
         return _do_cntlzw(val);
+    }
     static inline uint32_t _do_eneg (uint32_t val)
+    {
         if (val != 0x80000000)
             val ^= 0x80000000;
         return val;
+    }
     static inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
+    {
         return rotl32(op1, op2);
+    }
     static inline uint32_t _do_erndw (uint32_t val)
+    {
         return (val + 0x000080000000) & 0xFFFF0000;
+    }
     static inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
+    {
         /* No error here: 6 bits are used */
         return op1 << (op2 & 0x3F);
+    }
     static inline int32_t _do_esrws (int32_t op1, uint32_t op2)
+    {
         /* No error here: 6 bits are used */
         return op1 >> (op2 & 0x3F);
+    }
     static inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
+    {
         /* No error here: 6 bits are used */
         return op1 >> (op2 & 0x3F);
+    }
     static inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
+    {
         return op2 - op1;
+    }
     /* evabs */
     DO_SPE_OP1(abs);
     /* evaddw */
     DO_SPE_OP2(addw);
     /* evcntlsw */
     DO_SPE_OP1(cntlsw);
     /* evcntlzw */
     DO_SPE_OP1(cntlzw);
     /* evneg */
     DO_SPE_OP1(neg);
     /* evrlw */
     DO_SPE_OP2(rlw);
     /* evrnd */
     DO_SPE_OP1(rndw);
     /* evslw */
     DO_SPE_OP2(slw);
     /* evsrws */
     DO_SPE_OP2(srws);
     /* evsrwu */
     DO_SPE_OP2(srwu);
     /* evsubfw */
     DO_SPE_OP2(subfw);
     /* evsel is a little bit more complicated... */
     static inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
+    {
         if (n)
             return op1;
         else
             return op2;
+    }
     void do_evsel (void)
+    {
         T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
             (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
+    }
     /* Fixed-point vector comparisons */
     #define DO_SPE_CMP(name)                                                      \
     void do_ev##name (void)                                                       \
     {                                                                             \
         T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32,                   \
                                                    T1_64 >> 32) << 32,            \
                              _do_e##name(T0_64, T1_64));                          \
+    }
     static inline uint32_t _do_evcmp_merge (int t0, int t1)
+    {
         return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
+    }
     static inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
+    {
         return op1 == op2 ? 1 : 0;
+    }
     static inline int _do_ecmpgts (int32_t op1, int32_t op2)
+    {
         return op1 > op2 ? 1 : 0;
+    }
     static inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
+    {
         return op1 > op2 ? 1 : 0;
+    }
     static inline int _do_ecmplts (int32_t op1, int32_t op2)
+    {
         return op1 < op2 ? 1 : 0;
+    }
     static inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
+    {
         return op1 < op2 ? 1 : 0;
+    }
     /* evcmpeq */
     DO_SPE_CMP(cmpeq);
     /* evcmpgts */
     DO_SPE_CMP(cmpgts);
     /* evcmpgtu */
     DO_SPE_CMP(cmpgtu);
     /* evcmplts */
     DO_SPE_CMP(cmplts);
     /* evcmpltu */
     DO_SPE_CMP(cmpltu);
     /* Single precision floating-point conversions from/to integer */
     static inline uint32_t _do_efscfsi (int32_t val)
+    {
         union {
             uint32_t u;
             float32 f;
         } u;
         u.f = int32_to_float32(val, &env->spe_status);
         return u.u;
+    }
     static inline uint32_t _do_efscfui (uint32_t val)
+    {
         union {
             uint32_t u;
             float32 f;
         } u;
         u.f = uint32_to_float32(val, &env->spe_status);
         return u.u;
+    }
     static inline int32_t _do_efsctsi (uint32_t val)
+    {
         union {
             int32_t u;
             float32 f;
         } u;
         u.u = val;
         /* NaN are not treated the same way IEEE 754 does */
         if (unlikely(isnan(u.f)))
             return 0;
         return float32_to_int32(u.f, &env->spe_status);
+    }
     static inline uint32_t _do_efsctui (uint32_t val)
+    {
         union {
             int32_t u;
             float32 f;
         } u;
         u.u = val;
         /* NaN are not treated the same way IEEE 754 does */
         if (unlikely(isnan(u.f)))
             return 0;
         return float32_to_uint32(u.f, &env->spe_status);
+    }
     static inline int32_t _do_efsctsiz (uint32_t val)
+    {
         union {
             int32_t u;
             float32 f;
         } u;
         u.u = val;
         /* NaN are not treated the same way IEEE 754 does */
         if (unlikely(isnan(u.f)))
             return 0;
         return float32_to_int32_round_to_zero(u.f, &env->spe_status);
+    }
     static inline uint32_t _do_efsctuiz (uint32_t val)
+    {
         union {
             int32_t u;
             float32 f;
         } u;
         u.u = val;
         /* NaN are not treated the same way IEEE 754 does */
         if (unlikely(isnan(u.f)))
             return 0;
         return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
+    }
     void do_efscfsi (void)
+    {
         T0_64 = _do_efscfsi(T0_64);
+    }
     void do_efscfui (void)
+    {
         T0_64 = _do_efscfui(T0_64);
+    }
     void do_efsctsi (void)
+    {
         T0_64 = _do_efsctsi(T0_64);
+    }
     void do_efsctui (void)
+    {
         T0_64 = _do_efsctui(T0_64);
+    }
     void do_efsctsiz (void)
+    {
         T0_64 = _do_efsctsiz(T0_64);
+    }
     void do_efsctuiz (void)
+    {
         T0_64 = _do_efsctuiz(T0_64);
+    }
     /* Single precision floating-point conversion to/from fractional */
     static inline uint32_t _do_efscfsf (uint32_t val)
+    {
         union {
             uint32_t u;
             float32 f;
         } u;
         float32 tmp;
         u.f = int32_to_float32(val, &env->spe_status);
         tmp = int64_to_float32(1ULL << 32, &env->spe_status);
         u.f = float32_div(u.f, tmp, &env->spe_status);
         return u.u;
+    }
     static inline uint32_t _do_efscfuf (uint32_t val)
+    {
         union {
             uint32_t u;
             float32 f;
         } u;
         float32 tmp;
         u.f = uint32_to_float32(val, &env->spe_status);
         tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
         u.f = float32_div(u.f, tmp, &env->spe_status);
         return u.u;
+    }
     static inline int32_t _do_efsctsf (uint32_t val)
+    {
         union {
             int32_t u;
             float32 f;
         } u;
         float32 tmp;
         u.u = val;
         /* NaN are not treated the same way IEEE 754 does */
         if (unlikely(isnan(u.f)))
             return 0;
         tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
         u.f = float32_mul(u.f, tmp, &env->spe_status);
         return float32_to_int32(u.f, &env->spe_status);
+    }
     static inline uint32_t _do_efsctuf (uint32_t val)
+    {
         union {
             int32_t u;
             float32 f;
         } u;
         float32 tmp;
         u.u = val;
         /* NaN are not treated the same way IEEE 754 does */
         if (unlikely(isnan(u.f)))
             return 0;
         tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
         u.f = float32_mul(u.f, tmp, &env->spe_status);
         return float32_to_uint32(u.f, &env->spe_status);
+    }
     static inline int32_t _do_efsctsfz (uint32_t val)
+    {
         union {
             int32_t u;
             float32 f;
         } u;
         float32 tmp;
         u.u = val;
         /* NaN are not treated the same way IEEE 754 does */
         if (unlikely(isnan(u.f)))
             return 0;
         tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
         u.f = float32_mul(u.f, tmp, &env->spe_status);
         return float32_to_int32_round_to_zero(u.f, &env->spe_status);
+    }
     static inline uint32_t _do_efsctufz (uint32_t val)
+    {
         union {
             int32_t u;
             float32 f;
         } u;
         float32 tmp;
         u.u = val;
         /* NaN are not treated the same way IEEE 754 does */
         if (unlikely(isnan(u.f)))
             return 0;
         tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
         u.f = float32_mul(u.f, tmp, &env->spe_status);
         return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
+    }
     void do_efscfsf (void)
+    {
         T0_64 = _do_efscfsf(T0_64);
+    }
     void do_efscfuf (void)
+    {
         T0_64 = _do_efscfuf(T0_64);
+    }
     void do_efsctsf (void)
+    {
         T0_64 = _do_efsctsf(T0_64);
+    }

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Archipelago » qemu

Revision 0487d6a8