Revision 04f20795

b/hw/ppc405.h
1
/*
2
 * QEMU PowerPC 405 shared definitions
3
 * 
4
 * Copyright (c) 2007 Jocelyn Mayer
5
 * 
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24

  
25
#if !defined(PPC_405_H)
26
#define PPC_405_H
27

  
28
/* Bootinfo as set-up by u-boot */
29
typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
30
struct ppc4xx_bd_info_t {
31
    uint32_t bi_memstart;
32
    uint32_t bi_memsize;
33
    uint32_t bi_flashstart;
34
    uint32_t bi_flashsize;
35
    uint32_t bi_flashoffset; /* 0x10 */
36
    uint32_t bi_sramstart;
37
    uint32_t bi_sramsize;
38
    uint32_t bi_bootflags;
39
    uint32_t bi_ipaddr; /* 0x20 */
40
    uint8_t  bi_enetaddr[6];
41
    uint16_t bi_ethspeed;
42
    uint32_t bi_intfreq;
43
    uint32_t bi_busfreq; /* 0x30 */
44
    uint32_t bi_baudrate;
45
    uint8_t  bi_s_version[4];
46
    uint8_t  bi_r_version[32];
47
    uint32_t bi_procfreq;
48
    uint32_t bi_plb_busfreq;
49
    uint32_t bi_pci_busfreq;
50
    uint8_t  bi_pci_enetaddr[6];
51
    uint32_t bi_pci_enetaddr2[6];
52
    uint32_t bi_opbfreq;
53
    uint32_t bi_iic_fast[2];
54
};
55

  
56
/* PowerPC 405 core */
57
CPUState *ppc405_init (const unsigned char *cpu_model,
58
                       clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
59
                       uint32_t sysclk);
60
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd);
61

  
62
void ppc40x_core_reset (CPUState *env);
63
void ppc40x_chip_reset (CPUState *env);
64
void ppc40x_system_reset (CPUState *env);
65
/* */
66
typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
67
int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
68
                          uint32_t offset, uint32_t len,
69
                          CPUReadMemoryFunc **mem_read,
70
                          CPUWriteMemoryFunc **mem_write, void *opaque);
71
ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, uint32_t base);
72
/* PowerPC 4xx peripheral local bus arbitrer */
73
void ppc4xx_plb_init (CPUState *env);
74
/* PLB to OPB bridge */
75
void ppc4xx_pob_init (CPUState *env);
76
/* OPB arbitrer */
77
void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
78
/* PowerPC 4xx universal interrupt controller */
79
enum {
80
    PPCUIC_OUTPUT_INT = 0,
81
    PPCUIC_OUTPUT_CINT = 1,
82
    PPCUIC_OUTPUT_NB,
83
};
84
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
85
                       uint32_t dcr_base, int has_ssr, int has_vr);
86
/* SDRAM controller */
87
void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
88
                        target_ulong *ram_bases, target_ulong *ram_sizes,
89
                        int do_init);
90
/* Peripheral controller */
91
void ppc405_ebc_init (CPUState *env);
92
/* DMA controller */
93
void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
94
/* GPIO */
95
void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
96
/* Serial ports */
97
void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
98
                         uint32_t offset, qemu_irq irq,
99
                         CharDriverState *chr);
100
/* On Chip Memory */
101
void ppc405_ocm_init (CPUState *env, unsigned long offset);
102
/* I2C controller */
103
void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
104
/* PowerPC 405 microcontrollers */
105
CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4],
106
                         uint32_t sysclk, qemu_irq **picp,
107
                         ram_addr_t *offsetp, int do_init);
108
CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2],
109
                         uint32_t sysclk, qemu_irq **picp,
110
                         ram_addr_t *offsetp, int do_init);
111
/* IBM STBxxx microcontrollers */
112
CPUState *ppc_stb025_init (target_ulong ram_bases[2],
113
                           target_ulong ram_sizes[2],
114
                           uint32_t sysclk, qemu_irq **picp,
115
                           ram_addr_t *offsetp);
116

  
117
#endif /* !defined(PPC_405_H) */
b/hw/ppc405_uc.c
22 22
 * THE SOFTWARE.
23 23
 */
24 24
#include "vl.h"
25
#include "ppc405.h"
25 26

  
26 27
extern int loglevel;
27 28
extern FILE *logfile;
......
66 67
    return env;
67 68
}
68 69

  
70
ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd)
71
{
72
    ram_addr_t bdloc;
73
    int i, n;
74

  
75
    /* We put the bd structure at the top of memory */
76
    bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
77
    stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
78
    stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
79
    stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
80
    stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
81
    stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
82
    stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
83
    stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
84
    stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
85
    stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
86
    for (i = 0; i < 6; i++)
87
        stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
88
    stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
89
    stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
90
    stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
91
    stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
92
    for (i = 0; i < 4; i++)
93
        stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
94
    for (i = 0; i < 32; i++)
95
        stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
96
    stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
97
    stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
98
    for (i = 0; i < 6; i++)
99
        stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
100
    n = 0x6A;
101
    if (env->spr[SPR_PVR] == CPU_PPC_405EP) {
102
        for (i = 0; i < 6; i++)
103
            stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);
104
    }
105
    stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);
106
    n += 4;
107
    for (i = 0; i < 2; i++) {
108
        stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);
109
        n += 4;
110
    }
111

  
112
    return bdloc;
113
}
114

  
69 115
/*****************************************************************************/
70 116
/* Shared peripherals */
71 117

  
......
960 1006
    int i;
961 1007

  
962 1008
    for (i = 0; i < sdram->nbanks; i++) {
1009
#ifdef DEBUG_SDRAM
1010
        printf("%s: Unmap RAM area " ADDRX " " ADDRX "\n", __func__,
1011
               sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
1012
#endif
963 1013
        cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
964 1014
                                     sdram_size(sdram->bcr[i]),
965 1015
                                     IO_MEM_UNASSIGNED);
......
1141 1191
}
1142 1192

  
1143 1193
void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
1144
                        target_ulong *ram_bases, target_ulong *ram_sizes)
1194
                        target_ulong *ram_bases, target_ulong *ram_sizes,
1195
                        int do_init)
1145 1196
{
1146 1197
    ppc4xx_sdram_t *sdram;
1147 1198

  
......
1159 1210
                         sdram, &dcr_read_sdram, &dcr_write_sdram);
1160 1211
        ppc_dcr_register(env, SDRAM0_CFGDATA,
1161 1212
                         sdram, &dcr_read_sdram, &dcr_write_sdram);
1213
        if (do_init)
1214
            sdram_map_bcr(sdram);
1162 1215
    }
1163 1216
}
1164 1217

  
......
2079 2132
    /* XXX: TODO reset all internal peripherals */
2080 2133
    dbsr = env->spr[SPR_40x_DBSR];
2081 2134
    dbsr &= ~0x00000300;
2082
    dbsr |= 0x00000100;
2135
    dbsr |= 0x00000200;
2083 2136
    env->spr[SPR_40x_DBSR] = dbsr;
2084 2137
    cpu_loop_exit();
2085 2138
}
......
2124 2177
    PPC405CR_CPC0_SR     = 0x0BB,
2125 2178
};
2126 2179

  
2180
enum {
2181
    PPC405CR_CPU_CLK   = 0,
2182
    PPC405CR_TMR_CLK   = 1,
2183
    PPC405CR_PLB_CLK   = 2,
2184
    PPC405CR_SDRAM_CLK = 3,
2185
    PPC405CR_OPB_CLK   = 4,
2186
    PPC405CR_EXT_CLK   = 5,
2187
    PPC405CR_UART_CLK  = 6,
2188
    PPC405CR_CLK_NB    = 7,
2189
};
2190

  
2127 2191
typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
2128 2192
struct ppc405cr_cpc_t {
2129
    clk_setup_t clk_setup[7];
2193
    clk_setup_t clk_setup[PPC405CR_CLK_NB];
2130 2194
    uint32_t sysclk;
2131 2195
    uint32_t psr;
2132 2196
    uint32_t cr0;
......
2175 2239
    D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
2176 2240
    UART_clk = CPU_clk / D0;
2177 2241
    /* Setup CPU clocks */
2178
    clk_setup(&cpc->clk_setup[0], CPU_clk);
2242
    clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
2179 2243
    /* Setup time-base clock */
2180
    clk_setup(&cpc->clk_setup[1], TMR_clk);
2244
    clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
2181 2245
    /* Setup PLB clock */
2182
    clk_setup(&cpc->clk_setup[2], PLB_clk);
2246
    clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
2183 2247
    /* Setup SDRAM clock */
2184
    clk_setup(&cpc->clk_setup[3], SDRAM_clk);
2248
    clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
2185 2249
    /* Setup OPB clock */
2186
    clk_setup(&cpc->clk_setup[4], OPB_clk);
2250
    clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
2187 2251
    /* Setup external clock */
2188
    clk_setup(&cpc->clk_setup[5], EXT_clk);
2252
    clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
2189 2253
    /* Setup UART clock */
2190
    clk_setup(&cpc->clk_setup[6], UART_clk);
2254
    clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
2191 2255
}
2192 2256

  
2193 2257
static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
......
2357 2421

  
2358 2422
    cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2359 2423
    if (cpc != NULL) {
2360
        memcpy(cpc->clk_setup, clk_setup, 7 * sizeof(clk_setup_t));
2424
        memcpy(cpc->clk_setup, clk_setup,
2425
               PPC405CR_CLK_NB * sizeof(clk_setup_t));
2361 2426
        cpc->sysclk = sysclk;
2362 2427
        cpc->jtagid = 0x42051049;
2363 2428
        ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
......
2384 2449

  
2385 2450
CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4],
2386 2451
                         uint32_t sysclk, qemu_irq **picp,
2387
                         ram_addr_t *offsetp)
2452
                         ram_addr_t *offsetp, int do_init)
2388 2453
{
2389
    clk_setup_t clk_setup[7];
2454
    clk_setup_t clk_setup[PPC405CR_CLK_NB];
2390 2455
    qemu_irq dma_irqs[4];
2391 2456
    CPUState *env;
2392 2457
    ppc4xx_mmio_t *mmio;
......
2395 2460
    int i;
2396 2461

  
2397 2462
    memset(clk_setup, 0, sizeof(clk_setup));
2398
    env = ppc405_init("405cr", &clk_setup[0], &clk_setup[1], sysclk);
2463
    env = ppc405_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2464
                      &clk_setup[PPC405CR_TMR_CLK], sysclk);
2399 2465
    /* Memory mapped devices registers */
2400 2466
    mmio = ppc4xx_mmio_init(env, 0xEF600000);
2401 2467
    /* PLB arbitrer */
......
2413 2479
    pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2414 2480
    *picp = pic;
2415 2481
    /* SDRAM controller */
2416
    ppc405_sdram_init(env, pic[17], 1, ram_bases, ram_sizes);
2482
    ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
2417 2483
    offset = 0;
2418 2484
    for (i = 0; i < 4; i++)
2419 2485
        offset += ram_sizes[i];
2420 2486
    /* External bus controller */
2421 2487
    ppc405_ebc_init(env);
2422 2488
    /* DMA controller */
2423
    dma_irqs[0] = pic[5];
2424
    dma_irqs[1] = pic[6];
2425
    dma_irqs[2] = pic[7];
2426
    dma_irqs[3] = pic[8];
2489
    dma_irqs[0] = pic[26];
2490
    dma_irqs[1] = pic[25];
2491
    dma_irqs[2] = pic[24];
2492
    dma_irqs[3] = pic[23];
2427 2493
    ppc405_dma_init(env, dma_irqs);
2428 2494
    /* Serial ports */
2429 2495
    if (serial_hds[0] != NULL) {
2430
        ppc405_serial_init(env, mmio, 0x400, pic[0], serial_hds[0]);
2496
        ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
2431 2497
    }
2432 2498
    if (serial_hds[1] != NULL) {
2433
        ppc405_serial_init(env, mmio, 0x300, pic[1], serial_hds[1]);
2499
        ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
2434 2500
    }
2435 2501
    /* IIC controller */
2436 2502
    ppc405_i2c_init(env, mmio, 0x500);
......
2457 2523
    PPC405EP_CPC0_PCI    = 0x0F9,
2458 2524
};
2459 2525

  
2526
enum {
2527
    PPC405EP_CPU_CLK   = 0,
2528
    PPC405EP_PLB_CLK   = 1,
2529
    PPC405EP_OPB_CLK   = 2,
2530
    PPC405EP_EBC_CLK   = 3,
2531
    PPC405EP_MAL_CLK   = 4,
2532
    PPC405EP_PCI_CLK   = 5,
2533
    PPC405EP_UART0_CLK = 6,
2534
    PPC405EP_UART1_CLK = 7,
2535
    PPC405EP_CLK_NB    = 8,
2536
};
2537

  
2460 2538
typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2461 2539
struct ppc405ep_cpc_t {
2462 2540
    uint32_t sysclk;
2463
    clk_setup_t clk_setup[8];
2541
    clk_setup_t clk_setup[PPC405EP_CLK_NB];
2464 2542
    uint32_t boot;
2465 2543
    uint32_t epctl;
2466 2544
    uint32_t pllmr[2];
......
2548 2626
           UART0_clk, UART1_clk);
2549 2627
#endif
2550 2628
    /* Setup CPU clocks */
2551
    clk_setup(&cpc->clk_setup[0], CPU_clk);
2629
    clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2552 2630
    /* Setup PLB clock */
2553
    clk_setup(&cpc->clk_setup[1], PLB_clk);
2631
    clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2554 2632
    /* Setup OPB clock */
2555
    clk_setup(&cpc->clk_setup[2], OPB_clk);
2633
    clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2556 2634
    /* Setup external clock */
2557
    clk_setup(&cpc->clk_setup[3], EBC_clk);
2635
    clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2558 2636
    /* Setup MAL clock */
2559
    clk_setup(&cpc->clk_setup[4], MAL_clk);
2637
    clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2560 2638
    /* Setup PCI clock */
2561
    clk_setup(&cpc->clk_setup[5], PCI_clk);
2639
    clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2562 2640
    /* Setup UART0 clock */
2563
    clk_setup(&cpc->clk_setup[6], UART0_clk);
2641
    clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2564 2642
    /* Setup UART1 clock */
2565
    clk_setup(&cpc->clk_setup[7], UART0_clk);
2643
    clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2566 2644
}
2567 2645

  
2568 2646
static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
......
2664 2742

  
2665 2743
    cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
2666 2744
    if (cpc != NULL) {
2667
        memcpy(cpc->clk_setup, clk_setup, 7 * sizeof(clk_setup_t));
2745
        memcpy(cpc->clk_setup, clk_setup,
2746
               PPC405EP_CLK_NB * sizeof(clk_setup_t));
2668 2747
        cpc->jtagid = 0x20267049;
2669 2748
        cpc->sysclk = sysclk;
2670 2749
        ppc405ep_cpc_reset(cpc);
......
2690 2769

  
2691 2770
CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2],
2692 2771
                         uint32_t sysclk, qemu_irq **picp,
2693
                         ram_addr_t *offsetp)
2772
                         ram_addr_t *offsetp, int do_init)
2694 2773
{
2695
    clk_setup_t clk_setup[8];
2774
    clk_setup_t clk_setup[PPC405EP_CLK_NB];
2696 2775
    qemu_irq dma_irqs[4];
2697 2776
    CPUState *env;
2698 2777
    ppc4xx_mmio_t *mmio;
......
2702 2781

  
2703 2782
    memset(clk_setup, 0, sizeof(clk_setup));
2704 2783
    /* init CPUs */
2705
    env = ppc405_init("405ep", &clk_setup[0], &clk_setup[1], sysclk);
2784
    env = ppc405_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2785
                      &clk_setup[PPC405EP_PLB_CLK], sysclk);
2706 2786
    /* Internal devices init */
2707 2787
    /* Memory mapped devices registers */
2708 2788
    mmio = ppc4xx_mmio_init(env, 0xEF600000);
......
2721 2801
    pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2722 2802
    *picp = pic;
2723 2803
    /* SDRAM controller */
2724
    ppc405_sdram_init(env, pic[17], 2, ram_bases, ram_sizes);
2804
    ppc405_sdram_init(env, pic[14], 2, ram_bases, ram_sizes, do_init);
2725 2805
    offset = 0;
2726 2806
    for (i = 0; i < 2; i++)
2727 2807
        offset += ram_sizes[i];
2728 2808
    /* External bus controller */
2729 2809
    ppc405_ebc_init(env);
2730 2810
    /* DMA controller */
2731
    dma_irqs[0] = pic[5];
2732
    dma_irqs[1] = pic[6];
2733
    dma_irqs[2] = pic[7];
2734
    dma_irqs[3] = pic[8];
2811
    dma_irqs[0] = pic[26];
2812
    dma_irqs[1] = pic[25];
2813
    dma_irqs[2] = pic[24];
2814
    dma_irqs[3] = pic[23];
2735 2815
    ppc405_dma_init(env, dma_irqs);
2736 2816
    /* IIC controller */
2737 2817
    ppc405_i2c_init(env, mmio, 0x500);
......
2739 2819
    ppc405_gpio_init(env, mmio, 0x700);
2740 2820
    /* Serial ports */
2741 2821
    if (serial_hds[0] != NULL) {
2742
        ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
2822
        ppc405_serial_init(env, mmio, 0x300, pic[31], serial_hds[0]);
2743 2823
    }
2744 2824
    if (serial_hds[1] != NULL) {
2745
        ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
2825
        ppc405_serial_init(env, mmio, 0x400, pic[30], serial_hds[1]);
2746 2826
    }
2747 2827
    /* OCM */
2748 2828
    ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]);
b/target-ppc/translate_init.c
53 53
/* Generic callbacks:
54 54
 * do nothing but store/retrieve spr value
55 55
 */
56
#ifdef PPC_DUMP_SPR_ACCESSES
56 57
static void spr_read_generic (void *opaque, int sprn)
57 58
{
58
    gen_op_load_spr(sprn);
59
    gen_op_load_dump_spr(sprn);
59 60
}
60 61

  
61 62
static void spr_write_generic (void *opaque, int sprn)
62 63
{
63
    gen_op_store_spr(sprn);
64
    gen_op_store_dump_spr(sprn);
64 65
}
65

  
66
static void spr_read_dump (void *opaque, int sprn)
66
#else
67
static void spr_read_generic (void *opaque, int sprn)
67 68
{
68
    gen_op_load_dump_spr(sprn);
69
    gen_op_load_spr(sprn);
69 70
}
70 71

  
71
static void spr_write_dump (void *opaque, int sprn)
72
static void spr_write_generic (void *opaque, int sprn)
72 73
{
73
    gen_op_store_dump_spr(sprn);
74
    gen_op_store_spr(sprn);
74 75
}
76
#endif
75 77

  
76 78
#if !defined(CONFIG_USER_ONLY)
77 79
static void spr_write_clear (void *opaque, int sprn)
......
1730 1732
                 0x00000000);
1731 1733
    spr_register(env, SPR_SPRG4, "SPRG4",
1732 1734
                 SPR_NOACCESS, SPR_NOACCESS,
1733
                 SPR_NOACCESS, &spr_write_generic,
1735
                 &spr_read_generic, &spr_write_generic,
1734 1736
                 0x00000000);
1735 1737
    spr_register(env, SPR_USPRG4, "USPRG4",
1736 1738
                 &spr_read_ureg, SPR_NOACCESS,
......
1738 1740
                 0x00000000);
1739 1741
    spr_register(env, SPR_SPRG5, "SPRG5",
1740 1742
                 SPR_NOACCESS, SPR_NOACCESS,
1741
                 SPR_NOACCESS, &spr_write_generic,
1743
                 spr_read_generic, &spr_write_generic,
1742 1744
                 0x00000000);
1743 1745
    spr_register(env, SPR_USPRG5, "USPRG5",
1744 1746
                 &spr_read_ureg, SPR_NOACCESS,
......
1746 1748
                 0x00000000);
1747 1749
    spr_register(env, SPR_SPRG6, "SPRG6",
1748 1750
                 SPR_NOACCESS, SPR_NOACCESS,
1749
                 SPR_NOACCESS, &spr_write_generic,
1751
                 spr_read_generic, &spr_write_generic,
1750 1752
                 0x00000000);
1751 1753
    spr_register(env, SPR_USPRG6, "USPRG6",
1752 1754
                 &spr_read_ureg, SPR_NOACCESS,
......
1754 1756
                 0x00000000);
1755 1757
    spr_register(env, SPR_SPRG7, "SPRG7",
1756 1758
                 SPR_NOACCESS, SPR_NOACCESS,
1757
                 SPR_NOACCESS, &spr_write_generic,
1759
                 spr_read_generic, &spr_write_generic,
1758 1760
                 0x00000000);
1759 1761
    spr_register(env, SPR_USPRG7, "USPRG7",
1760 1762
                 &spr_read_ureg, SPR_NOACCESS,
......
2756 2758
        .pvr_mask    = 0xFFFFFF00,
2757 2759
        .insns_flags = PPC_INSNS_403,
2758 2760
        .flags       = PPC_FLAGS_403,
2759
        .msr_mask    = 0x000000000007D23D,
2761
        .msr_mask    = 0x000000000007D23DULL,
2760 2762
    },
2761 2763
#endif
2762 2764
#if defined (TODO)
......
2767 2769
        .pvr_mask    = 0xFFFFFF00,
2768 2770
        .insns_flags = PPC_INSNS_403,
2769 2771
        .flags       = PPC_FLAGS_403,
2770
        .msr_mask    = 0x000000000007D23D,
2772
        .msr_mask    = 0x000000000007D23DULL,
2771 2773
    },
2772 2774
#endif
2773 2775
#if defined (TODO)
......
2778 2780
        .pvr_mask    = 0xFFFFFF00,
2779 2781
        .insns_flags = PPC_INSNS_403,
2780 2782
        .flags       = PPC_FLAGS_403,
2781
        .msr_mask    = 0x000000000007D23D,
2783
        .msr_mask    = 0x000000000007D23DULL,
2782 2784
    },
2783 2785
#endif
2784 2786
#if defined (TODO)
......
2789 2791
        .pvr_mask    = 0xFFFFFF00,
2790 2792
        .insns_flags = PPC_INSNS_403,
2791 2793
        .flags       = PPC_FLAGS_403,
2792
        .msr_mask    = 0x000000000007D23D,
2794
        .msr_mask    = 0x000000000007D23DULL,
2793 2795
    },
2794 2796
#endif
2795 2797
#if defined (TODO)
......
2800 2802
        .pvr_mask    = 0xFFFFFF00,
2801 2803
        .insns_flags = PPC_INSNS_403,
2802 2804
        .flags       = PPC_FLAGS_403,
2803
        .msr_mask    = 0x000000000007D23D,
2805
        .msr_mask    = 0x000000000007D23DULL,
2804 2806
    },
2805 2807
#endif
2806 2808
    /* Generic PowerPC 405 */
......
2810 2812
        .pvr_mask    = 0xFFFF0000,
2811 2813
        .insns_flags = PPC_INSNS_405,
2812 2814
        .flags       = PPC_FLAGS_405,
2813
        .msr_mask    = 0x00000000020EFF30,
2815
        .msr_mask    = 0x00000000020EFF30ULL,
2814 2816
    },
2815 2817
    /* PowerPC 405 CR */
2816 2818
    {
......
2819 2821
        .pvr_mask    = 0xFFFFFFFF,
2820 2822
        .insns_flags = PPC_INSNS_405,
2821 2823
        .flags       = PPC_FLAGS_405,
2822
        .msr_mask    = 0x00000000020EFF30,
2824
        .msr_mask    = 0x00000000020EFF30ULL,
2823 2825
    },
2824 2826
#if defined (TODO)
2825 2827
    /* PowerPC 405 GP */
......
2829 2831
        .pvr_mask    = 0xFFFFFFFF,
2830 2832
        .insns_flags = PPC_INSNS_405,
2831 2833
        .flags       = PPC_FLAGS_405,
2832
        .msr_mask    = 0x00000000020EFF30,
2834
        .msr_mask    = 0x00000000020EFF30ULL,
2833 2835
    },
2834 2836
#endif
2835 2837
    /* PowerPC 405 EP */
......
2839 2841
        .pvr_mask    = 0xFFFFFFFF,
2840 2842
        .insns_flags = PPC_INSNS_405,
2841 2843
        .flags       = PPC_FLAGS_405,
2842
        .msr_mask    = 0x00000000020EFF30,
2844
        .msr_mask    = 0x00000000020EFF30ULL,
2843 2845
    },
2844 2846
#if defined (TODO)
2845 2847
    /* PowerPC 405 EZ */
......
2849 2851
        .pvr_mask    = 0xFFFFFFFF,
2850 2852
        .insns_flags = PPC_INSNS_405,
2851 2853
        .flags       = PPC_FLAGS_405,
2852
        .msr_mask    = 0x00000000020EFF30,
2854
        .msr_mask    = 0x00000000020EFF30ULL,
2853 2855
    },
2854 2856
#endif
2855 2857
#if defined (TODO)
......
2860 2862
        .pvr_mask    = 0xFFFFFFFF,
2861 2863
        .insns_flags = PPC_INSNS_405,
2862 2864
        .flags       = PPC_FLAGS_405,
2863
        .msr_mask    = 0x00000000020EFF30,
2865
        .msr_mask    = 0x00000000020EFF30ULL,
2864 2866
    },
2865 2867
#endif
2866
#if defined (TODO)
2867 2868
    /* PowerPC 405 D2 */
2868 2869
    {
2869 2870
        .name        = "405d2",
......
2871 2872
        .pvr_mask    = 0xFFFFFFFF,
2872 2873
        .insns_flags = PPC_INSNS_405,
2873 2874
        .flags       = PPC_FLAGS_405,
2874
        .msr_mask    = 0x00000000020EFF30,
2875
        .msr_mask    = 0x00000000020EFF30ULL,
2875 2876
    },
2876
#endif
2877
#if defined (TODO)
2878 2877
    /* PowerPC 405 D4 */
2879 2878
    {
2880 2879
        .name        = "405d4",
......
2882 2881
        .pvr_mask    = 0xFFFFFFFF,
2883 2882
        .insns_flags = PPC_INSNS_405,
2884 2883
        .flags       = PPC_FLAGS_405,
2885
        .msr_mask    = 0x00000000020EFF30,
2884
        .msr_mask    = 0x00000000020EFF30ULL,
2886 2885
    },
2887
#endif
2888 2886
#if defined (TODO)
2889 2887
    /* Npe405 H */
2890 2888
    {
......
2893 2891
        .pvr_mask    = 0xFFFFFFFF,
2894 2892
            .insns_flags = PPC_INSNS_405,
2895 2893
        .flags       = PPC_FLAGS_405,
2896
        .msr_mask    = 0x00000000020EFF30,
2894
        .msr_mask    = 0x00000000020EFF30ULL,
2897 2895
    },
2898 2896
#endif
2899 2897
#if defined (TODO)
......
2904 2902
        .pvr_mask    = 0xFFFFFFFF,
2905 2903
        .insns_flags = PPC_INSNS_405,
2906 2904
        .flags       = PPC_FLAGS_405,
2907
        .msr_mask    = 0x00000000020EFF30,
2905
        .msr_mask    = 0x00000000020EFF30ULL,
2908 2906
    },
2909 2907
#endif
2910 2908
#if defined (TODO)
......
2915 2913
        .pvr_mask    = 0xFFFFFFFF,
2916 2914
        .insns_flags = PPC_INSNS_405,
2917 2915
        .flags       = PPC_FLAGS_405,
2918
        .msr_mask    = 0x00000000020EFF30,
2916
        .msr_mask    = 0x00000000020EFF30ULL,
2919 2917
    },
2920 2918
#endif
2921 2919
#if defined (TODO)
......
2926 2924
        .pvr_mask    = 0xFFFFFFFF,
2927 2925
        .insns_flags = PPC_INSNS_405,
2928 2926
        .flags       = PPC_FLAGS_405,
2929
        .msr_mask    = 0x00000000020EFF30,
2927
        .msr_mask    = 0x00000000020EFF30ULL,
2930 2928
    },
2931 2929
#endif
2932 2930
#if defined (TODO)
......
2937 2935
        .pvr_mask    = 0xFFFFFFFF,
2938 2936
        .insns_flags = PPC_INSNS_405,
2939 2937
        .flags       = PPC_FLAGS_405,
2940
        .msr_mask    = 0x00000000020EFF30,
2938
        .msr_mask    = 0x00000000020EFF30ULL,
2941 2939
    },
2942 2940
#endif
2943
#if defined (TODO) || 1
2941
#if defined (TODO)
2944 2942
    /* STB03xx */
2945 2943
    {
2946 2944
        .name        = "STB03",
......
2948 2946
        .pvr_mask    = 0xFFFFFFFF,
2949 2947
        .insns_flags = PPC_INSNS_405,
2950 2948
        .flags       = PPC_FLAGS_405,
2951
        .msr_mask    = 0x00000000020EFF30,
2949
        .msr_mask    = 0x00000000020EFF30ULL,
2952 2950
    },
2953 2951
#endif
2954 2952
#if defined (TODO)
......
2959 2957
        .pvr_mask    = 0xFFFFFFFF,
2960 2958
        .insns_flags = PPC_INSNS_405,
2961 2959
        .flags       = PPC_FLAGS_405,
2962
        .msr_mask    = 0x00000000020EFF30,
2960
        .msr_mask    = 0x00000000020EFF30ULL,
2963 2961
    },
2964 2962
#endif
2965 2963
#if defined (TODO)
......
2970 2968
        .pvr_mask    = 0xFFFFFFFF,
2971 2969
        .insns_flags = PPC_INSNS_405,
2972 2970
        .flags       = PPC_FLAGS_405,
2973
        .msr_mask    = 0x00000000020EFF30,
2971
        .msr_mask    = 0x00000000020EFF30ULL,
2974 2972
    },
2975 2973
#endif
2976
#if defined (TODO) || 1
2974
#if defined (TODO)
2977 2975
    /* STB25xx */
2978 2976
    {
2979 2977
        .name        = "STB25",
......
2981 2979
        .pvr_mask    = 0xFFFFFFFF,
2982 2980
        .insns_flags = PPC_INSNS_405,
2983 2981
        .flags       = PPC_FLAGS_405,
2984
        .msr_mask    = 0x00000000020EFF30,
2982
        .msr_mask    = 0x00000000020EFF30ULL,
2985 2983
    },
2986 2984
#endif
2987 2985
#if defined (TODO)
......
2992 2990
        .pvr_mask    = 0xFFFFFFFF,
2993 2991
        .insns_flags = PPC_INSNS_405,
2994 2992
        .flags       = PPC_FLAGS_405,
2995
        .msr_mask    = 0x00000000020EFF30,
2993
        .msr_mask    = 0x00000000020EFF30ULL,
2996 2994
    },
2997 2995
#endif
2998 2996
        /* Xilinx PowerPC 405 cores */
......
3003 3001
        .pvr_mask    = 0xFFFFFFFF,
3004 3002
        .insns_flags = PPC_INSNS_405,
3005 3003
        .flags       = PPC_FLAGS_405,
3006
        .msr_mask    = 0x00000000020EFF30,
3004
        .msr_mask    = 0x00000000020EFF30ULL,
3007 3005
    },
3008 3006
    {
3009 3007
        .name        = "x2vp7",
......
3011 3009
        .pvr_mask    = 0xFFFFFFFF,
3012 3010
        .insns_flags = PPC_INSNS_405,
3013 3011
        .flags       = PPC_FLAGS_405,
3014
        .msr_mask    = 0x00000000020EFF30,
3012
        .msr_mask    = 0x00000000020EFF30ULL,
3015 3013
    },
3016 3014
    {
3017 3015
        .name        = "x2vp20",
......
3019 3017
        .pvr_mask    = 0xFFFFFFFF,
3020 3018
        .insns_flags = PPC_INSNS_405,
3021 3019
        .flags       = PPC_FLAGS_405,
3022
        .msr_mask    = 0x00000000020EFF30,
3020
        .msr_mask    = 0x00000000020EFF30ULL,
3023 3021
    },
3024 3022
    {
3025 3023
        .name        = "x2vp50",
......
3027 3025
        .pvr_mask    = 0xFFFFFFFF,
3028 3026
        .insns_flags = PPC_INSNS_405,
3029 3027
        .flags       = PPC_FLAGS_405,
3030
        .msr_mask    = 0x00000000020EFF30,
3028
        .msr_mask    = 0x00000000020EFF30ULL,
3031 3029
    },
3032 3030
#endif
3033 3031
#if defined (TODO)
......
3038 3036
        .pvr_mask    = 0xFFFF0000,
3039 3037
        .insns_flags = PPC_INSNS_440,
3040 3038
        .flags       = PPC_FLAGS_440,
3041
        .msr_mask    = 0x000000000006D630,
3039
        .msr_mask    = 0x000000000006D630ULL,
3042 3040
    },
3043 3041
#endif
3044 3042
#if defined (TODO)
......
3049 3047
        .pvr_mask    = 0xFFFF0000,
3050 3048
        .insns_flags = PPC_INSNS_440,
3051 3049
        .flags       = PPC_FLAGS_440,
3052
        .msr_mask    = 0x000000000006D630,
3050
        .msr_mask    = 0x000000000006D630ULL,
3053 3051
    },
3054 3052
#endif
3055 3053
#if defined (TODO)
......
3060 3058
        .pvr_mask    = 0xFFFFFF00,
3061 3059
        .insns_flags = PPC_INSNS_440,
3062 3060
        .flags       = PPC_FLAGS_440,
3063
        .msr_mask    = 0x000000000006D630,
3061
        .msr_mask    = 0x000000000006D630ULL,
3064 3062
    },
3065 3063
#endif
3066 3064
#if defined (TODO)
......
3071 3069
        .pvr_mask    = 0xFFFF0000,
3072 3070
        .insns_flags = PPC_INSNS_405,
3073 3071
        .flags       = PPC_FLAGS_440,
3074
        .msr_mask    = 0x000000000006D630,
3072
        .msr_mask    = 0x000000000006D630ULL,
3075 3073
    },
3076 3074
#endif
3077 3075
#if defined (TODO)
......
3082 3080
        .pvr_mask    = 0xFFFF0000,
3083 3081
        .insns_flags = PPC_INSNS_405,
3084 3082
        .flags       = PPC_FLAGS_440,
3085
        .msr_mask    = 0x000000000006D630,
3083
        .msr_mask    = 0x000000000006D630ULL,
3086 3084
    },
3087 3085
#endif
3088 3086
#if defined (TODO)
......
3093 3091
        .pvr_mask    = 0xFFFF0000,
3094 3092
        .insns_flags = PPC_INSNS_405,
3095 3093
        .flags       = PPC_FLAGS_440,
3096
        .msr_mask    = 0x000000000006D630,
3094
        .msr_mask    = 0x000000000006D630ULL,
3097 3095
    },
3098 3096
#endif
3099 3097
#if defined (TODO)
......
3104 3102
        .pvr_mask    = 0xFFFF0000,
3105 3103
        .insns_flags = PPC_INSNS_405,
3106 3104
        .flags       = PPC_FLAGS_440,
3107
        .msr_mask    = 0x000000000006D630,
3105
        .msr_mask    = 0x000000000006D630ULL,
3108 3106
    },
3109 3107
#endif
3110 3108
#if defined (TODO)
......
3115 3113
        .pvr_mask    = 0xFFFF0000,
3116 3114
        .insns_flags = PPC_INSNS_405,
3117 3115
        .flags       = PPC_FLAGS_440,
3118
        .msr_mask    = 0x000000000006D630,
3116
        .msr_mask    = 0x000000000006D630ULL,
3119 3117
    },
3120 3118
#endif
3121 3119
#if defined (TODO)
......
3126 3124
        .pvr_mask    = 0xFFFF0000,
3127 3125
        .insns_flags = PPC_INSNS_405,
3128 3126
        .flags       = PPC_FLAGS_440,
3129
        .msr_mask    = 0x000000000006D630,
3127
        .msr_mask    = 0x000000000006D630ULL,
3130 3128
    },
3131 3129
#endif
3132 3130
    /* Fake generic BookE PowerPC */
......
3136 3134
        .pvr_mask    = 0xFFFFFFFF,
3137 3135
        .insns_flags = PPC_INSNS_BOOKE,
3138 3136
        .flags       = PPC_FLAGS_BOOKE,
3139
        .msr_mask    = 0x000000000006D630,
3137
        .msr_mask    = 0x000000000006D630ULL,
3140 3138
    },
3141 3139
    /* PowerPC 460 cores - TODO */
3142 3140
    /* PowerPC MPC 5xx cores - TODO */
......
3155 3153
        .pvr_mask    = 0xFFFF0000,
3156 3154
        .insns_flags = PPC_INSNS_601,
3157 3155
        .flags       = PPC_FLAGS_601,
3158
        .msr_mask    = 0x000000000000FD70,
3156
        .msr_mask    = 0x000000000000FD70ULL,
3159 3157
    },
3160 3158
#endif
3161 3159
#if defined (TODO)
......
3166 3164
        .pvr_mask    = 0xFFFF0000,
3167 3165
        .insns_flags = PPC_INSNS_602,
3168 3166
        .flags       = PPC_FLAGS_602,
3169
        .msr_mask    = 0x0000000000C7FF73,
3167
        .msr_mask    = 0x0000000000C7FF73ULL,
3170 3168
    },
3171 3169
#endif
3172 3170
    /* PowerPC 603 */
......
3176 3174
        .pvr_mask    = 0xFFFFFFFF,
3177 3175
        .insns_flags = PPC_INSNS_603,
3178 3176
        .flags       = PPC_FLAGS_603,
3179
        .msr_mask    = 0x000000000007FF73,
3177
        .msr_mask    = 0x000000000007FF73ULL,
3180 3178
    },
3181 3179
    /* PowerPC 603e */
3182 3180
    {
......
3185 3183
        .pvr_mask    = 0xFFFFFFFF,
3186 3184
        .insns_flags = PPC_INSNS_603,
3187 3185
        .flags       = PPC_FLAGS_603,
3188
        .msr_mask    = 0x000000000007FF73,
3186
        .msr_mask    = 0x000000000007FF73ULL,
3189 3187
    },
3190 3188
    {
3191 3189
        .name        = "Stretch",
......
3193 3191
        .pvr_mask    = 0xFFFFFFFF,
3194 3192
        .insns_flags = PPC_INSNS_603,
3195 3193
        .flags       = PPC_FLAGS_603,
3196
        .msr_mask    = 0x000000000007FF73,
3194
        .msr_mask    = 0x000000000007FF73ULL,
3197 3195
    },
3198 3196
    /* PowerPC 603p */
3199 3197
    {
......
3202 3200
        .pvr_mask    = 0xFFFFFFFF,
3203 3201
        .insns_flags = PPC_INSNS_603,
3204 3202
        .flags       = PPC_FLAGS_603,
3205
        .msr_mask    = 0x000000000007FF73,
3203
        .msr_mask    = 0x000000000007FF73ULL,
3206 3204
    },
3207 3205
    /* PowerPC 603e7 */
3208 3206
    {
......
3211 3209
        .pvr_mask    = 0xFFFFFFFF,
3212 3210
        .insns_flags = PPC_INSNS_603,
3213 3211
        .flags       = PPC_FLAGS_603,
3214
        .msr_mask    = 0x000000000007FF73,
3212
        .msr_mask    = 0x000000000007FF73ULL,
3215 3213
    },
3216 3214
    /* PowerPC 603e7v */
3217 3215
    {
......
3220 3218
        .pvr_mask    = 0xFFFFFFFF,
3221 3219
        .insns_flags = PPC_INSNS_603,
3222 3220
        .flags       = PPC_FLAGS_603,
3223
        .msr_mask    = 0x000000000007FF73,
3221
        .msr_mask    = 0x000000000007FF73ULL,
3224 3222
    },
3225 3223
    /* PowerPC 603e7v2 */
3226 3224
    {
......
3229 3227
        .pvr_mask    = 0xFFFFFFFF,
3230 3228
        .insns_flags = PPC_INSNS_603,
3231 3229
        .flags       = PPC_FLAGS_603,
3232
        .msr_mask    = 0x000000000007FF73,
3230
        .msr_mask    = 0x000000000007FF73ULL,
3233 3231
    },
3234 3232
    /* PowerPC 603r */
3235 3233
    {
......
3238 3236
        .pvr_mask    = 0xFFFFFFFF,
3239 3237
        .insns_flags = PPC_INSNS_603,
3240 3238
        .flags       = PPC_FLAGS_603,
3241
        .msr_mask    = 0x000000000007FF73,
3239
        .msr_mask    = 0x000000000007FF73ULL,
3242 3240
    },
3243 3241
    {
3244 3242
        .name        = "Goldeneye",
......
3246 3244
        .pvr_mask    = 0xFFFFFFFF,
3247 3245
        .insns_flags = PPC_INSNS_603,
3248 3246
        .flags       = PPC_FLAGS_603,
3249
        .msr_mask    = 0x000000000007FF73,
3247
        .msr_mask    = 0x000000000007FF73ULL,
3250 3248
    },
3251 3249
#if defined (TODO)
3252 3250
    /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
......
3256 3254
        .pvr_mask    = 0xFFFF0000,
3257 3255
        .insns_flags = PPC_INSNS_G2,
3258 3256
        .flags       = PPC_FLAGS_G2,
3259
        .msr_mask    = 0x000000000006FFF2,
3257
        .msr_mask    = 0x000000000006FFF2ULL,
3260 3258
    },
3261 3259
    {
3262 3260
        .name        = "G2h4",
......
3264 3262
        .pvr_mask    = 0xFFFF0000,
3265 3263
        .insns_flags = PPC_INSNS_G2,
3266 3264
        .flags       = PPC_FLAGS_G2,
3267
        .msr_mask    = 0x000000000006FFF2,
3265
        .msr_mask    = 0x000000000006FFF2ULL,
3268 3266
    },
3269 3267
    {
3270 3268
        .name        = "G2gp",
......
3272 3270
        .pvr_mask    = 0xFFFF0000,
3273 3271
        .insns_flags = PPC_INSNS_G2,
3274 3272
        .flags       = PPC_FLAGS_G2,
3275
        .msr_mask    = 0x000000000006FFF2,
3273
        .msr_mask    = 0x000000000006FFF2ULL,
3276 3274
    },
3277 3275
    {
3278 3276
        .name        = "G2ls",
......
3280 3278
        .pvr_mask    = 0xFFFF0000,
3281 3279
        .insns_flags = PPC_INSNS_G2,
3282 3280
        .flags       = PPC_FLAGS_G2,
3283
        .msr_mask    = 0x000000000006FFF2,
3281
        .msr_mask    = 0x000000000006FFF2ULL,
3284 3282
    },
3285 3283
    { /* Same as G2, with LE mode support */
3286 3284
        .name        = "G2le",
......
3288 3286
        .pvr_mask    = 0xFFFF0000,
3289 3287
        .insns_flags = PPC_INSNS_G2,
3290 3288
        .flags       = PPC_FLAGS_G2,
3291
        .msr_mask    = 0x000000000007FFF3,
3289
        .msr_mask    = 0x000000000007FFF3ULL,
3292 3290
    },
3293 3291
    {
3294 3292
        .name        = "G2legp",
......
3296 3294
        .pvr_mask    = 0xFFFF0000,
3297 3295
        .insns_flags = PPC_INSNS_G2,
3298 3296
        .flags       = PPC_FLAGS_G2,
3299
        .msr_mask    = 0x000000000007FFF3,
3297
        .msr_mask    = 0x000000000007FFF3ULL,
3300 3298
    },
3301 3299
    {
3302 3300
        .name        = "G2lels",
......
3304 3302
        .pvr_mask    = 0xFFFF0000,
3305 3303
        .insns_flags = PPC_INSNS_G2,
3306 3304
        .flags       = PPC_FLAGS_G2,
3307
        .msr_mask    = 0x000000000007FFF3,
3305
        .msr_mask    = 0x000000000007FFF3ULL,
3308 3306
    },
3309 3307
#endif
3310 3308
    /* PowerPC 604 */
......
3314 3312
        .pvr_mask    = 0xFFFFFFFF,
3315 3313
        .insns_flags = PPC_INSNS_604,
3316 3314
        .flags       = PPC_FLAGS_604,
3317
        .msr_mask    = 0x000000000005FF77,
3315
        .msr_mask    = 0x000000000005FF77ULL,
3318 3316
    },
3319 3317
    /* PowerPC 604e */
3320 3318
    {
......
3323 3321
        .pvr_mask    = 0xFFFFFFFF,
3324 3322
        .insns_flags = PPC_INSNS_604,
3325 3323
        .flags       = PPC_FLAGS_604,
3326
        .msr_mask    = 0x000000000005FF77,
3324
        .msr_mask    = 0x000000000005FF77ULL,
3327 3325
    },
3328 3326
    /* PowerPC 604r */
3329 3327
    {
......
3332 3330
        .pvr_mask    = 0xFFFFFFFF,
3333 3331
        .insns_flags = PPC_INSNS_604,
3334 3332
        .flags       = PPC_FLAGS_604,
3335
        .msr_mask    = 0x000000000005FF77,
3333
        .msr_mask    = 0x000000000005FF77ULL,
3336 3334
    },
3337 3335
    /* generic G3 */
3338 3336
    {
......
3341 3339
        .pvr_mask    = 0xFFFFFFFF,
3342 3340
        .insns_flags = PPC_INSNS_7x0,
3343 3341
        .flags       = PPC_FLAGS_7x0,
3344
        .msr_mask    = 0x000000000007FF77,
3342
        .msr_mask    = 0x000000000007FF77ULL,
3345 3343
    },
3346 3344
    /* MPC740 (G3) */
3347 3345
    {
......
3350 3348
        .pvr_mask    = 0xFFFFFFFF,
3351 3349
        .insns_flags = PPC_INSNS_7x0,
3352 3350
        .flags       = PPC_FLAGS_7x0,
3353
        .msr_mask    = 0x000000000007FF77,
3351
        .msr_mask    = 0x000000000007FF77ULL,
3354 3352
    },
3355 3353
    {
3356 3354
        .name        = "Arthur",
......
3358 3356
        .pvr_mask    = 0xFFFFFFFF,
3359 3357
        .insns_flags = PPC_INSNS_7x0,
3360 3358
        .flags       = PPC_FLAGS_7x0,
3361
        .msr_mask    = 0x000000000007FF77,
3359
        .msr_mask    = 0x000000000007FF77ULL,
3362 3360
    },
3363 3361
#if defined (TODO)
3364 3362
    /* MPC745 (G3) */
......
3368 3366
        .pvr_mask    = 0xFFFFF000,
3369 3367
        .insns_flags = PPC_INSNS_7x5,
3370 3368
        .flags       = PPC_FLAGS_7x5,
3371
        .msr_mask    = 0x000000000007FF77,
3369
        .msr_mask    = 0x000000000007FF77ULL,
3372 3370
    },
3373 3371
    {
3374 3372
        .name        = "Goldfinger",
......
3376 3374
        .pvr_mask    = 0xFFFFF000,
3377 3375
        .insns_flags = PPC_INSNS_7x5,
3378 3376
        .flags       = PPC_FLAGS_7x5,
3379
        .msr_mask    = 0x000000000007FF77,
3377
        .msr_mask    = 0x000000000007FF77ULL,
3380 3378
    },
3381 3379
#endif
3382 3380
    /* MPC750 (G3) */
......
3386 3384
        .pvr_mask    = 0xFFFFFFFF,
3387 3385
        .insns_flags = PPC_INSNS_7x0,
3388 3386
        .flags       = PPC_FLAGS_7x0,
3389
        .msr_mask    = 0x000000000007FF77,
3387
        .msr_mask    = 0x000000000007FF77ULL,
3390 3388
    },
3391 3389
#if defined (TODO)
3392 3390
    /* MPC755 (G3) */
......
3396 3394
        .pvr_mask    = 0xFFFFF000,
3397 3395
        .insns_flags = PPC_INSNS_7x5,
3398 3396
        .flags       = PPC_FLAGS_7x5,
3399
        .msr_mask    = 0x000000000007FF77,
3397
        .msr_mask    = 0x000000000007FF77ULL,
3400 3398
    },
3401 3399
#endif
3402 3400
    /* MPC740P (G3) */
......
3406 3404
        .pvr_mask    = 0xFFFFFFFF,
3407 3405
        .insns_flags = PPC_INSNS_7x0,
3408 3406
        .flags       = PPC_FLAGS_7x0,
3409
        .msr_mask    = 0x000000000007FF77,
3407
        .msr_mask    = 0x000000000007FF77ULL,
3410 3408
    },
3411 3409
    {
3412 3410
        .name        = "Conan/Doyle",
......
3414 3412
        .pvr_mask    = 0xFFFFFFFF,
3415 3413
        .insns_flags = PPC_INSNS_7x0,
3416 3414
        .flags       = PPC_FLAGS_7x0,
3417
        .msr_mask    = 0x000000000007FF77,
3415
        .msr_mask    = 0x000000000007FF77ULL,
3418 3416
    },
3419 3417
#if defined (TODO)
3420 3418
    /* MPC745P (G3) */
......
3424 3422
        .pvr_mask    = 0xFFFFF000,
3425 3423
        .insns_flags = PPC_INSNS_7x5,
3426 3424
        .flags       = PPC_FLAGS_7x5,
3427
        .msr_mask    = 0x000000000007FF77,
3425
        .msr_mask    = 0x000000000007FF77ULL,
3428 3426
    },
3429 3427
#endif
3430 3428
    /* MPC750P (G3) */
......
3434 3432
        .pvr_mask    = 0xFFFFFFFF,
3435 3433
        .insns_flags = PPC_INSNS_7x0,
3436 3434
        .flags       = PPC_FLAGS_7x0,
3437
        .msr_mask    = 0x000000000007FF77,
3435
        .msr_mask    = 0x000000000007FF77ULL,
3438 3436
    },
3439 3437
#if defined (TODO)
3440 3438
    /* MPC755P (G3) */
......
3444 3442
        .pvr_mask    = 0xFFFFF000,
3445 3443
        .insns_flags = PPC_INSNS_7x5,
3446 3444
        .flags       = PPC_FLAGS_7x5,
3447
        .msr_mask    = 0x000000000007FF77,
3445
        .msr_mask    = 0x000000000007FF77ULL,
3448 3446
    },
3449 3447
#endif
3450 3448
    /* IBM 750CXe (G3 embedded) */
......
3454 3452
        .pvr_mask    = 0xFFFFFFFF,
3455 3453
        .insns_flags = PPC_INSNS_7x0,
3456 3454
        .flags       = PPC_FLAGS_7x0,
3457
        .msr_mask    = 0x000000000007FF77,
3455
        .msr_mask    = 0x000000000007FF77ULL,
3458 3456
    },
3459 3457
    /* IBM 750FX (G3 embedded) */
3460 3458
    {
......
3463 3461
        .pvr_mask    = 0xFFFFFFFF,
3464 3462
        .insns_flags = PPC_INSNS_7x0,
3465 3463
        .flags       = PPC_FLAGS_7x0,
3466
        .msr_mask    = 0x000000000007FF77,
3464
        .msr_mask    = 0x000000000007FF77ULL,
3467 3465
    },
3468 3466
    /* IBM 750GX (G3 embedded) */
3469 3467
    {
......
3472 3470
        .pvr_mask    = 0xFFFFFFFF,
3473 3471
        .insns_flags = PPC_INSNS_7x0,
3474 3472
        .flags       = PPC_FLAGS_7x0,
3475
        .msr_mask    = 0x000000000007FF77,
3473
        .msr_mask    = 0x000000000007FF77ULL,
3476 3474
    },
3477 3475
#if defined (TODO)
3478 3476
    /* generic G4 */
......
3482 3480
        .pvr_mask    = 0xFFFF0000,
3483 3481
        .insns_flags = PPC_INSNS_74xx,
3484 3482
        .flags       = PPC_FLAGS_74xx,
3485
        .msr_mask    = 0x000000000205FF77,
3483
        .msr_mask    = 0x000000000205FF77ULL,
3486 3484
    },
3487 3485
#endif
3488 3486
#if defined (TODO)
......
3493 3491
        .pvr_mask    = 0xFFFF0000,
3494 3492
        .insns_flags = PPC_INSNS_74xx,
3495 3493
        .flags       = PPC_FLAGS_74xx,
3496
        .msr_mask    = 0x000000000205FF77,
3494
        .msr_mask    = 0x000000000205FF77ULL,
3497 3495
    },
3498 3496
    {
3499 3497
        .name        = "Max",
......
3501 3499
        .pvr_mask    = 0xFFFF0000,
3502 3500
        .insns_flags = PPC_INSNS_74xx,
3503 3501
        .flags       = PPC_FLAGS_74xx,
3504
        .msr_mask    = 0x000000000205FF77,
3502
        .msr_mask    = 0x000000000205FF77ULL,
3505 3503
    },
3506 3504
#endif
3507 3505
#if defined (TODO)
......
3512 3510
        .pvr_mask    = 0xFFFF0000,
3513 3511
        .insns_flags = PPC_INSNS_74xx,
3514 3512
        .flags       = PPC_FLAGS_74xx,
3515
        .msr_mask    = 0x000000000205FF77,
3513
        .msr_mask    = 0x000000000205FF77ULL,
3516 3514
    },
3517 3515
    {
3518 3516
        .name        = "Nitro",
......
3520 3518
        .pvr_mask    = 0xFFFF0000,
3521 3519
        .insns_flags = PPC_INSNS_74xx,
3522 3520
        .flags       = PPC_FLAGS_74xx,
3523
        .msr_mask    = 0x000000000205FF77,
3521
        .msr_mask    = 0x000000000205FF77ULL,
3524 3522
    },
3525 3523
#endif
3526 3524
    /* XXX: 7441 */
......
3535 3533
        .pvr_mask    = 0xFFFF0000,
3536 3534
        .insns_flags = PPC_INSNS_74xx,
3537 3535
        .flags       = PPC_FLAGS_74xx,
3538
        .msr_mask    = 0x000000000205FF77,
3536
        .msr_mask    = 0x000000000205FF77ULL,
3539 3537
    },
3540 3538
    {
3541 3539
        .name        = "Vger",
......
3543 3541
        .pvr_mask    = 0xFFFF0000,
3544 3542
        .insns_flags = PPC_INSNS_74xx,
3545 3543
        .flags       = PPC_FLAGS_74xx,
3546
        .msr_mask    = 0x000000000205FF77,
3544
        .msr_mask    = 0x000000000205FF77ULL,
3547 3545
    },
3548 3546
#endif
3549 3547
    /* XXX: 7451 */
......
3555 3553
        .pvr_mask    = 0xFFFF0000,
3556 3554
        .insns_flags = PPC_INSNS_74xx,
3557 3555
        .flags       = PPC_FLAGS_74xx,
3558
        .msr_mask    = 0x000000000205FF77,
3556
        .msr_mask    = 0x000000000205FF77ULL,
3559 3557
    },
3560 3558
    {
3561 3559
        .name        = "Apollo 6",
......
3563 3561
        .pvr_mask    = 0xFFFF0000,
3564 3562
        .insns_flags = PPC_INSNS_74xx,
3565 3563
        .flags       = PPC_FLAGS_74xx,
3566
        .msr_mask    = 0x000000000205FF77,
3564
        .msr_mask    = 0x000000000205FF77ULL,
3567 3565
    },
3568 3566
#endif
3569 3567
#if defined (TODO)
......
3574 3572
        .pvr_mask    = 0xFFFF0000,
3575 3573
        .insns_flags = PPC_INSNS_74xx,
3576 3574
        .flags       = PPC_FLAGS_74xx,
3577
        .msr_mask    = 0x000000000205FF77,
3575
        .msr_mask    = 0x000000000205FF77ULL,
3578 3576
    },
3579 3577
    {
3580 3578
        .name        = "Apollo 7",
......
3582 3580
        .pvr_mask    = 0xFFFF0000,
3583 3581
        .insns_flags = PPC_INSNS_74xx,
3584 3582
        .flags       = PPC_FLAGS_74xx,
3585
        .msr_mask    = 0x000000000205FF77,
3583
        .msr_mask    = 0x000000000205FF77ULL,
3586 3584
    },
3587 3585
#endif
3588 3586
#if defined (TODO)
......
3593 3591
        .pvr_mask    = 0xFFFF0000,
3594 3592
        .insns_flags = PPC_INSNS_74xx,
3595 3593
        .flags       = PPC_FLAGS_74xx,
3596
        .msr_mask    = 0x000000000205FF77,
3594
        .msr_mask    = 0x000000000205FF77ULL,
3597 3595
    },
3598 3596
    {
3599 3597
        .name        = "Apollo 7 PM",
......
3601 3599
        .pvr_mask    = 0xFFFF0000,
3602 3600
        .insns_flags = PPC_INSNS_74xx,
3603 3601
        .flags       = PPC_FLAGS_74xx,
3604
        .msr_mask    = 0x000000000205FF77,
3602
        .msr_mask    = 0x000000000205FF77ULL,
3605 3603
    },
3606 3604
#endif
3607 3605
    /* 64 bits PowerPC */
......
3614 3612
        .pvr_mask    = 0xFFFF0000,
3615 3613
        .insns_flags = PPC_INSNS_620,
3616 3614
        .flags       = PPC_FLAGS_620,
3617
        .msr_mask    = 0x800000000005FF73,
3615
        .msr_mask    = 0x800000000005FF73ULL,
3618 3616
    },
3619 3617
#endif
3620 3618
#if defined (TODO)
......
3699 3697
        .msr_mask    = xxx,
3700 3698
    },
3701 3699
#endif
3702
#if defined (TODO) || 1
3700
#if defined (TODO)
3703 3701
    /* PowerPC 970 */
3704 3702
    {
3705 3703
        .name        = "970",
......
3707 3705
        .pvr_mask    = 0xFFFF0000,
3708 3706
        .insns_flags = PPC_INSNS_970,
3709 3707
        .flags       = PPC_FLAGS_970,
3710
        .msr_mask    = 0x900000000204FF36,
3708
        .msr_mask    = 0x900000000204FF36ULL,
3711 3709
    },
3712 3710
#endif
3713 3711
#if defined (TODO)
......
3718 3716
        .pvr_mask    = 0xFFFF0000,
3719 3717
        .insns_flags = PPC_INSNS_970FX,
3720 3718
        .flags       = PPC_FLAGS_970FX,
3721
        .msr_mask    = 0x800000000204FF36,
3719
        .msr_mask    = 0x800000000204FF36ULL,
3722 3720
    },
3723 3721
#endif
3724 3722
#if defined (TODO)
......
3857 3855
    },
3858 3856
#endif
3859 3857
    /* Generic PowerPCs */
3860
#if defined (TODO) || 1
3858
#if defined (TODO)
3861 3859
    {
3862 3860
        .name        = "ppc64",
3863 3861
        .pvr         = CPU_PPC_970,
3864 3862
        .pvr_mask    = 0xFFFF0000,
3865 3863
        .insns_flags = PPC_INSNS_PPC64,
3866 3864
        .flags       = PPC_FLAGS_PPC64,
3867
        .msr_mask    = 0xA00000000204FF36,
3865
        .msr_mask    = 0xA00000000204FF36ULL,
3868 3866
    },
3869 3867
#endif
3870 3868
    {
......
3873 3871
        .pvr_mask    = 0xFFFFFFFF,
3874 3872
        .insns_flags = PPC_INSNS_PPC32,
3875 3873
        .flags       = PPC_FLAGS_PPC32,
3876
        .msr_mask    = 0x000000000005FF77,
3874
        .msr_mask    = 0x000000000005FF77ULL,
3877 3875
    },
3878 3876
    /* Fallback */
3879 3877
    {
......
3882 3880
        .pvr_mask    = 0xFFFFFFFF,
3883 3881
        .insns_flags = PPC_INSNS_PPC32,
3884 3882
        .flags       = PPC_FLAGS_PPC32,
3885
        .msr_mask    = 0x000000000005FF77,
3883
        .msr_mask    = 0x000000000005FF77ULL,
3886 3884
    },
3887 3885
};
3888 3886

  
b/vl.h
1172 1172
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1173 1173
                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
1174 1174
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1175
/* PowerPC 405 core */
1176
CPUPPCState *ppc405_init (const unsigned char *cpu_model,
1177
                          clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
1178
                          uint32_t sysclk);
1179
void ppc40x_core_reset (CPUState *env);
1180
void ppc40x_chip_reset (CPUState *env);
1181
void ppc40x_system_reset (CPUState *env);
1182
/* */
1183
typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
1184
int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
1185
                          uint32_t offset, uint32_t len,
1186
                          CPUReadMemoryFunc **mem_read,
1187
                          CPUWriteMemoryFunc **mem_write, void *opaque);
1188
ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, uint32_t base);
1189
/* PowerPC 4xx peripheral local bus arbitrer */
1190
void ppc4xx_plb_init (CPUState *env);
1191
/* PLB to OPB bridge */
1192
void ppc4xx_pob_init (CPUState *env);
1193
/* OPB arbitrer */
1194
void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
1195
/* PowerPC 4xx universal interrupt controller */
1196
enum {
1197
    PPCUIC_OUTPUT_INT = 0,
1198
    PPCUIC_OUTPUT_CINT = 1,
1199
    PPCUIC_OUTPUT_NB,
1200
};
1201
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
1202
                       uint32_t dcr_base, int has_ssr, int has_vr);
1203
/* SDRAM controller */
1204
void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
1205
                        target_ulong *ram_bases, target_ulong *ram_sizes);
1206
/* Peripheral controller */
1207
void ppc405_ebc_init (CPUState *env);
1208
/* DMA controller */
1209
void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
1210
/* GPIO */
1211
void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
1212
/* Serial ports */
1213
void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
1214
                         uint32_t offset, qemu_irq irq,
1215
                         CharDriverState *chr);
1216
/* On Chip Memory */
1217
void ppc405_ocm_init (CPUState *env, unsigned long offset);
1218
/* I2C controller */
1219
void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
1220
/* PowerPC 405 microcontrollers */
1221
CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4],
1222
                         uint32_t sysclk, qemu_irq **picp,
1223
                         ram_addr_t *offsetp);
1224
CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2],
1225
                         uint32_t sysclk, qemu_irq **picp,
1226
                         ram_addr_t *offsetp);
1227 1175
#endif
1228 1176
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1229 1177

  

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