Revision 04f20795 vl.h
b/vl.h | ||
---|---|---|
1172 | 1172 |
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
1173 | 1173 |
dcr_read_cb drc_read, dcr_write_cb dcr_write); |
1174 | 1174 |
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); |
1175 |
/* PowerPC 405 core */ |
|
1176 |
CPUPPCState *ppc405_init (const unsigned char *cpu_model, |
|
1177 |
clk_setup_t *cpu_clk, clk_setup_t *tb_clk, |
|
1178 |
uint32_t sysclk); |
|
1179 |
void ppc40x_core_reset (CPUState *env); |
|
1180 |
void ppc40x_chip_reset (CPUState *env); |
|
1181 |
void ppc40x_system_reset (CPUState *env); |
|
1182 |
/* */ |
|
1183 |
typedef struct ppc4xx_mmio_t ppc4xx_mmio_t; |
|
1184 |
int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio, |
|
1185 |
uint32_t offset, uint32_t len, |
|
1186 |
CPUReadMemoryFunc **mem_read, |
|
1187 |
CPUWriteMemoryFunc **mem_write, void *opaque); |
|
1188 |
ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, uint32_t base); |
|
1189 |
/* PowerPC 4xx peripheral local bus arbitrer */ |
|
1190 |
void ppc4xx_plb_init (CPUState *env); |
|
1191 |
/* PLB to OPB bridge */ |
|
1192 |
void ppc4xx_pob_init (CPUState *env); |
|
1193 |
/* OPB arbitrer */ |
|
1194 |
void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset); |
|
1195 |
/* PowerPC 4xx universal interrupt controller */ |
|
1196 |
enum { |
|
1197 |
PPCUIC_OUTPUT_INT = 0, |
|
1198 |
PPCUIC_OUTPUT_CINT = 1, |
|
1199 |
PPCUIC_OUTPUT_NB, |
|
1200 |
}; |
|
1201 |
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, |
|
1202 |
uint32_t dcr_base, int has_ssr, int has_vr); |
|
1203 |
/* SDRAM controller */ |
|
1204 |
void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, |
|
1205 |
target_ulong *ram_bases, target_ulong *ram_sizes); |
|
1206 |
/* Peripheral controller */ |
|
1207 |
void ppc405_ebc_init (CPUState *env); |
|
1208 |
/* DMA controller */ |
|
1209 |
void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]); |
|
1210 |
/* GPIO */ |
|
1211 |
void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset); |
|
1212 |
/* Serial ports */ |
|
1213 |
void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio, |
|
1214 |
uint32_t offset, qemu_irq irq, |
|
1215 |
CharDriverState *chr); |
|
1216 |
/* On Chip Memory */ |
|
1217 |
void ppc405_ocm_init (CPUState *env, unsigned long offset); |
|
1218 |
/* I2C controller */ |
|
1219 |
void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset); |
|
1220 |
/* PowerPC 405 microcontrollers */ |
|
1221 |
CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4], |
|
1222 |
uint32_t sysclk, qemu_irq **picp, |
|
1223 |
ram_addr_t *offsetp); |
|
1224 |
CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2], |
|
1225 |
uint32_t sysclk, qemu_irq **picp, |
|
1226 |
ram_addr_t *offsetp); |
|
1227 | 1175 |
#endif |
1228 | 1176 |
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1229 | 1177 |
|
Also available in: Unified diff