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1
/*
2
 *  PowerPC CPU initialization for qemu.
3
 * 
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
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 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20

    
21
/* A lot of PowerPC definition have been included here.
22
 * Most of them are not usable for now but have been kept
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 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24
 */
25

    
26
//#define PPC_DUMP_CPU
27
//#define PPC_DEBUG_SPR
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//#define PPC_DEBUG_IRQ
29

    
30
struct ppc_def_t {
31
    const unsigned char *name;
32
    uint32_t pvr;
33
    uint32_t pvr_mask;
34
    uint64_t insns_flags;
35
    uint32_t flags;
36
    uint64_t msr_mask;
37
};
38

    
39
/* For user-mode emulation, we don't emulate any IRQ controller */
40
#if defined(CONFIG_USER_ONLY)
41
#define PPC_IRQ_INIT_FN(name)                                         \
42
static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
43
{                                                                     \
44
}
45
#else
46
#define PPC_IRQ_INIT_FN(name)                                         \
47
void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
48
#endif
49
PPC_IRQ_INIT_FN(405);
50
PPC_IRQ_INIT_FN(6xx);
51
PPC_IRQ_INIT_FN(970);
52

    
53
/* Generic callbacks:
54
 * do nothing but store/retrieve spr value
55
 */
56
#ifdef PPC_DUMP_SPR_ACCESSES
57
static void spr_read_generic (void *opaque, int sprn)
58
{
59
    gen_op_load_dump_spr(sprn);
60
}
61

    
62
static void spr_write_generic (void *opaque, int sprn)
63
{
64
    gen_op_store_dump_spr(sprn);
65
}
66
#else
67
static void spr_read_generic (void *opaque, int sprn)
68
{
69
    gen_op_load_spr(sprn);
70
}
71

    
72
static void spr_write_generic (void *opaque, int sprn)
73
{
74
    gen_op_store_spr(sprn);
75
}
76
#endif
77

    
78
#if !defined(CONFIG_USER_ONLY)
79
static void spr_write_clear (void *opaque, int sprn)
80
{
81
    gen_op_mask_spr(sprn);
82
}
83
#endif
84

    
85
/* SPR common to all PowerPC */
86
/* XER */
87
static void spr_read_xer (void *opaque, int sprn)
88
{
89
    gen_op_load_xer();
90
}
91

    
92
static void spr_write_xer (void *opaque, int sprn)
93
{
94
    gen_op_store_xer();
95
}
96

    
97
/* LR */
98
static void spr_read_lr (void *opaque, int sprn)
99
{
100
    gen_op_load_lr();
101
}
102

    
103
static void spr_write_lr (void *opaque, int sprn)
104
{
105
    gen_op_store_lr();
106
}
107

    
108
/* CTR */
109
static void spr_read_ctr (void *opaque, int sprn)
110
{
111
    gen_op_load_ctr();
112
}
113

    
114
static void spr_write_ctr (void *opaque, int sprn)
115
{
116
    gen_op_store_ctr();
117
}
118

    
119
/* User read access to SPR */
120
/* USPRx */
121
/* UMMCRx */
122
/* UPMCx */
123
/* USIA */
124
/* UDECR */
125
static void spr_read_ureg (void *opaque, int sprn)
126
{
127
    gen_op_load_spr(sprn + 0x10);
128
}
129

    
130
/* SPR common to all non-embedded PowerPC */
131
/* DECR */
132
#if !defined(CONFIG_USER_ONLY)
133
static void spr_read_decr (void *opaque, int sprn)
134
{
135
    gen_op_load_decr();
136
}
137

    
138
static void spr_write_decr (void *opaque, int sprn)
139
{
140
    gen_op_store_decr();
141
}
142
#endif
143

    
144
/* SPR common to all non-embedded PowerPC, except 601 */
145
/* Time base */
146
static void spr_read_tbl (void *opaque, int sprn)
147
{
148
    gen_op_load_tbl();
149
}
150

    
151
static void spr_read_tbu (void *opaque, int sprn)
152
{
153
    gen_op_load_tbu();
154
}
155

    
156
#if !defined(CONFIG_USER_ONLY)
157
static void spr_write_tbl (void *opaque, int sprn)
158
{
159
    gen_op_store_tbl();
160
}
161

    
162
static void spr_write_tbu (void *opaque, int sprn)
163
{
164
    gen_op_store_tbu();
165
}
166
#endif
167

    
168
#if !defined(CONFIG_USER_ONLY)
169
/* IBAT0U...IBAT0U */
170
/* IBAT0L...IBAT7L */
171
static void spr_read_ibat (void *opaque, int sprn)
172
{
173
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
174
}
175

    
176
static void spr_read_ibat_h (void *opaque, int sprn)
177
{
178
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
179
}
180

    
181
static void spr_write_ibatu (void *opaque, int sprn)
182
{
183
    DisasContext *ctx = opaque;
184

    
185
    gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
186
    RET_STOP(ctx);
187
}
188

    
189
static void spr_write_ibatu_h (void *opaque, int sprn)
190
{
191
    DisasContext *ctx = opaque;
192

    
193
    gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
194
    RET_STOP(ctx);
195
}
196

    
197
static void spr_write_ibatl (void *opaque, int sprn)
198
{
199
    DisasContext *ctx = opaque;
200

    
201
    gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
202
    RET_STOP(ctx);
203
}
204

    
205
static void spr_write_ibatl_h (void *opaque, int sprn)
206
{
207
    DisasContext *ctx = opaque;
208

    
209
    gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
210
    RET_STOP(ctx);
211
}
212

    
213
/* DBAT0U...DBAT7U */
214
/* DBAT0L...DBAT7L */
215
static void spr_read_dbat (void *opaque, int sprn)
216
{
217
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
218
}
219

    
220
static void spr_read_dbat_h (void *opaque, int sprn)
221
{
222
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
223
}
224

    
225
static void spr_write_dbatu (void *opaque, int sprn)
226
{
227
    DisasContext *ctx = opaque;
228

    
229
    gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
230
    RET_STOP(ctx);
231
}
232

    
233
static void spr_write_dbatu_h (void *opaque, int sprn)
234
{
235
    DisasContext *ctx = opaque;
236

    
237
    gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
238
    RET_STOP(ctx);
239
}
240

    
241
static void spr_write_dbatl (void *opaque, int sprn)
242
{
243
    DisasContext *ctx = opaque;
244

    
245
    gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
246
    RET_STOP(ctx);
247
}
248

    
249
static void spr_write_dbatl_h (void *opaque, int sprn)
250
{
251
    DisasContext *ctx = opaque;
252

    
253
    gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
254
    RET_STOP(ctx);
255
}
256

    
257
/* SDR1 */
258
static void spr_read_sdr1 (void *opaque, int sprn)
259
{
260
    gen_op_load_sdr1();
261
}
262

    
263
static void spr_write_sdr1 (void *opaque, int sprn)
264
{
265
    DisasContext *ctx = opaque;
266

    
267
    gen_op_store_sdr1();
268
    RET_STOP(ctx);
269
}
270

    
271
/* 64 bits PowerPC specific SPRs */
272
/* ASR */
273
#if defined(TARGET_PPC64)
274
static void spr_read_asr (void *opaque, int sprn)
275
{
276
    gen_op_load_asr();
277
}
278

    
279
static void spr_write_asr (void *opaque, int sprn)
280
{
281
    DisasContext *ctx = opaque;
282

    
283
    gen_op_store_asr();
284
    RET_STOP(ctx);
285
}
286
#endif
287
#endif /* !defined(CONFIG_USER_ONLY) */
288

    
289
/* PowerPC 601 specific registers */
290
/* RTC */
291
static void spr_read_601_rtcl (void *opaque, int sprn)
292
{
293
    gen_op_load_601_rtcl();
294
}
295

    
296
static void spr_read_601_rtcu (void *opaque, int sprn)
297
{
298
    gen_op_load_601_rtcu();
299
}
300

    
301
#if !defined(CONFIG_USER_ONLY)
302
static void spr_write_601_rtcu (void *opaque, int sprn)
303
{
304
    gen_op_store_601_rtcu();
305
}
306

    
307
static void spr_write_601_rtcl (void *opaque, int sprn)
308
{
309
    gen_op_store_601_rtcl();
310
}
311
#endif
312

    
313
/* Unified bats */
314
#if !defined(CONFIG_USER_ONLY)
315
static void spr_read_601_ubat (void *opaque, int sprn)
316
{
317
    gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
318
}
319

    
320
static void spr_write_601_ubatu (void *opaque, int sprn)
321
{
322
    DisasContext *ctx = opaque;
323

    
324
    gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
325
    RET_STOP(ctx);
326
}
327

    
328
static void spr_write_601_ubatl (void *opaque, int sprn)
329
{
330
    DisasContext *ctx = opaque;
331

    
332
    gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
333
    RET_STOP(ctx);
334
}
335
#endif
336

    
337
/* PowerPC 40x specific registers */
338
#if !defined(CONFIG_USER_ONLY)
339
static void spr_read_40x_pit (void *opaque, int sprn)
340
{
341
    gen_op_load_40x_pit();
342
}
343

    
344
static void spr_write_40x_pit (void *opaque, int sprn)
345
{
346
    gen_op_store_40x_pit();
347
}
348

    
349
static void spr_write_40x_dbcr0 (void *opaque, int sprn)
350
{
351
    DisasContext *ctx = opaque;
352

    
353
    gen_op_store_40x_dbcr0();
354
    /* We must stop translation as we may have rebooted */
355
    RET_STOP(ctx);
356
}
357

    
358
static void spr_write_booke_tcr (void *opaque, int sprn)
359
{
360
    gen_op_store_booke_tcr();
361
}
362

    
363
static void spr_write_booke_tsr (void *opaque, int sprn)
364
{
365
    gen_op_store_booke_tsr();
366
}
367
#endif
368

    
369
/* PowerPC 403 specific registers */
370
/* PBL1 / PBU1 / PBL2 / PBU2 */
371
#if !defined(CONFIG_USER_ONLY)
372
static void spr_read_403_pbr (void *opaque, int sprn)
373
{
374
    gen_op_load_403_pb(sprn - SPR_403_PBL1);
375
}
376

    
377
static void spr_write_403_pbr (void *opaque, int sprn)
378
{
379
    DisasContext *ctx = opaque;
380

    
381
    gen_op_store_403_pb(sprn - SPR_403_PBL1);
382
    RET_STOP(ctx);
383
}
384

    
385
static void spr_write_pir (void *opaque, int sprn)
386
{
387
    gen_op_store_pir();
388
}
389
#endif
390

    
391
#if defined(CONFIG_USER_ONLY)
392
#define spr_register(env, num, name, uea_read, uea_write,                     \
393
                     oea_read, oea_write, initial_value)                      \
394
do {                                                                          \
395
     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
396
} while (0)
397
static inline void _spr_register (CPUPPCState *env, int num,
398
                                  const unsigned char *name,
399
                                  void (*uea_read)(void *opaque, int sprn),
400
                                  void (*uea_write)(void *opaque, int sprn),
401
                                  target_ulong initial_value)
402
#else
403
static inline void spr_register (CPUPPCState *env, int num,
404
                                 const unsigned char *name,
405
                                 void (*uea_read)(void *opaque, int sprn),
406
                                 void (*uea_write)(void *opaque, int sprn),
407
                                 void (*oea_read)(void *opaque, int sprn),
408
                                 void (*oea_write)(void *opaque, int sprn),
409
                                 target_ulong initial_value)
410
#endif
411
{
412
    ppc_spr_t *spr;
413

    
414
    spr = &env->spr_cb[num];
415
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
416
#if !defined(CONFIG_USER_ONLY)
417
        spr->oea_read != NULL || spr->oea_write != NULL ||
418
#endif
419
        spr->uea_read != NULL || spr->uea_write != NULL) {
420
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
421
        exit(1);
422
    }
423
#if defined(PPC_DEBUG_SPR)
424
    printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
425
           initial_value);
426
#endif
427
    spr->name = name;
428
    spr->uea_read = uea_read;
429
    spr->uea_write = uea_write;
430
#if !defined(CONFIG_USER_ONLY)
431
    spr->oea_read = oea_read;
432
    spr->oea_write = oea_write;
433
#endif
434
    env->spr[num] = initial_value;
435
}
436

    
437
/* Generic PowerPC SPRs */
438
static void gen_spr_generic (CPUPPCState *env)
439
{
440
    /* Integer processing */
441
    spr_register(env, SPR_XER, "XER",
442
                 &spr_read_xer, &spr_write_xer,
443
                 &spr_read_xer, &spr_write_xer,
444
                 0x00000000);
445
    /* Branch contol */
446
    spr_register(env, SPR_LR, "LR",
447
                 &spr_read_lr, &spr_write_lr,
448
                 &spr_read_lr, &spr_write_lr,
449
                 0x00000000);
450
    spr_register(env, SPR_CTR, "CTR",
451
                 &spr_read_ctr, &spr_write_ctr,
452
                 &spr_read_ctr, &spr_write_ctr,
453
                 0x00000000);
454
    /* Interrupt processing */
455
    spr_register(env, SPR_SRR0, "SRR0",
456
                 SPR_NOACCESS, SPR_NOACCESS,
457
                 &spr_read_generic, &spr_write_generic,
458
                 0x00000000);
459
    spr_register(env, SPR_SRR1, "SRR1",
460
                 SPR_NOACCESS, SPR_NOACCESS,
461
                 &spr_read_generic, &spr_write_generic,
462
                 0x00000000);
463
    /* Processor control */
464
    spr_register(env, SPR_SPRG0, "SPRG0",
465
                 SPR_NOACCESS, SPR_NOACCESS,
466
                 &spr_read_generic, &spr_write_generic,
467
                 0x00000000);
468
    spr_register(env, SPR_SPRG1, "SPRG1",
469
                 SPR_NOACCESS, SPR_NOACCESS,
470
                 &spr_read_generic, &spr_write_generic,
471
                 0x00000000);
472
    spr_register(env, SPR_SPRG2, "SPRG2",
473
                 SPR_NOACCESS, SPR_NOACCESS,
474
                 &spr_read_generic, &spr_write_generic,
475
                 0x00000000);
476
    spr_register(env, SPR_SPRG3, "SPRG3",
477
                 SPR_NOACCESS, SPR_NOACCESS,
478
                 &spr_read_generic, &spr_write_generic,
479
                 0x00000000);
480
}
481

    
482
/* SPR common to all non-embedded PowerPC, including 601 */
483
static void gen_spr_ne_601 (CPUPPCState *env)
484
{
485
    /* Exception processing */
486
    spr_register(env, SPR_DSISR, "DSISR",
487
                 SPR_NOACCESS, SPR_NOACCESS,
488
                 &spr_read_generic, &spr_write_generic,
489
                 0x00000000);
490
    spr_register(env, SPR_DAR, "DAR",
491
                 SPR_NOACCESS, SPR_NOACCESS,
492
                 &spr_read_generic, &spr_write_generic,
493
                 0x00000000);
494
    /* Timer */
495
    spr_register(env, SPR_DECR, "DECR",
496
                 SPR_NOACCESS, SPR_NOACCESS,
497
                 &spr_read_decr, &spr_write_decr,
498
                 0x00000000);
499
    /* Memory management */
500
    spr_register(env, SPR_SDR1, "SDR1",
501
                 SPR_NOACCESS, SPR_NOACCESS,
502
                 &spr_read_sdr1, &spr_write_sdr1,
503
                 0x00000000);
504
}
505

    
506
/* BATs 0-3 */
507
static void gen_low_BATs (CPUPPCState *env)
508
{
509
    spr_register(env, SPR_IBAT0U, "IBAT0U",
510
                 SPR_NOACCESS, SPR_NOACCESS,
511
                 &spr_read_ibat, &spr_write_ibatu,
512
                 0x00000000);
513
    spr_register(env, SPR_IBAT0L, "IBAT0L",
514
                 SPR_NOACCESS, SPR_NOACCESS,
515
                 &spr_read_ibat, &spr_write_ibatl,
516
                 0x00000000);
517
    spr_register(env, SPR_IBAT1U, "IBAT1U",
518
                 SPR_NOACCESS, SPR_NOACCESS,
519
                 &spr_read_ibat, &spr_write_ibatu,
520
                 0x00000000);
521
    spr_register(env, SPR_IBAT1L, "IBAT1L",
522
                 SPR_NOACCESS, SPR_NOACCESS,
523
                 &spr_read_ibat, &spr_write_ibatl,
524
                 0x00000000);
525
    spr_register(env, SPR_IBAT2U, "IBAT2U",
526
                 SPR_NOACCESS, SPR_NOACCESS,
527
                 &spr_read_ibat, &spr_write_ibatu,
528
                 0x00000000);
529
    spr_register(env, SPR_IBAT2L, "IBAT2L",
530
                 SPR_NOACCESS, SPR_NOACCESS,
531
                 &spr_read_ibat, &spr_write_ibatl,
532
                 0x00000000);
533
    spr_register(env, SPR_IBAT3U, "IBAT3U",
534
                 SPR_NOACCESS, SPR_NOACCESS,
535
                 &spr_read_ibat, &spr_write_ibatu,
536
                 0x00000000);
537
    spr_register(env, SPR_IBAT3L, "IBAT3L",
538
                 SPR_NOACCESS, SPR_NOACCESS,
539
                 &spr_read_ibat, &spr_write_ibatl,
540
                 0x00000000);
541
    spr_register(env, SPR_DBAT0U, "DBAT0U",
542
                 SPR_NOACCESS, SPR_NOACCESS,
543
                 &spr_read_dbat, &spr_write_dbatu,
544
                 0x00000000);
545
    spr_register(env, SPR_DBAT0L, "DBAT0L",
546
                 SPR_NOACCESS, SPR_NOACCESS,
547
                 &spr_read_dbat, &spr_write_dbatl,
548
                 0x00000000);
549
    spr_register(env, SPR_DBAT1U, "DBAT1U",
550
                 SPR_NOACCESS, SPR_NOACCESS,
551
                 &spr_read_dbat, &spr_write_dbatu,
552
                 0x00000000);
553
    spr_register(env, SPR_DBAT1L, "DBAT1L",
554
                 SPR_NOACCESS, SPR_NOACCESS,
555
                 &spr_read_dbat, &spr_write_dbatl,
556
                 0x00000000);
557
    spr_register(env, SPR_DBAT2U, "DBAT2U",
558
                 SPR_NOACCESS, SPR_NOACCESS,
559
                 &spr_read_dbat, &spr_write_dbatu,
560
                 0x00000000);
561
    spr_register(env, SPR_DBAT2L, "DBAT2L",
562
                 SPR_NOACCESS, SPR_NOACCESS,
563
                 &spr_read_dbat, &spr_write_dbatl,
564
                 0x00000000);
565
    spr_register(env, SPR_DBAT3U, "DBAT3U",
566
                 SPR_NOACCESS, SPR_NOACCESS,
567
                 &spr_read_dbat, &spr_write_dbatu,
568
                 0x00000000);
569
    spr_register(env, SPR_DBAT3L, "DBAT3L",
570
                 SPR_NOACCESS, SPR_NOACCESS,
571
                 &spr_read_dbat, &spr_write_dbatl,
572
                 0x00000000);
573
    env->nb_BATs = 4;
574
}
575

    
576
/* BATs 4-7 */
577
static void gen_high_BATs (CPUPPCState *env)
578
{
579
    spr_register(env, SPR_IBAT4U, "IBAT4U",
580
                 SPR_NOACCESS, SPR_NOACCESS,
581
                 &spr_read_ibat_h, &spr_write_ibatu_h,
582
                 0x00000000);
583
    spr_register(env, SPR_IBAT4L, "IBAT4L",
584
                 SPR_NOACCESS, SPR_NOACCESS,
585
                 &spr_read_ibat_h, &spr_write_ibatl_h,
586
                 0x00000000);
587
    spr_register(env, SPR_IBAT5U, "IBAT5U",
588
                 SPR_NOACCESS, SPR_NOACCESS,
589
                 &spr_read_ibat_h, &spr_write_ibatu_h,
590
                 0x00000000);
591
    spr_register(env, SPR_IBAT5L, "IBAT5L",
592
                 SPR_NOACCESS, SPR_NOACCESS,
593
                 &spr_read_ibat_h, &spr_write_ibatl_h,
594
                 0x00000000);
595
    spr_register(env, SPR_IBAT6U, "IBAT6U",
596
                 SPR_NOACCESS, SPR_NOACCESS,
597
                 &spr_read_ibat_h, &spr_write_ibatu_h,
598
                 0x00000000);
599
    spr_register(env, SPR_IBAT6L, "IBAT6L",
600
                 SPR_NOACCESS, SPR_NOACCESS,
601
                 &spr_read_ibat_h, &spr_write_ibatl_h,
602
                 0x00000000);
603
    spr_register(env, SPR_IBAT7U, "IBAT7U",
604
                 SPR_NOACCESS, SPR_NOACCESS,
605
                 &spr_read_ibat_h, &spr_write_ibatu_h,
606
                 0x00000000);
607
    spr_register(env, SPR_IBAT7L, "IBAT7L",
608
                 SPR_NOACCESS, SPR_NOACCESS,
609
                 &spr_read_ibat_h, &spr_write_ibatl_h,
610
                 0x00000000);
611
    spr_register(env, SPR_DBAT4U, "DBAT4U",
612
                 SPR_NOACCESS, SPR_NOACCESS,
613
                 &spr_read_dbat_h, &spr_write_dbatu_h,
614
                 0x00000000);
615
    spr_register(env, SPR_DBAT4L, "DBAT4L",
616
                 SPR_NOACCESS, SPR_NOACCESS,
617
                 &spr_read_dbat_h, &spr_write_dbatl_h,
618
                 0x00000000);
619
    spr_register(env, SPR_DBAT5U, "DBAT5U",
620
                 SPR_NOACCESS, SPR_NOACCESS,
621
                 &spr_read_dbat_h, &spr_write_dbatu_h,
622
                 0x00000000);
623
    spr_register(env, SPR_DBAT5L, "DBAT5L",
624
                 SPR_NOACCESS, SPR_NOACCESS,
625
                 &spr_read_dbat_h, &spr_write_dbatl_h,
626
                 0x00000000);
627
    spr_register(env, SPR_DBAT6U, "DBAT6U",
628
                 SPR_NOACCESS, SPR_NOACCESS,
629
                 &spr_read_dbat_h, &spr_write_dbatu_h,
630
                 0x00000000);
631
    spr_register(env, SPR_DBAT6L, "DBAT6L",
632
                 SPR_NOACCESS, SPR_NOACCESS,
633
                 &spr_read_dbat_h, &spr_write_dbatl_h,
634
                 0x00000000);
635
    spr_register(env, SPR_DBAT7U, "DBAT7U",
636
                 SPR_NOACCESS, SPR_NOACCESS,
637
                 &spr_read_dbat_h, &spr_write_dbatu_h,
638
                 0x00000000);
639
    spr_register(env, SPR_DBAT7L, "DBAT7L",
640
                 SPR_NOACCESS, SPR_NOACCESS,
641
                 &spr_read_dbat_h, &spr_write_dbatl_h,
642
                 0x00000000);
643
    env->nb_BATs = 8;
644
}
645

    
646
/* Generic PowerPC time base */
647
static void gen_tbl (CPUPPCState *env)
648
{
649
    spr_register(env, SPR_VTBL,  "TBL",
650
                 &spr_read_tbl, SPR_NOACCESS,
651
                 &spr_read_tbl, SPR_NOACCESS,
652
                 0x00000000);
653
    spr_register(env, SPR_TBL,   "TBL",
654
                 SPR_NOACCESS, SPR_NOACCESS,
655
                 SPR_NOACCESS, &spr_write_tbl,
656
                 0x00000000);
657
    spr_register(env, SPR_VTBU,  "TBU",
658
                 &spr_read_tbu, SPR_NOACCESS,
659
                 &spr_read_tbu, SPR_NOACCESS,
660
                 0x00000000);
661
    spr_register(env, SPR_TBU,   "TBU",
662
                 SPR_NOACCESS, SPR_NOACCESS,
663
                 SPR_NOACCESS, &spr_write_tbu,
664
                 0x00000000);
665
}
666

    
667
/* Softare table search registers */
668
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
669
{
670
    env->nb_tlb = nb_tlbs;
671
    env->nb_ways = nb_ways;
672
    env->id_tlbs = 1;
673
    spr_register(env, SPR_DMISS, "DMISS",
674
                 SPR_NOACCESS, SPR_NOACCESS,
675
                 &spr_read_generic, SPR_NOACCESS,
676
                 0x00000000);
677
    spr_register(env, SPR_DCMP, "DCMP",
678
                 SPR_NOACCESS, SPR_NOACCESS,
679
                 &spr_read_generic, SPR_NOACCESS,
680
                 0x00000000);
681
    spr_register(env, SPR_HASH1, "HASH1",
682
                 SPR_NOACCESS, SPR_NOACCESS,
683
                 &spr_read_generic, SPR_NOACCESS,
684
                 0x00000000);
685
    spr_register(env, SPR_HASH2, "HASH2",
686
                 SPR_NOACCESS, SPR_NOACCESS,
687
                 &spr_read_generic, SPR_NOACCESS,
688
                 0x00000000);
689
    spr_register(env, SPR_IMISS, "IMISS",
690
                 SPR_NOACCESS, SPR_NOACCESS,
691
                 &spr_read_generic, SPR_NOACCESS,
692
                 0x00000000);
693
    spr_register(env, SPR_ICMP, "ICMP",
694
                 SPR_NOACCESS, SPR_NOACCESS,
695
                 &spr_read_generic, SPR_NOACCESS,
696
                 0x00000000);
697
    spr_register(env, SPR_RPA, "RPA",
698
                 SPR_NOACCESS, SPR_NOACCESS,
699
                 &spr_read_generic, &spr_write_generic,
700
                 0x00000000);
701
}
702

    
703
/* SPR common to MPC755 and G2 */
704
static void gen_spr_G2_755 (CPUPPCState *env)
705
{
706
    /* SGPRs */
707
    spr_register(env, SPR_SPRG4, "SPRG4",
708
                 SPR_NOACCESS, SPR_NOACCESS,
709
                 &spr_read_generic, &spr_write_generic,
710
                 0x00000000);
711
    spr_register(env, SPR_SPRG5, "SPRG5",
712
                 SPR_NOACCESS, SPR_NOACCESS,
713
                 &spr_read_generic, &spr_write_generic,
714
                 0x00000000);
715
    spr_register(env, SPR_SPRG6, "SPRG6",
716
                 SPR_NOACCESS, SPR_NOACCESS,
717
                 &spr_read_generic, &spr_write_generic,
718
                 0x00000000);
719
    spr_register(env, SPR_SPRG7, "SPRG7",
720
                 SPR_NOACCESS, SPR_NOACCESS,
721
                 &spr_read_generic, &spr_write_generic,
722
                 0x00000000);
723
    /* External access control */
724
    /* XXX : not implemented */
725
    spr_register(env, SPR_EAR, "EAR",
726
                 SPR_NOACCESS, SPR_NOACCESS,
727
                 &spr_read_generic, &spr_write_generic,
728
                 0x00000000);
729
}
730

    
731
/* SPR common to all 7xx PowerPC implementations */
732
static void gen_spr_7xx (CPUPPCState *env)
733
{
734
    /* Breakpoints */
735
    /* XXX : not implemented */
736
    spr_register(env, SPR_DABR, "DABR",
737
                 SPR_NOACCESS, SPR_NOACCESS,
738
                 &spr_read_generic, &spr_write_generic,
739
                 0x00000000);
740
    /* XXX : not implemented */
741
    spr_register(env, SPR_IABR, "IABR",
742
                 SPR_NOACCESS, SPR_NOACCESS,
743
                 &spr_read_generic, &spr_write_generic,
744
                 0x00000000);
745
    /* Cache management */
746
    /* XXX : not implemented */
747
    spr_register(env, SPR_ICTC, "ICTC",
748
                 SPR_NOACCESS, SPR_NOACCESS,
749
                 &spr_read_generic, &spr_write_generic,
750
                 0x00000000);
751
    /* XXX : not implemented */
752
    spr_register(env, SPR_L2CR, "L2CR",
753
                 SPR_NOACCESS, SPR_NOACCESS,
754
                 &spr_read_generic, &spr_write_generic,
755
                 0x00000000);
756
    /* Performance monitors */
757
    /* XXX : not implemented */
758
    spr_register(env, SPR_MMCR0, "MMCR0",
759
                 SPR_NOACCESS, SPR_NOACCESS,
760
                 &spr_read_generic, &spr_write_generic,
761
                 0x00000000);
762
    /* XXX : not implemented */
763
    spr_register(env, SPR_MMCR1, "MMCR1",
764
                 SPR_NOACCESS, SPR_NOACCESS,
765
                 &spr_read_generic, &spr_write_generic,
766
                 0x00000000);
767
    /* XXX : not implemented */
768
    spr_register(env, SPR_PMC1, "PMC1",
769
                 SPR_NOACCESS, SPR_NOACCESS,
770
                 &spr_read_generic, &spr_write_generic,
771
                 0x00000000);
772
    /* XXX : not implemented */
773
    spr_register(env, SPR_PMC2, "PMC2",
774
                 SPR_NOACCESS, SPR_NOACCESS,
775
                 &spr_read_generic, &spr_write_generic,
776
                 0x00000000);
777
    /* XXX : not implemented */
778
    spr_register(env, SPR_PMC3, "PMC3",
779
                 SPR_NOACCESS, SPR_NOACCESS,
780
                 &spr_read_generic, &spr_write_generic,
781
                 0x00000000);
782
    /* XXX : not implemented */
783
    spr_register(env, SPR_PMC4, "PMC4",
784
                 SPR_NOACCESS, SPR_NOACCESS,
785
                 &spr_read_generic, &spr_write_generic,
786
                 0x00000000);
787
    /* XXX : not implemented */
788
    spr_register(env, SPR_SIA, "SIA",
789
                 SPR_NOACCESS, SPR_NOACCESS,
790
                 &spr_read_generic, SPR_NOACCESS,
791
                 0x00000000);
792
    spr_register(env, SPR_UMMCR0, "UMMCR0",
793
                 &spr_read_ureg, SPR_NOACCESS,
794
                 &spr_read_ureg, SPR_NOACCESS,
795
                 0x00000000);
796
    spr_register(env, SPR_UMMCR1, "UMMCR1",
797
                 &spr_read_ureg, SPR_NOACCESS,
798
                 &spr_read_ureg, SPR_NOACCESS,
799
                 0x00000000);
800
    spr_register(env, SPR_UPMC1, "UPMC1",
801
                 &spr_read_ureg, SPR_NOACCESS,
802
                 &spr_read_ureg, SPR_NOACCESS,
803
                 0x00000000);
804
    spr_register(env, SPR_UPMC2, "UPMC2",
805
                 &spr_read_ureg, SPR_NOACCESS,
806
                 &spr_read_ureg, SPR_NOACCESS,
807
                 0x00000000);
808
    spr_register(env, SPR_UPMC3, "UPMC3",
809
                 &spr_read_ureg, SPR_NOACCESS,
810
                 &spr_read_ureg, SPR_NOACCESS,
811
                 0x00000000);
812
    spr_register(env, SPR_UPMC4, "UPMC4",
813
                 &spr_read_ureg, SPR_NOACCESS,
814
                 &spr_read_ureg, SPR_NOACCESS,
815
                 0x00000000);
816
    spr_register(env, SPR_USIA, "USIA",
817
                 &spr_read_ureg, SPR_NOACCESS,
818
                 &spr_read_ureg, SPR_NOACCESS,
819
                 0x00000000);
820
    /* Thermal management */
821
    /* XXX : not implemented */
822
    spr_register(env, SPR_THRM1, "THRM1",
823
                 SPR_NOACCESS, SPR_NOACCESS,
824
                 &spr_read_generic, &spr_write_generic,
825
                 0x00000000);
826
    /* XXX : not implemented */
827
    spr_register(env, SPR_THRM2, "THRM2",
828
                 SPR_NOACCESS, SPR_NOACCESS,
829
                 &spr_read_generic, &spr_write_generic,
830
                 0x00000000);
831
    /* XXX : not implemented */
832
    spr_register(env, SPR_THRM3, "THRM3",
833
                 SPR_NOACCESS, SPR_NOACCESS,
834
                 &spr_read_generic, &spr_write_generic,
835
                 0x00000000);
836
    /* External access control */
837
    /* XXX : not implemented */
838
    spr_register(env, SPR_EAR, "EAR",
839
                 SPR_NOACCESS, SPR_NOACCESS,
840
                 &spr_read_generic, &spr_write_generic,
841
                 0x00000000);
842
}
843

    
844
/* SPR specific to PowerPC 604 implementation */
845
static void gen_spr_604 (CPUPPCState *env)
846
{
847
    /* Processor identification */
848
    spr_register(env, SPR_PIR, "PIR",
849
                 SPR_NOACCESS, SPR_NOACCESS,
850
                 &spr_read_generic, &spr_write_pir,
851
                 0x00000000);
852
    /* Breakpoints */
853
    /* XXX : not implemented */
854
    spr_register(env, SPR_IABR, "IABR",
855
                 SPR_NOACCESS, SPR_NOACCESS,
856
                 &spr_read_generic, &spr_write_generic,
857
                 0x00000000);
858
    /* XXX : not implemented */
859
    spr_register(env, SPR_DABR, "DABR",
860
                 SPR_NOACCESS, SPR_NOACCESS,
861
                 &spr_read_generic, &spr_write_generic,
862
                 0x00000000);
863
    /* Performance counters */
864
    /* XXX : not implemented */
865
    spr_register(env, SPR_MMCR0, "MMCR0",
866
                 SPR_NOACCESS, SPR_NOACCESS,
867
                 &spr_read_generic, &spr_write_generic,
868
                 0x00000000);
869
    /* XXX : not implemented */
870
    spr_register(env, SPR_MMCR1, "MMCR1",
871
                 SPR_NOACCESS, SPR_NOACCESS,
872
                 &spr_read_generic, &spr_write_generic,
873
                 0x00000000);
874
    /* XXX : not implemented */
875
    spr_register(env, SPR_PMC1, "PMC1",
876
                 SPR_NOACCESS, SPR_NOACCESS,
877
                 &spr_read_generic, &spr_write_generic,
878
                 0x00000000);
879
    /* XXX : not implemented */
880
    spr_register(env, SPR_PMC2, "PMC2",
881
                 SPR_NOACCESS, SPR_NOACCESS,
882
                 &spr_read_generic, &spr_write_generic,
883
                 0x00000000);
884
    /* XXX : not implemented */
885
    spr_register(env, SPR_PMC3, "PMC3",
886
                 SPR_NOACCESS, SPR_NOACCESS,
887
                 &spr_read_generic, &spr_write_generic,
888
                 0x00000000);
889
    /* XXX : not implemented */
890
    spr_register(env, SPR_PMC4, "PMC4",
891
                 SPR_NOACCESS, SPR_NOACCESS,
892
                 &spr_read_generic, &spr_write_generic,
893
                 0x00000000);
894
    /* XXX : not implemented */
895
    spr_register(env, SPR_SIA, "SIA",
896
                 SPR_NOACCESS, SPR_NOACCESS,
897
                 &spr_read_generic, SPR_NOACCESS,
898
                 0x00000000);
899
    /* XXX : not implemented */
900
    spr_register(env, SPR_SDA, "SDA",
901
                 SPR_NOACCESS, SPR_NOACCESS,
902
                 &spr_read_generic, SPR_NOACCESS,
903
                 0x00000000);
904
    /* External access control */
905
    /* XXX : not implemented */
906
    spr_register(env, SPR_EAR, "EAR",
907
                 SPR_NOACCESS, SPR_NOACCESS,
908
                 &spr_read_generic, &spr_write_generic,
909
                 0x00000000);
910
}
911

    
912
/* SPR specific to PowerPC 603 implementation */
913
static void gen_spr_603 (CPUPPCState *env)
914
{
915
    /* External access control */
916
    /* XXX : not implemented */
917
    spr_register(env, SPR_EAR, "EAR",
918
                 SPR_NOACCESS, SPR_NOACCESS,
919
                 &spr_read_generic, &spr_write_generic,
920
                 0x00000000);
921
}
922

    
923
/* SPR specific to PowerPC G2 implementation */
924
static void gen_spr_G2 (CPUPPCState *env)
925
{
926
    /* Memory base address */
927
    /* MBAR */
928
    spr_register(env, SPR_MBAR, "MBAR",
929
                 SPR_NOACCESS, SPR_NOACCESS,
930
                 &spr_read_generic, &spr_write_generic,
931
                 0x00000000);
932
    /* System version register */
933
    /* SVR */
934
    spr_register(env, SPR_SVR, "SVR",
935
                 SPR_NOACCESS, SPR_NOACCESS,
936
                 &spr_read_generic, SPR_NOACCESS,
937
                 0x00000000);
938
    /* Exception processing */
939
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
940
                 SPR_NOACCESS, SPR_NOACCESS,
941
                 &spr_read_generic, &spr_write_generic,
942
                 0x00000000);
943
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
944
                 SPR_NOACCESS, SPR_NOACCESS,
945
                 &spr_read_generic, &spr_write_generic,
946
                 0x00000000);
947
    /* Breakpoints */
948
    /* XXX : not implemented */
949
    spr_register(env, SPR_DABR, "DABR",
950
                 SPR_NOACCESS, SPR_NOACCESS,
951
                 &spr_read_generic, &spr_write_generic,
952
                 0x00000000);
953
    /* XXX : not implemented */
954
    spr_register(env, SPR_DABR2, "DABR2",
955
                 SPR_NOACCESS, SPR_NOACCESS,
956
                 &spr_read_generic, &spr_write_generic,
957
                 0x00000000);
958
    /* XXX : not implemented */
959
    spr_register(env, SPR_IABR, "IABR",
960
                 SPR_NOACCESS, SPR_NOACCESS,
961
                 &spr_read_generic, &spr_write_generic,
962
                 0x00000000);
963
    /* XXX : not implemented */
964
    spr_register(env, SPR_IABR2, "IABR2",
965
                 SPR_NOACCESS, SPR_NOACCESS,
966
                 &spr_read_generic, &spr_write_generic,
967
                 0x00000000);
968
    /* XXX : not implemented */
969
    spr_register(env, SPR_IBCR, "IBCR",
970
                 SPR_NOACCESS, SPR_NOACCESS,
971
                 &spr_read_generic, &spr_write_generic,
972
                 0x00000000);
973
    /* XXX : not implemented */
974
    spr_register(env, SPR_DBCR, "DBCR",
975
                 SPR_NOACCESS, SPR_NOACCESS,
976
                 &spr_read_generic, &spr_write_generic,
977
                 0x00000000);
978
}
979

    
980
/* SPR specific to PowerPC 602 implementation */
981
static void gen_spr_602 (CPUPPCState *env)
982
{
983
    /* ESA registers */
984
    /* XXX : not implemented */
985
    spr_register(env, SPR_SER, "SER",
986
                 SPR_NOACCESS, SPR_NOACCESS,
987
                 &spr_read_generic, &spr_write_generic,
988
                 0x00000000);
989
    /* XXX : not implemented */
990
    spr_register(env, SPR_SEBR, "SEBR",
991
                 SPR_NOACCESS, SPR_NOACCESS,
992
                 &spr_read_generic, &spr_write_generic,
993
                 0x00000000);
994
    /* XXX : not implemented */
995
    spr_register(env, SPR_ESASR, "ESASR",
996
                 SPR_NOACCESS, SPR_NOACCESS,
997
                 &spr_read_generic, &spr_write_generic,
998
                 0x00000000);
999
    /* Floating point status */
1000
    /* XXX : not implemented */
1001
    spr_register(env, SPR_SP, "SP",
1002
                 SPR_NOACCESS, SPR_NOACCESS,
1003
                 &spr_read_generic, &spr_write_generic,
1004
                 0x00000000);
1005
    /* XXX : not implemented */
1006
    spr_register(env, SPR_LT, "LT",
1007
                 SPR_NOACCESS, SPR_NOACCESS,
1008
                 &spr_read_generic, &spr_write_generic,
1009
                 0x00000000);
1010
    /* Watchdog timer */
1011
    /* XXX : not implemented */
1012
    spr_register(env, SPR_TCR, "TCR",
1013
                 SPR_NOACCESS, SPR_NOACCESS,
1014
                 &spr_read_generic, &spr_write_generic,
1015
                 0x00000000);
1016
    /* Interrupt base */
1017
    spr_register(env, SPR_IBR, "IBR",
1018
                 SPR_NOACCESS, SPR_NOACCESS,
1019
                 &spr_read_generic, &spr_write_generic,
1020
                 0x00000000);
1021
}
1022

    
1023
/* SPR specific to PowerPC 601 implementation */
1024
static void gen_spr_601 (CPUPPCState *env)
1025
{
1026
    /* Multiplication/division register */
1027
    /* MQ */
1028
    spr_register(env, SPR_MQ, "MQ",
1029
                 &spr_read_generic, &spr_write_generic,
1030
                 &spr_read_generic, &spr_write_generic,
1031
                 0x00000000);
1032
    /* RTC registers */
1033
    spr_register(env, SPR_601_RTCU, "RTCU",
1034
                 SPR_NOACCESS, SPR_NOACCESS,
1035
                 SPR_NOACCESS, &spr_write_601_rtcu,
1036
                 0x00000000);
1037
    spr_register(env, SPR_601_VRTCU, "RTCU",
1038
                 &spr_read_601_rtcu, SPR_NOACCESS,
1039
                 &spr_read_601_rtcu, SPR_NOACCESS,
1040
                 0x00000000);
1041
    spr_register(env, SPR_601_RTCL, "RTCL",
1042
                 SPR_NOACCESS, SPR_NOACCESS,
1043
                 SPR_NOACCESS, &spr_write_601_rtcl,
1044
                 0x00000000);
1045
    spr_register(env, SPR_601_VRTCL, "RTCL",
1046
                 &spr_read_601_rtcl, SPR_NOACCESS,
1047
                 &spr_read_601_rtcl, SPR_NOACCESS,
1048
                 0x00000000);
1049
    /* Timer */
1050
#if 0 /* ? */
1051
    spr_register(env, SPR_601_UDECR, "UDECR",
1052
                 &spr_read_decr, SPR_NOACCESS,
1053
                 &spr_read_decr, SPR_NOACCESS,
1054
                 0x00000000);
1055
#endif
1056
    /* External access control */
1057
    /* XXX : not implemented */
1058
    spr_register(env, SPR_EAR, "EAR",
1059
                 SPR_NOACCESS, SPR_NOACCESS,
1060
                 &spr_read_generic, &spr_write_generic,
1061
                 0x00000000);
1062
    /* Memory management */
1063
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1064
                 SPR_NOACCESS, SPR_NOACCESS,
1065
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1066
                 0x00000000);
1067
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1068
                 SPR_NOACCESS, SPR_NOACCESS,
1069
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1070
                 0x00000000);
1071
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1072
                 SPR_NOACCESS, SPR_NOACCESS,
1073
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1074
                 0x00000000);
1075
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1076
                 SPR_NOACCESS, SPR_NOACCESS,
1077
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1078
                 0x00000000);
1079
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1080
                 SPR_NOACCESS, SPR_NOACCESS,
1081
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1082
                 0x00000000);
1083
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1084
                 SPR_NOACCESS, SPR_NOACCESS,
1085
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1086
                 0x00000000);
1087
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1088
                 SPR_NOACCESS, SPR_NOACCESS,
1089
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1090
                 0x00000000);
1091
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1092
                 SPR_NOACCESS, SPR_NOACCESS,
1093
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1094
                 0x00000000);
1095
}
1096

    
1097
/* PowerPC BookE SPR */
1098
static void gen_spr_BookE (CPUPPCState *env)
1099
{
1100
    /* Processor identification */
1101
    spr_register(env, SPR_BOOKE_PIR, "PIR",
1102
                 SPR_NOACCESS, SPR_NOACCESS,
1103
                 &spr_read_generic, &spr_write_pir,
1104
                 0x00000000);
1105
    /* Interrupt processing */
1106
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1107
                 SPR_NOACCESS, SPR_NOACCESS,
1108
                 &spr_read_generic, &spr_write_generic,
1109
                 0x00000000);
1110
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1111
                 SPR_NOACCESS, SPR_NOACCESS,
1112
                 &spr_read_generic, &spr_write_generic,
1113
                 0x00000000);
1114
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1115
                 SPR_NOACCESS, SPR_NOACCESS,
1116
                 &spr_read_generic, &spr_write_generic,
1117
                 0x00000000);
1118
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1119
                 SPR_NOACCESS, SPR_NOACCESS,
1120
                 &spr_read_generic, &spr_write_generic,
1121
                 0x00000000);
1122
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
1123
                 SPR_NOACCESS, SPR_NOACCESS,
1124
                 &spr_read_generic, &spr_write_generic,
1125
                 0x00000000);
1126
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
1127
                 SPR_NOACCESS, SPR_NOACCESS,
1128
                 &spr_read_generic, &spr_write_generic,
1129
                 0x00000000);
1130
    /* Debug */
1131
    /* XXX : not implemented */
1132
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1133
                 SPR_NOACCESS, SPR_NOACCESS,
1134
                 &spr_read_generic, &spr_write_generic,
1135
                 0x00000000);
1136
    /* XXX : not implemented */
1137
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1138
                 SPR_NOACCESS, SPR_NOACCESS,
1139
                 &spr_read_generic, &spr_write_generic,
1140
                 0x00000000);
1141
    /* XXX : not implemented */
1142
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1143
                 SPR_NOACCESS, SPR_NOACCESS,
1144
                 &spr_read_generic, &spr_write_generic,
1145
                 0x00000000);
1146
    /* XXX : not implemented */
1147
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1148
                 SPR_NOACCESS, SPR_NOACCESS,
1149
                 &spr_read_generic, &spr_write_generic,
1150
                 0x00000000);
1151
    /* XXX : not implemented */
1152
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1153
                 SPR_NOACCESS, SPR_NOACCESS,
1154
                 &spr_read_generic, &spr_write_generic,
1155
                 0x00000000);
1156
    /* XXX : not implemented */
1157
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1158
                 SPR_NOACCESS, SPR_NOACCESS,
1159
                 &spr_read_generic, &spr_write_generic,
1160
                 0x00000000);
1161
    /* XXX : not implemented */
1162
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1163
                 SPR_NOACCESS, SPR_NOACCESS,
1164
                 &spr_read_generic, &spr_write_generic,
1165
                 0x00000000);
1166
    /* XXX : not implemented */
1167
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1168
                 SPR_NOACCESS, SPR_NOACCESS,
1169
                 &spr_read_generic, &spr_write_generic,
1170
                 0x00000000);
1171
    /* XXX : not implemented */
1172
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1173
                 SPR_NOACCESS, SPR_NOACCESS,
1174
                 &spr_read_generic, &spr_write_generic,
1175
                 0x00000000);
1176
    /* XXX : not implemented */
1177
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1178
                 SPR_NOACCESS, SPR_NOACCESS,
1179
                 &spr_read_generic, &spr_write_generic,
1180
                 0x00000000);
1181
    /* XXX : not implemented */
1182
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1183
                 SPR_NOACCESS, SPR_NOACCESS,
1184
                 &spr_read_generic, &spr_write_generic,
1185
                 0x00000000);
1186
    /* XXX : not implemented */
1187
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1188
                 SPR_NOACCESS, SPR_NOACCESS,
1189
                 &spr_read_generic, &spr_write_clear,
1190
                 0x00000000);
1191
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1192
                 SPR_NOACCESS, SPR_NOACCESS,
1193
                 &spr_read_generic, &spr_write_generic,
1194
                 0x00000000);
1195
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1196
                 SPR_NOACCESS, SPR_NOACCESS,
1197
                 &spr_read_generic, &spr_write_generic,
1198
                 0x00000000);
1199
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1200
                 SPR_NOACCESS, SPR_NOACCESS,
1201
                 &spr_read_generic, &spr_write_generic,
1202
                 0x00000000);
1203
    /* Exception vectors */
1204
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1205
                 SPR_NOACCESS, SPR_NOACCESS,
1206
                 &spr_read_generic, &spr_write_generic,
1207
                 0x00000000);
1208
    spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1209
                 SPR_NOACCESS, SPR_NOACCESS,
1210
                 &spr_read_generic, &spr_write_generic,
1211
                 0x00000000);
1212
    spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1213
                 SPR_NOACCESS, SPR_NOACCESS,
1214
                 &spr_read_generic, &spr_write_generic,
1215
                 0x00000000);
1216
    spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1217
                 SPR_NOACCESS, SPR_NOACCESS,
1218
                 &spr_read_generic, &spr_write_generic,
1219
                 0x00000000);
1220
    spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1221
                 SPR_NOACCESS, SPR_NOACCESS,
1222
                 &spr_read_generic, &spr_write_generic,
1223
                 0x00000000);
1224
    spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1225
                 SPR_NOACCESS, SPR_NOACCESS,
1226
                 &spr_read_generic, &spr_write_generic,
1227
                 0x00000000);
1228
    spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1229
                 SPR_NOACCESS, SPR_NOACCESS,
1230
                 &spr_read_generic, &spr_write_generic,
1231
                 0x00000000);
1232
    spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1233
                 SPR_NOACCESS, SPR_NOACCESS,
1234
                 &spr_read_generic, &spr_write_generic,
1235
                 0x00000000);
1236
    spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1237
                 SPR_NOACCESS, SPR_NOACCESS,
1238
                 &spr_read_generic, &spr_write_generic,
1239
                 0x00000000);
1240
    spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1241
                 SPR_NOACCESS, SPR_NOACCESS,
1242
                 &spr_read_generic, &spr_write_generic,
1243
                 0x00000000);
1244
    spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1245
                 SPR_NOACCESS, SPR_NOACCESS,
1246
                 &spr_read_generic, &spr_write_generic,
1247
                 0x00000000);
1248
    spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1249
                 SPR_NOACCESS, SPR_NOACCESS,
1250
                 &spr_read_generic, &spr_write_generic,
1251
                 0x00000000);
1252
    spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1253
                 SPR_NOACCESS, SPR_NOACCESS,
1254
                 &spr_read_generic, &spr_write_generic,
1255
                 0x00000000);
1256
    spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1257
                 SPR_NOACCESS, SPR_NOACCESS,
1258
                 &spr_read_generic, &spr_write_generic,
1259
                 0x00000000);
1260
    spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1261
                 SPR_NOACCESS, SPR_NOACCESS,
1262
                 &spr_read_generic, &spr_write_generic,
1263
                 0x00000000);
1264
    spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1265
                 SPR_NOACCESS, SPR_NOACCESS,
1266
                 &spr_read_generic, &spr_write_generic,
1267
                 0x00000000);
1268
    spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1269
                 SPR_NOACCESS, SPR_NOACCESS,
1270
                 &spr_read_generic, &spr_write_generic,
1271
                 0x00000000);
1272
    spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1273
                 SPR_NOACCESS, SPR_NOACCESS,
1274
                 &spr_read_generic, &spr_write_generic,
1275
                 0x00000000);
1276
    spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1277
                 SPR_NOACCESS, SPR_NOACCESS,
1278
                 &spr_read_generic, &spr_write_generic,
1279
                 0x00000000);
1280
    spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1281
                 SPR_NOACCESS, SPR_NOACCESS,
1282
                 &spr_read_generic, &spr_write_generic,
1283
                 0x00000000);
1284
    spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1285
                 SPR_NOACCESS, SPR_NOACCESS,
1286
                 &spr_read_generic, &spr_write_generic,
1287
                 0x00000000);
1288
    spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1289
                 SPR_NOACCESS, SPR_NOACCESS,
1290
                 &spr_read_generic, &spr_write_generic,
1291
                 0x00000000);
1292
    spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1293
                 SPR_NOACCESS, SPR_NOACCESS,
1294
                 &spr_read_generic, &spr_write_generic,
1295
                 0x00000000);
1296
    spr_register(env, SPR_BOOKE_PID, "PID",
1297
                 SPR_NOACCESS, SPR_NOACCESS,
1298
                 &spr_read_generic, &spr_write_generic,
1299
                 0x00000000);
1300
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1301
                 SPR_NOACCESS, SPR_NOACCESS,
1302
                 &spr_read_generic, &spr_write_booke_tcr,
1303
                 0x00000000);
1304
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1305
                 SPR_NOACCESS, SPR_NOACCESS,
1306
                 &spr_read_generic, &spr_write_booke_tsr,
1307
                 0x00000000);
1308
    /* Timer */
1309
    spr_register(env, SPR_DECR, "DECR",
1310
                 SPR_NOACCESS, SPR_NOACCESS,
1311
                 &spr_read_decr, &spr_write_decr,
1312
                 0x00000000);
1313
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1314
                 SPR_NOACCESS, SPR_NOACCESS,
1315
                 SPR_NOACCESS, &spr_write_generic,
1316
                 0x00000000);
1317
    /* SPRGs */
1318
    spr_register(env, SPR_USPRG0, "USPRG0",
1319
                 &spr_read_generic, &spr_write_generic,
1320
                 &spr_read_generic, &spr_write_generic,
1321
                 0x00000000);
1322
    spr_register(env, SPR_SPRG4, "SPRG4",
1323
                 SPR_NOACCESS, SPR_NOACCESS,
1324
                 &spr_read_generic, &spr_write_generic,
1325
                 0x00000000);
1326
    spr_register(env, SPR_USPRG4, "USPRG4",
1327
                 &spr_read_ureg, SPR_NOACCESS,
1328
                 &spr_read_ureg, SPR_NOACCESS,
1329
                 0x00000000);
1330
    spr_register(env, SPR_SPRG5, "SPRG5",
1331
                 SPR_NOACCESS, SPR_NOACCESS,
1332
                 &spr_read_generic, &spr_write_generic,
1333
                 0x00000000);
1334
    spr_register(env, SPR_USPRG5, "USPRG5",
1335
                 &spr_read_ureg, SPR_NOACCESS,
1336
                 &spr_read_ureg, SPR_NOACCESS,
1337
                 0x00000000);
1338
    spr_register(env, SPR_SPRG6, "SPRG6",
1339
                 SPR_NOACCESS, SPR_NOACCESS,
1340
                 &spr_read_generic, &spr_write_generic,
1341
                 0x00000000);
1342
    spr_register(env, SPR_USPRG6, "USPRG6",
1343
                 &spr_read_ureg, SPR_NOACCESS,
1344
                 &spr_read_ureg, SPR_NOACCESS,
1345
                 0x00000000);
1346
    spr_register(env, SPR_SPRG7, "SPRG7",
1347
                 SPR_NOACCESS, SPR_NOACCESS,
1348
                 &spr_read_generic, &spr_write_generic,
1349
                 0x00000000);
1350
    spr_register(env, SPR_USPRG7, "USPRG7",
1351
                 &spr_read_ureg, SPR_NOACCESS,
1352
                 &spr_read_ureg, SPR_NOACCESS,
1353
                 0x00000000);
1354
}
1355

    
1356
/* FSL storage control registers */
1357
static void gen_spr_BookE_FSL (CPUPPCState *env)
1358
{
1359
    /* TLB assist registers */
1360
    spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1361
                 SPR_NOACCESS, SPR_NOACCESS,
1362
                 &spr_read_generic, &spr_write_generic,
1363
                 0x00000000);
1364
    spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1365
                 SPR_NOACCESS, SPR_NOACCESS,
1366
                 &spr_read_generic, &spr_write_generic,
1367
                 0x00000000);
1368
    spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1369
                 SPR_NOACCESS, SPR_NOACCESS,
1370
                 &spr_read_generic, &spr_write_generic,
1371
                 0x00000000);
1372
    spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1373
                 SPR_NOACCESS, SPR_NOACCESS,
1374
                 &spr_read_generic, &spr_write_generic,
1375
                 0x00000000);
1376
    spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1377
                 SPR_NOACCESS, SPR_NOACCESS,
1378
                 &spr_read_generic, &spr_write_generic,
1379
                 0x00000000);
1380
    spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1381
                 SPR_NOACCESS, SPR_NOACCESS,
1382
                 &spr_read_generic, &spr_write_generic,
1383
                 0x00000000);
1384
    spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1385
                 SPR_NOACCESS, SPR_NOACCESS,
1386
                 &spr_read_generic, &spr_write_generic,
1387
                 0x00000000);
1388
    if (env->nb_pids > 1) {
1389
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1390
                     SPR_NOACCESS, SPR_NOACCESS,
1391
                     &spr_read_generic, &spr_write_generic,
1392
                     0x00000000);
1393
    }
1394
    if (env->nb_pids > 2) {
1395
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1396
                     SPR_NOACCESS, SPR_NOACCESS,
1397
                     &spr_read_generic, &spr_write_generic,
1398
                     0x00000000);
1399
    }
1400
    spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1401
                 SPR_NOACCESS, SPR_NOACCESS,
1402
                 &spr_read_generic, SPR_NOACCESS,
1403
                 0x00000000); /* TOFIX */
1404
    spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1405
                 SPR_NOACCESS, SPR_NOACCESS,
1406
                 &spr_read_generic, &spr_write_generic,
1407
                 0x00000000); /* TOFIX */
1408
    switch (env->nb_ways) {
1409
    case 4:
1410
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1411
                     SPR_NOACCESS, SPR_NOACCESS,
1412
                     &spr_read_generic, SPR_NOACCESS,
1413
                     0x00000000); /* TOFIX */
1414
        /* Fallthru */
1415
    case 3:
1416
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1417
                     SPR_NOACCESS, SPR_NOACCESS,
1418
                     &spr_read_generic, SPR_NOACCESS,
1419
                     0x00000000); /* TOFIX */
1420
        /* Fallthru */
1421
    case 2:
1422
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1423
                     SPR_NOACCESS, SPR_NOACCESS,
1424
                     &spr_read_generic, SPR_NOACCESS,
1425
                     0x00000000); /* TOFIX */
1426
        /* Fallthru */
1427
    case 1:
1428
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1429
                     SPR_NOACCESS, SPR_NOACCESS,
1430
                     &spr_read_generic, SPR_NOACCESS,
1431
                     0x00000000); /* TOFIX */
1432
        /* Fallthru */
1433
    case 0:
1434
    default:
1435
        break;
1436
    }
1437
}
1438

    
1439
/* SPR specific to PowerPC 440 implementation */
1440
static void gen_spr_440 (CPUPPCState *env)
1441
{
1442
    /* Cache control */
1443
    /* XXX : not implemented */
1444
    spr_register(env, SPR_440_DNV0, "DNV0",
1445
                 SPR_NOACCESS, SPR_NOACCESS,
1446
                 &spr_read_generic, &spr_write_generic,
1447
                 0x00000000);
1448
    /* XXX : not implemented */
1449
    spr_register(env, SPR_440_DNV1, "DNV1",
1450
                 SPR_NOACCESS, SPR_NOACCESS,
1451
                 &spr_read_generic, &spr_write_generic,
1452
                 0x00000000);
1453
    /* XXX : not implemented */
1454
    spr_register(env, SPR_440_DNV2, "DNV2",
1455
                 SPR_NOACCESS, SPR_NOACCESS,
1456
                 &spr_read_generic, &spr_write_generic,
1457
                 0x00000000);
1458
    /* XXX : not implemented */
1459
    spr_register(env, SPR_440_DNV3, "DNV3",
1460
                 SPR_NOACCESS, SPR_NOACCESS,
1461
                 &spr_read_generic, &spr_write_generic,
1462
                 0x00000000);
1463
    /* XXX : not implemented */
1464
    spr_register(env, SPR_440_DVT0, "DVT0",
1465
                 SPR_NOACCESS, SPR_NOACCESS,
1466
                 &spr_read_generic, &spr_write_generic,
1467
                 0x00000000);
1468
    /* XXX : not implemented */
1469
    spr_register(env, SPR_440_DVT1, "DVT1",
1470
                 SPR_NOACCESS, SPR_NOACCESS,
1471
                 &spr_read_generic, &spr_write_generic,
1472
                 0x00000000);
1473
    /* XXX : not implemented */
1474
    spr_register(env, SPR_440_DVT2, "DVT2",
1475
                 SPR_NOACCESS, SPR_NOACCESS,
1476
                 &spr_read_generic, &spr_write_generic,
1477
                 0x00000000);
1478
    /* XXX : not implemented */
1479
    spr_register(env, SPR_440_DVT3, "DVT3",
1480
                 SPR_NOACCESS, SPR_NOACCESS,
1481
                 &spr_read_generic, &spr_write_generic,
1482
                 0x00000000);
1483
    /* XXX : not implemented */
1484
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1485
                 SPR_NOACCESS, SPR_NOACCESS,
1486
                 &spr_read_generic, &spr_write_generic,
1487
                 0x00000000);
1488
    /* XXX : not implemented */
1489
    spr_register(env, SPR_440_INV0, "INV0",
1490
                 SPR_NOACCESS, SPR_NOACCESS,
1491
                 &spr_read_generic, &spr_write_generic,
1492
                 0x00000000);
1493
    /* XXX : not implemented */
1494
    spr_register(env, SPR_440_INV1, "INV1",
1495
                 SPR_NOACCESS, SPR_NOACCESS,
1496
                 &spr_read_generic, &spr_write_generic,
1497
                 0x00000000);
1498
    /* XXX : not implemented */
1499
    spr_register(env, SPR_440_INV2, "INV2",
1500
                 SPR_NOACCESS, SPR_NOACCESS,
1501
                 &spr_read_generic, &spr_write_generic,
1502
                 0x00000000);
1503
    /* XXX : not implemented */
1504
    spr_register(env, SPR_440_INV3, "INV3",
1505
                 SPR_NOACCESS, SPR_NOACCESS,
1506
                 &spr_read_generic, &spr_write_generic,
1507
                 0x00000000);
1508
    /* XXX : not implemented */
1509
    spr_register(env, SPR_440_IVT0, "IVT0",
1510
                 SPR_NOACCESS, SPR_NOACCESS,
1511
                 &spr_read_generic, &spr_write_generic,
1512
                 0x00000000);
1513
    /* XXX : not implemented */
1514
    spr_register(env, SPR_440_IVT1, "IVT1",
1515
                 SPR_NOACCESS, SPR_NOACCESS,
1516
                 &spr_read_generic, &spr_write_generic,
1517
                 0x00000000);
1518
    /* XXX : not implemented */
1519
    spr_register(env, SPR_440_IVT2, "IVT2",
1520
                 SPR_NOACCESS, SPR_NOACCESS,
1521
                 &spr_read_generic, &spr_write_generic,
1522
                 0x00000000);
1523
    /* XXX : not implemented */
1524
    spr_register(env, SPR_440_IVT3, "IVT3",
1525
                 SPR_NOACCESS, SPR_NOACCESS,
1526
                 &spr_read_generic, &spr_write_generic,
1527
                 0x00000000);
1528
    /* XXX : not implemented */
1529
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1530
                 SPR_NOACCESS, SPR_NOACCESS,
1531
                 &spr_read_generic, &spr_write_generic,
1532
                 0x00000000);
1533
    /* Cache debug */
1534
    /* XXX : not implemented */
1535
    spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
1536
                 SPR_NOACCESS, SPR_NOACCESS,
1537
                 &spr_read_generic, SPR_NOACCESS,
1538
                 0x00000000);
1539
    /* XXX : not implemented */
1540
    spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
1541
                 SPR_NOACCESS, SPR_NOACCESS,
1542
                 &spr_read_generic, SPR_NOACCESS,
1543
                 0x00000000);
1544
    /* XXX : not implemented */
1545
    spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
1546
                 SPR_NOACCESS, SPR_NOACCESS,
1547
                 &spr_read_generic, SPR_NOACCESS,
1548
                 0x00000000);
1549
    /* XXX : not implemented */
1550
    spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
1551
                 SPR_NOACCESS, SPR_NOACCESS,
1552
                 &spr_read_generic, SPR_NOACCESS,
1553
                 0x00000000);
1554
    /* XXX : not implemented */
1555
    spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
1556
                 SPR_NOACCESS, SPR_NOACCESS,
1557
                 &spr_read_generic, SPR_NOACCESS,
1558
                 0x00000000);
1559
    /* XXX : not implemented */
1560
    spr_register(env, SPR_440_DBDR, "DBDR",
1561
                 SPR_NOACCESS, SPR_NOACCESS,
1562
                 &spr_read_generic, &spr_write_generic,
1563
                 0x00000000);
1564
    /* Processor control */
1565
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1566
                 SPR_NOACCESS, SPR_NOACCESS,
1567
                 &spr_read_generic, &spr_write_generic,
1568
                 0x00000000);
1569
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1570
                 SPR_NOACCESS, SPR_NOACCESS,
1571
                 &spr_read_generic, SPR_NOACCESS,
1572
                 0x00000000);
1573
    /* Storage control */
1574
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1575
                 SPR_NOACCESS, SPR_NOACCESS,
1576
                 &spr_read_generic, &spr_write_generic,
1577
                 0x00000000);
1578
}
1579

    
1580
/* SPR shared between PowerPC 40x implementations */
1581
static void gen_spr_40x (CPUPPCState *env)
1582
{
1583
    /* Cache */
1584
    /* XXX : not implemented */
1585
    spr_register(env, SPR_40x_DCCR, "DCCR",
1586
                 SPR_NOACCESS, SPR_NOACCESS,
1587
                 &spr_read_generic, &spr_write_generic,
1588
                 0x00000000);
1589
    /* XXX : not implemented */
1590
    spr_register(env, SPR_40x_DCWR, "DCWR",
1591
                 SPR_NOACCESS, SPR_NOACCESS,
1592
                 &spr_read_generic, &spr_write_generic,
1593
                 0x00000000);
1594
    /* XXX : not implemented */
1595
    spr_register(env, SPR_40x_ICCR, "ICCR",
1596
                 SPR_NOACCESS, SPR_NOACCESS,
1597
                 &spr_read_generic, &spr_write_generic,
1598
                 0x00000000);
1599
    /* XXX : not implemented */
1600
    spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
1601
                 SPR_NOACCESS, SPR_NOACCESS,
1602
                 &spr_read_generic, SPR_NOACCESS,
1603
                 0x00000000);
1604
    /* Bus access control */
1605
    spr_register(env, SPR_40x_SGR, "SGR",
1606
                 SPR_NOACCESS, SPR_NOACCESS,
1607
                 &spr_read_generic, &spr_write_generic,
1608
                 0xFFFFFFFF);
1609
    spr_register(env, SPR_40x_ZPR, "ZPR",
1610
                 SPR_NOACCESS, SPR_NOACCESS,
1611
                 &spr_read_generic, &spr_write_generic,
1612
                 0x00000000);
1613
    /* MMU */
1614
    spr_register(env, SPR_40x_PID, "PID",
1615
                 SPR_NOACCESS, SPR_NOACCESS,
1616
                 &spr_read_generic, &spr_write_generic,
1617
                 0x00000000);
1618
    /* Exception */
1619
    spr_register(env, SPR_40x_DEAR, "DEAR",
1620
                 SPR_NOACCESS, SPR_NOACCESS,
1621
                 &spr_read_generic, &spr_write_generic,
1622
                 0x00000000);
1623
    spr_register(env, SPR_40x_ESR, "ESR",
1624
                 SPR_NOACCESS, SPR_NOACCESS,
1625
                 &spr_read_generic, &spr_write_generic,
1626
                 0x00000000);
1627
    spr_register(env, SPR_40x_EVPR, "EVPR",
1628
                 SPR_NOACCESS, SPR_NOACCESS,
1629
                 &spr_read_generic, &spr_write_generic,
1630
                 0x00000000);
1631
    spr_register(env, SPR_40x_SRR2, "SRR2",
1632
                 &spr_read_generic, &spr_write_generic,
1633
                 &spr_read_generic, &spr_write_generic,
1634
                 0x00000000);
1635
    spr_register(env, SPR_40x_SRR3, "SRR3",
1636
                 &spr_read_generic, &spr_write_generic,
1637
                 &spr_read_generic, &spr_write_generic,
1638
                 0x00000000);
1639
    /* Timers */
1640
    spr_register(env, SPR_40x_PIT, "PIT",
1641
                 SPR_NOACCESS, SPR_NOACCESS,
1642
                 &spr_read_40x_pit, &spr_write_40x_pit,
1643
                 0x00000000);
1644
    spr_register(env, SPR_40x_TCR, "TCR",
1645
                 SPR_NOACCESS, SPR_NOACCESS,
1646
                 &spr_read_generic, &spr_write_booke_tcr,
1647
                 0x00000000);
1648
    spr_register(env, SPR_40x_TSR, "TSR",
1649
                 SPR_NOACCESS, SPR_NOACCESS,
1650
                 &spr_read_generic, &spr_write_booke_tsr,
1651
                 0x00000000);
1652
    /* Debug interface */
1653
    /* XXX : not implemented */
1654
    spr_register(env, SPR_40x_DAC1, "DAC1",
1655
                 SPR_NOACCESS, SPR_NOACCESS,
1656
                 &spr_read_generic, &spr_write_generic,
1657
                 0x00000000);
1658
    spr_register(env, SPR_40x_DAC2, "DAC2",
1659
                 SPR_NOACCESS, SPR_NOACCESS,
1660
                 &spr_read_generic, &spr_write_generic,
1661
                 0x00000000);
1662
    /* XXX : not implemented */
1663
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1664
                 SPR_NOACCESS, SPR_NOACCESS,
1665
                 &spr_read_generic, &spr_write_40x_dbcr0,
1666
                 0x00000000);
1667
    /* XXX : not implemented */
1668
    spr_register(env, SPR_40x_DBSR, "DBSR",
1669
                 SPR_NOACCESS, SPR_NOACCESS,
1670
                 &spr_read_generic, &spr_write_clear,
1671
                 /* Last reset was system reset */
1672
                 0x00000300);
1673
    /* XXX : not implemented */
1674
    spr_register(env, SPR_40x_IAC1, "IAC1",
1675
                 SPR_NOACCESS, SPR_NOACCESS,
1676
                 &spr_read_generic, &spr_write_generic,
1677
                 0x00000000);
1678
    spr_register(env, SPR_40x_IAC2, "IAC2",
1679
                 SPR_NOACCESS, SPR_NOACCESS,
1680
                 &spr_read_generic, &spr_write_generic,
1681
                 0x00000000);
1682
}
1683

    
1684
/* SPR specific to PowerPC 405 implementation */
1685
static void gen_spr_405 (CPUPPCState *env)
1686
{
1687
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1688
                 SPR_NOACCESS, SPR_NOACCESS,
1689
                 &spr_read_generic, &spr_write_generic,
1690
                 0x00700000);
1691
    /* Debug */
1692
    /* XXX : not implemented */
1693
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1694
                 SPR_NOACCESS, SPR_NOACCESS,
1695
                 &spr_read_generic, &spr_write_generic,
1696
                 0x00000000);
1697
    /* XXX : not implemented */
1698
    spr_register(env, SPR_405_DVC1, "DVC1",
1699
                 SPR_NOACCESS, SPR_NOACCESS,
1700
                 &spr_read_generic, &spr_write_generic,
1701
                 0x00000000);
1702
    /* XXX : not implemented */
1703
    spr_register(env, SPR_405_DVC2, "DVC2",
1704
                 SPR_NOACCESS, SPR_NOACCESS,
1705
                 &spr_read_generic, &spr_write_generic,
1706
                 0x00000000);
1707
    /* XXX : not implemented */
1708
    spr_register(env, SPR_405_IAC3, "IAC3",
1709
                 SPR_NOACCESS, SPR_NOACCESS,
1710
                 &spr_read_generic, &spr_write_generic,
1711
                 0x00000000);
1712
    /* XXX : not implemented */
1713
    spr_register(env, SPR_405_IAC4, "IAC4",
1714
                 SPR_NOACCESS, SPR_NOACCESS,
1715
                 &spr_read_generic, &spr_write_generic,
1716
                 0x00000000);
1717
    /* Storage control */
1718
    /* XXX : not implemented */
1719
    spr_register(env, SPR_405_SLER, "SLER",
1720
                 SPR_NOACCESS, SPR_NOACCESS,
1721
                 &spr_read_generic, &spr_write_generic,
1722
                 0x00000000);
1723
    /* XXX : not implemented */
1724
    spr_register(env, SPR_405_SU0R, "SU0R",
1725
                 SPR_NOACCESS, SPR_NOACCESS,
1726
                 &spr_read_generic, &spr_write_generic,
1727
                 0x00000000);
1728
    /* SPRG */
1729
    spr_register(env, SPR_USPRG0, "USPRG0",
1730
                 &spr_read_ureg, SPR_NOACCESS,
1731
                 &spr_read_ureg, SPR_NOACCESS,
1732
                 0x00000000);
1733
    spr_register(env, SPR_SPRG4, "SPRG4",
1734
                 SPR_NOACCESS, SPR_NOACCESS,
1735
                 &spr_read_generic, &spr_write_generic,
1736
                 0x00000000);
1737
    spr_register(env, SPR_USPRG4, "USPRG4",
1738
                 &spr_read_ureg, SPR_NOACCESS,
1739
                 &spr_read_ureg, SPR_NOACCESS,
1740
                 0x00000000);
1741
    spr_register(env, SPR_SPRG5, "SPRG5",
1742
                 SPR_NOACCESS, SPR_NOACCESS,
1743
                 spr_read_generic, &spr_write_generic,
1744
                 0x00000000);
1745
    spr_register(env, SPR_USPRG5, "USPRG5",
1746
                 &spr_read_ureg, SPR_NOACCESS,
1747
                 &spr_read_ureg, SPR_NOACCESS,
1748
                 0x00000000);
1749
    spr_register(env, SPR_SPRG6, "SPRG6",
1750
                 SPR_NOACCESS, SPR_NOACCESS,
1751
                 spr_read_generic, &spr_write_generic,
1752
                 0x00000000);
1753
    spr_register(env, SPR_USPRG6, "USPRG6",
1754
                 &spr_read_ureg, SPR_NOACCESS,
1755
                 &spr_read_ureg, SPR_NOACCESS,
1756
                 0x00000000);
1757
    spr_register(env, SPR_SPRG7, "SPRG7",
1758
                 SPR_NOACCESS, SPR_NOACCESS,
1759
                 spr_read_generic, &spr_write_generic,
1760
                 0x00000000);
1761
    spr_register(env, SPR_USPRG7, "USPRG7",
1762
                 &spr_read_ureg, SPR_NOACCESS,
1763
                 &spr_read_ureg, SPR_NOACCESS,
1764
                 0x00000000);
1765
}
1766

    
1767
/* SPR shared between PowerPC 401 & 403 implementations */
1768
static void gen_spr_401_403 (CPUPPCState *env)
1769
{
1770
    /* Time base */
1771
    spr_register(env, SPR_403_VTBL,  "TBL",
1772
                 &spr_read_tbl, SPR_NOACCESS,
1773
                 &spr_read_tbl, SPR_NOACCESS,
1774
                 0x00000000);
1775
    spr_register(env, SPR_403_TBL,   "TBL",
1776
                 SPR_NOACCESS, SPR_NOACCESS,
1777
                 SPR_NOACCESS, &spr_write_tbl,
1778
                 0x00000000);
1779
    spr_register(env, SPR_403_VTBU,  "TBU",
1780
                 &spr_read_tbu, SPR_NOACCESS,
1781
                 &spr_read_tbu, SPR_NOACCESS,
1782
                 0x00000000);
1783
    spr_register(env, SPR_403_TBU,   "TBU",
1784
                 SPR_NOACCESS, SPR_NOACCESS,
1785
                 SPR_NOACCESS, &spr_write_tbu,
1786
                 0x00000000);
1787
    /* Debug */
1788
    /* XXX: not implemented */
1789
    spr_register(env, SPR_403_CDBCR, "CDBCR",
1790
                 SPR_NOACCESS, SPR_NOACCESS,
1791
                 &spr_read_generic, &spr_write_generic,
1792
                 0x00000000);
1793
}
1794

    
1795
/* SPR specific to PowerPC 403 implementation */
1796
static void gen_spr_403 (CPUPPCState *env)
1797
{
1798
    /* MMU */
1799
    spr_register(env, SPR_403_PBL1,  "PBL1",
1800
                 SPR_NOACCESS, SPR_NOACCESS,
1801
                 &spr_read_403_pbr, &spr_write_403_pbr,
1802
                 0x00000000);
1803
    spr_register(env, SPR_403_PBU1,  "PBU1",
1804
                 SPR_NOACCESS, SPR_NOACCESS,
1805
                 &spr_read_403_pbr, &spr_write_403_pbr,
1806
                 0x00000000);
1807
    spr_register(env, SPR_403_PBL2,  "PBL2",
1808
                 SPR_NOACCESS, SPR_NOACCESS,
1809
                 &spr_read_403_pbr, &spr_write_403_pbr,
1810
                 0x00000000);
1811
    spr_register(env, SPR_403_PBU2,  "PBU2",
1812
                 SPR_NOACCESS, SPR_NOACCESS,
1813
                 &spr_read_403_pbr, &spr_write_403_pbr,
1814
                 0x00000000);
1815
    /* Debug */
1816
    /* XXX : not implemented */
1817
    spr_register(env, SPR_40x_DAC2, "DAC2",
1818
                 SPR_NOACCESS, SPR_NOACCESS,
1819
                 &spr_read_generic, &spr_write_generic,
1820
                 0x00000000);
1821
    /* XXX : not implemented */
1822
    spr_register(env, SPR_40x_IAC2, "IAC2",
1823
                 SPR_NOACCESS, SPR_NOACCESS,
1824
                 &spr_read_generic, &spr_write_generic,
1825
                 0x00000000);
1826
}
1827

    
1828
/* SPR specific to PowerPC compression coprocessor extension */
1829
#if defined (TODO)
1830
static void gen_spr_compress (CPUPPCState *env)
1831
{
1832
    spr_register(env, SPR_401_SKR, "SKR",
1833
                 SPR_NOACCESS, SPR_NOACCESS,
1834
                 &spr_read_generic, &spr_write_generic,
1835
                 0x00000000);
1836
}
1837
#endif
1838

    
1839
// XXX: TODO (64 bits PowerPC SPRs)
1840
/*
1841
 * ASR => SPR 280 (64 bits)
1842
 * FPECR => SPR 1022 (?)
1843
 * VRSAVE => SPR 256 (Altivec)
1844
 * SCOMC => SPR 276 (64 bits ?)
1845
 * SCOMD => SPR 277 (64 bits ?)
1846
 * HSPRG0 => SPR 304 (hypervisor)
1847
 * HSPRG1 => SPR 305 (hypervisor)
1848
 * HDEC => SPR 310 (hypervisor)
1849
 * HIOR => SPR 311 (hypervisor)
1850
 * RMOR => SPR 312 (970)
1851
 * HRMOR => SPR 313 (hypervisor)
1852
 * HSRR0 => SPR 314 (hypervisor)
1853
 * HSRR1 => SPR 315 (hypervisor)
1854
 * LPCR => SPR 316 (970)
1855
 * LPIDR => SPR 317 (970)
1856
 * ... and more (thermal management, performance counters, ...)
1857
 */
1858

    
1859
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1860
{
1861
    env->reserve = -1;
1862
    /* Default MMU definitions */
1863
    env->nb_BATs = -1;
1864
    env->nb_tlb = 0;
1865
    env->nb_ways = 0;
1866
    /* XXX: missing:
1867
     * 32 bits PowerPC:
1868
     * - MPC5xx(x)
1869
     * - MPC8xx(x)
1870
     * - RCPU (same as MPC5xx ?)
1871
     */
1872
    spr_register(env, SPR_PVR, "PVR",
1873
                 SPR_NOACCESS, SPR_NOACCESS,
1874
                 &spr_read_generic, SPR_NOACCESS,
1875
                 def->pvr);
1876
    printf("%s: PVR %08x mask %08x => %08x\n", __func__,
1877
           def->pvr, def->pvr_mask, def->pvr & def->pvr_mask);
1878
    switch (def->pvr) {
1879
    /* Embedded PowerPC from IBM                           */
1880
    case CPU_PPC_401A1:   /* 401 A1 family                 */
1881
    case CPU_PPC_401B2:   /* 401 B2 family                 */
1882
    case CPU_PPC_401C2:   /* 401 C2 family                 */
1883
    case CPU_PPC_401D2:   /* 401 D2 family                 */
1884
    case CPU_PPC_401E2:   /* 401 E2 family                 */
1885
    case CPU_PPC_401F2:   /* 401 F2 family                 */
1886
    case CPU_PPC_401G2:   /* 401 G2 family                 */
1887
    case CPU_PPC_IOP480:  /* IOP 480 family                */
1888
    case CPU_PPC_COBRA:   /* IBM Processor for Network Resources */
1889
        gen_spr_generic(env);
1890
        gen_spr_40x(env);
1891
        gen_spr_401_403(env);
1892
#if defined (TODO)
1893
        /* XXX: optional ? */
1894
        gen_spr_compress(env);
1895
#endif
1896
        env->nb_BATs = 0;
1897
        env->nb_tlb = 64;
1898
        env->nb_ways = 1;
1899
        env->id_tlbs = 0;
1900
        /* XXX: TODO: allocate internal IRQ controller */
1901
        break;
1902

    
1903
    case CPU_PPC_403GA:   /* 403 GA family                 */
1904
    case CPU_PPC_403GB:   /* 403 GB family                 */
1905
    case CPU_PPC_403GC:   /* 403 GC family                 */
1906
    case CPU_PPC_403GCX:  /* 403 GCX family                */
1907
        gen_spr_generic(env);
1908
        gen_spr_40x(env);
1909
        gen_spr_401_403(env);
1910
        gen_spr_403(env);
1911
        env->nb_BATs = 0;
1912
        env->nb_tlb = 64;
1913
        env->nb_ways = 1;
1914
        env->id_tlbs = 0;
1915
        /* XXX: TODO: allocate internal IRQ controller */
1916
        break;
1917

    
1918
    case CPU_PPC_405CR:   /* 405 GP/CR family              */
1919
    case CPU_PPC_405EP:   /* 405 EP family                 */
1920
    case CPU_PPC_405GPR:  /* 405 GPR family                */
1921
    case CPU_PPC_405D2:   /* 405 D2 family                 */
1922
    case CPU_PPC_405D4:   /* 405 D4 family                 */
1923
        gen_spr_generic(env);
1924
        /* Time base */
1925
        gen_tbl(env);
1926
        gen_spr_40x(env);
1927
        gen_spr_405(env);
1928
        env->nb_BATs = 0;
1929
        env->nb_tlb = 64;
1930
        env->nb_ways = 1;
1931
        env->id_tlbs = 0;
1932
        /* Allocate hardware IRQ controller */
1933
        ppc405_irq_init(env);
1934
        break;
1935

    
1936
    case CPU_PPC_NPE405H: /* NPe405 H family               */
1937
    case CPU_PPC_NPE405H2:
1938
    case CPU_PPC_NPE405L: /* Npe405 L family               */
1939
        gen_spr_generic(env);
1940
        /* Time base */
1941
        gen_tbl(env);
1942
        gen_spr_40x(env);
1943
        gen_spr_405(env);
1944
        env->nb_BATs = 0;
1945
        env->nb_tlb = 64;
1946
        env->nb_ways = 1;
1947
        env->id_tlbs = 0;
1948
        /* Allocate hardware IRQ controller */
1949
        ppc405_irq_init(env);
1950
        break;
1951

    
1952
#if defined (TODO)
1953
    case CPU_PPC_STB01000:
1954
#endif
1955
#if defined (TODO)
1956
    case CPU_PPC_STB01010:
1957
#endif
1958
#if defined (TODO)
1959
    case CPU_PPC_STB0210:
1960
#endif
1961
    case CPU_PPC_STB03:   /* STB03 family                  */
1962
#if defined (TODO)
1963
    case CPU_PPC_STB043:  /* STB043 family                  */
1964
#endif
1965
#if defined (TODO)
1966
    case CPU_PPC_STB045:  /* STB045 family                  */
1967
#endif
1968
    case CPU_PPC_STB25:   /* STB25 family                  */
1969
#if defined (TODO)
1970
    case CPU_PPC_STB130:  /* STB130 family                 */
1971
#endif
1972
        gen_spr_generic(env);
1973
        /* Time base */
1974
        gen_tbl(env);
1975
        gen_spr_40x(env);
1976
        gen_spr_405(env);
1977
        env->nb_BATs = 0;
1978
        env->nb_tlb = 64;
1979
        env->nb_ways = 1;
1980
        env->id_tlbs = 0;
1981
        /* Allocate hardware IRQ controller */
1982
        ppc405_irq_init(env);
1983
        break;
1984

    
1985
    case CPU_PPC_440EP:   /* 440 EP family                 */
1986
    case CPU_PPC_440GP:   /* 440 GP family                 */
1987
    case CPU_PPC_440GX:   /* 440 GX family                 */
1988
    case CPU_PPC_440GXc:  /* 440 GXc family                */
1989
    case CPU_PPC_440GXf:  /* 440 GXf family                */
1990
    case CPU_PPC_440SP:   /* 440 SP family                 */
1991
    case CPU_PPC_440SP2:
1992
    case CPU_PPC_440SPE:  /* 440 SPE family                */
1993
        gen_spr_generic(env);
1994
        /* Time base */
1995
        gen_tbl(env);
1996
        gen_spr_BookE(env);
1997
        gen_spr_440(env);
1998
        env->nb_BATs = 0;
1999
        env->nb_tlb = 64;
2000
        env->nb_ways = 1;
2001
        env->id_tlbs = 0;
2002
        /* XXX: TODO: allocate internal IRQ controller */
2003
        break;
2004

    
2005
    /* Embedded PowerPC from Freescale                     */
2006
#if defined (TODO)
2007
    case CPU_PPC_5xx:
2008
        break;
2009
#endif
2010
#if defined (TODO)
2011
    case CPU_PPC_8xx:     /* MPC821 / 823 / 850 / 860      */
2012
        break;
2013
#endif
2014
#if defined (TODO)
2015
    case CPU_PPC_82xx_HIP3:    /* MPC8240 / 8260                */
2016
    case CPU_PPC_82xx_HIP4:    /* MPC8240 / 8260                */
2017
        break;
2018
#endif
2019
#if defined (TODO)
2020
    case CPU_PPC_827x:    /* MPC 827x / 828x               */
2021
        break;
2022
#endif
2023

    
2024
    /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
2025
    case CPU_PPC_e500v110:
2026
    case CPU_PPC_e500v120:
2027
    case CPU_PPC_e500v210:
2028
    case CPU_PPC_e500v220:
2029
        gen_spr_generic(env);
2030
        /* Time base */
2031
        gen_tbl(env);
2032
        gen_spr_BookE(env);
2033
        gen_spr_BookE_FSL(env);
2034
        env->nb_BATs = 0;
2035
        env->nb_tlb = 64;
2036
        env->nb_ways = 1;
2037
        env->id_tlbs = 0;
2038
        /* XXX: TODO: allocate internal IRQ controller */
2039
        break;
2040

    
2041
#if defined (TODO)
2042
    case CPU_PPC_e600:
2043
        break;
2044
#endif
2045

    
2046
    /* 32 bits PowerPC                                     */
2047
    case CPU_PPC_601:     /* PowerPC 601                   */
2048
        gen_spr_generic(env);
2049
        gen_spr_ne_601(env);
2050
        gen_spr_601(env);
2051
        /* Hardware implementation registers */
2052
        /* XXX : not implemented */
2053
        spr_register(env, SPR_HID0, "HID0",
2054
                     SPR_NOACCESS, SPR_NOACCESS,
2055
                     &spr_read_generic, &spr_write_generic,
2056
                     0x00000000);
2057
        /* XXX : not implemented */
2058
        spr_register(env, SPR_HID1, "HID1",
2059
                     SPR_NOACCESS, SPR_NOACCESS,
2060
                     &spr_read_generic, &spr_write_generic,
2061
                     0x00000000);
2062
        /* XXX : not implemented */
2063
        spr_register(env, SPR_601_HID2, "HID2",
2064
                     SPR_NOACCESS, SPR_NOACCESS,
2065
                     &spr_read_generic, &spr_write_generic,
2066
                     0x00000000);
2067
        /* XXX : not implemented */
2068
        spr_register(env, SPR_601_HID5, "HID5",
2069
                     SPR_NOACCESS, SPR_NOACCESS,
2070
                     &spr_read_generic, &spr_write_generic,
2071
                     0x00000000);
2072
        /* XXX : not implemented */
2073
#if 0 /* ? */
2074
        spr_register(env, SPR_601_HID15, "HID15",
2075
                     SPR_NOACCESS, SPR_NOACCESS,
2076
                     &spr_read_generic, &spr_write_generic,
2077
                     0x00000000);
2078
#endif
2079
        env->nb_tlb = 64;
2080
        env->nb_ways = 2;
2081
        env->id_tlbs = 0;
2082
        env->id_tlbs = 0;
2083
        /* XXX: TODO: allocate internal IRQ controller */
2084
        break;
2085

    
2086
    case CPU_PPC_602:     /* PowerPC 602                   */
2087
        gen_spr_generic(env);
2088
        gen_spr_ne_601(env);
2089
        /* Memory management */
2090
        gen_low_BATs(env);
2091
        /* Time base */
2092
        gen_tbl(env);
2093
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2094
        gen_spr_602(env);
2095
        /* hardware implementation registers */
2096
        /* XXX : not implemented */
2097
        spr_register(env, SPR_HID0, "HID0",
2098
                     SPR_NOACCESS, SPR_NOACCESS,
2099
                     &spr_read_generic, &spr_write_generic,
2100
                     0x00000000);
2101
        /* XXX : not implemented */
2102
        spr_register(env, SPR_HID1, "HID1",
2103
                     SPR_NOACCESS, SPR_NOACCESS,
2104
                     &spr_read_generic, &spr_write_generic,
2105
                     0x00000000);
2106
        /* Allocate hardware IRQ controller */
2107
        ppc6xx_irq_init(env);
2108
        break;
2109

    
2110
    case CPU_PPC_603:     /* PowerPC 603                   */
2111
    case CPU_PPC_603E:    /* PowerPC 603e                  */
2112
    case CPU_PPC_603E7v:
2113
    case CPU_PPC_603E7v2:
2114
    case CPU_PPC_603P:    /* PowerPC 603p                  */
2115
    case CPU_PPC_603R:    /* PowerPC 603r                  */
2116
        gen_spr_generic(env);
2117
        gen_spr_ne_601(env);
2118
        /* Memory management */
2119
        gen_low_BATs(env);
2120
        /* Time base */
2121
        gen_tbl(env);
2122
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2123
        gen_spr_603(env);
2124
        /* hardware implementation registers */
2125
        /* XXX : not implemented */
2126
        spr_register(env, SPR_HID0, "HID0",
2127
                     SPR_NOACCESS, SPR_NOACCESS,
2128
                     &spr_read_generic, &spr_write_generic,
2129
                     0x00000000);
2130
        /* XXX : not implemented */
2131
        spr_register(env, SPR_HID1, "HID1",
2132
                     SPR_NOACCESS, SPR_NOACCESS,
2133
                     &spr_read_generic, &spr_write_generic,
2134
                     0x00000000);
2135
        /* Allocate hardware IRQ controller */
2136
        ppc6xx_irq_init(env);
2137
        break;
2138
        
2139
    case CPU_PPC_G2:      /* PowerPC G2 family             */
2140
    case CPU_PPC_G2H4:
2141
    case CPU_PPC_G2gp:
2142
    case CPU_PPC_G2ls:
2143
    case CPU_PPC_G2LE:    /* PowerPC G2LE family           */
2144
    case CPU_PPC_G2LEgp:
2145
    case CPU_PPC_G2LEls:
2146
        gen_spr_generic(env);
2147
        gen_spr_ne_601(env);
2148
        /* Memory management */
2149
        gen_low_BATs(env);
2150
        /* Time base */
2151
        gen_tbl(env);
2152
        /* Memory management */
2153
        gen_high_BATs(env);
2154
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2155
        gen_spr_G2_755(env);
2156
        gen_spr_G2(env);
2157
        /* Hardware implementation register */
2158
        /* XXX : not implemented */
2159
        spr_register(env, SPR_HID0, "HID0",
2160
                     SPR_NOACCESS, SPR_NOACCESS,
2161
                     &spr_read_generic, &spr_write_generic,
2162
                     0x00000000);
2163
        /* XXX : not implemented */
2164
        spr_register(env, SPR_HID1, "HID1",
2165
                     SPR_NOACCESS, SPR_NOACCESS,
2166
                     &spr_read_generic, &spr_write_generic,
2167
                     0x00000000);
2168
        /* XXX : not implemented */
2169
        spr_register(env, SPR_HID2, "HID2",
2170
                     SPR_NOACCESS, SPR_NOACCESS,
2171
                     &spr_read_generic, &spr_write_generic,
2172
                     0x00000000);
2173
        /* Allocate hardware IRQ controller */
2174
        ppc6xx_irq_init(env);
2175
        break;
2176

    
2177
    case CPU_PPC_604:     /* PowerPC 604                   */
2178
    case CPU_PPC_604E:    /* PowerPC 604e                  */
2179
    case CPU_PPC_604R:    /* PowerPC 604r                  */
2180
        gen_spr_generic(env);
2181
        gen_spr_ne_601(env);
2182
        /* Memory management */
2183
        gen_low_BATs(env);
2184
        /* Time base */
2185
        gen_tbl(env);
2186
        gen_spr_604(env);
2187
        /* Hardware implementation registers */
2188
        /* XXX : not implemented */
2189
        spr_register(env, SPR_HID0, "HID0",
2190
                     SPR_NOACCESS, SPR_NOACCESS,
2191
                     &spr_read_generic, &spr_write_generic,
2192
                     0x00000000);
2193
        /* XXX : not implemented */
2194
        spr_register(env, SPR_HID1, "HID1",
2195
                     SPR_NOACCESS, SPR_NOACCESS,
2196
                     &spr_read_generic, &spr_write_generic,
2197
                     0x00000000);
2198
        /* Allocate hardware IRQ controller */
2199
        ppc6xx_irq_init(env);
2200
        break;
2201

    
2202
    case CPU_PPC_74x:     /* PowerPC 740 / 750             */
2203
    case CPU_PPC_740E:
2204
    case CPU_PPC_750E:
2205
    case CPU_PPC_74xP:    /* PowerPC 740P / 750P           */
2206
    case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe            */
2207
    case CPU_PPC_750CXE22:
2208
    case CPU_PPC_750CXE23:
2209
    case CPU_PPC_750CXE24:
2210
    case CPU_PPC_750CXE24b:
2211
    case CPU_PPC_750CXE31:
2212
    case CPU_PPC_750CXE31b:
2213
    case CPU_PPC_750CXR:
2214
        gen_spr_generic(env);
2215
        gen_spr_ne_601(env);
2216
        /* Memory management */
2217
        gen_low_BATs(env);
2218
        /* Time base */
2219
        gen_tbl(env);
2220
        gen_spr_7xx(env);
2221
        /* Hardware implementation registers */
2222
        /* XXX : not implemented */
2223
        spr_register(env, SPR_HID0, "HID0",
2224
                     SPR_NOACCESS, SPR_NOACCESS,
2225
                     &spr_read_generic, &spr_write_generic,
2226
                     0x00000000);
2227
        /* XXX : not implemented */
2228
        spr_register(env, SPR_HID1, "HID1",
2229
                     SPR_NOACCESS, SPR_NOACCESS,
2230
                     &spr_read_generic, &spr_write_generic,
2231
                     0x00000000);
2232
        /* Allocate hardware IRQ controller */
2233
        ppc6xx_irq_init(env);
2234
        break;
2235

    
2236
    case CPU_PPC_750FX10: /* IBM PowerPC 750 FX            */
2237
    case CPU_PPC_750FX20:
2238
    case CPU_PPC_750FX21:
2239
    case CPU_PPC_750FX22:
2240
    case CPU_PPC_750FX23:
2241
    case CPU_PPC_750GX10: /* IBM PowerPC 750 GX            */
2242
    case CPU_PPC_750GX11:
2243
    case CPU_PPC_750GX12:
2244
        gen_spr_generic(env);
2245
        gen_spr_ne_601(env);
2246
        /* Memory management */
2247
        gen_low_BATs(env);
2248
        /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2249
        gen_high_BATs(env);
2250
        /* Time base */
2251
        gen_tbl(env);
2252
        gen_spr_7xx(env);
2253
        /* Hardware implementation registers */
2254
        /* XXX : not implemented */
2255
        spr_register(env, SPR_HID0, "HID0",
2256
                     SPR_NOACCESS, SPR_NOACCESS,
2257
                     &spr_read_generic, &spr_write_generic,
2258
                     0x00000000);
2259
        /* XXX : not implemented */
2260
        spr_register(env, SPR_HID1, "HID1",
2261
                     SPR_NOACCESS, SPR_NOACCESS,
2262
                     &spr_read_generic, &spr_write_generic,
2263
                     0x00000000);
2264
        /* XXX : not implemented */
2265
        spr_register(env, SPR_750_HID2, "HID2",
2266
                     SPR_NOACCESS, SPR_NOACCESS,
2267
                     &spr_read_generic, &spr_write_generic,
2268
                     0x00000000);
2269
        /* Allocate hardware IRQ controller */
2270
        ppc6xx_irq_init(env);
2271
        break;
2272

    
2273
    case CPU_PPC_755_10:  /* PowerPC 755                   */
2274
    case CPU_PPC_755_11:
2275
    case CPU_PPC_755_20:
2276
    case CPU_PPC_755D:
2277
    case CPU_PPC_755E:
2278
        gen_spr_generic(env);
2279
        gen_spr_ne_601(env);
2280
        /* Memory management */
2281
        gen_low_BATs(env);
2282
        /* Time base */
2283
        gen_tbl(env);
2284
        /* Memory management */
2285
        gen_high_BATs(env);
2286
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2287
        gen_spr_G2_755(env);
2288
        /* L2 cache control */
2289
        /* XXX : not implemented */
2290
        spr_register(env, SPR_ICTC, "ICTC",
2291
                     SPR_NOACCESS, SPR_NOACCESS,
2292
                     &spr_read_generic, &spr_write_generic,
2293
                     0x00000000);
2294
        /* XXX : not implemented */
2295
        spr_register(env, SPR_L2PM, "L2PM",
2296
                     SPR_NOACCESS, SPR_NOACCESS,
2297
                     &spr_read_generic, &spr_write_generic,
2298
                     0x00000000);
2299
        /* Hardware implementation registers */
2300
        /* XXX : not implemented */
2301
        spr_register(env, SPR_HID0, "HID0",
2302
                     SPR_NOACCESS, SPR_NOACCESS,
2303
                     &spr_read_generic, &spr_write_generic,
2304
                     0x00000000);
2305
        /* XXX : not implemented */
2306
        spr_register(env, SPR_HID1, "HID1",
2307
                     SPR_NOACCESS, SPR_NOACCESS,
2308
                     &spr_read_generic, &spr_write_generic,
2309
                     0x00000000);
2310
        /* XXX : not implemented */
2311
        spr_register(env, SPR_HID2, "HID2",
2312
                     SPR_NOACCESS, SPR_NOACCESS,
2313
                     &spr_read_generic, &spr_write_generic,
2314
                     0x00000000);
2315
        /* Allocate hardware IRQ controller */
2316
        ppc6xx_irq_init(env);
2317
        break;
2318

    
2319
#if defined (TODO)
2320
    /* G4 family */
2321
    case CPU_PPC_7400:    /* PowerPC 7400                  */
2322
    case CPU_PPC_7410C:   /* PowerPC 7410                  */
2323
    case CPU_PPC_7410D:
2324
    case CPU_PPC_7410E:
2325
    case CPU_PPC_7441:    /* PowerPC 7441                  */
2326
    case CPU_PPC_7445:    /* PowerPC 7445                  */
2327
    case CPU_PPC_7447:    /* PowerPC 7447                  */
2328
    case CPU_PPC_7447A:   /* PowerPC 7447A                 */
2329
    case CPU_PPC_7448:    /* PowerPC 7448                  */
2330
    case CPU_PPC_7450:    /* PowerPC 7450                  */
2331
    case CPU_PPC_7450b:
2332
    case CPU_PPC_7451:    /* PowerPC 7451                  */
2333
    case CPU_PPC_7451G:
2334
    case CPU_PPC_7455:    /* PowerPC 7455                  */
2335
    case CPU_PPC_7455F:
2336
    case CPU_PPC_7455G:
2337
    case CPU_PPC_7457:    /* PowerPC 7457                  */
2338
    case CPU_PPC_7457C:
2339
    case CPU_PPC_7457A:   /* PowerPC 7457A                 */
2340
        break;
2341
#endif
2342

    
2343
    /* 64 bits PowerPC                                     */
2344
#if defined (TARGET_PPC64)
2345
#if defined (TODO)
2346
    case CPU_PPC_620:     /* PowerPC 620                   */
2347
    case CPU_PPC_630:     /* PowerPC 630 (Power 3)         */
2348
    case CPU_PPC_631:     /* PowerPC 631 (Power 3+)        */
2349
    case CPU_PPC_POWER4:  /* Power 4                       */
2350
    case CPU_PPC_POWER4P: /* Power 4+                      */
2351
    case CPU_PPC_POWER5:  /* Power 5                       */
2352
    case CPU_PPC_POWER5P: /* Power 5+                      */
2353
#endif
2354
        break;
2355

    
2356
    case CPU_PPC_970:     /* PowerPC 970                   */
2357
    case CPU_PPC_970FX10: /* PowerPC 970 FX                */
2358
    case CPU_PPC_970FX20:
2359
    case CPU_PPC_970FX21:
2360
    case CPU_PPC_970FX30:
2361
    case CPU_PPC_970FX31:
2362
    case CPU_PPC_970MP10: /* PowerPC 970 MP                */
2363
    case CPU_PPC_970MP11:
2364
        gen_spr_generic(env);
2365
        gen_spr_ne_601(env);
2366
        /* XXX: not correct */
2367
        gen_low_BATs(env);
2368
        /* Time base */
2369
        gen_tbl(env);
2370
        gen_spr_7xx(env);
2371
        /* Hardware implementation registers */
2372
        /* XXX : not implemented */
2373
        spr_register(env, SPR_HID0, "HID0",
2374
                     SPR_NOACCESS, SPR_NOACCESS,
2375
                     &spr_read_generic, &spr_write_generic,
2376
                     0x00000000);
2377
        /* XXX : not implemented */
2378
        spr_register(env, SPR_HID1, "HID1",
2379
                     SPR_NOACCESS, SPR_NOACCESS,
2380
                     &spr_read_generic, &spr_write_generic,
2381
                     0x00000000);
2382
        /* XXX : not implemented */
2383
        spr_register(env, SPR_750_HID2, "HID2",
2384
                     SPR_NOACCESS, SPR_NOACCESS,
2385
                     &spr_read_generic, &spr_write_generic,
2386
                     0x00000000);
2387
        /* Allocate hardware IRQ controller */
2388
        ppc970_irq_init(env);
2389
        break;
2390

    
2391
#if defined (TODO)
2392
    case CPU_PPC_CELL10:  /* Cell family                   */
2393
    case CPU_PPC_CELL20:
2394
    case CPU_PPC_CELL30:
2395
    case CPU_PPC_CELL31:
2396
#endif
2397
        break;
2398

    
2399
#if defined (TODO)
2400
    case CPU_PPC_RS64:    /* Apache (RS64/A35)             */
2401
    case CPU_PPC_RS64II:  /* NorthStar (RS64-II/A50)       */
2402
    case CPU_PPC_RS64III: /* Pulsar (RS64-III)             */
2403
    case CPU_PPC_RS64IV:  /* IceStar/IStar/SStar (RS64-IV) */
2404
#endif
2405
        break;
2406
#endif /* defined (TARGET_PPC64) */
2407

    
2408
#if defined (TODO)
2409
        /* POWER                                               */
2410
    case CPU_POWER:       /* POWER                         */
2411
    case CPU_POWER2:      /* POWER2                        */
2412
        break;
2413
#endif
2414

    
2415
    default:
2416
        gen_spr_generic(env);
2417
        /* XXX: TODO: allocate internal IRQ controller */
2418
        break;
2419
    }
2420
    if (env->nb_BATs == -1)
2421
        env->nb_BATs = 4;
2422
    /* Allocate TLBs buffer when needed */
2423
    if (env->nb_tlb != 0) {
2424
        int nb_tlb = env->nb_tlb;
2425
        if (env->id_tlbs != 0)
2426
            nb_tlb *= 2;
2427
        env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
2428
        /* Pre-compute some useful values */
2429
        env->tlb_per_way = env->nb_tlb / env->nb_ways;
2430
    }
2431
}
2432

    
2433
#if defined(PPC_DUMP_CPU)
2434
static void dump_sprs (CPUPPCState *env)
2435
{
2436
    ppc_spr_t *spr;
2437
    uint32_t pvr = env->spr[SPR_PVR];
2438
    uint32_t sr, sw, ur, uw;
2439
    int i, j, n;
2440

    
2441
    printf("* SPRs for PVR=%08x\n", pvr);
2442
    for (i = 0; i < 32; i++) {
2443
        for (j = 0; j < 32; j++) {
2444
            n = (i << 5) | j;
2445
            spr = &env->spr_cb[n];
2446
#if !defined(CONFIG_USER_ONLY)
2447
            sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
2448
            sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
2449
#else
2450
            sw = 0;
2451
            sr = 0;
2452
#endif
2453
            uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
2454
            ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
2455
            if (sw || sr || uw || ur) {
2456
                printf("%4d (%03x) %8s s%c%c u%c%c\n",
2457
                       (i << 5) | j, (i << 5) | j, spr->name,
2458
                       sw ? 'w' : '-', sr ? 'r' : '-',
2459
                       uw ? 'w' : '-', ur ? 'r' : '-');
2460
            }
2461
        }
2462
    }
2463
    fflush(stdout);
2464
    fflush(stderr);
2465
}
2466
#endif
2467

    
2468
/*****************************************************************************/
2469
#include <stdlib.h>
2470
#include <string.h>
2471

    
2472
int fflush (FILE *stream);
2473

    
2474
/* Opcode types */
2475
enum {
2476
    PPC_DIRECT   = 0, /* Opcode routine        */
2477
    PPC_INDIRECT = 1, /* Indirect opcode table */
2478
};
2479

    
2480
static inline int is_indirect_opcode (void *handler)
2481
{
2482
    return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2483
}
2484

    
2485
static inline opc_handler_t **ind_table(void *handler)
2486
{
2487
    return (opc_handler_t **)((unsigned long)handler & ~3);
2488
}
2489

    
2490
/* Instruction table creation */
2491
/* Opcodes tables creation */
2492
static void fill_new_table (opc_handler_t **table, int len)
2493
{
2494
    int i;
2495

    
2496
    for (i = 0; i < len; i++)
2497
        table[i] = &invalid_handler;
2498
}
2499

    
2500
static int create_new_table (opc_handler_t **table, unsigned char idx)
2501
{
2502
    opc_handler_t **tmp;
2503

    
2504
    tmp = malloc(0x20 * sizeof(opc_handler_t));
2505
    if (tmp == NULL)
2506
        return -1;
2507
    fill_new_table(tmp, 0x20);
2508
    table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2509

    
2510
    return 0;
2511
}
2512

    
2513
static int insert_in_table (opc_handler_t **table, unsigned char idx,
2514
                            opc_handler_t *handler)
2515
{
2516
    if (table[idx] != &invalid_handler)
2517
        return -1;
2518
    table[idx] = handler;
2519

    
2520
    return 0;
2521
}
2522

    
2523
static int register_direct_insn (opc_handler_t **ppc_opcodes,
2524
                                 unsigned char idx, opc_handler_t *handler)
2525
{
2526
    if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2527
        printf("*** ERROR: opcode %02x already assigned in main "
2528
               "opcode table\n", idx);
2529
        return -1;
2530
    }
2531

    
2532
    return 0;
2533
}
2534

    
2535
static int register_ind_in_table (opc_handler_t **table,
2536
                                  unsigned char idx1, unsigned char idx2,
2537
                                  opc_handler_t *handler)
2538
{
2539
    if (table[idx1] == &invalid_handler) {
2540
        if (create_new_table(table, idx1) < 0) {
2541
            printf("*** ERROR: unable to create indirect table "
2542
                   "idx=%02x\n", idx1);
2543
            return -1;
2544
        }
2545
    } else {
2546
        if (!is_indirect_opcode(table[idx1])) {
2547
            printf("*** ERROR: idx %02x already assigned to a direct "
2548
                   "opcode\n", idx1);
2549
            return -1;
2550
        }
2551
    }
2552
    if (handler != NULL &&
2553
        insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2554
        printf("*** ERROR: opcode %02x already assigned in "
2555
               "opcode table %02x\n", idx2, idx1);
2556
        return -1;
2557
    }
2558

    
2559
    return 0;
2560
}
2561

    
2562
static int register_ind_insn (opc_handler_t **ppc_opcodes,
2563
                              unsigned char idx1, unsigned char idx2,
2564
                              opc_handler_t *handler)
2565
{
2566
    int ret;
2567

    
2568
    ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2569

    
2570
    return ret;
2571
}
2572

    
2573
static int register_dblind_insn (opc_handler_t **ppc_opcodes, 
2574
                                 unsigned char idx1, unsigned char idx2,
2575
                                 unsigned char idx3, opc_handler_t *handler)
2576
{
2577
    if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2578
        printf("*** ERROR: unable to join indirect table idx "
2579
               "[%02x-%02x]\n", idx1, idx2);
2580
        return -1;
2581
    }
2582
    if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2583
                              handler) < 0) {
2584
        printf("*** ERROR: unable to insert opcode "
2585
               "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2586
        return -1;
2587
    }
2588

    
2589
    return 0;
2590
}
2591

    
2592
static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2593
{
2594
    if (insn->opc2 != 0xFF) {
2595
        if (insn->opc3 != 0xFF) {
2596
            if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2597
                                     insn->opc3, &insn->handler) < 0)
2598
                return -1;
2599
        } else {
2600
            if (register_ind_insn(ppc_opcodes, insn->opc1,
2601
                                  insn->opc2, &insn->handler) < 0)
2602
                return -1;
2603
        }
2604
    } else {
2605
        if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2606
            return -1;
2607
    }
2608

    
2609
    return 0;
2610
}
2611

    
2612
static int test_opcode_table (opc_handler_t **table, int len)
2613
{
2614
    int i, count, tmp;
2615

    
2616
    for (i = 0, count = 0; i < len; i++) {
2617
        /* Consistency fixup */
2618
        if (table[i] == NULL)
2619
            table[i] = &invalid_handler;
2620
        if (table[i] != &invalid_handler) {
2621
            if (is_indirect_opcode(table[i])) {
2622
                tmp = test_opcode_table(ind_table(table[i]), 0x20);
2623
                if (tmp == 0) {
2624
                    free(table[i]);
2625
                    table[i] = &invalid_handler;
2626
                } else {
2627
                    count++;
2628
                }
2629
            } else {
2630
                count++;
2631
            }
2632
        }
2633
    }
2634

    
2635
    return count;
2636
}
2637

    
2638
static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2639
{
2640
    if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2641
        printf("*** WARNING: no opcode defined !\n");
2642
}
2643

    
2644
/*****************************************************************************/
2645
static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
2646
{
2647
    opcode_t *opc, *start, *end;
2648

    
2649
    fill_new_table(env->opcodes, 0x40);
2650
#if defined(PPC_DUMP_CPU)
2651
    printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
2652
           " %08x\n",
2653
           def->pvr, def->name, def->insns_flags, def->flags);
2654
#endif
2655
    if (&opc_start < &opc_end) {
2656
        start = &opc_start;
2657
        end = &opc_end;
2658
    } else {
2659
        start = &opc_end;
2660
        end = &opc_start;
2661
    }
2662
    for (opc = start + 1; opc != end; opc++) {
2663
        if ((opc->handler.type & def->insns_flags) != 0) {
2664
            if (register_insn(env->opcodes, opc) < 0) {
2665
                printf("*** ERROR initializing PowerPC instruction "
2666
                       "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2667
                       opc->opc3);
2668
                return -1;
2669
            }
2670
#if defined(PPC_DUMP_CPU)
2671
            if (opc1 != 0x00) {
2672
                if (opc->opc3 == 0xFF) {
2673
                    if (opc->opc2 == 0xFF) {
2674
                        printf(" %02x -- -- (%2d ----) : %s\n",
2675
                               opc->opc1, opc->opc1, opc->oname);
2676
                    } else {
2677
                        printf(" %02x %02x -- (%2d %4d) : %s\n",
2678
                               opc->opc1, opc->opc2, opc->opc1, opc->opc2,
2679
                               opc->oname);
2680
                    }
2681
                } else {
2682
                    printf(" %02x %02x %02x (%2d %4d) : %s\n",
2683
                           opc->opc1, opc->opc2, opc->opc3,
2684
                           opc->opc1, (opc->opc3 << 5) | opc->opc2,
2685
                           opc->oname);
2686
                }
2687
            }
2688
#endif
2689
        }
2690
    }
2691
    fix_opcode_tables(env->opcodes);
2692
    fflush(stdout);
2693
    fflush(stderr);
2694

    
2695
    return 0;
2696
}
2697

    
2698
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
2699
{
2700
    env->msr_mask = def->msr_mask;
2701
    env->flags = def->flags;
2702
    if (create_ppc_opcodes(env, def) < 0)
2703
        return -1;
2704
    init_ppc_proc(env, def);
2705
#if defined(PPC_DUMP_CPU)
2706
    dump_sprs(env);
2707
    if (env->tlb != NULL) {
2708
        printf("%d %s TLB in %d ways\n", env->nb_tlb,
2709
               env->id_tlbs ? "splitted" : "merged", env->nb_ways);
2710
    }
2711
#endif
2712

    
2713
    return 0;
2714
}
2715

    
2716
/*****************************************************************************/
2717
/* PowerPC CPU definitions */
2718
static ppc_def_t ppc_defs[] = {
2719
    /* Embedded PowerPC */
2720
#if defined (TODO)
2721
    /* PowerPC 401 */
2722
    {
2723
        .name        = "401",
2724
        .pvr         = CPU_PPC_401,
2725
        .pvr_mask    = 0xFFFF0000,
2726
        .insns_flags = PPC_INSNS_401,
2727
        .flags       = PPC_FLAGS_401,
2728
        .msr_mask    = xxx,
2729
    },
2730
#endif
2731
#if defined (TODO)
2732
    /* IOP480 (401 microcontroler) */
2733
    {
2734
        .name        = "iop480",
2735
        .pvr         = CPU_PPC_IOP480,
2736
        .pvr_mask    = 0xFFFF0000,
2737
        .insns_flags = PPC_INSNS_401,
2738
        .flags       = PPC_FLAGS_401,
2739
        .msr_mask    = xxx,
2740
    },
2741
#endif
2742
#if defined (TODO)
2743
    /* IBM Processor for Network Resources */
2744
    {
2745
        .name        = "Cobra",
2746
        .pvr         = CPU_PPC_COBRA,
2747
        .pvr_mask    = 0xFFFF0000,
2748
        .insns_flags = PPC_INSNS_401,
2749
        .flags       = PPC_FLAGS_401,
2750
        .msr_mask    = xxx,
2751
    },
2752
#endif
2753
#if defined (TODO)
2754
    /* Generic PowerPC 403 */
2755
    {
2756
        .name        = "403",
2757
        .pvr         = CPU_PPC_403,
2758
        .pvr_mask    = 0xFFFFFF00,
2759
        .insns_flags = PPC_INSNS_403,
2760
        .flags       = PPC_FLAGS_403,
2761
        .msr_mask    = 0x000000000007D23DULL,
2762
    },
2763
#endif
2764
#if defined (TODO)
2765
    /* PowerPC 403 GA */
2766
    {
2767
        .name        = "403ga",
2768
        .pvr         = CPU_PPC_403GA,
2769
        .pvr_mask    = 0xFFFFFF00,
2770
        .insns_flags = PPC_INSNS_403,
2771
        .flags       = PPC_FLAGS_403,
2772
        .msr_mask    = 0x000000000007D23DULL,
2773
    },
2774
#endif
2775
#if defined (TODO)
2776
    /* PowerPC 403 GB */
2777
    {
2778
        .name        = "403gb",
2779
        .pvr         = CPU_PPC_403GB,
2780
        .pvr_mask    = 0xFFFFFF00,
2781
        .insns_flags = PPC_INSNS_403,
2782
        .flags       = PPC_FLAGS_403,
2783
        .msr_mask    = 0x000000000007D23DULL,
2784
    },
2785
#endif
2786
#if defined (TODO)
2787
    /* PowerPC 403 GC */
2788
    {
2789
        .name        = "403gc",
2790
        .pvr         = CPU_PPC_403GC,
2791
        .pvr_mask    = 0xFFFFFF00,
2792
        .insns_flags = PPC_INSNS_403,
2793
        .flags       = PPC_FLAGS_403,
2794
        .msr_mask    = 0x000000000007D23DULL,
2795
    },
2796
#endif
2797
#if defined (TODO)
2798
    /* PowerPC 403 GCX */
2799
    {
2800
        .name        = "403gcx",
2801
        .pvr         = CPU_PPC_403GCX,
2802
        .pvr_mask    = 0xFFFFFF00,
2803
        .insns_flags = PPC_INSNS_403,
2804
        .flags       = PPC_FLAGS_403,
2805
        .msr_mask    = 0x000000000007D23DULL,
2806
    },
2807
#endif
2808
    /* Generic PowerPC 405 */
2809
    {
2810
        .name        = "405",
2811
        .pvr         = CPU_PPC_405,
2812
        .pvr_mask    = 0xFFFF0000,
2813
        .insns_flags = PPC_INSNS_405,
2814
        .flags       = PPC_FLAGS_405,
2815
        .msr_mask    = 0x00000000020EFF30ULL,
2816
    },
2817
    /* PowerPC 405 CR */
2818
    {
2819
        .name        = "405cr",
2820
        .pvr         = CPU_PPC_405,
2821
        .pvr_mask    = 0xFFFFFFFF,
2822
        .insns_flags = PPC_INSNS_405,
2823
        .flags       = PPC_FLAGS_405,
2824
        .msr_mask    = 0x00000000020EFF30ULL,
2825
    },
2826
#if defined (TODO)
2827
    /* PowerPC 405 GP */
2828
    {
2829
        .name        = "405gp",
2830
        .pvr         = CPU_PPC_405,
2831
        .pvr_mask    = 0xFFFFFFFF,
2832
        .insns_flags = PPC_INSNS_405,
2833
        .flags       = PPC_FLAGS_405,
2834
        .msr_mask    = 0x00000000020EFF30ULL,
2835
    },
2836
#endif
2837
    /* PowerPC 405 EP */
2838
    {
2839
        .name        = "405ep",
2840
        .pvr         = CPU_PPC_405EP,
2841
        .pvr_mask    = 0xFFFFFFFF,
2842
        .insns_flags = PPC_INSNS_405,
2843
        .flags       = PPC_FLAGS_405,
2844
        .msr_mask    = 0x00000000020EFF30ULL,
2845
    },
2846
#if defined (TODO)
2847
    /* PowerPC 405 EZ */
2848
    {
2849
        .name        = "405ez",
2850
        .pvr         = CPU_PPC_405EZ,
2851
        .pvr_mask    = 0xFFFFFFFF,
2852
        .insns_flags = PPC_INSNS_405,
2853
        .flags       = PPC_FLAGS_405,
2854
        .msr_mask    = 0x00000000020EFF30ULL,
2855
    },
2856
#endif
2857
#if defined (TODO)
2858
    /* PowerPC 405 GPR */
2859
    {
2860
        .name        = "405gpr",
2861
        .pvr         = CPU_PPC_405GPR,
2862
        .pvr_mask    = 0xFFFFFFFF,
2863
        .insns_flags = PPC_INSNS_405,
2864
        .flags       = PPC_FLAGS_405,
2865
        .msr_mask    = 0x00000000020EFF30ULL,
2866
    },
2867
#endif
2868
    /* PowerPC 405 D2 */
2869
    {
2870
        .name        = "405d2",
2871
        .pvr         = CPU_PPC_405D2,
2872
        .pvr_mask    = 0xFFFFFFFF,
2873
        .insns_flags = PPC_INSNS_405,
2874
        .flags       = PPC_FLAGS_405,
2875
        .msr_mask    = 0x00000000020EFF30ULL,
2876
    },
2877
    /* PowerPC 405 D4 */
2878
    {
2879
        .name        = "405d4",
2880
        .pvr         = CPU_PPC_405D4,
2881
        .pvr_mask    = 0xFFFFFFFF,
2882
        .insns_flags = PPC_INSNS_405,
2883
        .flags       = PPC_FLAGS_405,
2884
        .msr_mask    = 0x00000000020EFF30ULL,
2885
    },
2886
#if defined (TODO)
2887
    /* Npe405 H */
2888
    {
2889
        .name        = "Npe405H",
2890
        .pvr         = CPU_PPC_NPE405H,
2891
        .pvr_mask    = 0xFFFFFFFF,
2892
            .insns_flags = PPC_INSNS_405,
2893
        .flags       = PPC_FLAGS_405,
2894
        .msr_mask    = 0x00000000020EFF30ULL,
2895
    },
2896
#endif
2897
#if defined (TODO)
2898
    /* Npe405 L */
2899
    {
2900
        .name        = "Npe405L",
2901
        .pvr         = CPU_PPC_NPE405L,
2902
        .pvr_mask    = 0xFFFFFFFF,
2903
        .insns_flags = PPC_INSNS_405,
2904
        .flags       = PPC_FLAGS_405,
2905
        .msr_mask    = 0x00000000020EFF30ULL,
2906
    },
2907
#endif
2908
#if defined (TODO)
2909
    /* STB010000 */
2910
    {
2911
        .name        = "STB01000",
2912
        .pvr         = CPU_PPC_STB01000,
2913
        .pvr_mask    = 0xFFFFFFFF,
2914
        .insns_flags = PPC_INSNS_405,
2915
        .flags       = PPC_FLAGS_405,
2916
        .msr_mask    = 0x00000000020EFF30ULL,
2917
    },
2918
#endif
2919
#if defined (TODO)
2920
    /* STB01010 */
2921
    {
2922
        .name        = "STB01010",
2923
        .pvr         = CPU_PPC_STB01010,
2924
        .pvr_mask    = 0xFFFFFFFF,
2925
        .insns_flags = PPC_INSNS_405,
2926
        .flags       = PPC_FLAGS_405,
2927
        .msr_mask    = 0x00000000020EFF30ULL,
2928
    },
2929
#endif
2930
#if defined (TODO)
2931
    /* STB0210 */
2932
    {
2933
        .name        = "STB0210",
2934
        .pvr         = CPU_PPC_STB0210,
2935
        .pvr_mask    = 0xFFFFFFFF,
2936
        .insns_flags = PPC_INSNS_405,
2937
        .flags       = PPC_FLAGS_405,
2938
        .msr_mask    = 0x00000000020EFF30ULL,
2939
    },
2940
#endif
2941
#if defined (TODO)
2942
    /* STB03xx */
2943
    {
2944
        .name        = "STB03",
2945
        .pvr         = CPU_PPC_STB03,
2946
        .pvr_mask    = 0xFFFFFFFF,
2947
        .insns_flags = PPC_INSNS_405,
2948
        .flags       = PPC_FLAGS_405,
2949
        .msr_mask    = 0x00000000020EFF30ULL,
2950
    },
2951
#endif
2952
#if defined (TODO)
2953
    /* STB043x */
2954
    {
2955
        .name        = "STB043",
2956
        .pvr         = CPU_PPC_STB043,
2957
        .pvr_mask    = 0xFFFFFFFF,
2958
        .insns_flags = PPC_INSNS_405,
2959
        .flags       = PPC_FLAGS_405,
2960
        .msr_mask    = 0x00000000020EFF30ULL,
2961
    },
2962
#endif
2963
#if defined (TODO)
2964
    /* STB045x */
2965
    {
2966
        .name        = "STB045",
2967
        .pvr         = CPU_PPC_STB045,
2968
        .pvr_mask    = 0xFFFFFFFF,
2969
        .insns_flags = PPC_INSNS_405,
2970
        .flags       = PPC_FLAGS_405,
2971
        .msr_mask    = 0x00000000020EFF30ULL,
2972
    },
2973
#endif
2974
#if defined (TODO)
2975
    /* STB25xx */
2976
    {
2977
        .name        = "STB25",
2978
        .pvr         = CPU_PPC_STB25,
2979
        .pvr_mask    = 0xFFFFFFFF,
2980
        .insns_flags = PPC_INSNS_405,
2981
        .flags       = PPC_FLAGS_405,
2982
        .msr_mask    = 0x00000000020EFF30ULL,
2983
    },
2984
#endif
2985
#if defined (TODO)
2986
    /* STB130 */
2987
    {
2988
        .name        = "STB130",
2989
        .pvr         = CPU_PPC_STB130,
2990
        .pvr_mask    = 0xFFFFFFFF,
2991
        .insns_flags = PPC_INSNS_405,
2992
        .flags       = PPC_FLAGS_405,
2993
        .msr_mask    = 0x00000000020EFF30ULL,
2994
    },
2995
#endif
2996
        /* Xilinx PowerPC 405 cores */
2997
#if defined (TODO)
2998
    {
2999
        .name        = "x2vp4",
3000
        .pvr         = CPU_PPC_X2VP4,
3001
        .pvr_mask    = 0xFFFFFFFF,
3002
        .insns_flags = PPC_INSNS_405,
3003
        .flags       = PPC_FLAGS_405,
3004
        .msr_mask    = 0x00000000020EFF30ULL,
3005
    },
3006
    {
3007
        .name        = "x2vp7",
3008
        .pvr         = CPU_PPC_X2VP7,
3009
        .pvr_mask    = 0xFFFFFFFF,
3010
        .insns_flags = PPC_INSNS_405,
3011
        .flags       = PPC_FLAGS_405,
3012
        .msr_mask    = 0x00000000020EFF30ULL,
3013
    },
3014
    {
3015
        .name        = "x2vp20",
3016
        .pvr         = CPU_PPC_X2VP20,
3017
        .pvr_mask    = 0xFFFFFFFF,
3018
        .insns_flags = PPC_INSNS_405,
3019
        .flags       = PPC_FLAGS_405,
3020
        .msr_mask    = 0x00000000020EFF30ULL,
3021
    },
3022
    {
3023
        .name        = "x2vp50",
3024
        .pvr         = CPU_PPC_X2VP50,
3025
        .pvr_mask    = 0xFFFFFFFF,
3026
        .insns_flags = PPC_INSNS_405,
3027
        .flags       = PPC_FLAGS_405,
3028
        .msr_mask    = 0x00000000020EFF30ULL,
3029
    },
3030
#endif
3031
#if defined (TODO)
3032
    /* PowerPC 440 EP */
3033
    {
3034
        .name        = "440ep",
3035
        .pvr         = CPU_PPC_440EP,
3036
        .pvr_mask    = 0xFFFF0000,
3037
        .insns_flags = PPC_INSNS_440,
3038
        .flags       = PPC_FLAGS_440,
3039
        .msr_mask    = 0x000000000006D630ULL,
3040
    },
3041
#endif
3042
#if defined (TODO)
3043
    /* PowerPC 440 GR */
3044
    {
3045
        .name        = "440gr",
3046
        .pvr         = CPU_PPC_440GR,
3047
        .pvr_mask    = 0xFFFF0000,
3048
        .insns_flags = PPC_INSNS_440,
3049
        .flags       = PPC_FLAGS_440,
3050
        .msr_mask    = 0x000000000006D630ULL,
3051
    },
3052
#endif
3053
#if defined (TODO)
3054
    /* PowerPC 440 GP */
3055
    {
3056
        .name        = "440gp",
3057
        .pvr         = CPU_PPC_440GP,
3058
        .pvr_mask    = 0xFFFFFF00,
3059
        .insns_flags = PPC_INSNS_440,
3060
        .flags       = PPC_FLAGS_440,
3061
        .msr_mask    = 0x000000000006D630ULL,
3062
    },
3063
#endif
3064
#if defined (TODO)
3065
    /* PowerPC 440 GX */
3066
    {
3067
        .name        = "440gx",
3068
        .pvr         = CPU_PPC_440GX,
3069
        .pvr_mask    = 0xFFFF0000,
3070
        .insns_flags = PPC_INSNS_405,
3071
        .flags       = PPC_FLAGS_440,
3072
        .msr_mask    = 0x000000000006D630ULL,
3073
    },
3074
#endif
3075
#if defined (TODO)
3076
    /* PowerPC 440 GXc */
3077
    {
3078
        .name        = "440gxc",
3079
        .pvr         = CPU_PPC_440GXC,
3080
        .pvr_mask    = 0xFFFF0000,
3081
        .insns_flags = PPC_INSNS_405,
3082
        .flags       = PPC_FLAGS_440,
3083
        .msr_mask    = 0x000000000006D630ULL,
3084
    },
3085
#endif
3086
#if defined (TODO)
3087
    /* PowerPC 440 GXf */
3088
    {
3089
        .name        = "440gxf",
3090
        .pvr         = CPU_PPC_440GXF,
3091
        .pvr_mask    = 0xFFFF0000,
3092
        .insns_flags = PPC_INSNS_405,
3093
        .flags       = PPC_FLAGS_440,
3094
        .msr_mask    = 0x000000000006D630ULL,
3095
    },
3096
#endif
3097
#if defined (TODO)
3098
    /* PowerPC 440 SP */
3099
    {
3100
        .name        = "440sp",
3101
        .pvr         = CPU_PPC_440SP,
3102
        .pvr_mask    = 0xFFFF0000,
3103
        .insns_flags = PPC_INSNS_405,
3104
        .flags       = PPC_FLAGS_440,
3105
        .msr_mask    = 0x000000000006D630ULL,
3106
    },
3107
#endif
3108
#if defined (TODO)
3109
    /* PowerPC 440 SP2 */
3110
    {
3111
        .name        = "440sp2",
3112
        .pvr         = CPU_PPC_440SP2,
3113
        .pvr_mask    = 0xFFFF0000,
3114
        .insns_flags = PPC_INSNS_405,
3115
        .flags       = PPC_FLAGS_440,
3116
        .msr_mask    = 0x000000000006D630ULL,
3117
    },
3118
#endif
3119
#if defined (TODO)
3120
    /* PowerPC 440 SPE */
3121
    {
3122
        .name        = "440spe",
3123
        .pvr         = CPU_PPC_440SPE,
3124
        .pvr_mask    = 0xFFFF0000,
3125
        .insns_flags = PPC_INSNS_405,
3126
        .flags       = PPC_FLAGS_440,
3127
        .msr_mask    = 0x000000000006D630ULL,
3128
    },
3129
#endif
3130
    /* Fake generic BookE PowerPC */
3131
    {
3132
        .name        = "BookE",
3133
        .pvr         = CPU_PPC_e500,
3134
        .pvr_mask    = 0xFFFFFFFF,
3135
        .insns_flags = PPC_INSNS_BOOKE,
3136
        .flags       = PPC_FLAGS_BOOKE,
3137
        .msr_mask    = 0x000000000006D630ULL,
3138
    },
3139
    /* PowerPC 460 cores - TODO */
3140
    /* PowerPC MPC 5xx cores - TODO */
3141
    /* PowerPC MPC 8xx cores - TODO */
3142
    /* PowerPC MPC 8xxx cores - TODO */
3143
    /* e200 cores - TODO */
3144
    /* e500 cores - TODO */
3145
    /* e600 cores - TODO */
3146

    
3147
    /* 32 bits "classic" PowerPC */
3148
#if defined (TODO)
3149
    /* PowerPC 601 */
3150
    {
3151
        .name        = "601",
3152
        .pvr         = CPU_PPC_601,
3153
        .pvr_mask    = 0xFFFF0000,
3154
        .insns_flags = PPC_INSNS_601,
3155
        .flags       = PPC_FLAGS_601,
3156
        .msr_mask    = 0x000000000000FD70ULL,
3157
    },
3158
#endif
3159
#if defined (TODO)
3160
    /* PowerPC 602 */
3161
    {
3162
        .name        = "602",
3163
        .pvr         = CPU_PPC_602,
3164
        .pvr_mask    = 0xFFFF0000,
3165
        .insns_flags = PPC_INSNS_602,
3166
        .flags       = PPC_FLAGS_602,
3167
        .msr_mask    = 0x0000000000C7FF73ULL,
3168
    },
3169
#endif
3170
    /* PowerPC 603 */
3171
    {
3172
        .name        = "603",
3173
        .pvr         = CPU_PPC_603,
3174
        .pvr_mask    = 0xFFFFFFFF,
3175
        .insns_flags = PPC_INSNS_603,
3176
        .flags       = PPC_FLAGS_603,
3177
        .msr_mask    = 0x000000000007FF73ULL,
3178
    },
3179
    /* PowerPC 603e */
3180
    {
3181
        .name        = "603e",
3182
        .pvr         = CPU_PPC_603E,
3183
        .pvr_mask    = 0xFFFFFFFF,
3184
        .insns_flags = PPC_INSNS_603,
3185
        .flags       = PPC_FLAGS_603,
3186
        .msr_mask    = 0x000000000007FF73ULL,
3187
    },
3188
    {
3189
        .name        = "Stretch",
3190
        .pvr         = CPU_PPC_603E,
3191
        .pvr_mask    = 0xFFFFFFFF,
3192
        .insns_flags = PPC_INSNS_603,
3193
        .flags       = PPC_FLAGS_603,
3194
        .msr_mask    = 0x000000000007FF73ULL,
3195
    },
3196
    /* PowerPC 603p */
3197
    {
3198
        .name        = "603p",
3199
        .pvr         = CPU_PPC_603P,
3200
        .pvr_mask    = 0xFFFFFFFF,
3201
        .insns_flags = PPC_INSNS_603,
3202
        .flags       = PPC_FLAGS_603,
3203
        .msr_mask    = 0x000000000007FF73ULL,
3204
    },
3205
    /* PowerPC 603e7 */
3206
    {
3207
        .name        = "603e7",
3208
        .pvr         = CPU_PPC_603E7,
3209
        .pvr_mask    = 0xFFFFFFFF,
3210
        .insns_flags = PPC_INSNS_603,
3211
        .flags       = PPC_FLAGS_603,
3212
        .msr_mask    = 0x000000000007FF73ULL,
3213
    },
3214
    /* PowerPC 603e7v */
3215
    {
3216
        .name        = "603e7v",
3217
        .pvr         = CPU_PPC_603E7v,
3218
        .pvr_mask    = 0xFFFFFFFF,
3219
        .insns_flags = PPC_INSNS_603,
3220
        .flags       = PPC_FLAGS_603,
3221
        .msr_mask    = 0x000000000007FF73ULL,
3222
    },
3223
    /* PowerPC 603e7v2 */
3224
    {
3225
        .name        = "603e7v2",
3226
        .pvr         = CPU_PPC_603E7v2,
3227
        .pvr_mask    = 0xFFFFFFFF,
3228
        .insns_flags = PPC_INSNS_603,
3229
        .flags       = PPC_FLAGS_603,
3230
        .msr_mask    = 0x000000000007FF73ULL,
3231
    },
3232
    /* PowerPC 603r */
3233
    {
3234
        .name        = "603r",
3235
        .pvr         = CPU_PPC_603R,
3236
        .pvr_mask    = 0xFFFFFFFF,
3237
        .insns_flags = PPC_INSNS_603,
3238
        .flags       = PPC_FLAGS_603,
3239
        .msr_mask    = 0x000000000007FF73ULL,
3240
    },
3241
    {
3242
        .name        = "Goldeneye",
3243
        .pvr         = CPU_PPC_603R,
3244
        .pvr_mask    = 0xFFFFFFFF,
3245
        .insns_flags = PPC_INSNS_603,
3246
        .flags       = PPC_FLAGS_603,
3247
        .msr_mask    = 0x000000000007FF73ULL,
3248
    },
3249
#if defined (TODO)
3250
    /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
3251
    {
3252
        .name        = "G2",
3253
        .pvr         = CPU_PPC_G2,
3254
        .pvr_mask    = 0xFFFF0000,
3255
        .insns_flags = PPC_INSNS_G2,
3256
        .flags       = PPC_FLAGS_G2,
3257
        .msr_mask    = 0x000000000006FFF2ULL,
3258
    },
3259
    {
3260
        .name        = "G2h4",
3261
        .pvr         = CPU_PPC_G2H4,
3262
        .pvr_mask    = 0xFFFF0000,
3263
        .insns_flags = PPC_INSNS_G2,
3264
        .flags       = PPC_FLAGS_G2,
3265
        .msr_mask    = 0x000000000006FFF2ULL,
3266
    },
3267
    {
3268
        .name        = "G2gp",
3269
        .pvr         = CPU_PPC_G2gp,
3270
        .pvr_mask    = 0xFFFF0000,
3271
        .insns_flags = PPC_INSNS_G2,
3272
        .flags       = PPC_FLAGS_G2,
3273
        .msr_mask    = 0x000000000006FFF2ULL,
3274
    },
3275
    {
3276
        .name        = "G2ls",
3277
        .pvr         = CPU_PPC_G2ls,
3278
        .pvr_mask    = 0xFFFF0000,
3279
        .insns_flags = PPC_INSNS_G2,
3280
        .flags       = PPC_FLAGS_G2,
3281
        .msr_mask    = 0x000000000006FFF2ULL,
3282
    },
3283
    { /* Same as G2, with LE mode support */
3284
        .name        = "G2le",
3285
        .pvr         = CPU_PPC_G2LE,
3286
        .pvr_mask    = 0xFFFF0000,
3287
        .insns_flags = PPC_INSNS_G2,
3288
        .flags       = PPC_FLAGS_G2,
3289
        .msr_mask    = 0x000000000007FFF3ULL,
3290
    },
3291
    {
3292
        .name        = "G2legp",
3293
        .pvr         = CPU_PPC_G2LEgp,
3294
        .pvr_mask    = 0xFFFF0000,
3295
        .insns_flags = PPC_INSNS_G2,
3296
        .flags       = PPC_FLAGS_G2,
3297
        .msr_mask    = 0x000000000007FFF3ULL,
3298
    },
3299
    {
3300
        .name        = "G2lels",
3301
        .pvr         = CPU_PPC_G2LEls,
3302
        .pvr_mask    = 0xFFFF0000,
3303
        .insns_flags = PPC_INSNS_G2,
3304
        .flags       = PPC_FLAGS_G2,
3305
        .msr_mask    = 0x000000000007FFF3ULL,
3306
    },
3307
#endif
3308
    /* PowerPC 604 */
3309
    {
3310
        .name        = "604",
3311
        .pvr         = CPU_PPC_604,
3312
        .pvr_mask    = 0xFFFFFFFF,
3313
        .insns_flags = PPC_INSNS_604,
3314
        .flags       = PPC_FLAGS_604,
3315
        .msr_mask    = 0x000000000005FF77ULL,
3316
    },
3317
    /* PowerPC 604e */
3318
    {
3319
        .name        = "604e",
3320
        .pvr         = CPU_PPC_604E,
3321
        .pvr_mask    = 0xFFFFFFFF,
3322
        .insns_flags = PPC_INSNS_604,
3323
        .flags       = PPC_FLAGS_604,
3324
        .msr_mask    = 0x000000000005FF77ULL,
3325
    },
3326
    /* PowerPC 604r */
3327
    {
3328
        .name        = "604r",
3329
        .pvr         = CPU_PPC_604R,
3330
        .pvr_mask    = 0xFFFFFFFF,
3331
        .insns_flags = PPC_INSNS_604,
3332
        .flags       = PPC_FLAGS_604,
3333
        .msr_mask    = 0x000000000005FF77ULL,
3334
    },
3335
    /* generic G3 */
3336
    {
3337
        .name        = "G3",
3338
        .pvr         = CPU_PPC_74x,
3339
        .pvr_mask    = 0xFFFFFFFF,
3340
        .insns_flags = PPC_INSNS_7x0,
3341
        .flags       = PPC_FLAGS_7x0,
3342
        .msr_mask    = 0x000000000007FF77ULL,
3343
    },
3344
    /* MPC740 (G3) */
3345
    {
3346
        .name        = "740",
3347
        .pvr         = CPU_PPC_74x,
3348
        .pvr_mask    = 0xFFFFFFFF,
3349
        .insns_flags = PPC_INSNS_7x0,
3350
        .flags       = PPC_FLAGS_7x0,
3351
        .msr_mask    = 0x000000000007FF77ULL,
3352
    },
3353
    {
3354
        .name        = "Arthur",
3355
        .pvr         = CPU_PPC_74x,
3356
        .pvr_mask    = 0xFFFFFFFF,
3357
        .insns_flags = PPC_INSNS_7x0,
3358
        .flags       = PPC_FLAGS_7x0,
3359
        .msr_mask    = 0x000000000007FF77ULL,
3360
    },
3361
#if defined (TODO)
3362
    /* MPC745 (G3) */
3363
    {
3364
        .name        = "745",
3365
        .pvr         = CPU_PPC_74x,
3366
        .pvr_mask    = 0xFFFFF000,
3367
        .insns_flags = PPC_INSNS_7x5,
3368
        .flags       = PPC_FLAGS_7x5,
3369
        .msr_mask    = 0x000000000007FF77ULL,
3370
    },
3371
    {
3372
        .name        = "Goldfinger",
3373
        .pvr         = CPU_PPC_74x,
3374
        .pvr_mask    = 0xFFFFF000,
3375
        .insns_flags = PPC_INSNS_7x5,
3376
        .flags       = PPC_FLAGS_7x5,
3377
        .msr_mask    = 0x000000000007FF77ULL,
3378
    },
3379
#endif
3380
    /* MPC750 (G3) */
3381
    {
3382
        .name        = "750",
3383
        .pvr         = CPU_PPC_74x,
3384
        .pvr_mask    = 0xFFFFFFFF,
3385
        .insns_flags = PPC_INSNS_7x0,
3386
        .flags       = PPC_FLAGS_7x0,
3387
        .msr_mask    = 0x000000000007FF77ULL,
3388
    },
3389
#if defined (TODO)
3390
    /* MPC755 (G3) */
3391
    {
3392
        .name        = "755",
3393
        .pvr         = CPU_PPC_755,
3394
        .pvr_mask    = 0xFFFFF000,
3395
        .insns_flags = PPC_INSNS_7x5,
3396
        .flags       = PPC_FLAGS_7x5,
3397
        .msr_mask    = 0x000000000007FF77ULL,
3398
    },
3399
#endif
3400
    /* MPC740P (G3) */
3401
    {
3402
        .name        = "740p",
3403
        .pvr         = CPU_PPC_74xP,
3404
        .pvr_mask    = 0xFFFFFFFF,
3405
        .insns_flags = PPC_INSNS_7x0,
3406
        .flags       = PPC_FLAGS_7x0,
3407
        .msr_mask    = 0x000000000007FF77ULL,
3408
    },
3409
    {
3410
        .name        = "Conan/Doyle",
3411
        .pvr         = CPU_PPC_74xP,
3412
        .pvr_mask    = 0xFFFFFFFF,
3413
        .insns_flags = PPC_INSNS_7x0,
3414
        .flags       = PPC_FLAGS_7x0,
3415
        .msr_mask    = 0x000000000007FF77ULL,
3416
    },
3417
#if defined (TODO)
3418
    /* MPC745P (G3) */
3419
    {
3420
        .name        = "745p",
3421
        .pvr         = CPU_PPC_74xP,
3422
        .pvr_mask    = 0xFFFFF000,
3423
        .insns_flags = PPC_INSNS_7x5,
3424
        .flags       = PPC_FLAGS_7x5,
3425
        .msr_mask    = 0x000000000007FF77ULL,
3426
    },
3427
#endif
3428
    /* MPC750P (G3) */
3429
    {
3430
        .name        = "750p",
3431
        .pvr         = CPU_PPC_74xP,
3432
        .pvr_mask    = 0xFFFFFFFF,
3433
        .insns_flags = PPC_INSNS_7x0,
3434
        .flags       = PPC_FLAGS_7x0,
3435
        .msr_mask    = 0x000000000007FF77ULL,
3436
    },
3437
#if defined (TODO)
3438
    /* MPC755P (G3) */
3439
    {
3440
        .name        = "755p",
3441
        .pvr         = CPU_PPC_74xP,
3442
        .pvr_mask    = 0xFFFFF000,
3443
        .insns_flags = PPC_INSNS_7x5,
3444
        .flags       = PPC_FLAGS_7x5,
3445
        .msr_mask    = 0x000000000007FF77ULL,
3446
    },
3447
#endif
3448
    /* IBM 750CXe (G3 embedded) */
3449
    {
3450
        .name        = "750cxe",
3451
        .pvr         = CPU_PPC_750CXE,
3452
        .pvr_mask    = 0xFFFFFFFF,
3453
        .insns_flags = PPC_INSNS_7x0,
3454
        .flags       = PPC_FLAGS_7x0,
3455
        .msr_mask    = 0x000000000007FF77ULL,
3456
    },
3457
    /* IBM 750FX (G3 embedded) */
3458
    {
3459
        .name        = "750fx",
3460
        .pvr         = CPU_PPC_750FX,
3461
        .pvr_mask    = 0xFFFFFFFF,
3462
        .insns_flags = PPC_INSNS_7x0,
3463
        .flags       = PPC_FLAGS_7x0,
3464
        .msr_mask    = 0x000000000007FF77ULL,
3465
    },
3466
    /* IBM 750GX (G3 embedded) */
3467
    {
3468
        .name        = "750gx",
3469
        .pvr         = CPU_PPC_750GX,
3470
        .pvr_mask    = 0xFFFFFFFF,
3471
        .insns_flags = PPC_INSNS_7x0,
3472
        .flags       = PPC_FLAGS_7x0,
3473
        .msr_mask    = 0x000000000007FF77ULL,
3474
    },
3475
#if defined (TODO)
3476
    /* generic G4 */
3477
    {
3478
        .name        = "G4",
3479
        .pvr         = CPU_PPC_7400,
3480
        .pvr_mask    = 0xFFFF0000,
3481
        .insns_flags = PPC_INSNS_74xx,
3482
        .flags       = PPC_FLAGS_74xx,
3483
        .msr_mask    = 0x000000000205FF77ULL,
3484
    },
3485
#endif
3486
#if defined (TODO)
3487
    /* PowerPC 7400 (G4) */
3488
    {
3489
        .name        = "7400",
3490
        .pvr         = CPU_PPC_7400,
3491
        .pvr_mask    = 0xFFFF0000,
3492
        .insns_flags = PPC_INSNS_74xx,
3493
        .flags       = PPC_FLAGS_74xx,
3494
        .msr_mask    = 0x000000000205FF77ULL,
3495
    },
3496
    {
3497
        .name        = "Max",
3498
        .pvr         = CPU_PPC_7400,
3499
        .pvr_mask    = 0xFFFF0000,
3500
        .insns_flags = PPC_INSNS_74xx,
3501
        .flags       = PPC_FLAGS_74xx,
3502
        .msr_mask    = 0x000000000205FF77ULL,
3503
    },
3504
#endif
3505
#if defined (TODO)
3506
    /* PowerPC 7410 (G4) */
3507
    {
3508
        .name        = "7410",
3509
        .pvr         = CPU_PPC_7410,
3510
        .pvr_mask    = 0xFFFF0000,
3511
        .insns_flags = PPC_INSNS_74xx,
3512
        .flags       = PPC_FLAGS_74xx,
3513
        .msr_mask    = 0x000000000205FF77ULL,
3514
    },
3515
    {
3516
        .name        = "Nitro",
3517
        .pvr         = CPU_PPC_7410,
3518
        .pvr_mask    = 0xFFFF0000,
3519
        .insns_flags = PPC_INSNS_74xx,
3520
        .flags       = PPC_FLAGS_74xx,
3521
        .msr_mask    = 0x000000000205FF77ULL,
3522
    },
3523
#endif
3524
    /* XXX: 7441 */
3525
    /* XXX: 7445 */
3526
    /* XXX: 7447 */
3527
    /* XXX: 7447A */
3528
#if defined (TODO)
3529
    /* PowerPC 7450 (G4) */
3530
    {
3531
        .name        = "7450",
3532
        .pvr         = CPU_PPC_7450,
3533
        .pvr_mask    = 0xFFFF0000,
3534
        .insns_flags = PPC_INSNS_74xx,
3535
        .flags       = PPC_FLAGS_74xx,
3536
        .msr_mask    = 0x000000000205FF77ULL,
3537
    },
3538
    {
3539
        .name        = "Vger",
3540
        .pvr         = CPU_PPC_7450,
3541
        .pvr_mask    = 0xFFFF0000,
3542
        .insns_flags = PPC_INSNS_74xx,
3543
        .flags       = PPC_FLAGS_74xx,
3544
        .msr_mask    = 0x000000000205FF77ULL,
3545
    },
3546
#endif
3547
    /* XXX: 7451 */
3548
#if defined (TODO)
3549
    /* PowerPC 7455 (G4) */
3550
    {
3551
        .name        = "7455",
3552
        .pvr         = CPU_PPC_7455,
3553
        .pvr_mask    = 0xFFFF0000,
3554
        .insns_flags = PPC_INSNS_74xx,
3555
        .flags       = PPC_FLAGS_74xx,
3556
        .msr_mask    = 0x000000000205FF77ULL,
3557
    },
3558
    {
3559
        .name        = "Apollo 6",
3560
        .pvr         = CPU_PPC_7455,
3561
        .pvr_mask    = 0xFFFF0000,
3562
        .insns_flags = PPC_INSNS_74xx,
3563
        .flags       = PPC_FLAGS_74xx,
3564
        .msr_mask    = 0x000000000205FF77ULL,
3565
    },
3566
#endif
3567
#if defined (TODO)
3568
    /* PowerPC 7457 (G4) */
3569
    {
3570
        .name        = "7457",
3571
        .pvr         = CPU_PPC_7457,
3572
        .pvr_mask    = 0xFFFF0000,
3573
        .insns_flags = PPC_INSNS_74xx,
3574
        .flags       = PPC_FLAGS_74xx,
3575
        .msr_mask    = 0x000000000205FF77ULL,
3576
    },
3577
    {
3578
        .name        = "Apollo 7",
3579
        .pvr         = CPU_PPC_7457,
3580
        .pvr_mask    = 0xFFFF0000,
3581
        .insns_flags = PPC_INSNS_74xx,
3582
        .flags       = PPC_FLAGS_74xx,
3583
        .msr_mask    = 0x000000000205FF77ULL,
3584
    },
3585
#endif
3586
#if defined (TODO)
3587
    /* PowerPC 7457A (G4) */
3588
    {
3589
        .name        = "7457A",
3590
        .pvr         = CPU_PPC_7457A,
3591
        .pvr_mask    = 0xFFFF0000,
3592
        .insns_flags = PPC_INSNS_74xx,
3593
        .flags       = PPC_FLAGS_74xx,
3594
        .msr_mask    = 0x000000000205FF77ULL,
3595
    },
3596
    {
3597
        .name        = "Apollo 7 PM",
3598
        .pvr         = CPU_PPC_7457A,
3599
        .pvr_mask    = 0xFFFF0000,
3600
        .insns_flags = PPC_INSNS_74xx,
3601
        .flags       = PPC_FLAGS_74xx,
3602
        .msr_mask    = 0x000000000205FF77ULL,
3603
    },
3604
#endif
3605
    /* 64 bits PowerPC */
3606
#if defined (TARGET_PPC64)
3607
#if defined (TODO)
3608
    /* PowerPC 620 */
3609
    {
3610
        .name        = "620",
3611
        .pvr         = CPU_PPC_620,
3612
        .pvr_mask    = 0xFFFF0000,
3613
        .insns_flags = PPC_INSNS_620,
3614
        .flags       = PPC_FLAGS_620,
3615
        .msr_mask    = 0x800000000005FF73ULL,
3616
    },
3617
#endif
3618
#if defined (TODO)
3619
    /* PowerPC 630 (POWER3) */
3620
    {
3621
        .name        = "630",
3622
        .pvr         = CPU_PPC_630,
3623
        .pvr_mask    = 0xFFFF0000,
3624
        .insns_flags = PPC_INSNS_630,
3625
        .flags       = PPC_FLAGS_630,
3626
        .msr_mask    = xxx,
3627
    }
3628
    {
3629
        .name        = "POWER3",
3630
        .pvr         = CPU_PPC_630,
3631
        .pvr_mask    = 0xFFFF0000,
3632
        .insns_flags = PPC_INSNS_630,
3633
        .flags       = PPC_FLAGS_630,
3634
        .msr_mask    = xxx,
3635
    }
3636
#endif
3637
#if defined (TODO)
3638
    /* PowerPC 631 (Power 3+)*/
3639
    {
3640
        .name        = "631",
3641
        .pvr         = CPU_PPC_631,
3642
        .pvr_mask    = 0xFFFF0000,
3643
        .insns_flags = PPC_INSNS_631,
3644
        .flags       = PPC_FLAGS_631,
3645
        .msr_mask    = xxx,
3646
    },
3647
    {
3648
        .name        = "POWER3+",
3649
        .pvr         = CPU_PPC_631,
3650
        .pvr_mask    = 0xFFFF0000,
3651
        .insns_flags = PPC_INSNS_631,
3652
        .flags       = PPC_FLAGS_631,
3653
        .msr_mask    = xxx,
3654
    },
3655
#endif
3656
#if defined (TODO)
3657
    /* POWER4 */
3658
    {
3659
        .name        = "POWER4",
3660
        .pvr         = CPU_PPC_POWER4,
3661
        .pvr_mask    = 0xFFFF0000,
3662
        .insns_flags = PPC_INSNS_POWER4,
3663
        .flags       = PPC_FLAGS_POWER4,
3664
        .msr_mask    = xxx,
3665
    },
3666
#endif
3667
#if defined (TODO)
3668
    /* POWER4p */
3669
    {
3670
        .name        = "POWER4+",
3671
        .pvr         = CPU_PPC_POWER4P,
3672
        .pvr_mask    = 0xFFFF0000,
3673
        .insns_flags = PPC_INSNS_POWER4,
3674
        .flags       = PPC_FLAGS_POWER4,
3675
        .msr_mask    = xxx,
3676
    },
3677
#endif
3678
#if defined (TODO)
3679
    /* POWER5 */
3680
    {
3681
        .name        = "POWER5",
3682
        .pvr         = CPU_PPC_POWER5,
3683
        .pvr_mask    = 0xFFFF0000,
3684
        .insns_flags = PPC_INSNS_POWER5,
3685
        .flags       = PPC_FLAGS_POWER5,
3686
        .msr_mask    = xxx,
3687
    },
3688
#endif
3689
#if defined (TODO)
3690
    /* POWER5+ */
3691
    {
3692
        .name        = "POWER5+",
3693
        .pvr         = CPU_PPC_POWER5P,
3694
        .pvr_mask    = 0xFFFF0000,
3695
        .insns_flags = PPC_INSNS_POWER5,
3696
        .flags       = PPC_FLAGS_POWER5,
3697
        .msr_mask    = xxx,
3698
    },
3699
#endif
3700
#if defined (TODO)
3701
    /* PowerPC 970 */
3702
    {
3703
        .name        = "970",
3704
        .pvr         = CPU_PPC_970,
3705
        .pvr_mask    = 0xFFFF0000,
3706
        .insns_flags = PPC_INSNS_970,
3707
        .flags       = PPC_FLAGS_970,
3708
        .msr_mask    = 0x900000000204FF36ULL,
3709
    },
3710
#endif
3711
#if defined (TODO)
3712
    /* PowerPC 970FX (G5) */
3713
    {
3714
        .name        = "970fx",
3715
        .pvr         = CPU_PPC_970FX,
3716
        .pvr_mask    = 0xFFFF0000,
3717
        .insns_flags = PPC_INSNS_970FX,
3718
        .flags       = PPC_FLAGS_970FX,
3719
        .msr_mask    = 0x800000000204FF36ULL,
3720
    },
3721
#endif
3722
#if defined (TODO)
3723
    /* RS64 (Apache/A35) */
3724
    /* This one seems to support the whole POWER2 instruction set
3725
     * and the PowerPC 64 one.
3726
     */
3727
    {
3728
        .name        = "RS64",
3729
        .pvr         = CPU_PPC_RS64,
3730
        .pvr_mask    = 0xFFFF0000,
3731
        .insns_flags = PPC_INSNS_RS64,
3732
        .flags       = PPC_FLAGS_RS64,
3733
        .msr_mask    = xxx,
3734
    },
3735
    {
3736
        .name        = "Apache",
3737
        .pvr         = CPU_PPC_RS64,
3738
        .pvr_mask    = 0xFFFF0000,
3739
        .insns_flags = PPC_INSNS_RS64,
3740
        .flags       = PPC_FLAGS_RS64,
3741
        .msr_mask    = xxx,
3742
    },
3743
    {
3744
        .name        = "A35",
3745
        .pvr         = CPU_PPC_RS64,
3746
        .pvr_mask    = 0xFFFF0000,
3747
        .insns_flags = PPC_INSNS_RS64,
3748
        .flags       = PPC_FLAGS_RS64,
3749
        .msr_mask    = xxx,
3750
    },
3751
#endif
3752
#if defined (TODO)
3753
    /* RS64-II (NorthStar/A50) */
3754
    {
3755
        .name        = "RS64-II",
3756
        .pvr         = CPU_PPC_RS64II,
3757
        .pvr_mask    = 0xFFFF0000,
3758
        .insns_flags = PPC_INSNS_RS64,
3759
        .flags       = PPC_FLAGS_RS64,
3760
        .msr_mask    = xxx,
3761
    },
3762
    {
3763
        .name        = "NortStar",
3764
        .pvr         = CPU_PPC_RS64II,
3765
        .pvr_mask    = 0xFFFF0000,
3766
        .insns_flags = PPC_INSNS_RS64,
3767
        .flags       = PPC_FLAGS_RS64,
3768
        .msr_mask    = xxx,
3769
    },
3770
    {
3771
        .name        = "A50",
3772
        .pvr         = CPU_PPC_RS64II,
3773
        .pvr_mask    = 0xFFFF0000,
3774
        .insns_flags = PPC_INSNS_RS64,
3775
        .flags       = PPC_FLAGS_RS64,
3776
        .msr_mask    = xxx,
3777
    },
3778
#endif
3779
#if defined (TODO)
3780
    /* RS64-III (Pulsar) */
3781
    {
3782
        .name        = "RS64-III",
3783
        .pvr         = CPU_PPC_RS64III,
3784
        .pvr_mask    = 0xFFFF0000,
3785
        .insns_flags = PPC_INSNS_RS64,
3786
        .flags       = PPC_FLAGS_RS64,
3787
        .msr_mask    = xxx,
3788
    },
3789
    {
3790
        .name        = "Pulsar",
3791
        .pvr         = CPU_PPC_RS64III,
3792
        .pvr_mask    = 0xFFFF0000,
3793
        .insns_flags = PPC_INSNS_RS64,
3794
        .flags       = PPC_FLAGS_RS64,
3795
        .msr_mask    = xxx,
3796
    },
3797
#endif
3798
#if defined (TODO)
3799
    /* RS64-IV (IceStar/IStar/SStar) */
3800
    {
3801
        .name        = "RS64-IV",
3802
        .pvr         = CPU_PPC_RS64IV,
3803
        .pvr_mask    = 0xFFFF0000,
3804
        .insns_flags = PPC_INSNS_RS64,
3805
        .flags       = PPC_FLAGS_RS64,
3806
        .msr_mask    = xxx,
3807
    },
3808
    {
3809
        .name        = "IceStar",
3810
        .pvr         = CPU_PPC_RS64IV,
3811
        .pvr_mask    = 0xFFFF0000,
3812
        .insns_flags = PPC_INSNS_RS64,
3813
        .flags       = PPC_FLAGS_RS64,
3814
        .msr_mask    = xxx,
3815
    },
3816
    {
3817
        .name        = "IStar",
3818
        .pvr         = CPU_PPC_RS64IV,
3819
        .pvr_mask    = 0xFFFF0000,
3820
        .insns_flags = PPC_INSNS_RS64,
3821
        .flags       = PPC_FLAGS_RS64,
3822
        .msr_mask    = xxx,
3823
    },
3824
    {
3825
        .name        = "SStar",
3826
        .pvr         = CPU_PPC_RS64IV,
3827
        .pvr_mask    = 0xFFFF0000,
3828
        .insns_flags = PPC_INSNS_RS64,
3829
        .flags       = PPC_FLAGS_RS64,
3830
        .msr_mask    = xxx,
3831
    },
3832
#endif
3833
    /* POWER */
3834
#if defined (TODO)
3835
    /* Original POWER */
3836
    {
3837
        .name        = "POWER",
3838
        .pvr         = CPU_POWER,
3839
        .pvr_mask    = 0xFFFF0000,
3840
        .insns_flags = PPC_INSNS_POWER,
3841
        .flags       = PPC_FLAGS_POWER,
3842
        .msr_mask    = xxx,
3843
    },
3844
#endif
3845
#endif /* defined (TARGET_PPC64) */
3846
#if defined (TODO)
3847
    /* POWER2 */
3848
    {
3849
        .name        = "POWER2",
3850
        .pvr         = CPU_POWER2,
3851
        .pvr_mask    = 0xFFFF0000,
3852
        .insns_flags = PPC_INSNS_POWER,
3853
        .flags       = PPC_FLAGS_POWER,
3854
        .msr_mask    = xxx,
3855
    },
3856
#endif
3857
    /* Generic PowerPCs */
3858
#if defined (TODO)
3859
    {
3860
        .name        = "ppc64",
3861
        .pvr         = CPU_PPC_970,
3862
        .pvr_mask    = 0xFFFF0000,
3863
        .insns_flags = PPC_INSNS_PPC64,
3864
        .flags       = PPC_FLAGS_PPC64,
3865
        .msr_mask    = 0xA00000000204FF36ULL,
3866
    },
3867
#endif
3868
    {
3869
        .name        = "ppc32",
3870
        .pvr         = CPU_PPC_604,
3871
        .pvr_mask    = 0xFFFFFFFF,
3872
        .insns_flags = PPC_INSNS_PPC32,
3873
        .flags       = PPC_FLAGS_PPC32,
3874
        .msr_mask    = 0x000000000005FF77ULL,
3875
    },
3876
    /* Fallback */
3877
    {
3878
        .name        = "ppc",
3879
        .pvr         = CPU_PPC_604,
3880
        .pvr_mask    = 0xFFFFFFFF,
3881
        .insns_flags = PPC_INSNS_PPC32,
3882
        .flags       = PPC_FLAGS_PPC32,
3883
        .msr_mask    = 0x000000000005FF77ULL,
3884
    },
3885
};
3886

    
3887
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
3888
{
3889
    int i, ret;
3890

    
3891
    ret = -1;
3892
    *def = NULL;
3893
    for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) {
3894
        if (strcasecmp(name, ppc_defs[i].name) == 0) {
3895
            *def = &ppc_defs[i];
3896
            ret = 0;
3897
            break;
3898
        }
3899
    }
3900

    
3901
    return ret;
3902
}
3903

    
3904
int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
3905
{
3906
    int i, ret;
3907

    
3908
    ret = -1;
3909
    *def = NULL;
3910
    for (i = 0; ppc_defs[i].name != NULL; i++) {
3911
        if ((pvr & ppc_defs[i].pvr_mask) ==
3912
            (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
3913
            *def = &ppc_defs[i];
3914
            ret = 0;
3915
            break;
3916
        }
3917
    }
3918

    
3919
    return ret;
3920
}
3921

    
3922
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3923
{
3924
    int i;
3925

    
3926
    for (i = 0; ; i++) {
3927
        (*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
3928
                       ppc_defs[i].name,
3929
                       ppc_defs[i].pvr, ppc_defs[i].pvr_mask);
3930
        if (strcmp(ppc_defs[i].name, "ppc") == 0)
3931
            break;
3932
    }
3933
}