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/*
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* Sparc MMU helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h" |
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#include "trace.h" |
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#include "exec/address-spaces.h" |
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/* Sparc MMU emulation */
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|
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#if defined(CONFIG_USER_ONLY)
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|
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int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw, |
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int mmu_idx)
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{ |
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if (rw & 2) { |
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env1->exception_index = TT_TFAULT; |
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} else {
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env1->exception_index = TT_DFAULT; |
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} |
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return 1; |
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} |
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#else
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#ifndef TARGET_SPARC64
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/*
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* Sparc V8 Reference MMU (SRMMU)
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*/
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static const int access_table[8][8] = { |
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{ 0, 0, 0, 0, 8, 0, 12, 12 }, |
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{ 0, 0, 0, 0, 8, 0, 0, 0 }, |
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{ 8, 8, 0, 0, 0, 8, 12, 12 }, |
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{ 8, 8, 0, 0, 0, 8, 0, 0 }, |
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{ 8, 0, 8, 0, 8, 8, 12, 12 }, |
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{ 8, 0, 8, 0, 8, 0, 8, 0 }, |
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{ 8, 8, 8, 0, 8, 8, 12, 12 }, |
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{ 8, 8, 8, 0, 8, 8, 8, 0 } |
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}; |
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|
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static const int perm_table[2][8] = { |
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{ |
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC |
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}, |
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{ |
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PAGE_READ, |
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PAGE_READ | PAGE_WRITE, |
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PAGE_READ | PAGE_EXEC, |
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PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
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PAGE_EXEC, |
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PAGE_READ, |
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0,
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0,
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} |
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}; |
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|
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static int get_physical_address(CPUSPARCState *env, hwaddr *physical, |
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int *prot, int *access_index, |
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target_ulong address, int rw, int mmu_idx, |
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target_ulong *page_size) |
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{ |
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int access_perms = 0; |
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hwaddr pde_ptr; |
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uint32_t pde; |
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int error_code = 0, is_dirty, is_user; |
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unsigned long page_offset; |
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|
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is_user = mmu_idx == MMU_USER_IDX; |
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|
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
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*page_size = TARGET_PAGE_SIZE; |
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/* Boot mode: instruction fetches are taken from PROM */
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if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) { |
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*physical = env->prom_addr | (address & 0x7ffffULL);
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*prot = PAGE_READ | PAGE_EXEC; |
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return 0; |
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} |
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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return 0; |
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} |
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|
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1); |
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*physical = 0xffffffffffff0000ULL;
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|
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
|
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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|
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/* Ctx pde */
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return 1 << 2; |
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case 2: /* L0 PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 4 << 2; |
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case 1: /* L0 PDE */ |
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (1 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (1 << 8) | (4 << 2); |
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case 1: /* L1 PDE */ |
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (2 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (2 << 8) | (4 << 2); |
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case 1: /* L2 PDE */ |
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (3 << 8) | (1 << 2); |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return (3 << 8) | (4 << 2); |
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case 2: /* L3 PTE */ |
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page_offset = 0;
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} |
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*page_size = TARGET_PAGE_SIZE; |
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break;
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case 2: /* L2 PTE */ |
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page_offset = address & 0x3f000;
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*page_size = 0x40000;
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} |
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break;
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case 2: /* L1 PTE */ |
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page_offset = address & 0xfff000;
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*page_size = 0x1000000;
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} |
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} |
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|
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
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error_code = access_table[*access_index][access_perms]; |
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) { |
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return error_code;
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} |
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK; |
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if (is_dirty) {
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pde |= PG_MODIFIED_MASK; |
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} |
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stl_phys_notdirty(pde_ptr, pde); |
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} |
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/* the page can be put in the TLB */
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*prot = perm_table[is_user][access_perms]; |
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if (!(pde & PG_MODIFIED_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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*prot &= ~PAGE_WRITE; |
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} |
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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} |
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw, |
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int mmu_idx)
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{ |
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hwaddr paddr; |
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target_ulong vaddr; |
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target_ulong page_size; |
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int error_code = 0, prot, access_index; |
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address &= TARGET_PAGE_MASK; |
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error_code = get_physical_address(env, &paddr, &prot, &access_index, |
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address, rw, mmu_idx, &page_size); |
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vaddr = address; |
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if (error_code == 0) { |
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#ifdef DEBUG_MMU
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printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
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TARGET_FMT_lx "\n", address, paddr, vaddr);
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#endif
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tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); |
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return 0; |
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} |
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|
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if (env->mmuregs[3]) { /* Fault status register */ |
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
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} |
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env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
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env->mmuregs[4] = address; /* Fault address register */ |
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
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/* No fault mode: if a mapping is available, just override
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permissions. If no mapping is available, redirect accesses to
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neverland. Fake/overridden mappings will be flushed when
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switching to normal mode. */
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
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tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE); |
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return 0; |
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} else {
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if (rw & 2) { |
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env->exception_index = TT_TFAULT; |
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} else {
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env->exception_index = TT_DFAULT; |
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} |
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return 1; |
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} |
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} |
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|
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target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
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{ |
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hwaddr pde_ptr; |
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uint32_t pde; |
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/* Context base + context number */
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pde_ptr = (hwaddr)(env->mmuregs[1] << 4) + |
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(env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
258 |
case 2: /* PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 0; |
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case 1: /* L1 PDE */ |
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if (mmulev == 3) { |
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return pde;
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} |
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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case 3: /* Reserved */ |
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return 0; |
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case 2: /* L1 PTE */ |
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return pde;
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case 1: /* L2 PDE */ |
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if (mmulev == 2) { |
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return pde;
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} |
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
285 |
case 3: /* Reserved */ |
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return 0; |
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case 2: /* L2 PTE */ |
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return pde;
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case 1: /* L3 PDE */ |
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if (mmulev == 1) { |
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return pde;
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} |
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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case 1: /* PDE, should not happen */ |
300 |
case 3: /* Reserved */ |
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return 0; |
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case 2: /* L3 PTE */ |
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return pde;
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} |
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} |
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} |
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} |
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return 0; |
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} |
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|
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
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{ |
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target_ulong va, va1, va2; |
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unsigned int n, m, o; |
315 |
hwaddr pde_ptr, pa; |
316 |
uint32_t pde; |
317 |
|
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
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(hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); |
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for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
323 |
pde = mmu_probe(env, va, 2);
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if (pde) {
|
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pa = cpu_get_phys_page_debug(env, va); |
326 |
(*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
327 |
" PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
328 |
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
329 |
pde = mmu_probe(env, va1, 1);
|
330 |
if (pde) {
|
331 |
pa = cpu_get_phys_page_debug(env, va1); |
332 |
(*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: " |
333 |
TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n", |
334 |
va1, pa, pde); |
335 |
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
336 |
pde = mmu_probe(env, va2, 0);
|
337 |
if (pde) {
|
338 |
pa = cpu_get_phys_page_debug(env, va2); |
339 |
(*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: " |
340 |
TARGET_FMT_plx " PTE: "
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341 |
TARGET_FMT_lx "\n",
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342 |
va2, pa, pde); |
343 |
} |
344 |
} |
345 |
} |
346 |
} |
347 |
} |
348 |
} |
349 |
} |
350 |
|
351 |
/* Gdb expects all registers windows to be flushed in ram. This function handles
|
352 |
* reads (and only reads) in stack frames as if windows were flushed. We assume
|
353 |
* that the sparc ABI is followed.
|
354 |
*/
|
355 |
int target_memory_rw_debug(CPUSPARCState *env, target_ulong addr,
|
356 |
uint8_t *buf, int len, int is_write) |
357 |
{ |
358 |
int i;
|
359 |
int len1;
|
360 |
int cwp = env->cwp;
|
361 |
|
362 |
if (!is_write) {
|
363 |
for (i = 0; i < env->nwindows; i++) { |
364 |
int off;
|
365 |
target_ulong fp = env->regbase[cwp * 16 + 22]; |
366 |
|
367 |
/* Assume fp == 0 means end of frame. */
|
368 |
if (fp == 0) { |
369 |
break;
|
370 |
} |
371 |
|
372 |
cwp = cpu_cwp_inc(env, cwp + 1);
|
373 |
|
374 |
/* Invalid window ? */
|
375 |
if (env->wim & (1 << cwp)) { |
376 |
break;
|
377 |
} |
378 |
|
379 |
/* According to the ABI, the stack is growing downward. */
|
380 |
if (addr + len < fp) {
|
381 |
break;
|
382 |
} |
383 |
|
384 |
/* Not in this frame. */
|
385 |
if (addr > fp + 64) { |
386 |
continue;
|
387 |
} |
388 |
|
389 |
/* Handle access before this window. */
|
390 |
if (addr < fp) {
|
391 |
len1 = fp - addr; |
392 |
if (cpu_memory_rw_debug(env, addr, buf, len1, is_write) != 0) { |
393 |
return -1; |
394 |
} |
395 |
addr += len1; |
396 |
len -= len1; |
397 |
buf += len1; |
398 |
} |
399 |
|
400 |
/* Access byte per byte to registers. Not very efficient but speed
|
401 |
* is not critical.
|
402 |
*/
|
403 |
off = addr - fp; |
404 |
len1 = 64 - off;
|
405 |
|
406 |
if (len1 > len) {
|
407 |
len1 = len; |
408 |
} |
409 |
|
410 |
for (; len1; len1--) {
|
411 |
int reg = cwp * 16 + 8 + (off >> 2); |
412 |
union {
|
413 |
uint32_t v; |
414 |
uint8_t c[4];
|
415 |
} u; |
416 |
u.v = cpu_to_be32(env->regbase[reg]); |
417 |
*buf++ = u.c[off & 3];
|
418 |
addr++; |
419 |
len--; |
420 |
off++; |
421 |
} |
422 |
|
423 |
if (len == 0) { |
424 |
return 0; |
425 |
} |
426 |
} |
427 |
} |
428 |
return cpu_memory_rw_debug(env, addr, buf, len, is_write);
|
429 |
} |
430 |
|
431 |
#else /* !TARGET_SPARC64 */ |
432 |
|
433 |
/* 41 bit physical address space */
|
434 |
static inline hwaddr ultrasparc_truncate_physical(uint64_t x) |
435 |
{ |
436 |
return x & 0x1ffffffffffULL; |
437 |
} |
438 |
|
439 |
/*
|
440 |
* UltraSparc IIi I/DMMUs
|
441 |
*/
|
442 |
|
443 |
/* Returns true if TTE tag is valid and matches virtual address value
|
444 |
in context requires virtual address mask value calculated from TTE
|
445 |
entry size */
|
446 |
static inline int ultrasparc_tag_match(SparcTLBEntry *tlb, |
447 |
uint64_t address, uint64_t context, |
448 |
hwaddr *physical) |
449 |
{ |
450 |
uint64_t mask; |
451 |
|
452 |
switch (TTE_PGSIZE(tlb->tte)) {
|
453 |
default:
|
454 |
case 0x0: /* 8k */ |
455 |
mask = 0xffffffffffffe000ULL;
|
456 |
break;
|
457 |
case 0x1: /* 64k */ |
458 |
mask = 0xffffffffffff0000ULL;
|
459 |
break;
|
460 |
case 0x2: /* 512k */ |
461 |
mask = 0xfffffffffff80000ULL;
|
462 |
break;
|
463 |
case 0x3: /* 4M */ |
464 |
mask = 0xffffffffffc00000ULL;
|
465 |
break;
|
466 |
} |
467 |
|
468 |
/* valid, context match, virtual address match? */
|
469 |
if (TTE_IS_VALID(tlb->tte) &&
|
470 |
(TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context)) |
471 |
&& compare_masked(address, tlb->tag, mask)) { |
472 |
/* decode physical address */
|
473 |
*physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL;
|
474 |
return 1; |
475 |
} |
476 |
|
477 |
return 0; |
478 |
} |
479 |
|
480 |
static int get_physical_address_data(CPUSPARCState *env, |
481 |
hwaddr *physical, int *prot,
|
482 |
target_ulong address, int rw, int mmu_idx) |
483 |
{ |
484 |
unsigned int i; |
485 |
uint64_t context; |
486 |
uint64_t sfsr = 0;
|
487 |
|
488 |
int is_user = (mmu_idx == MMU_USER_IDX ||
|
489 |
mmu_idx == MMU_USER_SECONDARY_IDX); |
490 |
|
491 |
if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
492 |
*physical = ultrasparc_truncate_physical(address); |
493 |
*prot = PAGE_READ | PAGE_WRITE; |
494 |
return 0; |
495 |
} |
496 |
|
497 |
switch (mmu_idx) {
|
498 |
case MMU_USER_IDX:
|
499 |
case MMU_KERNEL_IDX:
|
500 |
context = env->dmmu.mmu_primary_context & 0x1fff;
|
501 |
sfsr |= SFSR_CT_PRIMARY; |
502 |
break;
|
503 |
case MMU_USER_SECONDARY_IDX:
|
504 |
case MMU_KERNEL_SECONDARY_IDX:
|
505 |
context = env->dmmu.mmu_secondary_context & 0x1fff;
|
506 |
sfsr |= SFSR_CT_SECONDARY; |
507 |
break;
|
508 |
case MMU_NUCLEUS_IDX:
|
509 |
sfsr |= SFSR_CT_NUCLEUS; |
510 |
/* FALLTHRU */
|
511 |
default:
|
512 |
context = 0;
|
513 |
break;
|
514 |
} |
515 |
|
516 |
if (rw == 1) { |
517 |
sfsr |= SFSR_WRITE_BIT; |
518 |
} else if (rw == 4) { |
519 |
sfsr |= SFSR_NF_BIT; |
520 |
} |
521 |
|
522 |
for (i = 0; i < 64; i++) { |
523 |
/* ctx match, vaddr match, valid? */
|
524 |
if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
|
525 |
int do_fault = 0; |
526 |
|
527 |
/* access ok? */
|
528 |
/* multiple bits in SFSR.FT may be set on TT_DFAULT */
|
529 |
if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
|
530 |
do_fault = 1;
|
531 |
sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
|
532 |
trace_mmu_helper_dfault(address, context, mmu_idx, env->tl); |
533 |
} |
534 |
if (rw == 4) { |
535 |
if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) {
|
536 |
do_fault = 1;
|
537 |
sfsr |= SFSR_FT_NF_E_BIT; |
538 |
} |
539 |
} else {
|
540 |
if (TTE_IS_NFO(env->dtlb[i].tte)) {
|
541 |
do_fault = 1;
|
542 |
sfsr |= SFSR_FT_NFO_BIT; |
543 |
} |
544 |
} |
545 |
|
546 |
if (do_fault) {
|
547 |
/* faults above are reported with TT_DFAULT. */
|
548 |
env->exception_index = TT_DFAULT; |
549 |
} else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) { |
550 |
do_fault = 1;
|
551 |
env->exception_index = TT_DPROT; |
552 |
|
553 |
trace_mmu_helper_dprot(address, context, mmu_idx, env->tl); |
554 |
} |
555 |
|
556 |
if (!do_fault) {
|
557 |
*prot = PAGE_READ; |
558 |
if (TTE_IS_W_OK(env->dtlb[i].tte)) {
|
559 |
*prot |= PAGE_WRITE; |
560 |
} |
561 |
|
562 |
TTE_SET_USED(env->dtlb[i].tte); |
563 |
|
564 |
return 0; |
565 |
} |
566 |
|
567 |
if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */ |
568 |
sfsr |= SFSR_OW_BIT; /* overflow (not read before
|
569 |
another fault) */
|
570 |
} |
571 |
|
572 |
if (env->pstate & PS_PRIV) {
|
573 |
sfsr |= SFSR_PR_BIT; |
574 |
} |
575 |
|
576 |
/* FIXME: ASI field in SFSR must be set */
|
577 |
env->dmmu.sfsr = sfsr | SFSR_VALID_BIT; |
578 |
|
579 |
env->dmmu.sfar = address; /* Fault address register */
|
580 |
|
581 |
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
|
582 |
|
583 |
return 1; |
584 |
} |
585 |
} |
586 |
|
587 |
trace_mmu_helper_dmiss(address, context); |
588 |
|
589 |
/*
|
590 |
* On MMU misses:
|
591 |
* - UltraSPARC IIi: SFSR and SFAR unmodified
|
592 |
* - JPS1: SFAR updated and some fields of SFSR updated
|
593 |
*/
|
594 |
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
|
595 |
env->exception_index = TT_DMISS; |
596 |
return 1; |
597 |
} |
598 |
|
599 |
static int get_physical_address_code(CPUSPARCState *env, |
600 |
hwaddr *physical, int *prot,
|
601 |
target_ulong address, int mmu_idx)
|
602 |
{ |
603 |
unsigned int i; |
604 |
uint64_t context; |
605 |
|
606 |
int is_user = (mmu_idx == MMU_USER_IDX ||
|
607 |
mmu_idx == MMU_USER_SECONDARY_IDX); |
608 |
|
609 |
if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) { |
610 |
/* IMMU disabled */
|
611 |
*physical = ultrasparc_truncate_physical(address); |
612 |
*prot = PAGE_EXEC; |
613 |
return 0; |
614 |
} |
615 |
|
616 |
if (env->tl == 0) { |
617 |
/* PRIMARY context */
|
618 |
context = env->dmmu.mmu_primary_context & 0x1fff;
|
619 |
} else {
|
620 |
/* NUCLEUS context */
|
621 |
context = 0;
|
622 |
} |
623 |
|
624 |
for (i = 0; i < 64; i++) { |
625 |
/* ctx match, vaddr match, valid? */
|
626 |
if (ultrasparc_tag_match(&env->itlb[i],
|
627 |
address, context, physical)) { |
628 |
/* access ok? */
|
629 |
if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
|
630 |
/* Fault status register */
|
631 |
if (env->immu.sfsr & SFSR_VALID_BIT) {
|
632 |
env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before
|
633 |
another fault) */
|
634 |
} else {
|
635 |
env->immu.sfsr = 0;
|
636 |
} |
637 |
if (env->pstate & PS_PRIV) {
|
638 |
env->immu.sfsr |= SFSR_PR_BIT; |
639 |
} |
640 |
if (env->tl > 0) { |
641 |
env->immu.sfsr |= SFSR_CT_NUCLEUS; |
642 |
} |
643 |
|
644 |
/* FIXME: ASI field in SFSR must be set */
|
645 |
env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT; |
646 |
env->exception_index = TT_TFAULT; |
647 |
|
648 |
env->immu.tag_access = (address & ~0x1fffULL) | context;
|
649 |
|
650 |
trace_mmu_helper_tfault(address, context); |
651 |
|
652 |
return 1; |
653 |
} |
654 |
*prot = PAGE_EXEC; |
655 |
TTE_SET_USED(env->itlb[i].tte); |
656 |
return 0; |
657 |
} |
658 |
} |
659 |
|
660 |
trace_mmu_helper_tmiss(address, context); |
661 |
|
662 |
/* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
|
663 |
env->immu.tag_access = (address & ~0x1fffULL) | context;
|
664 |
env->exception_index = TT_TMISS; |
665 |
return 1; |
666 |
} |
667 |
|
668 |
static int get_physical_address(CPUSPARCState *env, hwaddr *physical, |
669 |
int *prot, int *access_index, |
670 |
target_ulong address, int rw, int mmu_idx, |
671 |
target_ulong *page_size) |
672 |
{ |
673 |
/* ??? We treat everything as a small page, then explicitly flush
|
674 |
everything when an entry is evicted. */
|
675 |
*page_size = TARGET_PAGE_SIZE; |
676 |
|
677 |
/* safety net to catch wrong softmmu index use from dynamic code */
|
678 |
if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) { |
679 |
if (rw == 2) { |
680 |
trace_mmu_helper_get_phys_addr_code(env->tl, mmu_idx, |
681 |
env->dmmu.mmu_primary_context, |
682 |
env->dmmu.mmu_secondary_context, |
683 |
address); |
684 |
} else {
|
685 |
trace_mmu_helper_get_phys_addr_data(env->tl, mmu_idx, |
686 |
env->dmmu.mmu_primary_context, |
687 |
env->dmmu.mmu_secondary_context, |
688 |
address); |
689 |
} |
690 |
} |
691 |
|
692 |
if (rw == 2) { |
693 |
return get_physical_address_code(env, physical, prot, address,
|
694 |
mmu_idx); |
695 |
} else {
|
696 |
return get_physical_address_data(env, physical, prot, address, rw,
|
697 |
mmu_idx); |
698 |
} |
699 |
} |
700 |
|
701 |
/* Perform address translation */
|
702 |
int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw, |
703 |
int mmu_idx)
|
704 |
{ |
705 |
target_ulong vaddr; |
706 |
hwaddr paddr; |
707 |
target_ulong page_size; |
708 |
int error_code = 0, prot, access_index; |
709 |
|
710 |
address &= TARGET_PAGE_MASK; |
711 |
error_code = get_physical_address(env, &paddr, &prot, &access_index, |
712 |
address, rw, mmu_idx, &page_size); |
713 |
if (error_code == 0) { |
714 |
vaddr = address; |
715 |
|
716 |
trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, |
717 |
env->dmmu.mmu_primary_context, |
718 |
env->dmmu.mmu_secondary_context); |
719 |
|
720 |
tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); |
721 |
return 0; |
722 |
} |
723 |
/* XXX */
|
724 |
return 1; |
725 |
} |
726 |
|
727 |
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
|
728 |
{ |
729 |
unsigned int i; |
730 |
const char *mask; |
731 |
|
732 |
(*cpu_fprintf)(f, "MMU contexts: Primary: %" PRId64 ", Secondary: %" |
733 |
PRId64 "\n",
|
734 |
env->dmmu.mmu_primary_context, |
735 |
env->dmmu.mmu_secondary_context); |
736 |
if ((env->lsu & DMMU_E) == 0) { |
737 |
(*cpu_fprintf)(f, "DMMU disabled\n");
|
738 |
} else {
|
739 |
(*cpu_fprintf)(f, "DMMU dump\n");
|
740 |
for (i = 0; i < 64; i++) { |
741 |
switch (TTE_PGSIZE(env->dtlb[i].tte)) {
|
742 |
default:
|
743 |
case 0x0: |
744 |
mask = " 8k";
|
745 |
break;
|
746 |
case 0x1: |
747 |
mask = " 64k";
|
748 |
break;
|
749 |
case 0x2: |
750 |
mask = "512k";
|
751 |
break;
|
752 |
case 0x3: |
753 |
mask = " 4M";
|
754 |
break;
|
755 |
} |
756 |
if (TTE_IS_VALID(env->dtlb[i].tte)) {
|
757 |
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx" |
758 |
", %s, %s, %s, %s, ctx %" PRId64 " %s\n", |
759 |
i, |
760 |
env->dtlb[i].tag & (uint64_t)~0x1fffULL,
|
761 |
TTE_PA(env->dtlb[i].tte), |
762 |
mask, |
763 |
TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user", |
764 |
TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", |
765 |
TTE_IS_LOCKED(env->dtlb[i].tte) ? |
766 |
"locked" : "unlocked", |
767 |
env->dtlb[i].tag & (uint64_t)0x1fffULL,
|
768 |
TTE_IS_GLOBAL(env->dtlb[i].tte) ? |
769 |
"global" : "local"); |
770 |
} |
771 |
} |
772 |
} |
773 |
if ((env->lsu & IMMU_E) == 0) { |
774 |
(*cpu_fprintf)(f, "IMMU disabled\n");
|
775 |
} else {
|
776 |
(*cpu_fprintf)(f, "IMMU dump\n");
|
777 |
for (i = 0; i < 64; i++) { |
778 |
switch (TTE_PGSIZE(env->itlb[i].tte)) {
|
779 |
default:
|
780 |
case 0x0: |
781 |
mask = " 8k";
|
782 |
break;
|
783 |
case 0x1: |
784 |
mask = " 64k";
|
785 |
break;
|
786 |
case 0x2: |
787 |
mask = "512k";
|
788 |
break;
|
789 |
case 0x3: |
790 |
mask = " 4M";
|
791 |
break;
|
792 |
} |
793 |
if (TTE_IS_VALID(env->itlb[i].tte)) {
|
794 |
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx" |
795 |
", %s, %s, %s, ctx %" PRId64 " %s\n", |
796 |
i, |
797 |
env->itlb[i].tag & (uint64_t)~0x1fffULL,
|
798 |
TTE_PA(env->itlb[i].tte), |
799 |
mask, |
800 |
TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user", |
801 |
TTE_IS_LOCKED(env->itlb[i].tte) ? |
802 |
"locked" : "unlocked", |
803 |
env->itlb[i].tag & (uint64_t)0x1fffULL,
|
804 |
TTE_IS_GLOBAL(env->itlb[i].tte) ? |
805 |
"global" : "local"); |
806 |
} |
807 |
} |
808 |
} |
809 |
} |
810 |
|
811 |
#endif /* TARGET_SPARC64 */ |
812 |
|
813 |
static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys, |
814 |
target_ulong addr, int rw, int mmu_idx) |
815 |
{ |
816 |
target_ulong page_size; |
817 |
int prot, access_index;
|
818 |
|
819 |
return get_physical_address(env, phys, &prot, &access_index, addr, rw,
|
820 |
mmu_idx, &page_size); |
821 |
} |
822 |
|
823 |
#if defined(TARGET_SPARC64)
|
824 |
hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, |
825 |
int mmu_idx)
|
826 |
{ |
827 |
hwaddr phys_addr; |
828 |
|
829 |
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) { |
830 |
return -1; |
831 |
} |
832 |
return phys_addr;
|
833 |
} |
834 |
#endif
|
835 |
|
836 |
hwaddr cpu_get_phys_page_debug(CPUSPARCState *env, target_ulong addr) |
837 |
{ |
838 |
hwaddr phys_addr; |
839 |
int mmu_idx = cpu_mmu_index(env);
|
840 |
MemoryRegionSection section; |
841 |
|
842 |
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) { |
843 |
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) { |
844 |
return -1; |
845 |
} |
846 |
} |
847 |
section = memory_region_find(get_system_memory(), phys_addr, 1);
|
848 |
if (!int128_nz(section.size)) {
|
849 |
return -1; |
850 |
} |
851 |
return phys_addr;
|
852 |
} |
853 |
#endif
|