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/*
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 * i386 virtual CPU header
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#ifndef CPU_I386_H
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#define CPU_I386_H
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#include "config.h"
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#ifdef TARGET_X86_64
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#define TARGET_LONG_BITS 64
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#else
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#define TARGET_LONG_BITS 32
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#endif
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/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
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/* support for self modifying code even if the modified instruction is
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   close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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#define TARGET_HAS_ICE 1
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#ifdef TARGET_X86_64
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#define ELF_MACHINE        EM_X86_64
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#else
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#define ELF_MACHINE        EM_386
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#endif
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#include "cpu-defs.h"
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#include "softfloat.h"
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#if defined(__i386__) && !defined(CONFIG_SOFTMMU) && !defined(__APPLE__)
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#define USE_CODE_COPY
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#endif
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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#define R_AL 0
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#define R_CL 1
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#define R_DL 2
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#define R_BL 3
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#define R_AH 4
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#define R_CH 5
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#define R_DH 6
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#define R_BH 7
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#define R_ES 0
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#define R_CS 1
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#define R_SS 2
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#define R_DS 3
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#define R_FS 4
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#define R_GS 5
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/* segment descriptor fields */
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#define DESC_G_MASK     (1 << 23)
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#define DESC_B_SHIFT    22
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#define DESC_B_MASK     (1 << DESC_B_SHIFT)
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#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
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#define DESC_L_MASK     (1 << DESC_L_SHIFT)
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#define DESC_AVL_MASK   (1 << 20)
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#define DESC_P_MASK     (1 << 15)
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#define DESC_DPL_SHIFT  13
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#define DESC_DPL_MASK   (1 << DESC_DPL_SHIFT)
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#define DESC_S_MASK     (1 << 12)
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#define DESC_TYPE_SHIFT 8
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#define DESC_A_MASK     (1 << 8)
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#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
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#define DESC_C_MASK     (1 << 10) /* code: conforming */
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#define DESC_R_MASK     (1 << 9)  /* code: readable */
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#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
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#define DESC_W_MASK     (1 << 9)  /* data: writable */
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#define DESC_TSS_BUSY_MASK (1 << 9)
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/* eflags masks */
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#define CC_C           0x0001
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#define CC_P         0x0004
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#define CC_A        0x0010
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#define CC_Z        0x0040
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#define CC_S    0x0080
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#define CC_O    0x0800
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#define TF_SHIFT   8
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#define IOPL_SHIFT 12
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#define VM_SHIFT   17
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#define TF_MASK                 0x00000100
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#define IF_MASK                 0x00000200
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#define DF_MASK                 0x00000400
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#define IOPL_MASK                0x00003000
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#define NT_MASK                         0x00004000
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#define RF_MASK                        0x00010000
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#define VM_MASK                        0x00020000
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#define AC_MASK                        0x00040000
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#define VIF_MASK                0x00080000
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#define VIP_MASK                0x00100000
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#define ID_MASK                 0x00200000
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/* hidden flags - used internally by qemu to represent additional cpu
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   states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
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   using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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   with eflags. */
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/* current cpl */
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#define HF_CPL_SHIFT         0
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/* true if soft mmu is being used */
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#define HF_SOFTMMU_SHIFT     2
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/* true if hardware interrupts must be disabled for next instruction */
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#define HF_INHIBIT_IRQ_SHIFT 3
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/* 16 or 32 segments */
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#define HF_CS32_SHIFT        4
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#define HF_SS32_SHIFT        5
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/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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#define HF_ADDSEG_SHIFT      6
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/* copy of CR0.PE (protected mode) */
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#define HF_PE_SHIFT          7
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#define HF_TF_SHIFT          8 /* must be same as eflags */
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#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
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#define HF_EM_SHIFT         10
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#define HF_TS_SHIFT         11
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#define HF_IOPL_SHIFT       12 /* must be same as eflags */
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#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
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#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
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#define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
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#define HF_HALTED_SHIFT     18 /* CPU halted */
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#define HF_SMM_SHIFT        19 /* CPU in SMM mode */
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#define HF_GIF_SHIFT        20 /* if set CPU takes interrupts */
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#define HF_HIF_SHIFT        21 /* shadow copy of IF_MASK when in SVM */
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#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
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#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
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#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
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#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
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#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
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#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
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#define HF_PE_MASK           (1 << HF_PE_SHIFT)
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#define HF_TF_MASK           (1 << HF_TF_SHIFT)
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#define HF_MP_MASK           (1 << HF_MP_SHIFT)
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#define HF_EM_MASK           (1 << HF_EM_SHIFT)
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#define HF_TS_MASK           (1 << HF_TS_SHIFT)
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#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
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#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
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#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
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#define HF_HALTED_MASK       (1 << HF_HALTED_SHIFT)
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#define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
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#define HF_GIF_MASK          (1 << HF_GIF_SHIFT)
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#define HF_HIF_MASK          (1 << HF_HIF_SHIFT)
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#define CR0_PE_MASK  (1 << 0)
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#define CR0_MP_MASK  (1 << 1)
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#define CR0_EM_MASK  (1 << 2)
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#define CR0_TS_MASK  (1 << 3)
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#define CR0_ET_MASK  (1 << 4)
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#define CR0_NE_MASK  (1 << 5)
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#define CR0_WP_MASK  (1 << 16)
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#define CR0_AM_MASK  (1 << 18)
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#define CR0_PG_MASK  (1 << 31)
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#define CR4_VME_MASK  (1 << 0)
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#define CR4_PVI_MASK  (1 << 1)
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#define CR4_TSD_MASK  (1 << 2)
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#define CR4_DE_MASK   (1 << 3)
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#define CR4_PSE_MASK  (1 << 4)
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#define CR4_PAE_MASK  (1 << 5)
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#define CR4_PGE_MASK  (1 << 7)
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#define CR4_PCE_MASK  (1 << 8)
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#define CR4_OSFXSR_MASK (1 << 9)
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#define CR4_OSXMMEXCPT_MASK  (1 << 10)
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#define PG_PRESENT_BIT        0
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#define PG_RW_BIT        1
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#define PG_USER_BIT        2
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#define PG_PWT_BIT        3
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#define PG_PCD_BIT        4
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#define PG_ACCESSED_BIT        5
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#define PG_DIRTY_BIT        6
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#define PG_PSE_BIT        7
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#define PG_GLOBAL_BIT        8
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#define PG_NX_BIT        63
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#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
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#define PG_RW_MASK         (1 << PG_RW_BIT)
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#define PG_USER_MASK         (1 << PG_USER_BIT)
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#define PG_PWT_MASK         (1 << PG_PWT_BIT)
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#define PG_PCD_MASK         (1 << PG_PCD_BIT)
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_DIRTY_MASK         (1 << PG_DIRTY_BIT)
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#define PG_PSE_MASK         (1 << PG_PSE_BIT)
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#define PG_GLOBAL_MASK         (1 << PG_GLOBAL_BIT)
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#define PG_NX_MASK         (1LL << PG_NX_BIT)
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#define PG_ERROR_W_BIT     1
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#define PG_ERROR_P_MASK    0x01
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#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
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#define PG_ERROR_U_MASK    0x04
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#define PG_ERROR_RSVD_MASK 0x08
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#define PG_ERROR_I_D_MASK  0x10
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#define MSR_IA32_APICBASE               0x1b
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#define MSR_IA32_APICBASE_BSP           (1<<8)
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#define MSR_IA32_APICBASE_ENABLE        (1<<11)
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#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
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#define MSR_IA32_SYSENTER_CS            0x174
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#define MSR_IA32_SYSENTER_ESP           0x175
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#define MSR_IA32_SYSENTER_EIP           0x176
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#define MSR_MCG_CAP                     0x179
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#define MSR_MCG_STATUS                  0x17a
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#define MSR_MCG_CTL                     0x17b
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#define MSR_PAT                         0x277
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#define MSR_EFER                        0xc0000080
242

    
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#define MSR_EFER_SCE   (1 << 0)
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#define MSR_EFER_LME   (1 << 8)
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#define MSR_EFER_LMA   (1 << 10)
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#define MSR_EFER_NXE   (1 << 11)
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#define MSR_EFER_FFXSR (1 << 14)
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#define MSR_STAR                        0xc0000081
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#define MSR_LSTAR                       0xc0000082
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#define MSR_CSTAR                       0xc0000083
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#define MSR_FMASK                       0xc0000084
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#define MSR_FSBASE                      0xc0000100
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#define MSR_GSBASE                      0xc0000101
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#define MSR_KERNELGSBASE                0xc0000102
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#define MSR_VM_HSAVE_PA                 0xc0010117
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/* cpuid_features bits */
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#define CPUID_FP87 (1 << 0)
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#define CPUID_VME  (1 << 1)
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#define CPUID_DE   (1 << 2)
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#define CPUID_PSE  (1 << 3)
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#define CPUID_TSC  (1 << 4)
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#define CPUID_MSR  (1 << 5)
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#define CPUID_PAE  (1 << 6)
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#define CPUID_MCE  (1 << 7)
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#define CPUID_CX8  (1 << 8)
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#define CPUID_APIC (1 << 9)
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#define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
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#define CPUID_MTRR (1 << 12)
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#define CPUID_PGE  (1 << 13)
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#define CPUID_MCA  (1 << 14)
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#define CPUID_CMOV (1 << 15)
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#define CPUID_PAT  (1 << 16)
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#define CPUID_PSE36   (1 << 17)
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#define CPUID_CLFLUSH (1 << 19)
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/* ... */
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#define CPUID_MMX  (1 << 23)
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#define CPUID_FXSR (1 << 24)
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#define CPUID_SSE  (1 << 25)
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#define CPUID_SSE2 (1 << 26)
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#define CPUID_EXT_SSE3     (1 << 0)
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#define CPUID_EXT_MONITOR  (1 << 3)
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#define CPUID_EXT_CX16     (1 << 13)
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#define CPUID_EXT2_SYSCALL (1 << 11)
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#define CPUID_EXT2_NX      (1 << 20)
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#define CPUID_EXT2_FFXSR   (1 << 25)
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#define CPUID_EXT2_LM      (1 << 29)
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#define CPUID_EXT3_SVM     (1 << 2)
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#define EXCP00_DIVZ        0
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#define EXCP01_SSTP        1
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#define EXCP02_NMI        2
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#define EXCP03_INT3        3
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#define EXCP04_INTO        4
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#define EXCP05_BOUND        5
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#define EXCP06_ILLOP        6
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#define EXCP07_PREX        7
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#define EXCP08_DBLE        8
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#define EXCP09_XERR        9
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#define EXCP0A_TSS        10
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#define EXCP0B_NOSEG        11
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#define EXCP0C_STACK        12
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#define EXCP0D_GPF        13
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#define EXCP0E_PAGE        14
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#define EXCP10_COPR        16
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#define EXCP11_ALGN        17
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#define EXCP12_MCHK        18
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enum {
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    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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    CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
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    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
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    CC_OP_MULW,
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    CC_OP_MULL,
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    CC_OP_MULQ,
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    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADDW,
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    CC_OP_ADDL,
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    CC_OP_ADDQ,
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    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_ADCW,
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    CC_OP_ADCL,
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    CC_OP_ADCQ,
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    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SUBW,
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    CC_OP_SUBL,
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    CC_OP_SUBQ,
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    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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    CC_OP_SBBW,
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    CC_OP_SBBL,
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    CC_OP_SBBQ,
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    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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    CC_OP_LOGICW,
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    CC_OP_LOGICL,
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    CC_OP_LOGICQ,
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    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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    CC_OP_INCW,
350
    CC_OP_INCL,
351
    CC_OP_INCQ,
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    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
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    CC_OP_DECW,
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    CC_OP_DECL,
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    CC_OP_DECQ,
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    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
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    CC_OP_SHLW,
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    CC_OP_SHLL,
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    CC_OP_SHLQ,
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    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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    CC_OP_SARW,
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    CC_OP_SARL,
366
    CC_OP_SARQ,
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368
    CC_OP_NB,
369
};
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371
#ifdef FLOATX80
372
#define USE_X86LDOUBLE
373
#endif
374

    
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#ifdef USE_X86LDOUBLE
376
typedef floatx80 CPU86_LDouble;
377
#else
378
typedef float64 CPU86_LDouble;
379
#endif
380

    
381
typedef struct SegmentCache {
382
    uint32_t selector;
383
    target_ulong base;
384
    uint32_t limit;
385
    uint32_t flags;
386
} SegmentCache;
387

    
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typedef union {
389
    uint8_t _b[16];
390
    uint16_t _w[8];
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    uint32_t _l[4];
392
    uint64_t _q[2];
393
    float32 _s[4];
394
    float64 _d[2];
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} XMMReg;
396

    
397
typedef union {
398
    uint8_t _b[8];
399
    uint16_t _w[2];
400
    uint32_t _l[1];
401
    uint64_t q;
402
} MMXReg;
403

    
404
#ifdef WORDS_BIGENDIAN
405
#define XMM_B(n) _b[15 - (n)]
406
#define XMM_W(n) _w[7 - (n)]
407
#define XMM_L(n) _l[3 - (n)]
408
#define XMM_S(n) _s[3 - (n)]
409
#define XMM_Q(n) _q[1 - (n)]
410
#define XMM_D(n) _d[1 - (n)]
411

    
412
#define MMX_B(n) _b[7 - (n)]
413
#define MMX_W(n) _w[3 - (n)]
414
#define MMX_L(n) _l[1 - (n)]
415
#else
416
#define XMM_B(n) _b[n]
417
#define XMM_W(n) _w[n]
418
#define XMM_L(n) _l[n]
419
#define XMM_S(n) _s[n]
420
#define XMM_Q(n) _q[n]
421
#define XMM_D(n) _d[n]
422

    
423
#define MMX_B(n) _b[n]
424
#define MMX_W(n) _w[n]
425
#define MMX_L(n) _l[n]
426
#endif
427
#define MMX_Q(n) q
428

    
429
#ifdef TARGET_X86_64
430
#define CPU_NB_REGS 16
431
#else
432
#define CPU_NB_REGS 8
433
#endif
434

    
435
typedef struct CPUX86State {
436
#if TARGET_LONG_BITS > HOST_LONG_BITS
437
    /* temporaries if we cannot store them in host registers */
438
    target_ulong t0, t1, t2;
439
#endif
440

    
441
    /* standard registers */
442
    target_ulong regs[CPU_NB_REGS];
443
    target_ulong eip;
444
    target_ulong eflags; /* eflags register. During CPU emulation, CC
445
                        flags and DF are set to zero because they are
446
                        stored elsewhere */
447

    
448
    /* emulator internal eflags handling */
449
    target_ulong cc_src;
450
    target_ulong cc_dst;
451
    uint32_t cc_op;
452
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
453
    uint32_t hflags; /* hidden flags, see HF_xxx constants */
454

    
455
    /* segments */
456
    SegmentCache segs[6]; /* selector values */
457
    SegmentCache ldt;
458
    SegmentCache tr;
459
    SegmentCache gdt; /* only base and limit are used */
460
    SegmentCache idt; /* only base and limit are used */
461

    
462
    target_ulong cr[5]; /* NOTE: cr1 is unused */
463
    uint32_t a20_mask;
464

    
465
    /* FPU state */
466
    unsigned int fpstt; /* top of stack index */
467
    unsigned int fpus;
468
    unsigned int fpuc;
469
    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
470
    union {
471
#ifdef USE_X86LDOUBLE
472
        CPU86_LDouble d __attribute__((aligned(16)));
473
#else
474
        CPU86_LDouble d;
475
#endif
476
        MMXReg mmx;
477
    } fpregs[8];
478

    
479
    /* emulator internal variables */
480
    float_status fp_status;
481
    CPU86_LDouble ft0;
482
    union {
483
        float f;
484
        double d;
485
        int i32;
486
        int64_t i64;
487
    } fp_convert;
488

    
489
    float_status sse_status;
490
    uint32_t mxcsr;
491
    XMMReg xmm_regs[CPU_NB_REGS];
492
    XMMReg xmm_t0;
493
    MMXReg mmx_t0;
494

    
495
    /* sysenter registers */
496
    uint32_t sysenter_cs;
497
    uint32_t sysenter_esp;
498
    uint32_t sysenter_eip;
499
    uint64_t efer;
500
    uint64_t star;
501

    
502
    target_phys_addr_t vm_hsave;
503
    target_phys_addr_t vm_vmcb;
504
    uint64_t intercept;
505
    uint16_t intercept_cr_read;
506
    uint16_t intercept_cr_write;
507
    uint16_t intercept_dr_read;
508
    uint16_t intercept_dr_write;
509
    uint32_t intercept_exceptions;
510

    
511
#ifdef TARGET_X86_64
512
    target_ulong lstar;
513
    target_ulong cstar;
514
    target_ulong fmask;
515
    target_ulong kernelgsbase;
516
#endif
517

    
518
    uint64_t pat;
519

    
520
    /* temporary data for USE_CODE_COPY mode */
521
#ifdef USE_CODE_COPY
522
    uint32_t tmp0;
523
    uint32_t saved_esp;
524
    int native_fp_regs; /* if true, the FPU state is in the native CPU regs */
525
#endif
526

    
527
    /* exception/interrupt handling */
528
    jmp_buf jmp_env;
529
    int exception_index;
530
    int error_code;
531
    int exception_is_int;
532
    target_ulong exception_next_eip;
533
    target_ulong dr[8]; /* debug registers */
534
    uint32_t smbase;
535
    int interrupt_request;
536
    int user_mode_only; /* user mode only simulation */
537
    int old_exception;  /* exception in flight */
538

    
539
    CPU_COMMON
540

    
541
    /* processor features (e.g. for CPUID insn) */
542
    uint32_t cpuid_level;
543
    uint32_t cpuid_vendor1;
544
    uint32_t cpuid_vendor2;
545
    uint32_t cpuid_vendor3;
546
    uint32_t cpuid_version;
547
    uint32_t cpuid_features;
548
    uint32_t cpuid_ext_features;
549
    uint32_t cpuid_xlevel;
550
    uint32_t cpuid_model[12];
551
    uint32_t cpuid_ext2_features;
552
    uint32_t cpuid_ext3_features;
553
    uint32_t cpuid_apic_id;
554

    
555
#ifdef USE_KQEMU
556
    int kqemu_enabled;
557
    int last_io_time;
558
#endif
559
    /* in order to simplify APIC support, we leave this pointer to the
560
       user */
561
    struct APICState *apic_state;
562
} CPUX86State;
563

    
564
CPUX86State *cpu_x86_init(void);
565
int cpu_x86_exec(CPUX86State *s);
566
void cpu_x86_close(CPUX86State *s);
567
int cpu_get_pic_interrupt(CPUX86State *s);
568
/* MSDOS compatibility mode FPU exception support */
569
void cpu_set_ferr(CPUX86State *s);
570

    
571
/* this function must always be used to load data in the segment
572
   cache: it synchronizes the hflags with the segment cache values */
573
static inline void cpu_x86_load_seg_cache(CPUX86State *env,
574
                                          int seg_reg, unsigned int selector,
575
                                          target_ulong base,
576
                                          unsigned int limit,
577
                                          unsigned int flags)
578
{
579
    SegmentCache *sc;
580
    unsigned int new_hflags;
581

    
582
    sc = &env->segs[seg_reg];
583
    sc->selector = selector;
584
    sc->base = base;
585
    sc->limit = limit;
586
    sc->flags = flags;
587

    
588
    /* update the hidden flags */
589
    {
590
        if (seg_reg == R_CS) {
591
#ifdef TARGET_X86_64
592
            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
593
                /* long mode */
594
                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
595
                env->hflags &= ~(HF_ADDSEG_MASK);
596
            } else
597
#endif
598
            {
599
                /* legacy / compatibility case */
600
                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
601
                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
602
                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
603
                    new_hflags;
604
            }
605
        }
606
        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
607
            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
608
        if (env->hflags & HF_CS64_MASK) {
609
            /* zero base assumed for DS, ES and SS in long mode */
610
        } else if (!(env->cr[0] & CR0_PE_MASK) ||
611
                   (env->eflags & VM_MASK) ||
612
                   !(env->hflags & HF_CS32_MASK)) {
613
            /* XXX: try to avoid this test. The problem comes from the
614
               fact that is real mode or vm86 mode we only modify the
615
               'base' and 'selector' fields of the segment cache to go
616
               faster. A solution may be to force addseg to one in
617
               translate-i386.c. */
618
            new_hflags |= HF_ADDSEG_MASK;
619
        } else {
620
            new_hflags |= ((env->segs[R_DS].base |
621
                            env->segs[R_ES].base |
622
                            env->segs[R_SS].base) != 0) <<
623
                HF_ADDSEG_SHIFT;
624
        }
625
        env->hflags = (env->hflags &
626
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
627
    }
628
}
629

    
630
/* wrapper, just in case memory mappings must be changed */
631
static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
632
{
633
#if HF_CPL_MASK == 3
634
    s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
635
#else
636
#error HF_CPL_MASK is hardcoded
637
#endif
638
}
639

    
640
/* used for debug or cpu save/restore */
641
void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
642
CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
643

    
644
/* the following helpers are only usable in user mode simulation as
645
   they can trigger unexpected exceptions */
646
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
647
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
648
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
649

    
650
/* you can call this signal handler from your SIGBUS and SIGSEGV
651
   signal handlers to inform the virtual CPU of exceptions. non zero
652
   is returned if the signal was handled by the virtual CPU.  */
653
int cpu_x86_signal_handler(int host_signum, void *pinfo,
654
                           void *puc);
655
void cpu_x86_set_a20(CPUX86State *env, int a20_state);
656

    
657
uint64_t cpu_get_tsc(CPUX86State *env);
658

    
659
void cpu_set_apic_base(CPUX86State *env, uint64_t val);
660
uint64_t cpu_get_apic_base(CPUX86State *env);
661
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
662
#ifndef NO_CPU_IO_DEFS
663
uint8_t cpu_get_apic_tpr(CPUX86State *env);
664
#endif
665
void cpu_smm_update(CPUX86State *env);
666

    
667
/* will be suppressed */
668
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
669

    
670
/* used to debug */
671
#define X86_DUMP_FPU  0x0001 /* dump FPU state too */
672
#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
673

    
674
#ifdef USE_KQEMU
675
static inline int cpu_get_time_fast(void)
676
{
677
    int low, high;
678
    asm volatile("rdtsc" : "=a" (low), "=d" (high));
679
    return low;
680
}
681
#endif
682

    
683
#define TARGET_PAGE_BITS 12
684

    
685
#define CPUState CPUX86State
686
#define cpu_init cpu_x86_init
687
#define cpu_exec cpu_x86_exec
688
#define cpu_gen_code cpu_x86_gen_code
689
#define cpu_signal_handler cpu_x86_signal_handler
690

    
691
#include "cpu-all.h"
692

    
693
#include "svm.h"
694

    
695
#endif /* CPU_I386_H */