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1
/*
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 * QEMU PowerPC 405 evaluation boards emulation
3
 *
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 * Copyright (c) 2007 Jocelyn Mayer
5
 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
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#include "hw.h"
25
#include "ppc.h"
26
#include "ppc405.h"
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#include "nvram.h"
28
#include "flash.h"
29
#include "sysemu.h"
30
#include "block.h"
31
#include "boards.h"
32
#include "qemu-log.h"
33
#include "loader.h"
34

    
35
#define BIOS_FILENAME "ppc405_rom.bin"
36
#define BIOS_SIZE (2048 * 1024)
37

    
38
#define KERNEL_LOAD_ADDR 0x00000000
39
#define INITRD_LOAD_ADDR 0x01800000
40

    
41
#define USE_FLASH_BIOS
42

    
43
#define DEBUG_BOARD_INIT
44

    
45
/*****************************************************************************/
46
/* PPC405EP reference board (IBM) */
47
/* Standalone board with:
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 * - PowerPC 405EP CPU
49
 * - SDRAM (0x00000000)
50
 * - Flash (0xFFF80000)
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 * - SRAM  (0xFFF00000)
52
 * - NVRAM (0xF0000000)
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 * - FPGA  (0xF0300000)
54
 */
55
typedef struct ref405ep_fpga_t ref405ep_fpga_t;
56
struct ref405ep_fpga_t {
57
    uint8_t reg0;
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    uint8_t reg1;
59
};
60

    
61
static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
62
{
63
    ref405ep_fpga_t *fpga;
64
    uint32_t ret;
65

    
66
    fpga = opaque;
67
    switch (addr) {
68
    case 0x0:
69
        ret = fpga->reg0;
70
        break;
71
    case 0x1:
72
        ret = fpga->reg1;
73
        break;
74
    default:
75
        ret = 0;
76
        break;
77
    }
78

    
79
    return ret;
80
}
81

    
82
static void ref405ep_fpga_writeb (void *opaque,
83
                                  target_phys_addr_t addr, uint32_t value)
84
{
85
    ref405ep_fpga_t *fpga;
86

    
87
    fpga = opaque;
88
    switch (addr) {
89
    case 0x0:
90
        /* Read only */
91
        break;
92
    case 0x1:
93
        fpga->reg1 = value;
94
        break;
95
    default:
96
        break;
97
    }
98
}
99

    
100
static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
101
{
102
    uint32_t ret;
103

    
104
    ret = ref405ep_fpga_readb(opaque, addr) << 8;
105
    ret |= ref405ep_fpga_readb(opaque, addr + 1);
106

    
107
    return ret;
108
}
109

    
110
static void ref405ep_fpga_writew (void *opaque,
111
                                  target_phys_addr_t addr, uint32_t value)
112
{
113
    ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
114
    ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
115
}
116

    
117
static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
118
{
119
    uint32_t ret;
120

    
121
    ret = ref405ep_fpga_readb(opaque, addr) << 24;
122
    ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
123
    ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
124
    ret |= ref405ep_fpga_readb(opaque, addr + 3);
125

    
126
    return ret;
127
}
128

    
129
static void ref405ep_fpga_writel (void *opaque,
130
                                  target_phys_addr_t addr, uint32_t value)
131
{
132
    ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
133
    ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
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    ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
135
    ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
136
}
137

    
138
static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
139
    &ref405ep_fpga_readb,
140
    &ref405ep_fpga_readw,
141
    &ref405ep_fpga_readl,
142
};
143

    
144
static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
145
    &ref405ep_fpga_writeb,
146
    &ref405ep_fpga_writew,
147
    &ref405ep_fpga_writel,
148
};
149

    
150
static void ref405ep_fpga_reset (void *opaque)
151
{
152
    ref405ep_fpga_t *fpga;
153

    
154
    fpga = opaque;
155
    fpga->reg0 = 0x00;
156
    fpga->reg1 = 0x0F;
157
}
158

    
159
static void ref405ep_fpga_init (uint32_t base)
160
{
161
    ref405ep_fpga_t *fpga;
162
    int fpga_memory;
163

    
164
    fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
165
    fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
166
                                         ref405ep_fpga_write, fpga);
167
    cpu_register_physical_memory(base, 0x00000100, fpga_memory);
168
    qemu_register_reset(&ref405ep_fpga_reset, fpga);
169
}
170

    
171
static void ref405ep_init (ram_addr_t ram_size,
172
                           const char *boot_device,
173
                           const char *kernel_filename,
174
                           const char *kernel_cmdline,
175
                           const char *initrd_filename,
176
                           const char *cpu_model)
177
{
178
    char *filename;
179
    ppc4xx_bd_info_t bd;
180
    CPUPPCState *env;
181
    qemu_irq *pic;
182
    ram_addr_t sram_offset, bios_offset, bdloc;
183
    target_phys_addr_t ram_bases[2], ram_sizes[2];
184
    target_ulong sram_size, bios_size;
185
    //int phy_addr = 0;
186
    //static int phy_addr = 1;
187
    target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
188
    int linux_boot;
189
    int fl_idx, fl_sectors, len;
190
    DriveInfo *dinfo;
191

    
192
    /* XXX: fix this */
193
    ram_bases[0] = qemu_ram_alloc(0x08000000);
194
    ram_sizes[0] = 0x08000000;
195
    ram_bases[1] = 0x00000000;
196
    ram_sizes[1] = 0x00000000;
197
    ram_size = 128 * 1024 * 1024;
198
#ifdef DEBUG_BOARD_INIT
199
    printf("%s: register cpu\n", __func__);
200
#endif
201
    env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
202
                        kernel_filename == NULL ? 0 : 1);
203
    /* allocate SRAM */
204
    sram_size = 512 * 1024;
205
    sram_offset = qemu_ram_alloc(sram_size);
206
#ifdef DEBUG_BOARD_INIT
207
    printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
208
#endif
209
    cpu_register_physical_memory(0xFFF00000, sram_size,
210
                                 sram_offset | IO_MEM_RAM);
211
    /* allocate and load BIOS */
212
#ifdef DEBUG_BOARD_INIT
213
    printf("%s: register BIOS\n", __func__);
214
#endif
215
    fl_idx = 0;
216
#ifdef USE_FLASH_BIOS
217
    dinfo = drive_get(IF_PFLASH, 0, fl_idx);
218
    if (dinfo) {
219
        bios_size = bdrv_getlength(dinfo->bdrv);
220
        bios_offset = qemu_ram_alloc(bios_size);
221
        fl_sectors = (bios_size + 65535) >> 16;
222
#ifdef DEBUG_BOARD_INIT
223
        printf("Register parallel flash %d size " TARGET_FMT_lx
224
               " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
225
               fl_idx, bios_size, bios_offset, -bios_size,
226
               bdrv_get_device_name(dinfo->bdrv), fl_sectors);
227
#endif
228
        pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
229
                              dinfo->bdrv, 65536, fl_sectors, 1,
230
                              2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
231
                              1);
232
        fl_idx++;
233
    } else
234
#endif
235
    {
236
#ifdef DEBUG_BOARD_INIT
237
        printf("Load BIOS from file\n");
238
#endif
239
        bios_offset = qemu_ram_alloc(BIOS_SIZE);
240
        if (bios_name == NULL)
241
            bios_name = BIOS_FILENAME;
242
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
243
        if (filename) {
244
            bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
245
            qemu_free(filename);
246
        } else {
247
            bios_size = -1;
248
        }
249
        if (bios_size < 0 || bios_size > BIOS_SIZE) {
250
            fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
251
                    bios_name);
252
            exit(1);
253
        }
254
        bios_size = (bios_size + 0xfff) & ~0xfff;
255
        cpu_register_physical_memory((uint32_t)(-bios_size),
256
                                     bios_size, bios_offset | IO_MEM_ROM);
257
    }
258
    /* Register FPGA */
259
#ifdef DEBUG_BOARD_INIT
260
    printf("%s: register FPGA\n", __func__);
261
#endif
262
    ref405ep_fpga_init(0xF0300000);
263
    /* Register NVRAM */
264
#ifdef DEBUG_BOARD_INIT
265
    printf("%s: register NVRAM\n", __func__);
266
#endif
267
    m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
268
    /* Load kernel */
269
    linux_boot = (kernel_filename != NULL);
270
    if (linux_boot) {
271
#ifdef DEBUG_BOARD_INIT
272
        printf("%s: load kernel\n", __func__);
273
#endif
274
        memset(&bd, 0, sizeof(bd));
275
        bd.bi_memstart = 0x00000000;
276
        bd.bi_memsize = ram_size;
277
        bd.bi_flashstart = -bios_size;
278
        bd.bi_flashsize = -bios_size;
279
        bd.bi_flashoffset = 0;
280
        bd.bi_sramstart = 0xFFF00000;
281
        bd.bi_sramsize = sram_size;
282
        bd.bi_bootflags = 0;
283
        bd.bi_intfreq = 133333333;
284
        bd.bi_busfreq = 33333333;
285
        bd.bi_baudrate = 115200;
286
        bd.bi_s_version[0] = 'Q';
287
        bd.bi_s_version[1] = 'M';
288
        bd.bi_s_version[2] = 'U';
289
        bd.bi_s_version[3] = '\0';
290
        bd.bi_r_version[0] = 'Q';
291
        bd.bi_r_version[1] = 'E';
292
        bd.bi_r_version[2] = 'M';
293
        bd.bi_r_version[3] = 'U';
294
        bd.bi_r_version[4] = '\0';
295
        bd.bi_procfreq = 133333333;
296
        bd.bi_plb_busfreq = 33333333;
297
        bd.bi_pci_busfreq = 33333333;
298
        bd.bi_opbfreq = 33333333;
299
        bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
300
        env->gpr[3] = bdloc;
301
        kernel_base = KERNEL_LOAD_ADDR;
302
        /* now we can load the kernel */
303
        kernel_size = load_image_targphys(kernel_filename, kernel_base,
304
                                          ram_size - kernel_base);
305
        if (kernel_size < 0) {
306
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
307
                    kernel_filename);
308
            exit(1);
309
        }
310
        printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
311
               kernel_size, kernel_base);
312
        /* load initrd */
313
        if (initrd_filename) {
314
            initrd_base = INITRD_LOAD_ADDR;
315
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
316
                                              ram_size - initrd_base);
317
            if (initrd_size < 0) {
318
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
319
                        initrd_filename);
320
                exit(1);
321
            }
322
        } else {
323
            initrd_base = 0;
324
            initrd_size = 0;
325
        }
326
        env->gpr[4] = initrd_base;
327
        env->gpr[5] = initrd_size;
328
        if (kernel_cmdline != NULL) {
329
            len = strlen(kernel_cmdline);
330
            bdloc -= ((len + 255) & ~255);
331
            cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
332
            env->gpr[6] = bdloc;
333
            env->gpr[7] = bdloc + len;
334
        } else {
335
            env->gpr[6] = 0;
336
            env->gpr[7] = 0;
337
        }
338
        env->nip = KERNEL_LOAD_ADDR;
339
    } else {
340
        kernel_base = 0;
341
        kernel_size = 0;
342
        initrd_base = 0;
343
        initrd_size = 0;
344
        bdloc = 0;
345
    }
346
#ifdef DEBUG_BOARD_INIT
347
    printf("%s: Done\n", __func__);
348
#endif
349
    printf("bdloc %016lx\n", (unsigned long)bdloc);
350
}
351

    
352
static QEMUMachine ref405ep_machine = {
353
    .name = "ref405ep",
354
    .desc = "ref405ep",
355
    .init = ref405ep_init,
356
};
357

    
358
/*****************************************************************************/
359
/* AMCC Taihu evaluation board */
360
/* - PowerPC 405EP processor
361
 * - SDRAM               128 MB at 0x00000000
362
 * - Boot flash          2 MB   at 0xFFE00000
363
 * - Application flash   32 MB  at 0xFC000000
364
 * - 2 serial ports
365
 * - 2 ethernet PHY
366
 * - 1 USB 1.1 device    0x50000000
367
 * - 1 LCD display       0x50100000
368
 * - 1 CPLD              0x50100000
369
 * - 1 I2C EEPROM
370
 * - 1 I2C thermal sensor
371
 * - a set of LEDs
372
 * - bit-bang SPI port using GPIOs
373
 * - 1 EBC interface connector 0 0x50200000
374
 * - 1 cardbus controller + expansion slot.
375
 * - 1 PCI expansion slot.
376
 */
377
typedef struct taihu_cpld_t taihu_cpld_t;
378
struct taihu_cpld_t {
379
    uint8_t reg0;
380
    uint8_t reg1;
381
};
382

    
383
static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
384
{
385
    taihu_cpld_t *cpld;
386
    uint32_t ret;
387

    
388
    cpld = opaque;
389
    switch (addr) {
390
    case 0x0:
391
        ret = cpld->reg0;
392
        break;
393
    case 0x1:
394
        ret = cpld->reg1;
395
        break;
396
    default:
397
        ret = 0;
398
        break;
399
    }
400

    
401
    return ret;
402
}
403

    
404
static void taihu_cpld_writeb (void *opaque,
405
                               target_phys_addr_t addr, uint32_t value)
406
{
407
    taihu_cpld_t *cpld;
408

    
409
    cpld = opaque;
410
    switch (addr) {
411
    case 0x0:
412
        /* Read only */
413
        break;
414
    case 0x1:
415
        cpld->reg1 = value;
416
        break;
417
    default:
418
        break;
419
    }
420
}
421

    
422
static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
423
{
424
    uint32_t ret;
425

    
426
    ret = taihu_cpld_readb(opaque, addr) << 8;
427
    ret |= taihu_cpld_readb(opaque, addr + 1);
428

    
429
    return ret;
430
}
431

    
432
static void taihu_cpld_writew (void *opaque,
433
                               target_phys_addr_t addr, uint32_t value)
434
{
435
    taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
436
    taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
437
}
438

    
439
static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
440
{
441
    uint32_t ret;
442

    
443
    ret = taihu_cpld_readb(opaque, addr) << 24;
444
    ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
445
    ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
446
    ret |= taihu_cpld_readb(opaque, addr + 3);
447

    
448
    return ret;
449
}
450

    
451
static void taihu_cpld_writel (void *opaque,
452
                               target_phys_addr_t addr, uint32_t value)
453
{
454
    taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
455
    taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
456
    taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
457
    taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
458
}
459

    
460
static CPUReadMemoryFunc * const taihu_cpld_read[] = {
461
    &taihu_cpld_readb,
462
    &taihu_cpld_readw,
463
    &taihu_cpld_readl,
464
};
465

    
466
static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
467
    &taihu_cpld_writeb,
468
    &taihu_cpld_writew,
469
    &taihu_cpld_writel,
470
};
471

    
472
static void taihu_cpld_reset (void *opaque)
473
{
474
    taihu_cpld_t *cpld;
475

    
476
    cpld = opaque;
477
    cpld->reg0 = 0x01;
478
    cpld->reg1 = 0x80;
479
}
480

    
481
static void taihu_cpld_init (uint32_t base)
482
{
483
    taihu_cpld_t *cpld;
484
    int cpld_memory;
485

    
486
    cpld = qemu_mallocz(sizeof(taihu_cpld_t));
487
    cpld_memory = cpu_register_io_memory(taihu_cpld_read,
488
                                         taihu_cpld_write, cpld);
489
    cpu_register_physical_memory(base, 0x00000100, cpld_memory);
490
    qemu_register_reset(&taihu_cpld_reset, cpld);
491
}
492

    
493
static void taihu_405ep_init(ram_addr_t ram_size,
494
                             const char *boot_device,
495
                             const char *kernel_filename,
496
                             const char *kernel_cmdline,
497
                             const char *initrd_filename,
498
                             const char *cpu_model)
499
{
500
    char *filename;
501
    CPUPPCState *env;
502
    qemu_irq *pic;
503
    ram_addr_t bios_offset;
504
    target_phys_addr_t ram_bases[2], ram_sizes[2];
505
    target_ulong bios_size;
506
    target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
507
    int linux_boot;
508
    int fl_idx, fl_sectors;
509
    DriveInfo *dinfo;
510

    
511
    /* RAM is soldered to the board so the size cannot be changed */
512
    ram_bases[0] = qemu_ram_alloc(0x04000000);
513
    ram_sizes[0] = 0x04000000;
514
    ram_bases[1] = qemu_ram_alloc(0x04000000);
515
    ram_sizes[1] = 0x04000000;
516
    ram_size = 0x08000000;
517
#ifdef DEBUG_BOARD_INIT
518
    printf("%s: register cpu\n", __func__);
519
#endif
520
    env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
521
                        kernel_filename == NULL ? 0 : 1);
522
    /* allocate and load BIOS */
523
#ifdef DEBUG_BOARD_INIT
524
    printf("%s: register BIOS\n", __func__);
525
#endif
526
    fl_idx = 0;
527
#if defined(USE_FLASH_BIOS)
528
    dinfo = drive_get(IF_PFLASH, 0, fl_idx);
529
    if (dinfo) {
530
        bios_size = bdrv_getlength(dinfo->bdrv);
531
        /* XXX: should check that size is 2MB */
532
        //        bios_size = 2 * 1024 * 1024;
533
        fl_sectors = (bios_size + 65535) >> 16;
534
        bios_offset = qemu_ram_alloc(bios_size);
535
#ifdef DEBUG_BOARD_INIT
536
        printf("Register parallel flash %d size " TARGET_FMT_lx
537
               " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
538
               fl_idx, bios_size, bios_offset, -bios_size,
539
               bdrv_get_device_name(dinfo->bdrv), fl_sectors);
540
#endif
541
        pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
542
                              dinfo->bdrv, 65536, fl_sectors, 1,
543
                              4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
544
                              1);
545
        fl_idx++;
546
    } else
547
#endif
548
    {
549
#ifdef DEBUG_BOARD_INIT
550
        printf("Load BIOS from file\n");
551
#endif
552
        if (bios_name == NULL)
553
            bios_name = BIOS_FILENAME;
554
        bios_offset = qemu_ram_alloc(BIOS_SIZE);
555
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
556
        if (filename) {
557
            bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
558
        } else {
559
            bios_size = -1;
560
        }
561
        if (bios_size < 0 || bios_size > BIOS_SIZE) {
562
            fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
563
                    bios_name);
564
            exit(1);
565
        }
566
        bios_size = (bios_size + 0xfff) & ~0xfff;
567
        cpu_register_physical_memory((uint32_t)(-bios_size),
568
                                     bios_size, bios_offset | IO_MEM_ROM);
569
    }
570
    /* Register Linux flash */
571
    dinfo = drive_get(IF_PFLASH, 0, fl_idx);
572
    if (dinfo) {
573
        bios_size = bdrv_getlength(dinfo->bdrv);
574
        /* XXX: should check that size is 32MB */
575
        bios_size = 32 * 1024 * 1024;
576
        fl_sectors = (bios_size + 65535) >> 16;
577
#ifdef DEBUG_BOARD_INIT
578
        printf("Register parallel flash %d size " TARGET_FMT_lx
579
               " at offset %08lx  addr " TARGET_FMT_lx " '%s'\n",
580
               fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
581
               bdrv_get_device_name(dinfo->bdrv));
582
#endif
583
        bios_offset = qemu_ram_alloc(bios_size);
584
        pflash_cfi02_register(0xfc000000, bios_offset,
585
                              dinfo->bdrv, 65536, fl_sectors, 1,
586
                              4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
587
                              1);
588
        fl_idx++;
589
    }
590
    /* Register CLPD & LCD display */
591
#ifdef DEBUG_BOARD_INIT
592
    printf("%s: register CPLD\n", __func__);
593
#endif
594
    taihu_cpld_init(0x50100000);
595
    /* Load kernel */
596
    linux_boot = (kernel_filename != NULL);
597
    if (linux_boot) {
598
#ifdef DEBUG_BOARD_INIT
599
        printf("%s: load kernel\n", __func__);
600
#endif
601
        kernel_base = KERNEL_LOAD_ADDR;
602
        /* now we can load the kernel */
603
        kernel_size = load_image_targphys(kernel_filename, kernel_base,
604
                                          ram_size - kernel_base);
605
        if (kernel_size < 0) {
606
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
607
                    kernel_filename);
608
            exit(1);
609
        }
610
        /* load initrd */
611
        if (initrd_filename) {
612
            initrd_base = INITRD_LOAD_ADDR;
613
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
614
                                              ram_size - initrd_base);
615
            if (initrd_size < 0) {
616
                fprintf(stderr,
617
                        "qemu: could not load initial ram disk '%s'\n",
618
                        initrd_filename);
619
                exit(1);
620
            }
621
        } else {
622
            initrd_base = 0;
623
            initrd_size = 0;
624
        }
625
    } else {
626
        kernel_base = 0;
627
        kernel_size = 0;
628
        initrd_base = 0;
629
        initrd_size = 0;
630
    }
631
#ifdef DEBUG_BOARD_INIT
632
    printf("%s: Done\n", __func__);
633
#endif
634
}
635

    
636
static QEMUMachine taihu_machine = {
637
    .name = "taihu",
638
    .desc = "taihu",
639
    .init = taihu_405ep_init,
640
};
641

    
642
static void ppc405_machine_init(void)
643
{
644
    qemu_register_machine(&ref405ep_machine);
645
    qemu_register_machine(&taihu_machine);
646
}
647

    
648
machine_init(ppc405_machine_init);