Revision 060718c1 target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 79 | 79 |
int mem_idx; |
| 80 | 80 |
int fpu_enabled; |
| 81 | 81 |
int address_mask_32bit; |
| 82 |
int singlestep; |
|
| 82 | 83 |
uint32_t cc_op; /* current CC operation */ |
| 83 | 84 |
struct TranslationBlock *tb; |
| 84 | 85 |
sparc_def_t *def; |
| ... | ... | |
| 234 | 235 |
|
| 235 | 236 |
tb = s->tb; |
| 236 | 237 |
if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && |
| 237 |
(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
|
|
| 238 |
(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && |
|
| 239 |
!s->singlestep) {
|
|
| 238 | 240 |
/* jump to same page: we can use a direct jump */ |
| 239 | 241 |
tcg_gen_goto_tb(tb_num); |
| 240 | 242 |
tcg_gen_movi_tl(cpu_pc, pc); |
| ... | ... | |
| 4694 | 4696 |
#ifdef TARGET_SPARC64 |
| 4695 | 4697 |
dc->address_mask_32bit = env->pstate & PS_AM; |
| 4696 | 4698 |
#endif |
| 4699 |
dc->singlestep = (env->singlestep_enabled || singlestep); |
|
| 4697 | 4700 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
| 4698 | 4701 |
|
| 4699 | 4702 |
cpu_tmp0 = tcg_temp_new(); |
| ... | ... | |
| 4754 | 4757 |
break; |
| 4755 | 4758 |
/* if single step mode, we generate only one instruction and |
| 4756 | 4759 |
generate an exception */ |
| 4757 |
if (env->singlestep_enabled || singlestep) {
|
|
| 4758 |
tcg_gen_movi_tl(cpu_pc, dc->pc); |
|
| 4759 |
tcg_gen_exit_tb(0); |
|
| 4760 |
if (dc->singlestep) {
|
|
| 4760 | 4761 |
break; |
| 4761 | 4762 |
} |
| 4762 | 4763 |
} while ((gen_opc_ptr < gen_opc_end) && |
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