Revision 067a3ddc

b/hw/arm_gic.c
721 721
{
722 722
    int i;
723 723

  
724
    qdev_init_irq_sink(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
724
    qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
725 725
    for (i = 0; i < NCPU; i++) {
726 726
        sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
727 727
    }
b/hw/armv7m.c
186 186
    cpu_pic = arm_pic_init_cpu(env);
187 187
    sysbus_connect_irq(sysbus_from_qdev(nvic), 0, cpu_pic[ARM_PIC_CPU_IRQ]);
188 188
    for (i = 0; i < 64; i++) {
189
        pic[i] = qdev_get_irq_sink(nvic, i);
189
        pic[i] = qdev_get_gpio_in(nvic, i);
190 190
    }
191 191

  
192 192
    image_size = load_elf(kernel_filename, 0, &entry, &lowaddr, NULL);
b/hw/axis_dev88.c
304 304
    sysbus_connect_irq(s, 0, cpu_irq[0]);
305 305
    sysbus_connect_irq(s, 1, cpu_irq[1]);
306 306
    for (i = 0; i < 30; i++) {
307
        irq[i] = qdev_get_irq_sink(dev, i);
307
        irq[i] = qdev_get_gpio_in(dev, i);
308 308
    }
309
    nmi[0] = qdev_get_irq_sink(dev, 30);
310
    nmi[1] = qdev_get_irq_sink(dev, 31);
309
    nmi[0] = qdev_get_gpio_in(dev, 30);
310
    nmi[1] = qdev_get_gpio_in(dev, 31);
311 311

  
312 312
    etraxfs_dmac = etraxfs_dmac_init(env, 0x30000000, 10);
313 313
    for (i = 0; i < 10; i++) {
b/hw/esp.c
684 684
    register_savevm("esp", -1, 3, esp_save, esp_load, s);
685 685
    qemu_register_reset(esp_reset, 0, s);
686 686

  
687
    qdev_init_irq_sink(&dev->qdev, parent_esp_reset, 1);
687
    qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
688 688

  
689 689
    scsi_bus_new(&dev->qdev, esp_scsi_attach);
690 690
}
b/hw/etraxfs.c
90 90
    /* FIXME: Is there a proper way to signal vectors to the CPU core?  */
91 91
    qdev_set_prop_ptr(dev, "interrupt_vector", &env->interrupt_vector);
92 92
    for (i = 0; i < 30; i++) {
93
        irq[i] = qdev_get_irq_sink(dev, i);
93
        irq[i] = qdev_get_gpio_in(dev, i);
94 94
    }
95
    nmi[0] = qdev_get_irq_sink(dev, 30);
96
    nmi[1] = qdev_get_irq_sink(dev, 31);
95
    nmi[0] = qdev_get_gpio_in(dev, 30);
96
    nmi[1] = qdev_get_gpio_in(dev, 31);
97 97

  
98 98
    etraxfs_dmac = etraxfs_dmac_init(env, 0x30000000, 10);
99 99
    for (i = 0; i < 10; i++) {
b/hw/etraxfs_pic.c
141 141
    int intr_vect_regs;
142 142

  
143 143
    s->interrupt_vector = qdev_get_prop_ptr(&dev->qdev, "interrupt_vector");
144
    qdev_init_irq_sink(&dev->qdev, irq_handler, 32);
144
    qdev_init_gpio_in(&dev->qdev, irq_handler, 32);
145 145
    sysbus_init_irq(dev, &s->parent_irq);
146 146
    sysbus_init_irq(dev, &s->parent_nmi);
147 147

  
b/hw/integratorcp.c
378 378
    icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
379 379
    int iomemtype;
380 380

  
381
    qdev_init_irq_sink(&dev->qdev, icp_pic_set_irq, 32);
381
    qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
382 382
    sysbus_init_irq(dev, &s->parent_irq);
383 383
    sysbus_init_irq(dev, &s->parent_fiq);
384 384
    iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
......
484 484
                                cpu_pic[ARM_PIC_CPU_IRQ],
485 485
                                cpu_pic[ARM_PIC_CPU_FIQ], NULL);
486 486
    for (i = 0; i < 32; i++) {
487
        pic[i] = qdev_get_irq_sink(dev, i);
487
        pic[i] = qdev_get_gpio_in(dev, i);
488 488
    }
489 489
    sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
490 490
    sysbus_create_varargs("integrator_pit", 0x13000000,
b/hw/mpcore.c
320 320
    priv = sysbus_create_simple("arm11mpcore_priv", MPCORE_PRIV_BASE, NULL);
321 321
    sysbus_pass_irq(dev, sysbus_from_qdev(priv));
322 322
    for (i = 0; i < 32; i++) {
323
        s->cpuic[i] = qdev_get_irq_sink(priv, i);
323
        s->cpuic[i] = qdev_get_gpio_in(priv, i);
324 324
    }
325 325
    /* ??? IRQ routing is hardcoded to "normal" mode.  */
326 326
    for (n = 0; n < 4; n++) {
327 327
        gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
328 328
                                   s->cpuic[10 + n]);
329 329
        for (i = 0; i < 64; i++) {
330
            s->rvic[n][i] = qdev_get_irq_sink(gic, i);
330
            s->rvic[n][i] = qdev_get_gpio_in(gic, i);
331 331
        }
332 332
    }
333
    qdev_init_irq_sink(&dev->qdev, mpcore_rirq_set_irq, 64);
333
    qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64);
334 334
}
335 335

  
336 336
static void mpcore_register_devices(void)
b/hw/musicpal.c
1040 1040
    mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
1041 1041
    int iomemtype;
1042 1042

  
1043
    qdev_init_irq_sink(&dev->qdev, mv88w8618_pic_set_irq, 32);
1043
    qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
1044 1044
    sysbus_init_irq(dev, &s->parent_irq);
1045 1045
    iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1046 1046
                                       mv88w8618_pic_writefn, s);
......
1534 1534
    dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1535 1535
                               cpu_pic[ARM_PIC_CPU_IRQ]);
1536 1536
    for (i = 0; i < 32; i++) {
1537
        pic[i] = qdev_get_irq_sink(dev, i);
1537
        pic[i] = qdev_get_gpio_in(dev, i);
1538 1538
    }
1539 1539
    sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1540 1540
                          pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
b/hw/pcnet.c
2127 2127

  
2128 2128
    s->dma_opaque = qdev_get_prop_ptr(&dev->qdev, "dma");
2129 2129

  
2130
    qdev_init_irq_sink(&dev->qdev, parent_lance_reset, 1);
2130
    qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
2131 2131

  
2132 2132
    sysbus_init_mmio(dev, 4, s->mmio_index);
2133 2133

  
b/hw/pl190.c
235 235
    iomemtype = cpu_register_io_memory(0, pl190_readfn,
236 236
                                       pl190_writefn, s);
237 237
    sysbus_init_mmio(dev, 0x1000, iomemtype);
238
    qdev_init_irq_sink(&dev->qdev, pl190_set_irq, 32);
238
    qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
239 239
    sysbus_init_irq(dev, &s->irq);
240 240
    sysbus_init_irq(dev, &s->fiq);
241 241
    pl190_reset(s);
b/hw/qdev.c
156 156
}
157 157

  
158 158

  
159
qemu_irq qdev_get_irq_sink(DeviceState *dev, int n)
160
{
161
    assert(n >= 0 && n < dev->num_irq_sink);
162
    return dev->irq_sink[n];
163
}
164

  
165
/* Register device IRQ sinks.  */
166
void qdev_init_irq_sink(DeviceState *dev, qemu_irq_handler handler, int nirq)
167
{
168
    dev->num_irq_sink = nirq;
169
    dev->irq_sink = qemu_allocate_irqs(handler, dev, nirq);
170
}
171

  
172 159
/* Get a character (serial) device interface.  */
173 160
CharDriverState *qdev_init_chardev(DeviceState *dev)
174 161
{
b/hw/qdev.h
17 17
    DeviceType *type;
18 18
    BusState *parent_bus;
19 19
    DeviceProperty *props;
20
    int num_irq_sink;
21
    qemu_irq *irq_sink;
22 20
    int num_gpio_out;
23 21
    qemu_irq *gpio_out;
24 22
    int num_gpio_in;
......
55 53
void qdev_set_prop_ptr(DeviceState *dev, const char *name, void *value);
56 54
void qdev_set_netdev(DeviceState *dev, NICInfo *nd);
57 55

  
58
qemu_irq qdev_get_irq_sink(DeviceState *dev, int n);
59 56
qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);
60 57
void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin);
61 58

  
......
77 74
void qdev_register(const char *name, int size, DeviceInfo *info);
78 75

  
79 76
/* Register device properties.  */
80
void qdev_init_irq_sink(DeviceState *dev, qemu_irq_handler handler, int nirq);
77
/* GPIO inputs also double as IRQ sinks.  */
81 78
void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n);
82 79
void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n);
83 80

  
b/hw/realview.c
84 84
                                    cpu_irq[3], NULL);
85 85
    }
86 86
    for (n = 0; n < 64; n++) {
87
        pic[n] = qdev_get_irq_sink(dev, n);
87
        pic[n] = qdev_get_gpio_in(dev, n);
88 88
    }
89 89

  
90 90
    sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
b/hw/sun4m.c
379 379
    s = sysbus_from_qdev(dev);
380 380
    sysbus_mmio_map(s, 0, leaddr);
381 381
    sysbus_connect_irq(s, 0, irq);
382
    *reset = qdev_get_irq_sink(dev, 0);
382
    *reset = qdev_get_gpio_in(dev, 0);
383 383
}
384 384

  
385 385
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
b/hw/syborg.c
58 58
    dev = sysbus_create_simple("syborg,interrupt", 0xC0000000,
59 59
                               cpu_pic[ARM_PIC_CPU_IRQ]);
60 60
    for (i = 0; i < 64; i++) {
61
        pic[i] = qdev_get_irq_sink(dev, i);
61
        pic[i] = qdev_get_gpio_in(dev, i);
62 62
    }
63 63

  
64 64
    sysbus_create_simple("syborg,rtc", 0xC0001000, NULL);
b/hw/syborg_interrupt.c
209 209

  
210 210
    sysbus_init_irq(dev, &s->parent_irq);
211 211
    s->num_irqs = qdev_get_prop_int(&dev->qdev, "num-interrupts", 64);
212
    qdev_init_irq_sink(&dev->qdev, syborg_int_set_irq, s->num_irqs);
212
    qdev_init_gpio_in(&dev->qdev, syborg_int_set_irq, s->num_irqs);
213 213
    iomemtype = cpu_register_io_memory(0, syborg_int_readfn,
214 214
                                       syborg_int_writefn, s);
215 215
    sysbus_init_mmio(dev, 0x1000, iomemtype);
b/hw/versatilepb.c
135 135
    int iomemtype;
136 136
    int i;
137 137

  
138
    qdev_init_irq_sink(&dev->qdev, vpb_sic_set_irq, 32);
138
    qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
139 139
    for (i = 0; i < 32; i++) {
140 140
        sysbus_init_irq(dev, &s->parent[i]);
141 141
    }
......
188 188
    dev = sysbus_create_varargs("pl190", 0x10140000,
189 189
                                cpu_pic[0], cpu_pic[1], NULL);
190 190
    for (n = 0; n < 32; n++) {
191
        pic[n] = qdev_get_irq_sink(dev, n);
191
        pic[n] = qdev_get_gpio_in(dev, n);
192 192
    }
193 193
    dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
194 194
    for (n = 0; n < 32; n++) {
195 195
        sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
196
        sic[n] = qdev_get_irq_sink(dev, n);
196
        sic[n] = qdev_get_gpio_in(dev, n);
197 197
    }
198 198

  
199 199
    sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);

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