Revision 06afe2c8 target-sh4/helper.c

b/target-sh4/helper.c
251 251
    for (i = 0; i < nbtlb; i++) {
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	if (!entries[i].v)
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	    continue;		/* Invalid entry */
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	if (use_asid && entries[i].asid != asid && !entries[i].sh)
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	if (use_asid && entries[i].asid != asid)
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	    continue;		/* Bad ASID */
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#if 0
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	switch (entries[i].sz) {
......
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    else if (e == MMU_DTLB_MISS && update) {
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	e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
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	if (e >= 0) {
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	    tlb_t * ientry;
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	    n = itlb_replacement(env);
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	    env->itlb[n] = env->utlb[e];
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	    ientry = &env->itlb[n];
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	    if (ientry->v) {
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		if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
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		    tlb_flush_page(env, ientry->vpn << 10);
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	    }
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	    *ientry = env->utlb[e];
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	    e = n;
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	} else if (e == MMU_DTLB_MISS)
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	    e = MMU_ITLB_MISS;
......
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    int use_asid, is_code, n;
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    tlb_t *matching = NULL;
358 364

  
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    use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
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    use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
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    is_code = env->pc == address;	/* Hack */
361 367

  
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    /* Use a hack to find if this is an instruction or data access */
......
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    int n = cpu_mmucr_urc(env->mmucr);
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    tlb_t * entry = &env->utlb[n];
542 548

  
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    if (entry->v) {
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        /* Overwriting valid entry in utlb. */
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        target_ulong address = entry->vpn << 10;
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	if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
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	    tlb_flush_page(env, address);
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	}
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    }
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    /* per utlb access cannot implemented. */
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    increment_urc(env);
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    /* Take values into cpu status from registers. */
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    entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
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    entry->vpn  = cpu_pteh_vpn(env->pteh);

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