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/*
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 * SH7750 device
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 *
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 * Copyright (c) 2007 Magnus Damm
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 * Copyright (c) 2005 Samuel Tardieu
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include <stdio.h>
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#include <assert.h>
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#include "hw.h"
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#include "sh.h"
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#include "sysemu.h"
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#include "sh7750_regs.h"
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#include "sh7750_regnames.h"
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#include "sh_intc.h"
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#include "exec-all.h"
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#include "cpu.h"
35

    
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#define NB_DEVICES 4
37

    
38
typedef struct SH7750State {
39
    /* CPU */
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    CPUSH4State *cpu;
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    /* Peripheral frequency in Hz */
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    uint32_t periph_freq;
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    /* SDRAM controller */
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    uint16_t rfcr;
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    /* IO ports */
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    uint16_t gpioic;
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    uint32_t pctra;
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    uint32_t pctrb;
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    uint16_t portdira;                /* Cached */
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    uint16_t portpullupa;        /* Cached */
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    uint16_t portdirb;                /* Cached */
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    uint16_t portpullupb;        /* Cached */
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    uint16_t pdtra;
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    uint16_t pdtrb;
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    uint16_t periph_pdtra;        /* Imposed by the peripherals */
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    uint16_t periph_portdira;        /* Direction seen from the peripherals */
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    uint16_t periph_pdtrb;        /* Imposed by the peripherals */
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    uint16_t periph_portdirb;        /* Direction seen from the peripherals */
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    sh7750_io_device *devices[NB_DEVICES];        /* External peripherals */
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    uint16_t icr;
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    /* Cache */
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    uint32_t ccr;
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65
    struct intc_desc intc;
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} SH7750State;
67

    
68

    
69
/**********************************************************************
70
 I/O ports
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**********************************************************************/
72

    
73
int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
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{
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    int i;
76

    
77
    for (i = 0; i < NB_DEVICES; i++) {
78
        if (s->devices[i] == NULL) {
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            s->devices[i] = device;
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            return 0;
81
        }
82
    }
83
    return -1;
84
}
85

    
86
static uint16_t portdir(uint32_t v)
87
{
88
#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
89
    return
90
        EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
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        EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
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        EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
93
        EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
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        EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
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        EVENPORTMASK(0);
96
}
97

    
98
static uint16_t portpullup(uint32_t v)
99
{
100
#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
101
    return
102
        ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
103
        ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
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        ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
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        ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
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        ODDPORTMASK(1) | ODDPORTMASK(0);
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}
108

    
109
static uint16_t porta_lines(SH7750State * s)
110
{
111
    return (s->portdira & s->pdtra) |        /* CPU */
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        (s->periph_portdira & s->periph_pdtra) |        /* Peripherals */
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        (~(s->portdira | s->periph_portdira) & s->portpullupa);        /* Pullups */
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}
115

    
116
static uint16_t portb_lines(SH7750State * s)
117
{
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    return (s->portdirb & s->pdtrb) |        /* CPU */
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        (s->periph_portdirb & s->periph_pdtrb) |        /* Peripherals */
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        (~(s->portdirb | s->periph_portdirb) & s->portpullupb);        /* Pullups */
121
}
122

    
123
static void gen_port_interrupts(SH7750State * s)
124
{
125
    /* XXXXX interrupts not generated */
126
}
127

    
128
static void porta_changed(SH7750State * s, uint16_t prev)
129
{
130
    uint16_t currenta, changes;
131
    int i, r = 0;
132

    
133
#if 0
134
    fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
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            prev, porta_lines(s));
136
    fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
137
#endif
138
    currenta = porta_lines(s);
139
    if (currenta == prev)
140
        return;
141
    changes = currenta ^ prev;
142

    
143
    for (i = 0; i < NB_DEVICES; i++) {
144
        if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
145
            r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
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                                               &s->periph_pdtra,
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                                               &s->periph_portdira,
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                                               &s->periph_pdtrb,
149
                                               &s->periph_portdirb);
150
        }
151
    }
152

    
153
    if (r)
154
        gen_port_interrupts(s);
155
}
156

    
157
static void portb_changed(SH7750State * s, uint16_t prev)
158
{
159
    uint16_t currentb, changes;
160
    int i, r = 0;
161

    
162
    currentb = portb_lines(s);
163
    if (currentb == prev)
164
        return;
165
    changes = currentb ^ prev;
166

    
167
    for (i = 0; i < NB_DEVICES; i++) {
168
        if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
169
            r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
170
                                               &s->periph_pdtra,
171
                                               &s->periph_portdira,
172
                                               &s->periph_pdtrb,
173
                                               &s->periph_portdirb);
174
        }
175
    }
176

    
177
    if (r)
178
        gen_port_interrupts(s);
179
}
180

    
181
/**********************************************************************
182
 Memory
183
**********************************************************************/
184

    
185
static void error_access(const char *kind, target_phys_addr_t addr)
186
{
187
    fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
188
            kind, regname(addr), addr);
189
}
190

    
191
static void ignore_access(const char *kind, target_phys_addr_t addr)
192
{
193
    fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
194
            kind, regname(addr), addr);
195
}
196

    
197
static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
198
{
199
    switch (addr) {
200
    default:
201
        error_access("byte read", addr);
202
        assert(0);
203
    }
204
}
205

    
206
static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
207
{
208
    SH7750State *s = opaque;
209

    
210
    switch (addr) {
211
    case SH7750_FRQCR_A7:
212
        return 0;
213
    case SH7750_RFCR_A7:
214
        fprintf(stderr,
215
                "Read access to refresh count register, incrementing\n");
216
        return s->rfcr++;
217
    case SH7750_PDTRA_A7:
218
        return porta_lines(s);
219
    case SH7750_PDTRB_A7:
220
        return portb_lines(s);
221
    case 0x1fd00000:
222
        return s->icr;
223
    default:
224
        error_access("word read", addr);
225
        assert(0);
226
    }
227
}
228

    
229
static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
230
{
231
    SH7750State *s = opaque;
232

    
233
    switch (addr) {
234
    case SH7750_MMUCR_A7:
235
        return s->cpu->mmucr;
236
    case SH7750_PTEH_A7:
237
        return s->cpu->pteh;
238
    case SH7750_PTEL_A7:
239
        return s->cpu->ptel;
240
    case SH7750_TTB_A7:
241
        return s->cpu->ttb;
242
    case SH7750_TEA_A7:
243
        return s->cpu->tea;
244
    case SH7750_TRA_A7:
245
        return s->cpu->tra;
246
    case SH7750_EXPEVT_A7:
247
        return s->cpu->expevt;
248
    case SH7750_INTEVT_A7:
249
        return s->cpu->intevt;
250
    case SH7750_CCR_A7:
251
        return s->ccr;
252
    case 0x1f000030:                /* Processor version PVR */
253
        return 0x00050000;        /* SH7750R */
254
    case 0x1f000040:                /* Processor version CVR */
255
        return 0x00110000;        /* Minimum caches */
256
    case 0x1f000044:                /* Processor version PRR */
257
        return 0x00000100;        /* SH7750R */
258
    default:
259
        error_access("long read", addr);
260
        assert(0);
261
    }
262
}
263

    
264
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
265
                              uint32_t mem_value)
266
{
267
    switch (addr) {
268
        /* PRECHARGE ? XXXXX */
269
    case SH7750_PRECHARGE0_A7:
270
    case SH7750_PRECHARGE1_A7:
271
        ignore_access("byte write", addr);
272
        return;
273
    default:
274
        error_access("byte write", addr);
275
        assert(0);
276
    }
277
}
278

    
279
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
280
                              uint32_t mem_value)
281
{
282
    SH7750State *s = opaque;
283
    uint16_t temp;
284

    
285
    switch (addr) {
286
        /* SDRAM controller */
287
    case SH7750_BCR2_A7:
288
    case SH7750_BCR3_A7:
289
    case SH7750_RTCOR_A7:
290
    case SH7750_RTCNT_A7:
291
    case SH7750_RTCSR_A7:
292
        ignore_access("word write", addr);
293
        return;
294
        /* IO ports */
295
    case SH7750_PDTRA_A7:
296
        temp = porta_lines(s);
297
        s->pdtra = mem_value;
298
        porta_changed(s, temp);
299
        return;
300
    case SH7750_PDTRB_A7:
301
        temp = portb_lines(s);
302
        s->pdtrb = mem_value;
303
        portb_changed(s, temp);
304
        return;
305
    case SH7750_RFCR_A7:
306
        fprintf(stderr, "Write access to refresh count register\n");
307
        s->rfcr = mem_value;
308
        return;
309
    case SH7750_GPIOIC_A7:
310
        s->gpioic = mem_value;
311
        if (mem_value != 0) {
312
            fprintf(stderr, "I/O interrupts not implemented\n");
313
            assert(0);
314
        }
315
        return;
316
    case 0x1fd00000:
317
        s->icr = mem_value;
318
        return;
319
    default:
320
        error_access("word write", addr);
321
        assert(0);
322
    }
323
}
324

    
325
static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
326
                              uint32_t mem_value)
327
{
328
    SH7750State *s = opaque;
329
    uint16_t temp;
330

    
331
    switch (addr) {
332
        /* SDRAM controller */
333
    case SH7750_BCR1_A7:
334
    case SH7750_BCR4_A7:
335
    case SH7750_WCR1_A7:
336
    case SH7750_WCR2_A7:
337
    case SH7750_WCR3_A7:
338
    case SH7750_MCR_A7:
339
        ignore_access("long write", addr);
340
        return;
341
        /* IO ports */
342
    case SH7750_PCTRA_A7:
343
        temp = porta_lines(s);
344
        s->pctra = mem_value;
345
        s->portdira = portdir(mem_value);
346
        s->portpullupa = portpullup(mem_value);
347
        porta_changed(s, temp);
348
        return;
349
    case SH7750_PCTRB_A7:
350
        temp = portb_lines(s);
351
        s->pctrb = mem_value;
352
        s->portdirb = portdir(mem_value);
353
        s->portpullupb = portpullup(mem_value);
354
        portb_changed(s, temp);
355
        return;
356
    case SH7750_MMUCR_A7:
357
        s->cpu->mmucr = mem_value;
358
        return;
359
    case SH7750_PTEH_A7:
360
        /* If asid changes, clear all registered tlb entries. */
361
        if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
362
            tlb_flush(s->cpu, 1);
363
        s->cpu->pteh = mem_value;
364
        return;
365
    case SH7750_PTEL_A7:
366
        s->cpu->ptel = mem_value;
367
        return;
368
    case SH7750_PTEA_A7:
369
        s->cpu->ptea = mem_value & 0x0000000f;
370
        return;
371
    case SH7750_TTB_A7:
372
        s->cpu->ttb = mem_value;
373
        return;
374
    case SH7750_TEA_A7:
375
        s->cpu->tea = mem_value;
376
        return;
377
    case SH7750_TRA_A7:
378
        s->cpu->tra = mem_value & 0x000007ff;
379
        return;
380
    case SH7750_EXPEVT_A7:
381
        s->cpu->expevt = mem_value & 0x000007ff;
382
        return;
383
    case SH7750_INTEVT_A7:
384
        s->cpu->intevt = mem_value & 0x000007ff;
385
        return;
386
    case SH7750_CCR_A7:
387
        s->ccr = mem_value;
388
        return;
389
    default:
390
        error_access("long write", addr);
391
        assert(0);
392
    }
393
}
394

    
395
static CPUReadMemoryFunc *sh7750_mem_read[] = {
396
    sh7750_mem_readb,
397
    sh7750_mem_readw,
398
    sh7750_mem_readl
399
};
400

    
401
static CPUWriteMemoryFunc *sh7750_mem_write[] = {
402
    sh7750_mem_writeb,
403
    sh7750_mem_writew,
404
    sh7750_mem_writel
405
};
406

    
407
/* sh775x interrupt controller tables for sh_intc.c
408
 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
409
 */
410

    
411
enum {
412
        UNUSED = 0,
413

    
414
        /* interrupt sources */
415
        IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
416
        HUDI, GPIOI,
417
        DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
418
        DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
419
        DMAC_DMAE,
420
        PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
421
        PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
422
        TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
423
        RTC_ATI, RTC_PRI, RTC_CUI,
424
        SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
425
        SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
426
        WDT,
427
        REF_RCMI, REF_ROVI,
428

    
429
        /* interrupt groups */
430
        DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
431

    
432
        NR_SOURCES,
433
};
434

    
435
static struct intc_vect vectors[] = {
436
        INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
437
        INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
438
        INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
439
        INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
440
        INTC_VECT(RTC_CUI, 0x4c0),
441
        INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
442
        INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
443
        INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
444
        INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
445
        INTC_VECT(WDT, 0x560),
446
        INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
447
};
448

    
449
static struct intc_group groups[] = {
450
        INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
451
        INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
452
        INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
453
        INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
454
        INTC_GROUP(REF, REF_RCMI, REF_ROVI),
455
};
456

    
457
static struct intc_prio_reg prio_registers[] = {
458
        { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
459
        { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
460
        { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
461
        { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
462
        { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
463
                                                 TMU4, TMU3,
464
                                                 PCIC1, PCIC0_PCISERR } },
465
};
466

    
467
/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
468

    
469
static struct intc_vect vectors_dma4[] = {
470
        INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
471
        INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
472
        INTC_VECT(DMAC_DMAE, 0x6c0),
473
};
474

    
475
static struct intc_group groups_dma4[] = {
476
        INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
477
                   DMAC_DMTE3, DMAC_DMAE),
478
};
479

    
480
/* SH7750R and SH7751R both have 8-channel DMA controllers */
481

    
482
static struct intc_vect vectors_dma8[] = {
483
        INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
484
        INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
485
        INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
486
        INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
487
        INTC_VECT(DMAC_DMAE, 0x6c0),
488
};
489

    
490
static struct intc_group groups_dma8[] = {
491
        INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
492
                   DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
493
                   DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
494
};
495

    
496
/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
497

    
498
static struct intc_vect vectors_tmu34[] = {
499
        INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
500
};
501

    
502
static struct intc_mask_reg mask_registers[] = {
503
        { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
504
          { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
505
            0, 0, 0, 0, 0, 0, TMU4, TMU3,
506
            PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
507
            PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
508
            PCIC1_PCIDMA3, PCIC0_PCISERR } },
509
};
510

    
511
/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
512

    
513
static struct intc_vect vectors_irlm[] = {
514
        INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
515
        INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
516
};
517

    
518
/* SH7751 and SH7751R both have PCI */
519

    
520
static struct intc_vect vectors_pci[] = {
521
        INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
522
        INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
523
        INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
524
        INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
525
};
526

    
527
static struct intc_group groups_pci[] = {
528
        INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
529
                   PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
530
};
531

    
532
#define SH_CPU_SH7750  (1 << 0)
533
#define SH_CPU_SH7750S (1 << 1)
534
#define SH_CPU_SH7750R (1 << 2)
535
#define SH_CPU_SH7751  (1 << 3)
536
#define SH_CPU_SH7751R (1 << 4)
537
#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
538
#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
539

    
540
/**********************************************************************
541
 Memory mapped cache and TLB
542
**********************************************************************/
543

    
544
#define MM_REGION_MASK   0x07000000
545
#define MM_ICACHE_ADDR   (0)
546
#define MM_ICACHE_DATA   (1)
547
#define MM_ITLB_ADDR     (2)
548
#define MM_ITLB_DATA     (3)
549
#define MM_OCACHE_ADDR   (4)
550
#define MM_OCACHE_DATA   (5)
551
#define MM_UTLB_ADDR     (6)
552
#define MM_UTLB_DATA     (7)
553
#define MM_REGION_TYPE(addr)  ((addr & MM_REGION_MASK) >> 24)
554

    
555
static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
556
{
557
    assert(0);
558

    
559
    return 0;
560
}
561

    
562
static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
563
{
564
    uint32_t ret = 0;
565

    
566
    switch (MM_REGION_TYPE(addr)) {
567
    case MM_ICACHE_ADDR:
568
    case MM_ICACHE_DATA:
569
        /* do nothing */
570
        break;
571
    case MM_ITLB_ADDR:
572
    case MM_ITLB_DATA:
573
        /* XXXXX */
574
        assert(0);
575
        break;
576
    case MM_OCACHE_ADDR:
577
    case MM_OCACHE_DATA:
578
        /* do nothing */
579
        break;
580
    case MM_UTLB_ADDR:
581
    case MM_UTLB_DATA:
582
        /* XXXXX */
583
        assert(0);
584
        break;
585
    default:
586
        assert(0);
587
    }
588

    
589
    return ret;
590
}
591

    
592
static void invalid_write(void *opaque, target_phys_addr_t addr,
593
                          uint32_t mem_value)
594
{
595
    assert(0);
596
}
597

    
598
static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
599
                                uint32_t mem_value)
600
{
601
    SH7750State *s = opaque;
602

    
603
    switch (MM_REGION_TYPE(addr)) {
604
    case MM_ICACHE_ADDR:
605
    case MM_ICACHE_DATA:
606
        /* do nothing */
607
        break;
608
    case MM_ITLB_ADDR:
609
    case MM_ITLB_DATA:
610
        /* XXXXX */
611
        assert(0);
612
        break;
613
    case MM_OCACHE_ADDR:
614
    case MM_OCACHE_DATA:
615
        /* do nothing */
616
        break;
617
    case MM_UTLB_ADDR:
618
        cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value);
619
        break;
620
    case MM_UTLB_DATA:
621
        /* XXXXX */
622
        assert(0);
623
        break;
624
    default:
625
        assert(0);
626
        break;
627
    }
628
}
629

    
630
static CPUReadMemoryFunc *sh7750_mmct_read[] = {
631
    invalid_read,
632
    invalid_read,
633
    sh7750_mmct_readl
634
};
635

    
636
static CPUWriteMemoryFunc *sh7750_mmct_write[] = {
637
    invalid_write,
638
    invalid_write,
639
    sh7750_mmct_writel
640
};
641

    
642
SH7750State *sh7750_init(CPUSH4State * cpu)
643
{
644
    SH7750State *s;
645
    int sh7750_io_memory;
646
    int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
647
    int cpu_model = SH_CPU_SH7751R; /* for now */
648

    
649
    s = qemu_mallocz(sizeof(SH7750State));
650
    s->cpu = cpu;
651
    s->periph_freq = 60000000;        /* 60MHz */
652
    sh7750_io_memory = cpu_register_io_memory(0,
653
                                              sh7750_mem_read,
654
                                              sh7750_mem_write, s);
655
    cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
656

    
657
    sh7750_mm_cache_and_tlb = cpu_register_io_memory(0,
658
                                                     sh7750_mmct_read,
659
                                                     sh7750_mmct_write, s);
660
    cpu_register_physical_memory(0xf0000000, 0x08000000,
661
                                 sh7750_mm_cache_and_tlb);
662

    
663
    sh_intc_init(&s->intc, NR_SOURCES,
664
                 _INTC_ARRAY(mask_registers),
665
                 _INTC_ARRAY(prio_registers));
666

    
667
    sh_intc_register_sources(&s->intc, 
668
                             _INTC_ARRAY(vectors),
669
                             _INTC_ARRAY(groups));
670

    
671
    cpu->intc_handle = &s->intc;
672

    
673
    sh_serial_init(0x1fe00000, 0, s->periph_freq, serial_hds[0],
674
                   sh_intc_source(&s->intc, SCI1_ERI),
675
                   sh_intc_source(&s->intc, SCI1_RXI),
676
                   sh_intc_source(&s->intc, SCI1_TXI),
677
                   sh_intc_source(&s->intc, SCI1_TEI),
678
                   NULL);
679
    sh_serial_init(0x1fe80000, SH_SERIAL_FEAT_SCIF,
680
                   s->periph_freq, serial_hds[1],
681
                   sh_intc_source(&s->intc, SCIF_ERI),
682
                   sh_intc_source(&s->intc, SCIF_RXI),
683
                   sh_intc_source(&s->intc, SCIF_TXI),
684
                   NULL,
685
                   sh_intc_source(&s->intc, SCIF_BRI));
686

    
687
    tmu012_init(0x1fd80000,
688
                TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
689
                s->periph_freq,
690
                sh_intc_source(&s->intc, TMU0),
691
                sh_intc_source(&s->intc, TMU1),
692
                sh_intc_source(&s->intc, TMU2_TUNI),
693
                sh_intc_source(&s->intc, TMU2_TICPI));
694

    
695
    if (cpu_model & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
696
        sh_intc_register_sources(&s->intc, 
697
                                 _INTC_ARRAY(vectors_dma4),
698
                                 _INTC_ARRAY(groups_dma4));
699
    }
700

    
701
    if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
702
        sh_intc_register_sources(&s->intc, 
703
                                 _INTC_ARRAY(vectors_dma8),
704
                                 _INTC_ARRAY(groups_dma8));
705
    }
706

    
707
    if (cpu_model & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
708
        sh_intc_register_sources(&s->intc, 
709
                                 _INTC_ARRAY(vectors_tmu34),
710
                                 NULL, 0);
711
        tmu012_init(0x1e100000, 0, s->periph_freq,
712
                    sh_intc_source(&s->intc, TMU3),
713
                    sh_intc_source(&s->intc, TMU4),
714
                    NULL, NULL);
715
    }
716

    
717
    if (cpu_model & (SH_CPU_SH7751_ALL)) {
718
        sh_intc_register_sources(&s->intc, 
719
                                 _INTC_ARRAY(vectors_pci),
720
                                 _INTC_ARRAY(groups_pci));
721
    }
722

    
723
    if (cpu_model & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
724
        sh_intc_register_sources(&s->intc, 
725
                                 _INTC_ARRAY(vectors_irlm),
726
                                 NULL, 0);
727
    }
728

    
729
    return s;
730
}