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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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int gen_new_label(void);
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static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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}
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static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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}
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static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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}
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static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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}
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static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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}
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static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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}
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static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
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                                    TCGv_i32 arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
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                                    TCGv_i64 arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
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                                       TCGv_ptr base, TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
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                                       TCGv_ptr base, TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
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                                                TCGv_i32 addr, TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I32(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
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                                                TCGv_i64 addr, TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I64(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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}
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static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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}
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static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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}
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static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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}
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static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
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                                     TCGv_i32 arg2, TCGv_i32 arg3,
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                                     TCGArg arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = arg4;
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
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                                     TCGv_i64 arg2, TCGv_i64 arg3,
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                                     TCGArg arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = arg4;
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
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                                   TCGv_i32 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
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}
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static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
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                                   TCGv_i64 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
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}
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static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4,
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                                    TCGv_i32 arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = arg6;
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}
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320 a9751609 Richard Henderson
static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
321 be210acb Richard Henderson
                                    TCGv_i64 arg3, TCGv_i64 arg4,
322 be210acb Richard Henderson
                                    TCGv_i64 arg5, TCGArg arg6)
323 be210acb Richard Henderson
{
324 be210acb Richard Henderson
    *gen_opc_ptr++ = opc;
325 be210acb Richard Henderson
    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
326 be210acb Richard Henderson
    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
327 be210acb Richard Henderson
    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
328 be210acb Richard Henderson
    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
329 be210acb Richard Henderson
    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
330 be210acb Richard Henderson
    *gen_opparam_ptr++ = arg6;
331 be210acb Richard Henderson
}
332 be210acb Richard Henderson
333 a9751609 Richard Henderson
static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
334 a9751609 Richard Henderson
                                     TCGv_i32 arg2, TCGv_i32 arg3,
335 a9751609 Richard Henderson
                                     TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
336 ac56dd48 pbrook
{
337 ac56dd48 pbrook
    *gen_opc_ptr++ = opc;
338 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
339 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
340 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
341 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
342 a7812ae4 pbrook
    *gen_opparam_ptr++ = arg5;
343 a7812ae4 pbrook
    *gen_opparam_ptr++ = arg6;
344 a7812ae4 pbrook
}
345 a7812ae4 pbrook
346 a9751609 Richard Henderson
static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
347 a9751609 Richard Henderson
                                     TCGv_i64 arg2, TCGv_i64 arg3,
348 a9751609 Richard Henderson
                                     TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
349 a7812ae4 pbrook
{
350 a7812ae4 pbrook
    *gen_opc_ptr++ = opc;
351 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
352 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
353 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
354 a7812ae4 pbrook
    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
355 c896fe29 bellard
    *gen_opparam_ptr++ = arg5;
356 c896fe29 bellard
    *gen_opparam_ptr++ = arg6;
357 c896fe29 bellard
}
358 c896fe29 bellard
359 c896fe29 bellard
static inline void gen_set_label(int n)
360 c896fe29 bellard
{
361 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_set_label, n);
362 c896fe29 bellard
}
363 c896fe29 bellard
364 fb50d413 blueswir1
static inline void tcg_gen_br(int label)
365 fb50d413 blueswir1
{
366 fb50d413 blueswir1
    tcg_gen_op1i(INDEX_op_br, label);
367 fb50d413 blueswir1
}
368 fb50d413 blueswir1
369 a7812ae4 pbrook
static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
370 c896fe29 bellard
{
371 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I32(ret, arg))
372 a7812ae4 pbrook
        tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
373 c896fe29 bellard
}
374 c896fe29 bellard
375 a7812ae4 pbrook
static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
376 c896fe29 bellard
{
377 a7812ae4 pbrook
    tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
378 c896fe29 bellard
}
379 c896fe29 bellard
380 2bece2c8 Richard Henderson
/* A version of dh_sizemask from def-helper.h that doesn't rely on
381 2bece2c8 Richard Henderson
   preprocessor magic.  */
382 2bece2c8 Richard Henderson
static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed)
383 2bece2c8 Richard Henderson
{
384 2bece2c8 Richard Henderson
    return (is_64bit << n*2) | (is_signed << (n*2 + 1));
385 2bece2c8 Richard Henderson
}
386 2bece2c8 Richard Henderson
387 c896fe29 bellard
/* helper calls */
388 a7812ae4 pbrook
static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
389 a7812ae4 pbrook
                                   TCGArg ret, int nargs, TCGArg *args)
390 a7812ae4 pbrook
{
391 a7812ae4 pbrook
    TCGv_ptr fn;
392 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
393 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
394 a7812ae4 pbrook
                  nargs, args);
395 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
396 a7812ae4 pbrook
}
397 c896fe29 bellard
398 dbfff4de Aurelien Jarno
/* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
399 dbfff4de Aurelien Jarno
   reserved for helpers in tcg-runtime.c. These helpers are all const
400 dbfff4de Aurelien Jarno
   and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
401 dbfff4de Aurelien Jarno
   TCG_CALL_PURE. This may need to be adjusted if these functions
402 dbfff4de Aurelien Jarno
   start to be used with other helpers. */
403 2bece2c8 Richard Henderson
static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret,
404 31d66551 Aurelien Jarno
                                    TCGv_i32 a, TCGv_i32 b)
405 31d66551 Aurelien Jarno
{
406 31d66551 Aurelien Jarno
    TCGv_ptr fn;
407 31d66551 Aurelien Jarno
    TCGArg args[2];
408 31d66551 Aurelien Jarno
    fn = tcg_const_ptr((tcg_target_long)func);
409 31d66551 Aurelien Jarno
    args[0] = GET_TCGV_I32(a);
410 31d66551 Aurelien Jarno
    args[1] = GET_TCGV_I32(b);
411 2bece2c8 Richard Henderson
    tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
412 2bece2c8 Richard Henderson
                  GET_TCGV_I32(ret), 2, args);
413 31d66551 Aurelien Jarno
    tcg_temp_free_ptr(fn);
414 31d66551 Aurelien Jarno
}
415 31d66551 Aurelien Jarno
416 2bece2c8 Richard Henderson
static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret,
417 a7812ae4 pbrook
                                    TCGv_i64 a, TCGv_i64 b)
418 c896fe29 bellard
{
419 a7812ae4 pbrook
    TCGv_ptr fn;
420 a7812ae4 pbrook
    TCGArg args[2];
421 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
422 a7812ae4 pbrook
    args[0] = GET_TCGV_I64(a);
423 a7812ae4 pbrook
    args[1] = GET_TCGV_I64(b);
424 2bece2c8 Richard Henderson
    tcg_gen_callN(&tcg_ctx, fn, TCG_CALL_CONST | TCG_CALL_PURE, sizemask,
425 2bece2c8 Richard Henderson
                  GET_TCGV_I64(ret), 2, args);
426 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
427 f8422f52 blueswir1
}
428 f8422f52 blueswir1
429 c896fe29 bellard
/* 32 bit ops */
430 c896fe29 bellard
431 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
432 c896fe29 bellard
{
433 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
434 c896fe29 bellard
}
435 c896fe29 bellard
436 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
437 c896fe29 bellard
{
438 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
439 c896fe29 bellard
}
440 c896fe29 bellard
441 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
442 c896fe29 bellard
{
443 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
444 c896fe29 bellard
}
445 c896fe29 bellard
446 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
447 c896fe29 bellard
{
448 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
449 c896fe29 bellard
}
450 c896fe29 bellard
451 a7812ae4 pbrook
static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
452 c896fe29 bellard
{
453 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
454 c896fe29 bellard
}
455 c896fe29 bellard
456 a7812ae4 pbrook
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
457 c896fe29 bellard
{
458 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
459 c896fe29 bellard
}
460 c896fe29 bellard
461 a7812ae4 pbrook
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
462 c896fe29 bellard
{
463 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
464 c896fe29 bellard
}
465 c896fe29 bellard
466 a7812ae4 pbrook
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
467 c896fe29 bellard
{
468 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
469 c896fe29 bellard
}
470 c896fe29 bellard
471 a7812ae4 pbrook
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
472 c896fe29 bellard
{
473 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
474 c896fe29 bellard
}
475 c896fe29 bellard
476 a7812ae4 pbrook
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
477 c896fe29 bellard
{
478 7089442c blueswir1
    /* some cases can be optimized here */
479 7089442c blueswir1
    if (arg2 == 0) {
480 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
481 7089442c blueswir1
    } else {
482 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
483 e8996ee0 bellard
        tcg_gen_add_i32(ret, arg1, t0);
484 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
485 7089442c blueswir1
    }
486 c896fe29 bellard
}
487 c896fe29 bellard
488 a7812ae4 pbrook
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
489 c896fe29 bellard
{
490 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
491 c896fe29 bellard
}
492 c896fe29 bellard
493 a7812ae4 pbrook
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
494 0045734a aurel32
{
495 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg1);
496 0045734a aurel32
    tcg_gen_sub_i32(ret, t0, arg2);
497 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
498 0045734a aurel32
}
499 0045734a aurel32
500 a7812ae4 pbrook
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
501 c896fe29 bellard
{
502 7089442c blueswir1
    /* some cases can be optimized here */
503 7089442c blueswir1
    if (arg2 == 0) {
504 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
505 7089442c blueswir1
    } else {
506 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
507 e8996ee0 bellard
        tcg_gen_sub_i32(ret, arg1, t0);
508 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
509 7089442c blueswir1
    }
510 c896fe29 bellard
}
511 c896fe29 bellard
512 a7812ae4 pbrook
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
513 c896fe29 bellard
{
514 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
515 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
516 7fc81051 aurel32
    } else {
517 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
518 7fc81051 aurel32
    }
519 c896fe29 bellard
}
520 c896fe29 bellard
521 a7812ae4 pbrook
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
522 c896fe29 bellard
{
523 c896fe29 bellard
    /* some cases can be optimized here */
524 c896fe29 bellard
    if (arg2 == 0) {
525 c896fe29 bellard
        tcg_gen_movi_i32(ret, 0);
526 c896fe29 bellard
    } else if (arg2 == 0xffffffff) {
527 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
528 c896fe29 bellard
    } else {
529 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
530 e8996ee0 bellard
        tcg_gen_and_i32(ret, arg1, t0);
531 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
532 c896fe29 bellard
    }
533 c896fe29 bellard
}
534 c896fe29 bellard
535 a7812ae4 pbrook
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
536 c896fe29 bellard
{
537 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
538 7fc81051 aurel32
        tcg_gen_mov_i32(ret, arg1);
539 7fc81051 aurel32
    } else {
540 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
541 7fc81051 aurel32
    }
542 c896fe29 bellard
}
543 c896fe29 bellard
544 a7812ae4 pbrook
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
545 c896fe29 bellard
{
546 c896fe29 bellard
    /* some cases can be optimized here */
547 c896fe29 bellard
    if (arg2 == 0xffffffff) {
548 7089442c blueswir1
        tcg_gen_movi_i32(ret, 0xffffffff);
549 c896fe29 bellard
    } else if (arg2 == 0) {
550 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
551 c896fe29 bellard
    } else {
552 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
553 e8996ee0 bellard
        tcg_gen_or_i32(ret, arg1, t0);
554 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
555 c896fe29 bellard
    }
556 c896fe29 bellard
}
557 c896fe29 bellard
558 a7812ae4 pbrook
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
559 c896fe29 bellard
{
560 7fc81051 aurel32
    if (TCGV_EQUAL_I32(arg1, arg2)) {
561 7fc81051 aurel32
        tcg_gen_movi_i32(ret, 0);
562 7fc81051 aurel32
    } else {
563 7fc81051 aurel32
        tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
564 7fc81051 aurel32
    }
565 c896fe29 bellard
}
566 c896fe29 bellard
567 a7812ae4 pbrook
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
568 c896fe29 bellard
{
569 c896fe29 bellard
    /* some cases can be optimized here */
570 c896fe29 bellard
    if (arg2 == 0) {
571 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
572 c896fe29 bellard
    } else {
573 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
574 e8996ee0 bellard
        tcg_gen_xor_i32(ret, arg1, t0);
575 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
576 c896fe29 bellard
    }
577 c896fe29 bellard
}
578 c896fe29 bellard
579 a7812ae4 pbrook
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
580 c896fe29 bellard
{
581 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
582 c896fe29 bellard
}
583 c896fe29 bellard
584 a7812ae4 pbrook
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
585 c896fe29 bellard
{
586 34151a20 bellard
    if (arg2 == 0) {
587 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
588 34151a20 bellard
    } else {
589 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
590 e8996ee0 bellard
        tcg_gen_shl_i32(ret, arg1, t0);
591 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
592 34151a20 bellard
    }
593 c896fe29 bellard
}
594 c896fe29 bellard
595 a7812ae4 pbrook
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
596 c896fe29 bellard
{
597 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
598 c896fe29 bellard
}
599 c896fe29 bellard
600 a7812ae4 pbrook
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
601 c896fe29 bellard
{
602 34151a20 bellard
    if (arg2 == 0) {
603 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
604 34151a20 bellard
    } else {
605 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
606 e8996ee0 bellard
        tcg_gen_shr_i32(ret, arg1, t0);
607 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
608 34151a20 bellard
    }
609 c896fe29 bellard
}
610 c896fe29 bellard
611 a7812ae4 pbrook
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
612 c896fe29 bellard
{
613 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
614 c896fe29 bellard
}
615 c896fe29 bellard
616 a7812ae4 pbrook
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
617 c896fe29 bellard
{
618 34151a20 bellard
    if (arg2 == 0) {
619 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
620 34151a20 bellard
    } else {
621 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
622 e8996ee0 bellard
        tcg_gen_sar_i32(ret, arg1, t0);
623 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
624 34151a20 bellard
    }
625 c896fe29 bellard
}
626 c896fe29 bellard
627 8a56e840 Richard Henderson
static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
628 8a56e840 Richard Henderson
                                      TCGv_i32 arg2, int label_index)
629 c896fe29 bellard
{
630 a7812ae4 pbrook
    tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
631 c896fe29 bellard
}
632 c896fe29 bellard
633 8a56e840 Richard Henderson
static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
634 8a56e840 Richard Henderson
                                       int32_t arg2, int label_index)
635 cb63669a pbrook
{
636 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
637 cb63669a pbrook
    tcg_gen_brcond_i32(cond, arg1, t0, label_index);
638 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
639 cb63669a pbrook
}
640 cb63669a pbrook
641 8a56e840 Richard Henderson
static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
642 5105c556 Aurelien Jarno
                                       TCGv_i32 arg1, TCGv_i32 arg2)
643 5105c556 Aurelien Jarno
{
644 5105c556 Aurelien Jarno
    tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
645 5105c556 Aurelien Jarno
}
646 5105c556 Aurelien Jarno
647 8a56e840 Richard Henderson
static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
648 8a56e840 Richard Henderson
                                        TCGv_i32 arg1, int32_t arg2)
649 5105c556 Aurelien Jarno
{
650 5105c556 Aurelien Jarno
    TCGv_i32 t0 = tcg_const_i32(arg2);
651 5105c556 Aurelien Jarno
    tcg_gen_setcond_i32(cond, ret, arg1, t0);
652 5105c556 Aurelien Jarno
    tcg_temp_free_i32(t0);
653 5105c556 Aurelien Jarno
}
654 5105c556 Aurelien Jarno
655 a7812ae4 pbrook
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
656 c896fe29 bellard
{
657 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
658 c896fe29 bellard
}
659 c896fe29 bellard
660 a7812ae4 pbrook
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
661 f730fd27 ths
{
662 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
663 e8996ee0 bellard
    tcg_gen_mul_i32(ret, arg1, t0);
664 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
665 f730fd27 ths
}
666 f730fd27 ths
667 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i32
668 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
669 c896fe29 bellard
{
670 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
671 c896fe29 bellard
}
672 c896fe29 bellard
673 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
674 c896fe29 bellard
{
675 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
676 c896fe29 bellard
}
677 c896fe29 bellard
678 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
679 c896fe29 bellard
{
680 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
681 c896fe29 bellard
}
682 c896fe29 bellard
683 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
684 c896fe29 bellard
{
685 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
686 c896fe29 bellard
}
687 31d66551 Aurelien Jarno
#elif defined(TCG_TARGET_HAS_div2_i32)
688 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
689 c896fe29 bellard
{
690 a7812ae4 pbrook
    TCGv_i32 t0;
691 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
692 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
693 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
694 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
695 c896fe29 bellard
}
696 c896fe29 bellard
697 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
698 c896fe29 bellard
{
699 a7812ae4 pbrook
    TCGv_i32 t0;
700 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
701 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
702 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
703 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
704 c896fe29 bellard
}
705 c896fe29 bellard
706 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
707 c896fe29 bellard
{
708 a7812ae4 pbrook
    TCGv_i32 t0;
709 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
710 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
711 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
712 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
713 c896fe29 bellard
}
714 c896fe29 bellard
715 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
716 c896fe29 bellard
{
717 a7812ae4 pbrook
    TCGv_i32 t0;
718 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
719 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
720 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
721 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
722 c896fe29 bellard
}
723 31d66551 Aurelien Jarno
#else
724 31d66551 Aurelien Jarno
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
725 31d66551 Aurelien Jarno
{
726 2bece2c8 Richard Henderson
    int sizemask = 0;
727 2bece2c8 Richard Henderson
    /* Return value and both arguments are 32-bit and signed.  */
728 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 0, 1);
729 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 0, 1);
730 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 0, 1);
731 2bece2c8 Richard Henderson
732 2bece2c8 Richard Henderson
    tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2);
733 31d66551 Aurelien Jarno
}
734 31d66551 Aurelien Jarno
735 31d66551 Aurelien Jarno
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
736 31d66551 Aurelien Jarno
{
737 2bece2c8 Richard Henderson
    int sizemask = 0;
738 2bece2c8 Richard Henderson
    /* Return value and both arguments are 32-bit and signed.  */
739 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 0, 1);
740 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 0, 1);
741 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 0, 1);
742 2bece2c8 Richard Henderson
743 2bece2c8 Richard Henderson
    tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2);
744 31d66551 Aurelien Jarno
}
745 31d66551 Aurelien Jarno
746 31d66551 Aurelien Jarno
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
747 31d66551 Aurelien Jarno
{
748 2bece2c8 Richard Henderson
    int sizemask = 0;
749 2bece2c8 Richard Henderson
    /* Return value and both arguments are 32-bit and unsigned.  */
750 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 0, 0);
751 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 0, 0);
752 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 0, 0);
753 2bece2c8 Richard Henderson
754 0909cbde Richard Henderson
    tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2);
755 31d66551 Aurelien Jarno
}
756 31d66551 Aurelien Jarno
757 31d66551 Aurelien Jarno
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
758 31d66551 Aurelien Jarno
{
759 2bece2c8 Richard Henderson
    int sizemask = 0;
760 2bece2c8 Richard Henderson
    /* Return value and both arguments are 32-bit and unsigned.  */
761 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 0, 0);
762 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 0, 0);
763 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 0, 0);
764 2bece2c8 Richard Henderson
765 0909cbde Richard Henderson
    tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2);
766 31d66551 Aurelien Jarno
}
767 c896fe29 bellard
#endif
768 c896fe29 bellard
769 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
770 c896fe29 bellard
771 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
772 c896fe29 bellard
{
773 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg)) {
774 a7812ae4 pbrook
        tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
775 4d07272d blueswir1
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
776 4d07272d blueswir1
    }
777 c896fe29 bellard
}
778 c896fe29 bellard
779 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
780 c896fe29 bellard
{
781 a7812ae4 pbrook
    tcg_gen_movi_i32(TCGV_LOW(ret), arg);
782 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
783 c896fe29 bellard
}
784 c896fe29 bellard
785 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
786 a7812ae4 pbrook
                                    tcg_target_long offset)
787 c896fe29 bellard
{
788 a7812ae4 pbrook
    tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
789 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
790 c896fe29 bellard
}
791 c896fe29 bellard
792 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
793 a7812ae4 pbrook
                                    tcg_target_long offset)
794 c896fe29 bellard
{
795 a7812ae4 pbrook
    tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
796 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
797 c896fe29 bellard
}
798 c896fe29 bellard
799 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
800 a7812ae4 pbrook
                                     tcg_target_long offset)
801 c896fe29 bellard
{
802 a747723b aurel32
    tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
803 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
804 c896fe29 bellard
}
805 c896fe29 bellard
806 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
807 a7812ae4 pbrook
                                     tcg_target_long offset)
808 c896fe29 bellard
{
809 a7812ae4 pbrook
    tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
810 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
811 c896fe29 bellard
}
812 c896fe29 bellard
813 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
814 a7812ae4 pbrook
                                     tcg_target_long offset)
815 c896fe29 bellard
{
816 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
817 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
818 c896fe29 bellard
}
819 c896fe29 bellard
820 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
821 a7812ae4 pbrook
                                     tcg_target_long offset)
822 c896fe29 bellard
{
823 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
824 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
825 c896fe29 bellard
}
826 c896fe29 bellard
827 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
828 a7812ae4 pbrook
                                  tcg_target_long offset)
829 c896fe29 bellard
{
830 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
831 c896fe29 bellard
       same temporary */
832 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
833 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
834 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
835 c896fe29 bellard
#else
836 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
837 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
838 c896fe29 bellard
#endif
839 c896fe29 bellard
}
840 c896fe29 bellard
841 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
842 a7812ae4 pbrook
                                   tcg_target_long offset)
843 c896fe29 bellard
{
844 a7812ae4 pbrook
    tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
845 c896fe29 bellard
}
846 c896fe29 bellard
847 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
848 a7812ae4 pbrook
                                    tcg_target_long offset)
849 c896fe29 bellard
{
850 a7812ae4 pbrook
    tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
851 c896fe29 bellard
}
852 c896fe29 bellard
853 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
854 a7812ae4 pbrook
                                    tcg_target_long offset)
855 c896fe29 bellard
{
856 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
857 c896fe29 bellard
}
858 c896fe29 bellard
859 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
860 a7812ae4 pbrook
                                  tcg_target_long offset)
861 c896fe29 bellard
{
862 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
863 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
864 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
865 c896fe29 bellard
#else
866 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
867 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
868 c896fe29 bellard
#endif
869 c896fe29 bellard
}
870 c896fe29 bellard
871 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
872 c896fe29 bellard
{
873 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
874 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
875 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
876 c896fe29 bellard
}
877 c896fe29 bellard
878 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
879 c896fe29 bellard
{
880 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
881 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
882 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
883 c896fe29 bellard
}
884 c896fe29 bellard
885 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
886 c896fe29 bellard
{
887 a7812ae4 pbrook
    tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
888 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
889 c896fe29 bellard
}
890 c896fe29 bellard
891 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
892 c896fe29 bellard
{
893 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
894 e5105083 aurel32
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
895 c896fe29 bellard
}
896 c896fe29 bellard
897 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
898 c896fe29 bellard
{
899 e5105083 aurel32
    tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
900 e5105083 aurel32
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
901 c896fe29 bellard
}
902 c896fe29 bellard
903 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
904 c896fe29 bellard
{
905 a7812ae4 pbrook
    tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
906 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
907 c896fe29 bellard
}
908 c896fe29 bellard
909 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
910 c896fe29 bellard
{
911 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
912 e5105083 aurel32
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
913 c896fe29 bellard
}
914 c896fe29 bellard
915 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
916 c896fe29 bellard
{
917 a7812ae4 pbrook
    tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
918 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
919 c896fe29 bellard
}
920 c896fe29 bellard
921 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
922 c896fe29 bellard
   specific code (x86) */
923 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
924 c896fe29 bellard
{
925 2bece2c8 Richard Henderson
    int sizemask = 0;
926 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
927 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
928 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
929 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
930 2bece2c8 Richard Henderson
931 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2);
932 c896fe29 bellard
}
933 c896fe29 bellard
934 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
935 c896fe29 bellard
{
936 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
937 c896fe29 bellard
}
938 c896fe29 bellard
939 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
940 c896fe29 bellard
{
941 2bece2c8 Richard Henderson
    int sizemask = 0;
942 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
943 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
944 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
945 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
946 2bece2c8 Richard Henderson
947 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2);
948 c896fe29 bellard
}
949 c896fe29 bellard
950 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
951 c896fe29 bellard
{
952 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
953 c896fe29 bellard
}
954 c896fe29 bellard
955 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
956 c896fe29 bellard
{
957 2bece2c8 Richard Henderson
    int sizemask = 0;
958 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
959 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
960 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
961 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
962 2bece2c8 Richard Henderson
963 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2);
964 c896fe29 bellard
}
965 c896fe29 bellard
966 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
967 c896fe29 bellard
{
968 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
969 c896fe29 bellard
}
970 c896fe29 bellard
971 8a56e840 Richard Henderson
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
972 8a56e840 Richard Henderson
                                      TCGv_i64 arg2, int label_index)
973 c896fe29 bellard
{
974 a7812ae4 pbrook
    tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
975 a7812ae4 pbrook
                      TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
976 a7812ae4 pbrook
                      TCGV_HIGH(arg2), cond, label_index);
977 c896fe29 bellard
}
978 c896fe29 bellard
979 8a56e840 Richard Henderson
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
980 5105c556 Aurelien Jarno
                                       TCGv_i64 arg1, TCGv_i64 arg2)
981 5105c556 Aurelien Jarno
{
982 5105c556 Aurelien Jarno
    tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
983 5105c556 Aurelien Jarno
                     TCGV_LOW(arg1), TCGV_HIGH(arg1),
984 5105c556 Aurelien Jarno
                     TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
985 5105c556 Aurelien Jarno
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
986 5105c556 Aurelien Jarno
}
987 5105c556 Aurelien Jarno
988 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
989 c896fe29 bellard
{
990 a7812ae4 pbrook
    TCGv_i64 t0;
991 a7812ae4 pbrook
    TCGv_i32 t1;
992 c896fe29 bellard
993 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
994 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
995 a7812ae4 pbrook
996 a7812ae4 pbrook
    tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
997 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_LOW(arg2));
998 a7812ae4 pbrook
999 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
1000 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1001 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
1002 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1003 a7812ae4 pbrook
1004 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
1005 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1006 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1007 c896fe29 bellard
}
1008 c896fe29 bellard
1009 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1010 c896fe29 bellard
{
1011 2bece2c8 Richard Henderson
    int sizemask = 0;
1012 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
1013 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
1014 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
1015 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
1016 2bece2c8 Richard Henderson
1017 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1018 c896fe29 bellard
}
1019 c896fe29 bellard
1020 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1021 c896fe29 bellard
{
1022 2bece2c8 Richard Henderson
    int sizemask = 0;
1023 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
1024 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
1025 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
1026 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
1027 2bece2c8 Richard Henderson
1028 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1029 c896fe29 bellard
}
1030 c896fe29 bellard
1031 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1032 c896fe29 bellard
{
1033 2bece2c8 Richard Henderson
    int sizemask = 0;
1034 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and unsigned.  */
1035 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 0);
1036 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 0);
1037 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 0);
1038 2bece2c8 Richard Henderson
1039 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1040 c896fe29 bellard
}
1041 c896fe29 bellard
1042 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1043 c896fe29 bellard
{
1044 2bece2c8 Richard Henderson
    int sizemask = 0;
1045 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and unsigned.  */
1046 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 0);
1047 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 0);
1048 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 0);
1049 2bece2c8 Richard Henderson
1050 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1051 c896fe29 bellard
}
1052 c896fe29 bellard
1053 c896fe29 bellard
#else
1054 c896fe29 bellard
1055 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
1056 c896fe29 bellard
{
1057 fe75bcf7 aurel32
    if (!TCGV_EQUAL_I64(ret, arg))
1058 a7812ae4 pbrook
        tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
1059 c896fe29 bellard
}
1060 c896fe29 bellard
1061 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
1062 c896fe29 bellard
{
1063 a7812ae4 pbrook
    tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
1064 c896fe29 bellard
}
1065 c896fe29 bellard
1066 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
1067 ac56dd48 pbrook
                                    tcg_target_long offset)
1068 c896fe29 bellard
{
1069 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
1070 c896fe29 bellard
}
1071 c896fe29 bellard
1072 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
1073 ac56dd48 pbrook
                                    tcg_target_long offset)
1074 c896fe29 bellard
{
1075 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
1076 c896fe29 bellard
}
1077 c896fe29 bellard
1078 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
1079 ac56dd48 pbrook
                                     tcg_target_long offset)
1080 c896fe29 bellard
{
1081 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
1082 c896fe29 bellard
}
1083 c896fe29 bellard
1084 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
1085 ac56dd48 pbrook
                                     tcg_target_long offset)
1086 c896fe29 bellard
{
1087 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
1088 c896fe29 bellard
}
1089 c896fe29 bellard
1090 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
1091 ac56dd48 pbrook
                                     tcg_target_long offset)
1092 c896fe29 bellard
{
1093 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
1094 c896fe29 bellard
}
1095 c896fe29 bellard
1096 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
1097 ac56dd48 pbrook
                                     tcg_target_long offset)
1098 c896fe29 bellard
{
1099 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
1100 c896fe29 bellard
}
1101 c896fe29 bellard
1102 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
1103 c896fe29 bellard
{
1104 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
1105 c896fe29 bellard
}
1106 c896fe29 bellard
1107 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
1108 ac56dd48 pbrook
                                   tcg_target_long offset)
1109 c896fe29 bellard
{
1110 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
1111 c896fe29 bellard
}
1112 c896fe29 bellard
1113 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
1114 ac56dd48 pbrook
                                    tcg_target_long offset)
1115 c896fe29 bellard
{
1116 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
1117 c896fe29 bellard
}
1118 c896fe29 bellard
1119 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
1120 ac56dd48 pbrook
                                    tcg_target_long offset)
1121 c896fe29 bellard
{
1122 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
1123 c896fe29 bellard
}
1124 c896fe29 bellard
1125 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
1126 c896fe29 bellard
{
1127 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
1128 c896fe29 bellard
}
1129 c896fe29 bellard
1130 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1131 c896fe29 bellard
{
1132 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
1133 c896fe29 bellard
}
1134 c896fe29 bellard
1135 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1136 c896fe29 bellard
{
1137 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
1138 c896fe29 bellard
}
1139 c896fe29 bellard
1140 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1141 c896fe29 bellard
{
1142 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1143 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
1144 7fc81051 aurel32
    } else {
1145 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1146 7fc81051 aurel32
    }
1147 c896fe29 bellard
}
1148 c896fe29 bellard
1149 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1150 c896fe29 bellard
{
1151 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1152 e8996ee0 bellard
    tcg_gen_and_i64(ret, arg1, t0);
1153 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1154 c896fe29 bellard
}
1155 c896fe29 bellard
1156 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1157 c896fe29 bellard
{
1158 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1159 7fc81051 aurel32
        tcg_gen_mov_i64(ret, arg1);
1160 7fc81051 aurel32
    } else {
1161 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1162 7fc81051 aurel32
    }
1163 c896fe29 bellard
}
1164 c896fe29 bellard
1165 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1166 c896fe29 bellard
{
1167 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1168 e8996ee0 bellard
    tcg_gen_or_i64(ret, arg1, t0);
1169 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1170 c896fe29 bellard
}
1171 c896fe29 bellard
1172 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1173 c896fe29 bellard
{
1174 7fc81051 aurel32
    if (TCGV_EQUAL_I64(arg1, arg2)) {
1175 7fc81051 aurel32
        tcg_gen_movi_i64(ret, 0);
1176 7fc81051 aurel32
    } else {
1177 7fc81051 aurel32
        tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1178 7fc81051 aurel32
    }
1179 c896fe29 bellard
}
1180 c896fe29 bellard
1181 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1182 c896fe29 bellard
{
1183 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1184 e8996ee0 bellard
    tcg_gen_xor_i64(ret, arg1, t0);
1185 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1186 c896fe29 bellard
}
1187 c896fe29 bellard
1188 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1189 c896fe29 bellard
{
1190 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1191 c896fe29 bellard
}
1192 c896fe29 bellard
1193 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1194 c896fe29 bellard
{
1195 34151a20 bellard
    if (arg2 == 0) {
1196 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1197 34151a20 bellard
    } else {
1198 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1199 e8996ee0 bellard
        tcg_gen_shl_i64(ret, arg1, t0);
1200 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1201 34151a20 bellard
    }
1202 c896fe29 bellard
}
1203 c896fe29 bellard
1204 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1205 c896fe29 bellard
{
1206 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1207 c896fe29 bellard
}
1208 c896fe29 bellard
1209 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1210 c896fe29 bellard
{
1211 34151a20 bellard
    if (arg2 == 0) {
1212 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1213 34151a20 bellard
    } else {
1214 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1215 e8996ee0 bellard
        tcg_gen_shr_i64(ret, arg1, t0);
1216 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1217 34151a20 bellard
    }
1218 c896fe29 bellard
}
1219 c896fe29 bellard
1220 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1221 c896fe29 bellard
{
1222 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1223 c896fe29 bellard
}
1224 c896fe29 bellard
1225 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1226 c896fe29 bellard
{
1227 34151a20 bellard
    if (arg2 == 0) {
1228 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1229 34151a20 bellard
    } else {
1230 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1231 e8996ee0 bellard
        tcg_gen_sar_i64(ret, arg1, t0);
1232 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1233 34151a20 bellard
    }
1234 c896fe29 bellard
}
1235 c896fe29 bellard
1236 8a56e840 Richard Henderson
static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1237 8a56e840 Richard Henderson
                                      TCGv_i64 arg2, int label_index)
1238 c896fe29 bellard
{
1239 a7812ae4 pbrook
    tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1240 c896fe29 bellard
}
1241 c896fe29 bellard
1242 8a56e840 Richard Henderson
static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
1243 5105c556 Aurelien Jarno
                                       TCGv_i64 arg1, TCGv_i64 arg2)
1244 5105c556 Aurelien Jarno
{
1245 5105c556 Aurelien Jarno
    tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1246 5105c556 Aurelien Jarno
}
1247 5105c556 Aurelien Jarno
1248 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1249 c896fe29 bellard
{
1250 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1251 c896fe29 bellard
}
1252 c896fe29 bellard
1253 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
1254 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1255 c896fe29 bellard
{
1256 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1257 c896fe29 bellard
}
1258 c896fe29 bellard
1259 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1260 c896fe29 bellard
{
1261 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1262 c896fe29 bellard
}
1263 c896fe29 bellard
1264 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1265 c896fe29 bellard
{
1266 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1267 c896fe29 bellard
}
1268 c896fe29 bellard
1269 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1270 c896fe29 bellard
{
1271 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1272 c896fe29 bellard
}
1273 31d66551 Aurelien Jarno
#elif defined(TCG_TARGET_HAS_div2_i64)
1274 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1275 c896fe29 bellard
{
1276 a7812ae4 pbrook
    TCGv_i64 t0;
1277 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1278 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1279 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1280 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1281 c896fe29 bellard
}
1282 c896fe29 bellard
1283 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1284 c896fe29 bellard
{
1285 a7812ae4 pbrook
    TCGv_i64 t0;
1286 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1287 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1288 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1289 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1290 c896fe29 bellard
}
1291 c896fe29 bellard
1292 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1293 c896fe29 bellard
{
1294 a7812ae4 pbrook
    TCGv_i64 t0;
1295 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1296 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1297 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1298 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1299 c896fe29 bellard
}
1300 c896fe29 bellard
1301 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1302 c896fe29 bellard
{
1303 a7812ae4 pbrook
    TCGv_i64 t0;
1304 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1305 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1306 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1307 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1308 c896fe29 bellard
}
1309 31d66551 Aurelien Jarno
#else
1310 31d66551 Aurelien Jarno
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1311 31d66551 Aurelien Jarno
{
1312 2bece2c8 Richard Henderson
    int sizemask = 0;
1313 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
1314 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
1315 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
1316 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
1317 2bece2c8 Richard Henderson
1318 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1319 31d66551 Aurelien Jarno
}
1320 31d66551 Aurelien Jarno
1321 31d66551 Aurelien Jarno
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1322 31d66551 Aurelien Jarno
{
1323 2bece2c8 Richard Henderson
    int sizemask = 0;
1324 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and signed.  */
1325 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 1);
1326 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 1);
1327 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 1);
1328 2bece2c8 Richard Henderson
1329 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1330 31d66551 Aurelien Jarno
}
1331 31d66551 Aurelien Jarno
1332 31d66551 Aurelien Jarno
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1333 31d66551 Aurelien Jarno
{
1334 2bece2c8 Richard Henderson
    int sizemask = 0;
1335 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and unsigned.  */
1336 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 0);
1337 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 0);
1338 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 0);
1339 2bece2c8 Richard Henderson
1340 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1341 31d66551 Aurelien Jarno
}
1342 31d66551 Aurelien Jarno
1343 31d66551 Aurelien Jarno
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1344 31d66551 Aurelien Jarno
{
1345 2bece2c8 Richard Henderson
    int sizemask = 0;
1346 2bece2c8 Richard Henderson
    /* Return value and both arguments are 64-bit and unsigned.  */
1347 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(0, 1, 0);
1348 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(1, 1, 0);
1349 2bece2c8 Richard Henderson
    sizemask |= tcg_gen_sizemask(2, 1, 0);
1350 2bece2c8 Richard Henderson
1351 2bece2c8 Richard Henderson
    tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1352 31d66551 Aurelien Jarno
}
1353 c896fe29 bellard
#endif
1354 c896fe29 bellard
1355 c896fe29 bellard
#endif
1356 c896fe29 bellard
1357 a7812ae4 pbrook
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1358 6359706f aurel32
{
1359 6359706f aurel32
    /* some cases can be optimized here */
1360 6359706f aurel32
    if (arg2 == 0) {
1361 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1362 6359706f aurel32
    } else {
1363 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1364 6359706f aurel32
        tcg_gen_add_i64(ret, arg1, t0);
1365 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1366 6359706f aurel32
    }
1367 6359706f aurel32
}
1368 6359706f aurel32
1369 a7812ae4 pbrook
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1370 0045734a aurel32
{
1371 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg1);
1372 0045734a aurel32
    tcg_gen_sub_i64(ret, t0, arg2);
1373 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1374 0045734a aurel32
}
1375 0045734a aurel32
1376 a7812ae4 pbrook
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1377 6359706f aurel32
{
1378 6359706f aurel32
    /* some cases can be optimized here */
1379 6359706f aurel32
    if (arg2 == 0) {
1380 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1381 6359706f aurel32
    } else {
1382 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1383 6359706f aurel32
        tcg_gen_sub_i64(ret, arg1, t0);
1384 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1385 6359706f aurel32
    }
1386 6359706f aurel32
}
1387 8a56e840 Richard Henderson
static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
1388 8a56e840 Richard Henderson
                                       int64_t arg2, int label_index)
1389 f02bb954 aurel32
{
1390 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1391 f02bb954 aurel32
    tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1392 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1393 f02bb954 aurel32
}
1394 f02bb954 aurel32
1395 8a56e840 Richard Henderson
static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1396 8a56e840 Richard Henderson
                                        TCGv_i64 arg1, int64_t arg2)
1397 5105c556 Aurelien Jarno
{
1398 5105c556 Aurelien Jarno
    TCGv_i64 t0 = tcg_const_i64(arg2);
1399 5105c556 Aurelien Jarno
    tcg_gen_setcond_i64(cond, ret, arg1, t0);
1400 5105c556 Aurelien Jarno
    tcg_temp_free_i64(t0);
1401 5105c556 Aurelien Jarno
}
1402 5105c556 Aurelien Jarno
1403 a7812ae4 pbrook
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1404 f02bb954 aurel32
{
1405 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1406 f02bb954 aurel32
    tcg_gen_mul_i64(ret, arg1, t0);
1407 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1408 f02bb954 aurel32
}
1409 f02bb954 aurel32
1410 6359706f aurel32
1411 c896fe29 bellard
/***************************************/
1412 c896fe29 bellard
/* optional operations */
1413 c896fe29 bellard
1414 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1415 c896fe29 bellard
{
1416 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
1417 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1418 c896fe29 bellard
#else
1419 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
1420 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
1421 c896fe29 bellard
#endif
1422 c896fe29 bellard
}
1423 c896fe29 bellard
1424 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1425 c896fe29 bellard
{
1426 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
1427 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1428 c896fe29 bellard
#else
1429 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
1430 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
1431 c896fe29 bellard
#endif
1432 c896fe29 bellard
}
1433 c896fe29 bellard
1434 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1435 86831435 pbrook
{
1436 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext8u_i32
1437 cfc86988 Aurelien Jarno
    tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1438 cfc86988 Aurelien Jarno
#else
1439 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffu);
1440 cfc86988 Aurelien Jarno
#endif
1441 86831435 pbrook
}
1442 86831435 pbrook
1443 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1444 86831435 pbrook
{
1445 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext16u_i32
1446 cfc86988 Aurelien Jarno
    tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1447 cfc86988 Aurelien Jarno
#else
1448 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffffu);
1449 cfc86988 Aurelien Jarno
#endif
1450 86831435 pbrook
}
1451 86831435 pbrook
1452 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
1453 a7812ae4 pbrook
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1454 c896fe29 bellard
{
1455 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
1456 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1457 c896fe29 bellard
#else
1458 dfa1a3f1 aurel32
    TCGv_i32 t0 = tcg_temp_new_i32();
1459 c896fe29 bellard
    
1460 dfa1a3f1 aurel32
    tcg_gen_ext8u_i32(t0, arg);
1461 dfa1a3f1 aurel32
    tcg_gen_shli_i32(t0, t0, 8);
1462 dfa1a3f1 aurel32
    tcg_gen_shri_i32(ret, arg, 8);
1463 dfa1a3f1 aurel32
    tcg_gen_or_i32(ret, ret, t0);
1464 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1465 c896fe29 bellard
#endif
1466 c896fe29 bellard
}
1467 c896fe29 bellard
1468 66896cb8 aurel32
static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1469 c896fe29 bellard
{
1470 66896cb8 aurel32
#ifdef TCG_TARGET_HAS_bswap32_i32
1471 66896cb8 aurel32
    tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1472 c896fe29 bellard
#else
1473 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1474 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1475 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1476 c896fe29 bellard
    
1477 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
1478 c896fe29 bellard
    
1479 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1480 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1481 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1482 c896fe29 bellard
    
1483 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
1484 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1485 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1486 c896fe29 bellard
    
1487 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
1488 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1489 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1490 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1491 c896fe29 bellard
#endif
1492 c896fe29 bellard
}
1493 c896fe29 bellard
1494 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1495 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1496 c896fe29 bellard
{
1497 a7812ae4 pbrook
    tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1498 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1499 c896fe29 bellard
}
1500 c896fe29 bellard
1501 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1502 c896fe29 bellard
{
1503 a7812ae4 pbrook
    tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1504 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1505 c896fe29 bellard
}
1506 c896fe29 bellard
1507 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1508 c896fe29 bellard
{
1509 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1510 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1511 c896fe29 bellard
}
1512 c896fe29 bellard
1513 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1514 86831435 pbrook
{
1515 a7812ae4 pbrook
    tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1516 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1517 86831435 pbrook
}
1518 86831435 pbrook
1519 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1520 86831435 pbrook
{
1521 a7812ae4 pbrook
    tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1522 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1523 86831435 pbrook
}
1524 86831435 pbrook
1525 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1526 86831435 pbrook
{
1527 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1528 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1529 86831435 pbrook
}
1530 86831435 pbrook
1531 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1532 c896fe29 bellard
{
1533 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1534 c896fe29 bellard
}
1535 c896fe29 bellard
1536 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1537 c896fe29 bellard
{
1538 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1539 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1540 c896fe29 bellard
}
1541 c896fe29 bellard
1542 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1543 c896fe29 bellard
{
1544 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1545 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1546 c896fe29 bellard
}
1547 c896fe29 bellard
1548 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1549 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1550 9a5c57fd aurel32
{
1551 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1552 9a5c57fd aurel32
    tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1553 9a5c57fd aurel32
}
1554 9a5c57fd aurel32
1555 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1556 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1557 9a5c57fd aurel32
{
1558 9a5c57fd aurel32
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1559 9a5c57fd aurel32
    tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1560 9a5c57fd aurel32
}
1561 9a5c57fd aurel32
1562 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1563 c896fe29 bellard
{
1564 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1565 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1566 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1567 c896fe29 bellard
1568 66896cb8 aurel32
    tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1569 66896cb8 aurel32
    tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1570 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1571 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1572 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1573 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1574 c896fe29 bellard
}
1575 c896fe29 bellard
#else
1576 c896fe29 bellard
1577 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1578 c896fe29 bellard
{
1579 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
1580 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1581 c896fe29 bellard
#else
1582 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
1583 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
1584 c896fe29 bellard
#endif
1585 c896fe29 bellard
}
1586 c896fe29 bellard
1587 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1588 c896fe29 bellard
{
1589 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
1590 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1591 c896fe29 bellard
#else
1592 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
1593 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
1594 c896fe29 bellard
#endif
1595 c896fe29 bellard
}
1596 c896fe29 bellard
1597 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1598 c896fe29 bellard
{
1599 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
1600 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1601 c896fe29 bellard
#else
1602 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
1603 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
1604 c896fe29 bellard
#endif
1605 c896fe29 bellard
}
1606 c896fe29 bellard
1607 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1608 86831435 pbrook
{
1609 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext8u_i64
1610 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1611 cfc86988 Aurelien Jarno
#else
1612 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffu);
1613 cfc86988 Aurelien Jarno
#endif
1614 86831435 pbrook
}
1615 86831435 pbrook
1616 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1617 86831435 pbrook
{
1618 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext16u_i64
1619 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1620 cfc86988 Aurelien Jarno
#else
1621 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffu);
1622 cfc86988 Aurelien Jarno
#endif
1623 86831435 pbrook
}
1624 86831435 pbrook
1625 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1626 86831435 pbrook
{
1627 cfc86988 Aurelien Jarno
#ifdef TCG_TARGET_HAS_ext32u_i64
1628 cfc86988 Aurelien Jarno
    tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1629 cfc86988 Aurelien Jarno
#else
1630 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1631 cfc86988 Aurelien Jarno
#endif
1632 86831435 pbrook
}
1633 86831435 pbrook
1634 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1635 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1636 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1637 c896fe29 bellard
{
1638 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1639 c896fe29 bellard
}
1640 c896fe29 bellard
1641 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1642 c896fe29 bellard
   registers */
1643 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1644 c896fe29 bellard
{
1645 cfc86988 Aurelien Jarno
    tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1646 c896fe29 bellard
}
1647 c896fe29 bellard
1648 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1649 c896fe29 bellard
   registers */
1650 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1651 c896fe29 bellard
{
1652 a7812ae4 pbrook
    tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1653 c896fe29 bellard
}
1654 c896fe29 bellard
1655 9a5c57fd aurel32
/* Note: we assume the six high bytes are set to zero */
1656 9a5c57fd aurel32
static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1657 9a5c57fd aurel32
{
1658 9a5c57fd aurel32
#ifdef TCG_TARGET_HAS_bswap16_i64
1659 9a5c57fd aurel32
    tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1660 9a5c57fd aurel32
#else
1661 9a5c57fd aurel32
    TCGv_i64 t0 = tcg_temp_new_i64();
1662 9a5c57fd aurel32
1663 9a5c57fd aurel32
    tcg_gen_ext8u_i64(t0, arg);
1664 9a5c57fd aurel32
    tcg_gen_shli_i64(t0, t0, 8);
1665 9a5c57fd aurel32
    tcg_gen_shri_i64(ret, arg, 8);
1666 9a5c57fd aurel32
    tcg_gen_or_i64(ret, ret, t0);
1667 9a5c57fd aurel32
    tcg_temp_free_i64(t0);
1668 9a5c57fd aurel32
#endif
1669 9a5c57fd aurel32
}
1670 9a5c57fd aurel32
1671 9a5c57fd aurel32
/* Note: we assume the four high bytes are set to zero */
1672 9a5c57fd aurel32
static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1673 9a5c57fd aurel32
{
1674 9a5c57fd aurel32
#ifdef TCG_TARGET_HAS_bswap32_i64
1675 9a5c57fd aurel32
    tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1676 9a5c57fd aurel32
#else
1677 9a5c57fd aurel32
    TCGv_i64 t0, t1;
1678 9a5c57fd aurel32
    t0 = tcg_temp_new_i64();
1679 9a5c57fd aurel32
    t1 = tcg_temp_new_i64();
1680 9a5c57fd aurel32
1681 9a5c57fd aurel32
    tcg_gen_shli_i64(t0, arg, 24);
1682 9a5c57fd aurel32
    tcg_gen_ext32u_i64(t0, t0);
1683 9a5c57fd aurel32
1684 9a5c57fd aurel32
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1685 9a5c57fd aurel32
    tcg_gen_shli_i64(t1, t1, 8);
1686 9a5c57fd aurel32
    tcg_gen_or_i64(t0, t0, t1);
1687 9a5c57fd aurel32
1688 9a5c57fd aurel32
    tcg_gen_shri_i64(t1, arg, 8);
1689 9a5c57fd aurel32
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1690 9a5c57fd aurel32
    tcg_gen_or_i64(t0, t0, t1);
1691 9a5c57fd aurel32
1692 9a5c57fd aurel32
    tcg_gen_shri_i64(t1, arg, 24);
1693 9a5c57fd aurel32
    tcg_gen_or_i64(ret, t0, t1);
1694 9a5c57fd aurel32
    tcg_temp_free_i64(t0);
1695 9a5c57fd aurel32
    tcg_temp_free_i64(t1);
1696 9a5c57fd aurel32
#endif
1697 9a5c57fd aurel32
}
1698 9a5c57fd aurel32
1699 66896cb8 aurel32
static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1700 c896fe29 bellard
{
1701 66896cb8 aurel32
#ifdef TCG_TARGET_HAS_bswap64_i64
1702 66896cb8 aurel32
    tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1703 c896fe29 bellard
#else
1704 b348113d Stefan Weil
    TCGv_i64 t0 = tcg_temp_new_i64();
1705 b348113d Stefan Weil
    TCGv_i64 t1 = tcg_temp_new_i64();
1706 c896fe29 bellard
    
1707 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1708 c896fe29 bellard
    
1709 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1710 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1711 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1712 c896fe29 bellard
    
1713 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1714 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1715 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1716 c896fe29 bellard
1717 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1718 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1719 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1720 c896fe29 bellard
1721 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1722 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1723 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1724 c896fe29 bellard
    
1725 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1726 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1727 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1728 c896fe29 bellard
1729 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1730 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1731 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1732 c896fe29 bellard
1733 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1734 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1735 b348113d Stefan Weil
    tcg_temp_free_i64(t0);
1736 b348113d Stefan Weil
    tcg_temp_free_i64(t1);
1737 c896fe29 bellard
#endif
1738 c896fe29 bellard
}
1739 c896fe29 bellard
1740 c896fe29 bellard
#endif
1741 c896fe29 bellard
1742 a7812ae4 pbrook
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1743 390efc54 pbrook
{
1744 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i32
1745 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1746 390efc54 pbrook
#else
1747 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(0);
1748 e8996ee0 bellard
    tcg_gen_sub_i32(ret, t0, arg);
1749 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1750 390efc54 pbrook
#endif
1751 390efc54 pbrook
}
1752 390efc54 pbrook
1753 a7812ae4 pbrook
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1754 390efc54 pbrook
{
1755 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i64
1756 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1757 390efc54 pbrook
#else
1758 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(0);
1759 e8996ee0 bellard
    tcg_gen_sub_i64(ret, t0, arg);
1760 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1761 390efc54 pbrook
#endif
1762 390efc54 pbrook
}
1763 390efc54 pbrook
1764 a7812ae4 pbrook
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1765 0b6ce4cf bellard
{
1766 d2604285 aurel32
#ifdef TCG_TARGET_HAS_not_i32
1767 d2604285 aurel32
    tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1768 d2604285 aurel32
#else
1769 e8996ee0 bellard
    tcg_gen_xori_i32(ret, arg, -1);
1770 d2604285 aurel32
#endif
1771 0b6ce4cf bellard
}
1772 0b6ce4cf bellard
1773 a7812ae4 pbrook
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1774 0b6ce4cf bellard
{
1775 d2604285 aurel32
#ifdef TCG_TARGET_HAS_not_i64
1776 43e860ef aurel32
    tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1777 a10f9f4f Richard Henderson
#elif defined(TCG_TARGET_HAS_not_i32) && TCG_TARGET_REG_BITS == 32
1778 a10f9f4f Richard Henderson
    tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1779 a10f9f4f Richard Henderson
    tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1780 d2604285 aurel32
#else
1781 e8996ee0 bellard
    tcg_gen_xori_i64(ret, arg, -1);
1782 d2604285 aurel32
#endif
1783 0b6ce4cf bellard
}
1784 5ff9d6a4 bellard
1785 a7812ae4 pbrook
static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1786 5ff9d6a4 bellard
{
1787 a7812ae4 pbrook
    tcg_gen_op1_i32(INDEX_op_discard, arg);
1788 5ff9d6a4 bellard
}
1789 5ff9d6a4 bellard
1790 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1791 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1792 5ff9d6a4 bellard
{
1793 a7812ae4 pbrook
    tcg_gen_discard_i32(TCGV_LOW(arg));
1794 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1795 5ff9d6a4 bellard
}
1796 5ff9d6a4 bellard
#else
1797 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1798 5ff9d6a4 bellard
{
1799 a7812ae4 pbrook
    tcg_gen_op1_i64(INDEX_op_discard, arg);
1800 5ff9d6a4 bellard
}
1801 5ff9d6a4 bellard
#endif
1802 5ff9d6a4 bellard
1803 a7812ae4 pbrook
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1804 36aa55dc pbrook
{
1805 36aa55dc pbrook
#if TCG_TARGET_REG_BITS == 32
1806 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(dest), low);
1807 36aa55dc pbrook
    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1808 36aa55dc pbrook
#else
1809 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1810 36aa55dc pbrook
    /* This extension is only needed for type correctness.
1811 36aa55dc pbrook
       We may be able to do better given target specific information.  */
1812 36aa55dc pbrook
    tcg_gen_extu_i32_i64(tmp, high);
1813 36aa55dc pbrook
    tcg_gen_shli_i64(tmp, tmp, 32);
1814 36aa55dc pbrook
    tcg_gen_extu_i32_i64(dest, low);
1815 36aa55dc pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1816 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1817 36aa55dc pbrook
#endif
1818 36aa55dc pbrook
}
1819 36aa55dc pbrook
1820 a7812ae4 pbrook
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1821 945ca823 blueswir1
{
1822 945ca823 blueswir1
#if TCG_TARGET_REG_BITS == 32
1823 a7812ae4 pbrook
    tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1824 945ca823 blueswir1
#else
1825 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1826 88422e2e pbrook
    tcg_gen_ext32u_i64(dest, low);
1827 945ca823 blueswir1
    tcg_gen_shli_i64(tmp, high, 32);
1828 88422e2e pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1829 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1830 945ca823 blueswir1
#endif
1831 945ca823 blueswir1
}
1832 945ca823 blueswir1
1833 a7812ae4 pbrook
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1834 f24cb33e aurel32
{
1835 241cbed4 Richard Henderson
#ifdef TCG_TARGET_HAS_andc_i32
1836 241cbed4 Richard Henderson
    tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1837 241cbed4 Richard Henderson
#else
1838 a7812ae4 pbrook
    TCGv_i32 t0;
1839 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1840 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1841 f24cb33e aurel32
    tcg_gen_and_i32(ret, arg1, t0);
1842 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1843 241cbed4 Richard Henderson
#endif
1844 f24cb33e aurel32
}
1845 f24cb33e aurel32
1846 a7812ae4 pbrook
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1847 f24cb33e aurel32
{
1848 241cbed4 Richard Henderson
#ifdef TCG_TARGET_HAS_andc_i64
1849 241cbed4 Richard Henderson
    tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1850 241cbed4 Richard Henderson
#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32
1851 241cbed4 Richard Henderson
    tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1852 241cbed4 Richard Henderson
    tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1853 241cbed4 Richard Henderson
#else
1854 a7812ae4 pbrook
    TCGv_i64 t0;
1855 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1856 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1857 f24cb33e aurel32
    tcg_gen_and_i64(ret, arg1, t0);
1858 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1859 241cbed4 Richard Henderson
#endif
1860 f24cb33e aurel32
}
1861 f24cb33e aurel32
1862 a7812ae4 pbrook
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1863 f24cb33e aurel32
{
1864 8d625cf1 Richard Henderson
#ifdef TCG_TARGET_HAS_eqv_i32
1865 8d625cf1 Richard Henderson
    tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
1866 8d625cf1 Richard Henderson
#else
1867 7fc81051 aurel32
    tcg_gen_xor_i32(ret, arg1, arg2);
1868 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1869 8d625cf1 Richard Henderson
#endif
1870 f24cb33e aurel32
}
1871 f24cb33e aurel32
1872 a7812ae4 pbrook
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1873 f24cb33e aurel32
{
1874 8d625cf1 Richard Henderson
#ifdef TCG_TARGET_HAS_eqv_i64
1875 8d625cf1 Richard Henderson
    tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1876 8d625cf1 Richard Henderson
#elif defined(TCG_TARGET_HAS_eqv_i32) && TCG_TARGET_REG_BITS == 32
1877 8d625cf1 Richard Henderson
    tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1878 8d625cf1 Richard Henderson
    tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1879 8d625cf1 Richard Henderson
#else
1880 7fc81051 aurel32
    tcg_gen_xor_i64(ret, arg1, arg2);
1881 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1882 8d625cf1 Richard Henderson
#endif
1883 f24cb33e aurel32
}
1884 f24cb33e aurel32
1885 a7812ae4 pbrook
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1886 f24cb33e aurel32
{
1887 9940a96b Richard Henderson
#ifdef TCG_TARGET_HAS_nand_i32
1888 9940a96b Richard Henderson
    tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
1889 9940a96b Richard Henderson
#else
1890 7fc81051 aurel32
    tcg_gen_and_i32(ret, arg1, arg2);
1891 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1892 9940a96b Richard Henderson
#endif
1893 f24cb33e aurel32
}
1894 f24cb33e aurel32
1895 a7812ae4 pbrook
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1896 f24cb33e aurel32
{
1897 9940a96b Richard Henderson
#ifdef TCG_TARGET_HAS_nand_i64
1898 9940a96b Richard Henderson
    tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1899 9940a96b Richard Henderson
#elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32
1900 9940a96b Richard Henderson
    tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1901 9940a96b Richard Henderson
    tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1902 9940a96b Richard Henderson
#else
1903 7fc81051 aurel32
    tcg_gen_and_i64(ret, arg1, arg2);
1904 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1905 9940a96b Richard Henderson
#endif
1906 f24cb33e aurel32
}
1907 f24cb33e aurel32
1908 a7812ae4 pbrook
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1909 f24cb33e aurel32
{
1910 32d98fbd Richard Henderson
#ifdef TCG_TARGET_HAS_nor_i32
1911 32d98fbd Richard Henderson
    tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
1912 32d98fbd Richard Henderson
#else
1913 7fc81051 aurel32
    tcg_gen_or_i32(ret, arg1, arg2);
1914 7fc81051 aurel32
    tcg_gen_not_i32(ret, ret);
1915 32d98fbd Richard Henderson
#endif
1916 f24cb33e aurel32
}
1917 f24cb33e aurel32
1918 a7812ae4 pbrook
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1919 f24cb33e aurel32
{
1920 32d98fbd Richard Henderson
#ifdef TCG_TARGET_HAS_nor_i64
1921 32d98fbd Richard Henderson
    tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
1922 32d98fbd Richard Henderson
#elif defined(TCG_TARGET_HAS_nor_i32) && TCG_TARGET_REG_BITS == 32
1923 32d98fbd Richard Henderson
    tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1924 32d98fbd Richard Henderson
    tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1925 32d98fbd Richard Henderson
#else
1926 7fc81051 aurel32
    tcg_gen_or_i64(ret, arg1, arg2);
1927 7fc81051 aurel32
    tcg_gen_not_i64(ret, ret);
1928 32d98fbd Richard Henderson
#endif
1929 f24cb33e aurel32
}
1930 f24cb33e aurel32
1931 a7812ae4 pbrook
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1932 f24cb33e aurel32
{
1933 791d1262 Richard Henderson
#ifdef TCG_TARGET_HAS_orc_i32
1934 791d1262 Richard Henderson
    tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
1935 791d1262 Richard Henderson
#else
1936 a7812ae4 pbrook
    TCGv_i32 t0;
1937 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1938 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1939 f24cb33e aurel32
    tcg_gen_or_i32(ret, arg1, t0);
1940 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1941 791d1262 Richard Henderson
#endif
1942 f24cb33e aurel32
}
1943 f24cb33e aurel32
1944 a7812ae4 pbrook
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1945 f24cb33e aurel32
{
1946 791d1262 Richard Henderson
#ifdef TCG_TARGET_HAS_orc_i64
1947 791d1262 Richard Henderson
    tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
1948 791d1262 Richard Henderson
#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32
1949 791d1262 Richard Henderson
    tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1950 791d1262 Richard Henderson
    tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1951 791d1262 Richard Henderson
#else
1952 a7812ae4 pbrook
    TCGv_i64 t0;
1953 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1954 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1955 f24cb33e aurel32
    tcg_gen_or_i64(ret, arg1, t0);
1956 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1957 791d1262 Richard Henderson
#endif
1958 f24cb33e aurel32
}
1959 f24cb33e aurel32
1960 a7812ae4 pbrook
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1961 15824571 aurel32
{
1962 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
1963 d42f183c aurel32
    tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
1964 d42f183c aurel32
#else
1965 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1966 15824571 aurel32
1967 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1968 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1969 15824571 aurel32
    tcg_gen_shl_i32(t0, arg1, arg2);
1970 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
1971 15824571 aurel32
    tcg_gen_shr_i32(t1, arg1, t1);
1972 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
1973 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1974 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1975 d42f183c aurel32
#endif
1976 15824571 aurel32
}
1977 15824571 aurel32
1978 a7812ae4 pbrook
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1979 15824571 aurel32
{
1980 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
1981 d42f183c aurel32
    tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
1982 d42f183c aurel32
#else
1983 a7812ae4 pbrook
    TCGv_i64 t0, t1;
1984 15824571 aurel32
1985 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1986 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
1987 15824571 aurel32
    tcg_gen_shl_i64(t0, arg1, arg2);
1988 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
1989 15824571 aurel32
    tcg_gen_shr_i64(t1, arg1, t1);
1990 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
1991 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1992 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
1993 d42f183c aurel32
#endif
1994 15824571 aurel32
}
1995 15824571 aurel32
1996 a7812ae4 pbrook
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1997 15824571 aurel32
{
1998 15824571 aurel32
    /* some cases can be optimized here */
1999 15824571 aurel32
    if (arg2 == 0) {
2000 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
2001 15824571 aurel32
    } else {
2002 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
2003 d42f183c aurel32
        TCGv_i32 t0 = tcg_const_i32(arg2);
2004 d42f183c aurel32
        tcg_gen_rotl_i32(ret, arg1, t0);
2005 d42f183c aurel32
        tcg_temp_free_i32(t0);
2006 d42f183c aurel32
#else
2007 a7812ae4 pbrook
        TCGv_i32 t0, t1;
2008 a7812ae4 pbrook
        t0 = tcg_temp_new_i32();
2009 a7812ae4 pbrook
        t1 = tcg_temp_new_i32();
2010 15824571 aurel32
        tcg_gen_shli_i32(t0, arg1, arg2);
2011 15824571 aurel32
        tcg_gen_shri_i32(t1, arg1, 32 - arg2);
2012 15824571 aurel32
        tcg_gen_or_i32(ret, t0, t1);
2013 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
2014 a7812ae4 pbrook
        tcg_temp_free_i32(t1);
2015 d42f183c aurel32
#endif
2016 15824571 aurel32
    }
2017 15824571 aurel32
}
2018 15824571 aurel32
2019 a7812ae4 pbrook
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2020 15824571 aurel32
{
2021 15824571 aurel32
    /* some cases can be optimized here */
2022 15824571 aurel32
    if (arg2 == 0) {
2023 15824571 aurel32
        tcg_gen_mov_i64(ret, arg1);
2024 15824571 aurel32
    } else {
2025 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
2026 d42f183c aurel32
        TCGv_i64 t0 = tcg_const_i64(arg2);
2027 d42f183c aurel32
        tcg_gen_rotl_i64(ret, arg1, t0);
2028 d42f183c aurel32
        tcg_temp_free_i64(t0);
2029 d42f183c aurel32
#else
2030 a7812ae4 pbrook
        TCGv_i64 t0, t1;
2031 a7812ae4 pbrook
        t0 = tcg_temp_new_i64();
2032 a7812ae4 pbrook
        t1 = tcg_temp_new_i64();
2033 15824571 aurel32
        tcg_gen_shli_i64(t0, arg1, arg2);
2034 15824571 aurel32
        tcg_gen_shri_i64(t1, arg1, 64 - arg2);
2035 15824571 aurel32
        tcg_gen_or_i64(ret, t0, t1);
2036 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
2037 a7812ae4 pbrook
        tcg_temp_free_i64(t1);
2038 d42f183c aurel32
#endif
2039 15824571 aurel32
    }
2040 15824571 aurel32
}
2041 15824571 aurel32
2042 a7812ae4 pbrook
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
2043 15824571 aurel32
{
2044 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i32
2045 d42f183c aurel32
    tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
2046 d42f183c aurel32
#else
2047 a7812ae4 pbrook
    TCGv_i32 t0, t1;
2048 15824571 aurel32
2049 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
2050 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
2051 15824571 aurel32
    tcg_gen_shr_i32(t0, arg1, arg2);
2052 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
2053 15824571 aurel32
    tcg_gen_shl_i32(t1, arg1, t1);
2054 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
2055 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
2056 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
2057 d42f183c aurel32
#endif
2058 15824571 aurel32
}
2059 15824571 aurel32
2060 a7812ae4 pbrook
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2061 15824571 aurel32
{
2062 d42f183c aurel32
#ifdef TCG_TARGET_HAS_rot_i64
2063 d42f183c aurel32
    tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2064 d42f183c aurel32
#else
2065 a7812ae4 pbrook
    TCGv_i64 t0, t1;
2066 15824571 aurel32
2067 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
2068 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
2069 d9885a0b Aurelien Jarno
    tcg_gen_shr_i64(t0, arg1, arg2);
2070 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
2071 15824571 aurel32
    tcg_gen_shl_i64(t1, arg1, t1);
2072 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
2073 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
2074 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
2075 d42f183c aurel32
#endif
2076 15824571 aurel32
}
2077 15824571 aurel32
2078 a7812ae4 pbrook
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
2079 15824571 aurel32
{
2080 15824571 aurel32
    /* some cases can be optimized here */
2081 15824571 aurel32
    if (arg2 == 0) {
2082 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
2083 15824571 aurel32
    } else {
2084 15824571 aurel32
        tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
2085 15824571 aurel32
    }
2086 15824571 aurel32
}
2087 15824571 aurel32
2088 a7812ae4 pbrook
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2089 15824571 aurel32
{
2090 15824571 aurel32
    /* some cases can be optimized here */
2091 15824571 aurel32
    if (arg2 == 0) {
2092 de3526b2 pbrook
        tcg_gen_mov_i64(ret, arg1);
2093 15824571 aurel32
    } else {
2094 15824571 aurel32
        tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2095 15824571 aurel32
    }
2096 15824571 aurel32
}
2097 15824571 aurel32
2098 b7767f0f Richard Henderson
static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
2099 b7767f0f Richard Henderson
                                       TCGv_i32 arg2, unsigned int ofs,
2100 b7767f0f Richard Henderson
                                       unsigned int len)
2101 b7767f0f Richard Henderson
{
2102 b7767f0f Richard Henderson
#ifdef TCG_TARGET_HAS_deposit_i32
2103 b7767f0f Richard Henderson
  tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
2104 b7767f0f Richard Henderson
#else
2105 b7767f0f Richard Henderson
  uint32_t mask = (1u << len) - 1;
2106 b7767f0f Richard Henderson
  TCGv_i32 t1 = tcg_temp_new_i32 ();
2107 b7767f0f Richard Henderson
2108 b7767f0f Richard Henderson
  tcg_gen_andi_i32(t1, arg2, mask);
2109 b7767f0f Richard Henderson
  tcg_gen_shli_i32(t1, t1, ofs);
2110 b7767f0f Richard Henderson
  tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
2111 b7767f0f Richard Henderson
  tcg_gen_or_i32(ret, ret, t1);
2112 b7767f0f Richard Henderson
2113 b7767f0f Richard Henderson
  tcg_temp_free_i32(t1);
2114 b7767f0f Richard Henderson
#endif
2115 b7767f0f Richard Henderson
}
2116 b7767f0f Richard Henderson
2117 b7767f0f Richard Henderson
static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
2118 b7767f0f Richard Henderson
                                       TCGv_i64 arg2, unsigned int ofs,
2119 b7767f0f Richard Henderson
                                       unsigned int len)
2120 b7767f0f Richard Henderson
{
2121 b7767f0f Richard Henderson
#ifdef TCG_TARGET_HAS_deposit_i64
2122 b7767f0f Richard Henderson
  tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
2123 b7767f0f Richard Henderson
#else
2124 b7767f0f Richard Henderson
  uint64_t mask = (1ull << len) - 1;
2125 b7767f0f Richard Henderson
  TCGv_i64 t1 = tcg_temp_new_i64 ();
2126 b7767f0f Richard Henderson
2127 b7767f0f Richard Henderson
  tcg_gen_andi_i64(t1, arg2, mask);
2128 b7767f0f Richard Henderson
  tcg_gen_shli_i64(t1, t1, ofs);
2129 b7767f0f Richard Henderson
  tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
2130 b7767f0f Richard Henderson
  tcg_gen_or_i64(ret, ret, t1);
2131 b7767f0f Richard Henderson
2132 b7767f0f Richard Henderson
  tcg_temp_free_i64(t1);
2133 b7767f0f Richard Henderson
#endif
2134 b7767f0f Richard Henderson
}
2135 b7767f0f Richard Henderson
2136 c896fe29 bellard
/***************************************/
2137 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
2138 c896fe29 bellard
   type. */
2139 c896fe29 bellard
#ifndef TARGET_LONG_BITS
2140 c896fe29 bellard
#error must include QEMU headers
2141 c896fe29 bellard
#endif
2142 c896fe29 bellard
2143 a7812ae4 pbrook
#if TARGET_LONG_BITS == 32
2144 a7812ae4 pbrook
#define TCGv TCGv_i32
2145 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i32()
2146 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i32
2147 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i32
2148 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i32()
2149 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i32
2150 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
2151 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
2152 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
2153 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
2154 a7812ae4 pbrook
#else
2155 a7812ae4 pbrook
#define TCGv TCGv_i64
2156 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i64()
2157 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i64
2158 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i64
2159 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i64()
2160 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i64
2161 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
2162 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
2163 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
2164 fe75bcf7 aurel32
#define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
2165 a7812ae4 pbrook
#endif
2166 a7812ae4 pbrook
2167 7e4597d7 bellard
/* debug info: write the PC of the corresponding QEMU CPU instruction */
2168 7e4597d7 bellard
static inline void tcg_gen_debug_insn_start(uint64_t pc)
2169 7e4597d7 bellard
{
2170 7e4597d7 bellard
    /* XXX: must really use a 32 bit size for TCGArg in all cases */
2171 7e4597d7 bellard
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2172 bcb0126f pbrook
    tcg_gen_op2ii(INDEX_op_debug_insn_start, 
2173 bcb0126f pbrook
                  (uint32_t)(pc), (uint32_t)(pc >> 32));
2174 7e4597d7 bellard
#else
2175 7e4597d7 bellard
    tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
2176 7e4597d7 bellard
#endif
2177 7e4597d7 bellard
}
2178 7e4597d7 bellard
2179 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
2180 c896fe29 bellard
{
2181 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
2182 c896fe29 bellard
}
2183 c896fe29 bellard
2184 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
2185 c896fe29 bellard
{
2186 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
2187 c896fe29 bellard
}
2188 c896fe29 bellard
2189 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
2190 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2191 c896fe29 bellard
{
2192 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2193 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2194 c896fe29 bellard
#else
2195 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
2196 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2197 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2198 c896fe29 bellard
#endif
2199 c896fe29 bellard
}
2200 c896fe29 bellard
2201 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2202 c896fe29 bellard
{
2203 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2204 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2205 c896fe29 bellard
#else
2206 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
2207 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2208 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2209 c896fe29 bellard
#endif
2210 c896fe29 bellard
}
2211 c896fe29 bellard
2212 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2213 c896fe29 bellard
{
2214 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2215 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2216 c896fe29 bellard
#else
2217 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
2218 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2219 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2220 c896fe29 bellard
#endif
2221 c896fe29 bellard
}
2222 c896fe29 bellard
2223 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2224 c896fe29 bellard
{
2225 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2226 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2227 c896fe29 bellard
#else
2228 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
2229 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2230 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2231 c896fe29 bellard
#endif
2232 c896fe29 bellard
}
2233 c896fe29 bellard
2234 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2235 c896fe29 bellard
{
2236 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2237 86feb1c8 Richard Henderson
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2238 c896fe29 bellard
#else
2239 86feb1c8 Richard Henderson
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2240 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2241 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2242 c896fe29 bellard
#endif
2243 c896fe29 bellard
}
2244 c896fe29 bellard
2245 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2246 c896fe29 bellard
{
2247 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2248 86feb1c8 Richard Henderson
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2249 c896fe29 bellard
#else
2250 86feb1c8 Richard Henderson
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2251 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2252 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2253 c896fe29 bellard
#endif
2254 c896fe29 bellard
}
2255 c896fe29 bellard
2256 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2257 c896fe29 bellard
{
2258 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2259 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
2260 c896fe29 bellard
#else
2261 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2262 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2263 c896fe29 bellard
#endif
2264 c896fe29 bellard
}
2265 c896fe29 bellard
2266 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2267 c896fe29 bellard
{
2268 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2269 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
2270 c896fe29 bellard
#else
2271 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2272 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2273 c896fe29 bellard
#endif
2274 c896fe29 bellard
}
2275 c896fe29 bellard
2276 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2277 c896fe29 bellard
{
2278 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2279 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
2280 c896fe29 bellard
#else
2281 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2282 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2283 c896fe29 bellard
#endif
2284 c896fe29 bellard
}
2285 c896fe29 bellard
2286 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2287 c896fe29 bellard
{
2288 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2289 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
2290 c896fe29 bellard
#else
2291 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2292 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
2293 c896fe29 bellard
#endif
2294 c896fe29 bellard
}
2295 c896fe29 bellard
2296 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2297 c896fe29 bellard
{
2298 c896fe29 bellard
#if TARGET_LONG_BITS == 32
2299 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2300 a7812ae4 pbrook
                     mem_index);
2301 c896fe29 bellard
#else
2302 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2303 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2304 c896fe29 bellard
#endif
2305 c896fe29 bellard
}
2306 c896fe29 bellard
2307 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i32
2308 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i32
2309 f8422f52 blueswir1
2310 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
2311 c896fe29 bellard
2312 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2313 c896fe29 bellard
{
2314 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2315 c896fe29 bellard
}
2316 c896fe29 bellard
2317 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2318 c896fe29 bellard
{
2319 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2320 c896fe29 bellard
}
2321 c896fe29 bellard
2322 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2323 c896fe29 bellard
{
2324 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2325 c896fe29 bellard
}
2326 c896fe29 bellard
2327 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2328 c896fe29 bellard
{
2329 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2330 c896fe29 bellard
}
2331 c896fe29 bellard
2332 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2333 c896fe29 bellard
{
2334 3e1dbadd Richard Henderson
#if TARGET_LONG_BITS == 32
2335 3e1dbadd Richard Henderson
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2336 3e1dbadd Richard Henderson
#else
2337 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
2338 3e1dbadd Richard Henderson
#endif
2339 c896fe29 bellard
}
2340 c896fe29 bellard
2341 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2342 c896fe29 bellard
{
2343 3e1dbadd Richard Henderson
#if TARGET_LONG_BITS == 32
2344 3e1dbadd Richard Henderson
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2345 3e1dbadd Richard Henderson
#else
2346 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
2347 3e1dbadd Richard Henderson
#endif
2348 c896fe29 bellard
}
2349 c896fe29 bellard
2350 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2351 c896fe29 bellard
{
2352 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2353 c896fe29 bellard
}
2354 c896fe29 bellard
2355 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2356 c896fe29 bellard
{
2357 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2358 c896fe29 bellard
}
2359 c896fe29 bellard
2360 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2361 c896fe29 bellard
{
2362 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2363 c896fe29 bellard
}
2364 c896fe29 bellard
2365 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2366 c896fe29 bellard
{
2367 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2368 c896fe29 bellard
}
2369 c896fe29 bellard
2370 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2371 c896fe29 bellard
{
2372 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2373 c896fe29 bellard
}
2374 c896fe29 bellard
2375 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i64
2376 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i64
2377 f8422f52 blueswir1
2378 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
2379 f8422f52 blueswir1
2380 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
2381 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
2382 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
2383 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2384 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2385 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2386 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2387 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2388 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2389 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
2390 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
2391 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
2392 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
2393 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
2394 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
2395 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
2396 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
2397 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i64
2398 10460c8a pbrook
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
2399 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
2400 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
2401 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
2402 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
2403 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
2404 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
2405 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
2406 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i64
2407 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
2408 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
2409 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i64
2410 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i64
2411 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i64
2412 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i64
2413 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
2414 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2415 be210acb Richard Henderson
#define tcg_gen_setcond_tl tcg_gen_setcond_i64
2416 add1e7ea Aurelien Jarno
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
2417 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i64
2418 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i64
2419 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i64
2420 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i64
2421 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i64
2422 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i64
2423 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i64
2424 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2425 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2426 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2427 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2428 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2429 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2430 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2431 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2432 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2433 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2434 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2435 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2436 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2437 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2438 911d79ba aurel32
#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2439 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2440 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i64
2441 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i64
2442 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i64
2443 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i64
2444 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i64
2445 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i64
2446 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
2447 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
2448 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
2449 b7767f0f Richard Henderson
#define tcg_gen_deposit_tl tcg_gen_deposit_i64
2450 a98824ac blueswir1
#define tcg_const_tl tcg_const_i64
2451 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i64
2452 f8422f52 blueswir1
#else
2453 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i32
2454 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i32
2455 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2456 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2457 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2458 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2459 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
2460 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
2461 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i32
2462 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i32
2463 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i32
2464 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st_i32
2465 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i32
2466 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i32
2467 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i32
2468 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i32
2469 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i32
2470 0045734a aurel32
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
2471 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i32
2472 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i32
2473 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i32
2474 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i32
2475 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i32
2476 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i32
2477 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i32
2478 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i32
2479 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i32
2480 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i32
2481 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i32
2482 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i32
2483 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i32
2484 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i32
2485 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
2486 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2487 be210acb Richard Henderson
#define tcg_gen_setcond_tl tcg_gen_setcond_i32
2488 add1e7ea Aurelien Jarno
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
2489 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i32
2490 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i32
2491 ab36421e aurel32
#define tcg_gen_div_tl tcg_gen_div_i32
2492 ab36421e aurel32
#define tcg_gen_rem_tl tcg_gen_rem_i32
2493 864951af aurel32
#define tcg_gen_divu_tl tcg_gen_divu_i32
2494 864951af aurel32
#define tcg_gen_remu_tl tcg_gen_remu_i32
2495 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i32
2496 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2497 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2498 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2499 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2500 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2501 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2502 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2503 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2504 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2505 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2506 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
2507 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
2508 911d79ba aurel32
#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2509 911d79ba aurel32
#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2510 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2511 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i32
2512 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
2513 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i32
2514 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i32
2515 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i32
2516 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2517 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
2518 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2519 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
2520 b7767f0f Richard Henderson
#define tcg_gen_deposit_tl tcg_gen_deposit_i32
2521 a98824ac blueswir1
#define tcg_const_tl tcg_const_i32
2522 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i32
2523 f8422f52 blueswir1
#endif
2524 6ddbc6e4 pbrook
2525 6ddbc6e4 pbrook
#if TCG_TARGET_REG_BITS == 32
2526 48d38ca5 ths
#define tcg_gen_add_ptr tcg_gen_add_i32
2527 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i32
2528 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
2529 6ddbc6e4 pbrook
#else /* TCG_TARGET_REG_BITS == 32 */
2530 48d38ca5 ths
#define tcg_gen_add_ptr tcg_gen_add_i64
2531 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i64
2532 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2533 6ddbc6e4 pbrook
#endif /* TCG_TARGET_REG_BITS != 32 */