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/*
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* High Precisition Event Timer emulation
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*
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* Copyright (c) 2007 Alexander Graf
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* Copyright (c) 2008 IBM Corporation
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*
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* Authors: Beth Kon <bkon@us.ibm.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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* *****************************************************************
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*
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* This driver attempts to emulate an HPET device in software.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "console.h" |
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#include "qemu-timer.h" |
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#include "hpet_emul.h" |
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#include "sysbus.h" |
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#include "mc146818rtc.h" |
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//#define HPET_DEBUG
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#ifdef HPET_DEBUG
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
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#define HPET_MSI_SUPPORT 0 |
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struct HPETState;
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typedef struct HPETTimer { /* timers */ |
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uint8_t tn; /*timer number*/
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QEMUTimer *qemu_timer; |
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struct HPETState *state;
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/* Memory-mapped, software visible timer registers */
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uint64_t config; /* configuration/cap */
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uint64_t cmp; /* comparator */
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uint64_t fsb; /* FSB route */
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/* Hidden register state */
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uint64_t period; /* Last value written to comparator */
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uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
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* mode. Next pop will be actual timer expiration.
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*/
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} HPETTimer; |
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|
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typedef struct HPETState { |
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SysBusDevice busdev; |
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uint64_t hpet_offset; |
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qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; |
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uint32_t flags; |
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uint8_t rtc_irq_level; |
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uint8_t num_timers; |
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HPETTimer timer[HPET_MAX_TIMERS]; |
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|
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/* Memory-mapped, software visible registers */
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uint64_t capability; /* capabilities */
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uint64_t config; /* configuration */
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uint64_t isr; /* interrupt status reg */
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uint64_t hpet_counter; /* main counter */
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} HPETState; |
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static uint32_t hpet_in_legacy_mode(HPETState *s)
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{
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return s->config & HPET_CFG_LEGACY;
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} |
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static uint32_t timer_int_route(struct HPETTimer *timer) |
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{
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return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
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} |
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static uint32_t timer_fsb_route(HPETTimer *t)
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{
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return t->config & HPET_TN_FSB_ENABLE;
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} |
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static uint32_t hpet_enabled(HPETState *s)
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{
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return s->config & HPET_CFG_ENABLE;
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} |
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static uint32_t timer_is_periodic(HPETTimer *t)
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{
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return t->config & HPET_TN_PERIODIC;
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} |
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static uint32_t timer_enabled(HPETTimer *t)
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{
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return t->config & HPET_TN_ENABLE;
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} |
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static uint32_t hpet_time_after(uint64_t a, uint64_t b)
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{
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return ((int32_t)(b) - (int32_t)(a) < 0); |
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} |
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static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
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{
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return ((int64_t)(b) - (int64_t)(a) < 0); |
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} |
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static uint64_t ticks_to_ns(uint64_t value)
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{
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return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
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} |
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static uint64_t ns_to_ticks(uint64_t value)
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{
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return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
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} |
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static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
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{
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new &= mask; |
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new |= old & ~mask; |
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return new;
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} |
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static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) |
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{
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return (!(old & mask) && (new & mask));
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} |
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static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) |
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{
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return ((old & mask) && !(new & mask));
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} |
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static uint64_t hpet_get_ticks(HPETState *s)
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{
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return ns_to_ticks(qemu_get_clock(vm_clock) + s->hpet_offset);
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} |
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/*
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* calculate diff between comparator value and current ticks
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*/
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static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) |
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{
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if (t->config & HPET_TN_32BIT) {
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uint32_t diff, cmp; |
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cmp = (uint32_t)t->cmp; |
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diff = cmp - (uint32_t)current; |
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diff = (int32_t)diff > 0 ? diff : (uint32_t)0; |
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return (uint64_t)diff;
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} else {
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uint64_t diff, cmp; |
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cmp = t->cmp; |
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diff = cmp - current; |
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diff = (int64_t)diff > 0 ? diff : (uint64_t)0; |
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return diff;
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} |
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} |
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static void update_irq(struct HPETTimer *timer, int set) |
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{
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uint64_t mask; |
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HPETState *s; |
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int route;
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if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) { |
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/* if LegacyReplacementRoute bit is set, HPET specification requires
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* timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
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* timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
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*/
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route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ; |
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} else {
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route = timer_int_route(timer); |
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} |
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s = timer->state; |
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mask = 1 << timer->tn;
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if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
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s->isr &= ~mask; |
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if (!timer_fsb_route(timer)) {
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qemu_irq_lower(s->irqs[route]); |
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} |
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} else if (timer_fsb_route(timer)) { |
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stl_phys(timer->fsb >> 32, timer->fsb & 0xffffffff); |
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} else if (timer->config & HPET_TN_TYPE_LEVEL) { |
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s->isr |= mask; |
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qemu_irq_raise(s->irqs[route]); |
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} else {
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s->isr &= ~mask; |
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qemu_irq_pulse(s->irqs[route]); |
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} |
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} |
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|
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static void hpet_pre_save(void *opaque) |
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{
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HPETState *s = opaque; |
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/* save current counter value */
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s->hpet_counter = hpet_get_ticks(s); |
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} |
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static int hpet_pre_load(void *opaque) |
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{
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HPETState *s = opaque; |
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/* version 1 only supports 3, later versions will load the actual value */
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s->num_timers = HPET_MIN_TIMERS; |
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return 0; |
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} |
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static int hpet_post_load(void *opaque, int version_id) |
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{
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HPETState *s = opaque; |
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/* Recalculate the offset between the main counter and guest time */
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s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); |
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/* Push number of timers into capability returned via HPET_ID */
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s->capability &= ~HPET_ID_NUM_TIM_MASK; |
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s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
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/* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
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s->flags &= ~(1 << HPET_MSI_SUPPORT);
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if (s->timer[0].config & HPET_TN_FSB_CAP) { |
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s->flags |= 1 << HPET_MSI_SUPPORT;
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} |
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return 0; |
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} |
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|
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static const VMStateDescription vmstate_hpet_timer = { |
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.name = "hpet_timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT8(tn, HPETTimer), |
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VMSTATE_UINT64(config, HPETTimer), |
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VMSTATE_UINT64(cmp, HPETTimer), |
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VMSTATE_UINT64(fsb, HPETTimer), |
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VMSTATE_UINT64(period, HPETTimer), |
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VMSTATE_UINT8(wrap_flag, HPETTimer), |
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VMSTATE_TIMER(qemu_timer, HPETTimer), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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static const VMStateDescription vmstate_hpet = { |
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.name = "hpet",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.pre_save = hpet_pre_save, |
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.pre_load = hpet_pre_load, |
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.post_load = hpet_post_load, |
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.fields = (VMStateField []) {
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VMSTATE_UINT64(config, HPETState), |
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VMSTATE_UINT64(isr, HPETState), |
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VMSTATE_UINT64(hpet_counter, HPETState), |
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VMSTATE_UINT8_V(num_timers, HPETState, 2),
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VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
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vmstate_hpet_timer, HPETTimer), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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/*
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* timer expiration callback
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*/
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static void hpet_timer(void *opaque) |
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{
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HPETTimer *t = opaque; |
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uint64_t diff; |
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|
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uint64_t period = t->period; |
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uint64_t cur_tick = hpet_get_ticks(t->state); |
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|
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if (timer_is_periodic(t) && period != 0) { |
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if (t->config & HPET_TN_32BIT) {
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while (hpet_time_after(cur_tick, t->cmp)) {
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t->cmp = (uint32_t)(t->cmp + t->period); |
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} |
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} else {
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while (hpet_time_after64(cur_tick, t->cmp)) {
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t->cmp += period; |
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} |
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} |
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diff = hpet_calculate_diff(t, cur_tick); |
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qemu_mod_timer(t->qemu_timer, |
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qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff)); |
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} else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
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if (t->wrap_flag) {
|
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diff = hpet_calculate_diff(t, cur_tick); |
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qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock) + |
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(int64_t)ticks_to_ns(diff)); |
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t->wrap_flag = 0;
|
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} |
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} |
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update_irq(t, 1);
|
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} |
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|
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static void hpet_set_timer(HPETTimer *t) |
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{
|
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uint64_t diff; |
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uint32_t wrap_diff; /* how many ticks until we wrap? */
|
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uint64_t cur_tick = hpet_get_ticks(t->state); |
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|
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/* whenever new timer is being set up, make sure wrap_flag is 0 */
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t->wrap_flag = 0;
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diff = hpet_calculate_diff(t, cur_tick); |
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|
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/* hpet spec says in one-shot 32-bit mode, generate an interrupt when
|
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* counter wraps in addition to an interrupt with comparator match.
|
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*/
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if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
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wrap_diff = 0xffffffff - (uint32_t)cur_tick;
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if (wrap_diff < (uint32_t)diff) {
|
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diff = wrap_diff; |
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t->wrap_flag = 1;
|
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} |
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} |
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qemu_mod_timer(t->qemu_timer, |
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qemu_get_clock(vm_clock) + (int64_t)ticks_to_ns(diff)); |
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} |
| 334 |
|
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static void hpet_del_timer(HPETTimer *t) |
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{
|
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qemu_del_timer(t->qemu_timer); |
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update_irq(t, 0);
|
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} |
| 340 |
|
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#ifdef HPET_DEBUG
|
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static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr) |
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{
|
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printf("qemu: hpet_read b at %" PRIx64 "\n", addr); |
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return 0; |
| 346 |
} |
| 347 |
|
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static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr) |
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{
|
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printf("qemu: hpet_read w at %" PRIx64 "\n", addr); |
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return 0; |
| 352 |
} |
| 353 |
#endif
|
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|
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static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr) |
| 356 |
{
|
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HPETState *s = opaque; |
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uint64_t cur_tick, index; |
| 359 |
|
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DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
| 361 |
index = addr; |
| 362 |
/*address range of all TN regs*/
|
| 363 |
if (index >= 0x100 && index <= 0x3ff) { |
| 364 |
uint8_t timer_id = (addr - 0x100) / 0x20; |
| 365 |
HPETTimer *timer = &s->timer[timer_id]; |
| 366 |
|
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if (timer_id > s->num_timers) {
|
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DPRINTF("qemu: timer id out of range\n");
|
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return 0; |
| 370 |
} |
| 371 |
|
| 372 |
switch ((addr - 0x100) % 0x20) { |
| 373 |
case HPET_TN_CFG:
|
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return timer->config;
|
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case HPET_TN_CFG + 4: // Interrupt capabilities |
| 376 |
return timer->config >> 32; |
| 377 |
case HPET_TN_CMP: // comparator register |
| 378 |
return timer->cmp;
|
| 379 |
case HPET_TN_CMP + 4: |
| 380 |
return timer->cmp >> 32; |
| 381 |
case HPET_TN_ROUTE:
|
| 382 |
return timer->fsb;
|
| 383 |
case HPET_TN_ROUTE + 4: |
| 384 |
return timer->fsb >> 32; |
| 385 |
default:
|
| 386 |
DPRINTF("qemu: invalid hpet_ram_readl\n");
|
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break;
|
| 388 |
} |
| 389 |
} else {
|
| 390 |
switch (index) {
|
| 391 |
case HPET_ID:
|
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return s->capability;
|
| 393 |
case HPET_PERIOD:
|
| 394 |
return s->capability >> 32; |
| 395 |
case HPET_CFG:
|
| 396 |
return s->config;
|
| 397 |
case HPET_CFG + 4: |
| 398 |
DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
|
| 399 |
return 0; |
| 400 |
case HPET_COUNTER:
|
| 401 |
if (hpet_enabled(s)) {
|
| 402 |
cur_tick = hpet_get_ticks(s); |
| 403 |
} else {
|
| 404 |
cur_tick = s->hpet_counter; |
| 405 |
} |
| 406 |
DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick); |
| 407 |
return cur_tick;
|
| 408 |
case HPET_COUNTER + 4: |
| 409 |
if (hpet_enabled(s)) {
|
| 410 |
cur_tick = hpet_get_ticks(s); |
| 411 |
} else {
|
| 412 |
cur_tick = s->hpet_counter; |
| 413 |
} |
| 414 |
DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); |
| 415 |
return cur_tick >> 32; |
| 416 |
case HPET_STATUS:
|
| 417 |
return s->isr;
|
| 418 |
default:
|
| 419 |
DPRINTF("qemu: invalid hpet_ram_readl\n");
|
| 420 |
break;
|
| 421 |
} |
| 422 |
} |
| 423 |
return 0; |
| 424 |
} |
| 425 |
|
| 426 |
#ifdef HPET_DEBUG
|
| 427 |
static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr, |
| 428 |
uint32_t value) |
| 429 |
{
|
| 430 |
printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n", |
| 431 |
addr, value); |
| 432 |
} |
| 433 |
|
| 434 |
static void hpet_ram_writew(void *opaque, target_phys_addr_t addr, |
| 435 |
uint32_t value) |
| 436 |
{
|
| 437 |
printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n", |
| 438 |
addr, value); |
| 439 |
} |
| 440 |
#endif
|
| 441 |
|
| 442 |
static void hpet_ram_writel(void *opaque, target_phys_addr_t addr, |
| 443 |
uint32_t value) |
| 444 |
{
|
| 445 |
int i;
|
| 446 |
HPETState *s = opaque; |
| 447 |
uint64_t old_val, new_val, val, index; |
| 448 |
|
| 449 |
DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
| 450 |
index = addr; |
| 451 |
old_val = hpet_ram_readl(opaque, addr); |
| 452 |
new_val = value; |
| 453 |
|
| 454 |
/*address range of all TN regs*/
|
| 455 |
if (index >= 0x100 && index <= 0x3ff) { |
| 456 |
uint8_t timer_id = (addr - 0x100) / 0x20; |
| 457 |
HPETTimer *timer = &s->timer[timer_id]; |
| 458 |
|
| 459 |
DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
|
| 460 |
if (timer_id > s->num_timers) {
|
| 461 |
DPRINTF("qemu: timer id out of range\n");
|
| 462 |
return;
|
| 463 |
} |
| 464 |
switch ((addr - 0x100) % 0x20) { |
| 465 |
case HPET_TN_CFG:
|
| 466 |
DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
|
| 467 |
if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
|
| 468 |
update_irq(timer, 0);
|
| 469 |
} |
| 470 |
val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); |
| 471 |
timer->config = (timer->config & 0xffffffff00000000ULL) | val;
|
| 472 |
if (new_val & HPET_TN_32BIT) {
|
| 473 |
timer->cmp = (uint32_t)timer->cmp; |
| 474 |
timer->period = (uint32_t)timer->period; |
| 475 |
} |
| 476 |
if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
|
| 477 |
hpet_set_timer(timer); |
| 478 |
} else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) { |
| 479 |
hpet_del_timer(timer); |
| 480 |
} |
| 481 |
break;
|
| 482 |
case HPET_TN_CFG + 4: // Interrupt capabilities |
| 483 |
DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
|
| 484 |
break;
|
| 485 |
case HPET_TN_CMP: // comparator register |
| 486 |
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
|
| 487 |
if (timer->config & HPET_TN_32BIT) {
|
| 488 |
new_val = (uint32_t)new_val; |
| 489 |
} |
| 490 |
if (!timer_is_periodic(timer)
|
| 491 |
|| (timer->config & HPET_TN_SETVAL)) {
|
| 492 |
timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
|
| 493 |
} |
| 494 |
if (timer_is_periodic(timer)) {
|
| 495 |
/*
|
| 496 |
* FIXME: Clamp period to reasonable min value?
|
| 497 |
* Clamp period to reasonable max value
|
| 498 |
*/
|
| 499 |
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
| 500 |
timer->period = |
| 501 |
(timer->period & 0xffffffff00000000ULL) | new_val;
|
| 502 |
} |
| 503 |
timer->config &= ~HPET_TN_SETVAL; |
| 504 |
if (hpet_enabled(s)) {
|
| 505 |
hpet_set_timer(timer); |
| 506 |
} |
| 507 |
break;
|
| 508 |
case HPET_TN_CMP + 4: // comparator register high order |
| 509 |
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
|
| 510 |
if (!timer_is_periodic(timer)
|
| 511 |
|| (timer->config & HPET_TN_SETVAL)) {
|
| 512 |
timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32; |
| 513 |
} else {
|
| 514 |
/*
|
| 515 |
* FIXME: Clamp period to reasonable min value?
|
| 516 |
* Clamp period to reasonable max value
|
| 517 |
*/
|
| 518 |
new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; |
| 519 |
timer->period = |
| 520 |
(timer->period & 0xffffffffULL) | new_val << 32; |
| 521 |
} |
| 522 |
timer->config &= ~HPET_TN_SETVAL; |
| 523 |
if (hpet_enabled(s)) {
|
| 524 |
hpet_set_timer(timer); |
| 525 |
} |
| 526 |
break;
|
| 527 |
case HPET_TN_ROUTE:
|
| 528 |
timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
|
| 529 |
break;
|
| 530 |
case HPET_TN_ROUTE + 4: |
| 531 |
timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff); |
| 532 |
break;
|
| 533 |
default:
|
| 534 |
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
| 535 |
break;
|
| 536 |
} |
| 537 |
return;
|
| 538 |
} else {
|
| 539 |
switch (index) {
|
| 540 |
case HPET_ID:
|
| 541 |
return;
|
| 542 |
case HPET_CFG:
|
| 543 |
val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); |
| 544 |
s->config = (s->config & 0xffffffff00000000ULL) | val;
|
| 545 |
if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
|
| 546 |
/* Enable main counter and interrupt generation. */
|
| 547 |
s->hpet_offset = |
| 548 |
ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock); |
| 549 |
for (i = 0; i < s->num_timers; i++) { |
| 550 |
if ((&s->timer[i])->cmp != ~0ULL) { |
| 551 |
hpet_set_timer(&s->timer[i]); |
| 552 |
} |
| 553 |
} |
| 554 |
} else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
| 555 |
/* Halt main counter and disable interrupt generation. */
|
| 556 |
s->hpet_counter = hpet_get_ticks(s); |
| 557 |
for (i = 0; i < s->num_timers; i++) { |
| 558 |
hpet_del_timer(&s->timer[i]); |
| 559 |
} |
| 560 |
} |
| 561 |
/* i8254 and RTC are disabled when HPET is in legacy mode */
|
| 562 |
if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
|
| 563 |
hpet_pit_disable(); |
| 564 |
qemu_irq_lower(s->irqs[RTC_ISA_IRQ]); |
| 565 |
} else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
| 566 |
hpet_pit_enable(); |
| 567 |
qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level); |
| 568 |
} |
| 569 |
break;
|
| 570 |
case HPET_CFG + 4: |
| 571 |
DPRINTF("qemu: invalid HPET_CFG+4 write \n");
|
| 572 |
break;
|
| 573 |
case HPET_STATUS:
|
| 574 |
val = new_val & s->isr; |
| 575 |
for (i = 0; i < s->num_timers; i++) { |
| 576 |
if (val & (1 << i)) { |
| 577 |
update_irq(&s->timer[i], 0);
|
| 578 |
} |
| 579 |
} |
| 580 |
break;
|
| 581 |
case HPET_COUNTER:
|
| 582 |
if (hpet_enabled(s)) {
|
| 583 |
DPRINTF("qemu: Writing counter while HPET enabled!\n");
|
| 584 |
} |
| 585 |
s->hpet_counter = |
| 586 |
(s->hpet_counter & 0xffffffff00000000ULL) | value;
|
| 587 |
DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", |
| 588 |
value, s->hpet_counter); |
| 589 |
break;
|
| 590 |
case HPET_COUNTER + 4: |
| 591 |
if (hpet_enabled(s)) {
|
| 592 |
DPRINTF("qemu: Writing counter while HPET enabled!\n");
|
| 593 |
} |
| 594 |
s->hpet_counter = |
| 595 |
(s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32); |
| 596 |
DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", |
| 597 |
value, s->hpet_counter); |
| 598 |
break;
|
| 599 |
default:
|
| 600 |
DPRINTF("qemu: invalid hpet_ram_writel\n");
|
| 601 |
break;
|
| 602 |
} |
| 603 |
} |
| 604 |
} |
| 605 |
|
| 606 |
static CPUReadMemoryFunc * const hpet_ram_read[] = { |
| 607 |
#ifdef HPET_DEBUG
|
| 608 |
hpet_ram_readb, |
| 609 |
hpet_ram_readw, |
| 610 |
#else
|
| 611 |
NULL,
|
| 612 |
NULL,
|
| 613 |
#endif
|
| 614 |
hpet_ram_readl, |
| 615 |
}; |
| 616 |
|
| 617 |
static CPUWriteMemoryFunc * const hpet_ram_write[] = { |
| 618 |
#ifdef HPET_DEBUG
|
| 619 |
hpet_ram_writeb, |
| 620 |
hpet_ram_writew, |
| 621 |
#else
|
| 622 |
NULL,
|
| 623 |
NULL,
|
| 624 |
#endif
|
| 625 |
hpet_ram_writel, |
| 626 |
}; |
| 627 |
|
| 628 |
static void hpet_reset(DeviceState *d) |
| 629 |
{
|
| 630 |
HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d)); |
| 631 |
int i;
|
| 632 |
static int count = 0; |
| 633 |
|
| 634 |
for (i = 0; i < s->num_timers; i++) { |
| 635 |
HPETTimer *timer = &s->timer[i]; |
| 636 |
|
| 637 |
hpet_del_timer(timer); |
| 638 |
timer->cmp = ~0ULL;
|
| 639 |
timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
| 640 |
if (s->flags & (1 << HPET_MSI_SUPPORT)) { |
| 641 |
timer->config |= HPET_TN_FSB_CAP; |
| 642 |
} |
| 643 |
/* advertise availability of ioapic inti2 */
|
| 644 |
timer->config |= 0x00000004ULL << 32; |
| 645 |
timer->period = 0ULL;
|
| 646 |
timer->wrap_flag = 0;
|
| 647 |
} |
| 648 |
|
| 649 |
s->hpet_counter = 0ULL;
|
| 650 |
s->hpet_offset = 0ULL;
|
| 651 |
s->config = 0ULL;
|
| 652 |
if (count > 0) { |
| 653 |
/* we don't enable pit when hpet_reset is first called (by hpet_init)
|
| 654 |
* because hpet is taking over for pit here. On subsequent invocations,
|
| 655 |
* hpet_reset is called due to system reset. At this point control must
|
| 656 |
* be returned to pit until SW reenables hpet.
|
| 657 |
*/
|
| 658 |
hpet_pit_enable(); |
| 659 |
} |
| 660 |
count = 1;
|
| 661 |
} |
| 662 |
|
| 663 |
static void hpet_handle_rtc_irq(void *opaque, int n, int level) |
| 664 |
{
|
| 665 |
HPETState *s = FROM_SYSBUS(HPETState, opaque); |
| 666 |
|
| 667 |
s->rtc_irq_level = level; |
| 668 |
if (!hpet_in_legacy_mode(s)) {
|
| 669 |
qemu_set_irq(s->irqs[RTC_ISA_IRQ], level); |
| 670 |
} |
| 671 |
} |
| 672 |
|
| 673 |
static int hpet_init(SysBusDevice *dev) |
| 674 |
{
|
| 675 |
HPETState *s = FROM_SYSBUS(HPETState, dev); |
| 676 |
int i, iomemtype;
|
| 677 |
HPETTimer *timer; |
| 678 |
|
| 679 |
for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) { |
| 680 |
sysbus_init_irq(dev, &s->irqs[i]); |
| 681 |
} |
| 682 |
|
| 683 |
if (s->num_timers < HPET_MIN_TIMERS) {
|
| 684 |
s->num_timers = HPET_MIN_TIMERS; |
| 685 |
} else if (s->num_timers > HPET_MAX_TIMERS) { |
| 686 |
s->num_timers = HPET_MAX_TIMERS; |
| 687 |
} |
| 688 |
for (i = 0; i < HPET_MAX_TIMERS; i++) { |
| 689 |
timer = &s->timer[i]; |
| 690 |
timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer); |
| 691 |
timer->tn = i; |
| 692 |
timer->state = s; |
| 693 |
} |
| 694 |
|
| 695 |
/* 64-bit main counter; LegacyReplacementRoute. */
|
| 696 |
s->capability = 0x8086a001ULL;
|
| 697 |
s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
|
| 698 |
s->capability |= ((HPET_CLK_PERIOD) << 32);
|
| 699 |
|
| 700 |
isa_reserve_irq(RTC_ISA_IRQ); |
| 701 |
qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
|
| 702 |
|
| 703 |
/* HPET Area */
|
| 704 |
iomemtype = cpu_register_io_memory(hpet_ram_read, |
| 705 |
hpet_ram_write, s); |
| 706 |
sysbus_init_mmio(dev, 0x400, iomemtype);
|
| 707 |
return 0; |
| 708 |
} |
| 709 |
|
| 710 |
static SysBusDeviceInfo hpet_device_info = {
|
| 711 |
.qdev.name = "hpet",
|
| 712 |
.qdev.size = sizeof(HPETState),
|
| 713 |
.qdev.no_user = 1,
|
| 714 |
.qdev.vmsd = &vmstate_hpet, |
| 715 |
.qdev.reset = hpet_reset, |
| 716 |
.init = hpet_init, |
| 717 |
.qdev.props = (Property[]) {
|
| 718 |
DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
|
| 719 |
DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false), |
| 720 |
DEFINE_PROP_END_OF_LIST(), |
| 721 |
}, |
| 722 |
}; |
| 723 |
|
| 724 |
static void hpet_register_device(void) |
| 725 |
{
|
| 726 |
sysbus_register_withprop(&hpet_device_info); |
| 727 |
} |
| 728 |
|
| 729 |
device_init(hpet_register_device) |