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1
/*
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 *  PowerPC emulation for qemu: main translation routines.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
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 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20
#include <stdarg.h>
21
#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
25

    
26
#include "cpu.h"
27
#include "exec-all.h"
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#include "disas.h"
29

    
30
/* Include definitions for instructions classes and implementations flags */
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//#define DO_SINGLE_STEP
32
//#define PPC_DEBUG_DISAS
33
//#define DEBUG_MEMORY_ACCESSES
34
//#define DO_PPC_STATISTICS
35
//#define OPTIMIZE_FPRF_UPDATE
36

    
37
/*****************************************************************************/
38
/* Code translation helpers                                                  */
39
#if defined(USE_DIRECT_JUMP)
40
#define TBPARAM(x)
41
#else
42
#define TBPARAM(x) (long)(x)
43
#endif
44

    
45
enum {
46
#define DEF(s, n, copy_size) INDEX_op_ ## s,
47
#include "opc.h"
48
#undef DEF
49
    NB_OPS,
50
};
51

    
52
static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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#if defined(OPTIMIZE_FPRF_UPDATE)
55
static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
56
static uint16_t **gen_fprf_ptr;
57
#endif
58

    
59
#include "gen-op.h"
60

    
61
static always_inline void gen_set_T0 (target_ulong val)
62
{
63
#if defined(TARGET_PPC64)
64
    if (val >> 32)
65
        gen_op_set_T0_64(val >> 32, val);
66
    else
67
#endif
68
        gen_op_set_T0(val);
69
}
70

    
71
static always_inline void gen_set_T1 (target_ulong val)
72
{
73
#if defined(TARGET_PPC64)
74
    if (val >> 32)
75
        gen_op_set_T1_64(val >> 32, val);
76
    else
77
#endif
78
        gen_op_set_T1(val);
79
}
80

    
81
#define GEN8(func, NAME)                                                      \
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static GenOpFunc *NAME ## _table [8] = {                                      \
83
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
85
};                                                                            \
86
static always_inline void func (int n)                                        \
87
{                                                                             \
88
    NAME ## _table[n]();                                                      \
89
}
90

    
91
#define GEN16(func, NAME)                                                     \
92
static GenOpFunc *NAME ## _table [16] = {                                     \
93
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
95
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
96
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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};                                                                            \
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static always_inline void func (int n)                                        \
99
{                                                                             \
100
    NAME ## _table[n]();                                                      \
101
}
102

    
103
#define GEN32(func, NAME)                                                     \
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static GenOpFunc *NAME ## _table [32] = {                                     \
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
110
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
111
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
112
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
113
};                                                                            \
114
static always_inline void func (int n)                                        \
115
{                                                                             \
116
    NAME ## _table[n]();                                                      \
117
}
118

    
119
/* Condition register moves */
120
GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
121
GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
122
GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
123
#if 0 // Unused
124
GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
125
#endif
126

    
127
/* General purpose registers moves */
128
GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
129
GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
130
GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
131

    
132
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
133
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
134
#if 0 // unused
135
GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
136
#endif
137

    
138
/* floating point registers moves */
139
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
140
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
141
GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
142
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
143
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
144
#if 0 // unused
145
GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
146
#endif
147

    
148
/* internal defines */
149
typedef struct DisasContext {
150
    struct TranslationBlock *tb;
151
    target_ulong nip;
152
    uint32_t opcode;
153
    uint32_t exception;
154
    /* Routine used to access memory */
155
    int mem_idx;
156
    /* Translation flags */
157
#if !defined(CONFIG_USER_ONLY)
158
    int supervisor;
159
#endif
160
#if defined(TARGET_PPC64)
161
    int sf_mode;
162
#endif
163
    int fpu_enabled;
164
    int altivec_enabled;
165
#if defined(TARGET_PPCEMB)
166
    int spe_enabled;
167
#endif
168
    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
169
    int singlestep_enabled;
170
    int dcache_line_size;
171
} DisasContext;
172

    
173
struct opc_handler_t {
174
    /* invalid bits */
175
    uint32_t inval;
176
    /* instruction type */
177
    uint64_t type;
178
    /* handler */
179
    void (*handler)(DisasContext *ctx);
180
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
181
    const unsigned char *oname;
182
#endif
183
#if defined(DO_PPC_STATISTICS)
184
    uint64_t count;
185
#endif
186
};
187

    
188
static always_inline void gen_set_Rc0 (DisasContext *ctx)
189
{
190
#if defined(TARGET_PPC64)
191
    if (ctx->sf_mode)
192
        gen_op_cmpi_64(0);
193
    else
194
#endif
195
        gen_op_cmpi(0);
196
    gen_op_set_Rc0();
197
}
198

    
199
static always_inline void gen_reset_fpstatus (void)
200
{
201
#ifdef CONFIG_SOFTFLOAT
202
    gen_op_reset_fpstatus();
203
#endif
204
}
205

    
206
static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
207
{
208
    if (set_fprf != 0) {
209
        /* This case might be optimized later */
210
#if defined(OPTIMIZE_FPRF_UPDATE)
211
        *gen_fprf_ptr++ = gen_opc_ptr;
212
#endif
213
        gen_op_compute_fprf(1);
214
        if (unlikely(set_rc))
215
            gen_op_store_T0_crf(1);
216
        gen_op_float_check_status();
217
    } else if (unlikely(set_rc)) {
218
        /* We always need to compute fpcc */
219
        gen_op_compute_fprf(0);
220
        gen_op_store_T0_crf(1);
221
        if (set_fprf)
222
            gen_op_float_check_status();
223
    }
224
}
225

    
226
static always_inline void gen_optimize_fprf (void)
227
{
228
#if defined(OPTIMIZE_FPRF_UPDATE)
229
    uint16_t **ptr;
230

    
231
    for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
232
        *ptr = INDEX_op_nop1;
233
    gen_fprf_ptr = gen_fprf_buf;
234
#endif
235
}
236

    
237
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
238
{
239
#if defined(TARGET_PPC64)
240
    if (ctx->sf_mode)
241
        gen_op_update_nip_64(nip >> 32, nip);
242
    else
243
#endif
244
        gen_op_update_nip(nip);
245
}
246

    
247
#define GEN_EXCP(ctx, excp, error)                                            \
248
do {                                                                          \
249
    if ((ctx)->exception == POWERPC_EXCP_NONE) {                              \
250
        gen_update_nip(ctx, (ctx)->nip);                                      \
251
    }                                                                         \
252
    gen_op_raise_exception_err((excp), (error));                              \
253
    ctx->exception = (excp);                                                  \
254
} while (0)
255

    
256
#define GEN_EXCP_INVAL(ctx)                                                   \
257
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
258
         POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
259

    
260
#define GEN_EXCP_PRIVOPC(ctx)                                                 \
261
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
262
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
263

    
264
#define GEN_EXCP_PRIVREG(ctx)                                                 \
265
GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \
266
         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
267

    
268
#define GEN_EXCP_NO_FP(ctx)                                                   \
269
GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
270

    
271
#define GEN_EXCP_NO_AP(ctx)                                                   \
272
GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
273

    
274
#define GEN_EXCP_NO_VR(ctx)                                                   \
275
GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
276

    
277
/* Stop translation */
278
static always_inline void GEN_STOP (DisasContext *ctx)
279
{
280
    gen_update_nip(ctx, ctx->nip);
281
    ctx->exception = POWERPC_EXCP_STOP;
282
}
283

    
284
/* No need to update nip here, as execution flow will change */
285
static always_inline void GEN_SYNC (DisasContext *ctx)
286
{
287
    ctx->exception = POWERPC_EXCP_SYNC;
288
}
289

    
290
#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
291
static void gen_##name (DisasContext *ctx);                                   \
292
GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \
293
static void gen_##name (DisasContext *ctx)
294

    
295
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
296
static void gen_##name (DisasContext *ctx);                                   \
297
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \
298
static void gen_##name (DisasContext *ctx)
299

    
300
typedef struct opcode_t {
301
    unsigned char opc1, opc2, opc3;
302
#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
303
    unsigned char pad[5];
304
#else
305
    unsigned char pad[1];
306
#endif
307
    opc_handler_t handler;
308
    const unsigned char *oname;
309
} opcode_t;
310

    
311
/*****************************************************************************/
312
/***                           Instruction decoding                        ***/
313
#define EXTRACT_HELPER(name, shift, nb)                                       \
314
static always_inline uint32_t name (uint32_t opcode)                          \
315
{                                                                             \
316
    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
317
}
318

    
319
#define EXTRACT_SHELPER(name, shift, nb)                                      \
320
static always_inline int32_t name (uint32_t opcode)                           \
321
{                                                                             \
322
    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
323
}
324

    
325
/* Opcode part 1 */
326
EXTRACT_HELPER(opc1, 26, 6);
327
/* Opcode part 2 */
328
EXTRACT_HELPER(opc2, 1, 5);
329
/* Opcode part 3 */
330
EXTRACT_HELPER(opc3, 6, 5);
331
/* Update Cr0 flags */
332
EXTRACT_HELPER(Rc, 0, 1);
333
/* Destination */
334
EXTRACT_HELPER(rD, 21, 5);
335
/* Source */
336
EXTRACT_HELPER(rS, 21, 5);
337
/* First operand */
338
EXTRACT_HELPER(rA, 16, 5);
339
/* Second operand */
340
EXTRACT_HELPER(rB, 11, 5);
341
/* Third operand */
342
EXTRACT_HELPER(rC, 6, 5);
343
/***                               Get CRn                                 ***/
344
EXTRACT_HELPER(crfD, 23, 3);
345
EXTRACT_HELPER(crfS, 18, 3);
346
EXTRACT_HELPER(crbD, 21, 5);
347
EXTRACT_HELPER(crbA, 16, 5);
348
EXTRACT_HELPER(crbB, 11, 5);
349
/* SPR / TBL */
350
EXTRACT_HELPER(_SPR, 11, 10);
351
static always_inline uint32_t SPR (uint32_t opcode)
352
{
353
    uint32_t sprn = _SPR(opcode);
354

    
355
    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
356
}
357
/***                              Get constants                            ***/
358
EXTRACT_HELPER(IMM, 12, 8);
359
/* 16 bits signed immediate value */
360
EXTRACT_SHELPER(SIMM, 0, 16);
361
/* 16 bits unsigned immediate value */
362
EXTRACT_HELPER(UIMM, 0, 16);
363
/* Bit count */
364
EXTRACT_HELPER(NB, 11, 5);
365
/* Shift count */
366
EXTRACT_HELPER(SH, 11, 5);
367
/* Mask start */
368
EXTRACT_HELPER(MB, 6, 5);
369
/* Mask end */
370
EXTRACT_HELPER(ME, 1, 5);
371
/* Trap operand */
372
EXTRACT_HELPER(TO, 21, 5);
373

    
374
EXTRACT_HELPER(CRM, 12, 8);
375
EXTRACT_HELPER(FM, 17, 8);
376
EXTRACT_HELPER(SR, 16, 4);
377
EXTRACT_HELPER(FPIMM, 20, 4);
378

    
379
/***                            Jump target decoding                       ***/
380
/* Displacement */
381
EXTRACT_SHELPER(d, 0, 16);
382
/* Immediate address */
383
static always_inline target_ulong LI (uint32_t opcode)
384
{
385
    return (opcode >> 0) & 0x03FFFFFC;
386
}
387

    
388
static always_inline uint32_t BD (uint32_t opcode)
389
{
390
    return (opcode >> 0) & 0xFFFC;
391
}
392

    
393
EXTRACT_HELPER(BO, 21, 5);
394
EXTRACT_HELPER(BI, 16, 5);
395
/* Absolute/relative address */
396
EXTRACT_HELPER(AA, 1, 1);
397
/* Link */
398
EXTRACT_HELPER(LK, 0, 1);
399

    
400
/* Create a mask between <start> and <end> bits */
401
static always_inline target_ulong MASK (uint32_t start, uint32_t end)
402
{
403
    target_ulong ret;
404

    
405
#if defined(TARGET_PPC64)
406
    if (likely(start == 0)) {
407
        ret = (uint64_t)(-1ULL) << (63 - end);
408
    } else if (likely(end == 63)) {
409
        ret = (uint64_t)(-1ULL) >> start;
410
    }
411
#else
412
    if (likely(start == 0)) {
413
        ret = (uint32_t)(-1ULL) << (31  - end);
414
    } else if (likely(end == 31)) {
415
        ret = (uint32_t)(-1ULL) >> start;
416
    }
417
#endif
418
    else {
419
        ret = (((target_ulong)(-1ULL)) >> (start)) ^
420
            (((target_ulong)(-1ULL) >> (end)) >> 1);
421
        if (unlikely(start > end))
422
            return ~ret;
423
    }
424

    
425
    return ret;
426
}
427

    
428
/*****************************************************************************/
429
/* PowerPC Instructions types definitions                                    */
430
enum {
431
    PPC_NONE          = 0x0000000000000000ULL,
432
    /* PowerPC base instructions set                                         */
433
    PPC_INSNS_BASE    = 0x0000000000000001ULL,
434
    /* integer operations instructions                                       */
435
#define PPC_INTEGER PPC_INSNS_BASE
436
    /* flow control instructions                                             */
437
#define PPC_FLOW    PPC_INSNS_BASE
438
    /* virtual memory instructions                                           */
439
#define PPC_MEM     PPC_INSNS_BASE
440
    /* ld/st with reservation instructions                                   */
441
#define PPC_RES     PPC_INSNS_BASE
442
    /* cache control instructions                                            */
443
#define PPC_CACHE   PPC_INSNS_BASE
444
    /* spr/msr access instructions                                           */
445
#define PPC_MISC    PPC_INSNS_BASE
446
    /* Optional floating point instructions                                  */
447
    PPC_FLOAT         = 0x0000000000000002ULL,
448
    PPC_FLOAT_FSQRT   = 0x0000000000000004ULL,
449
    PPC_FLOAT_FRES    = 0x0000000000000008ULL,
450
    PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,
451
    PPC_FLOAT_FSEL    = 0x0000000000000020ULL,
452
    PPC_FLOAT_STFIWX  = 0x0000000000000040ULL,
453
    /* external control instructions                                         */
454
    PPC_EXTERN        = 0x0000000000000080ULL,
455
    /* segment register access instructions                                  */
456
    PPC_SEGMENT       = 0x0000000000000100ULL,
457
    /* Optional cache control instruction                                    */
458
    PPC_CACHE_DCBA    = 0x0000000000000200ULL,
459
    /* Optional memory control instructions                                  */
460
    PPC_MEM_TLBIA     = 0x0000000000000400ULL,
461
    PPC_MEM_TLBIE     = 0x0000000000000800ULL,
462
    PPC_MEM_TLBSYNC   = 0x0000000000001000ULL,
463
    /* eieio & sync                                                          */
464
    PPC_MEM_SYNC      = 0x0000000000002000ULL,
465
    /* PowerPC 6xx TLB management instructions                               */
466
    PPC_6xx_TLB       = 0x0000000000004000ULL,
467
    /* Altivec support                                                       */
468
    PPC_ALTIVEC       = 0x0000000000008000ULL,
469
    /* Time base mftb instruction                                            */
470
    PPC_MFTB          = 0x0000000000010000ULL,
471
    /* Embedded PowerPC dedicated instructions                               */
472
    PPC_EMB_COMMON    = 0x0000000000020000ULL,
473
    /* PowerPC 40x exception model                                           */
474
    PPC_40x_EXCP      = 0x0000000000040000ULL,
475
    /* PowerPC 40x TLB management instructions                               */
476
    PPC_40x_TLB       = 0x0000000000080000ULL,
477
    /* PowerPC 405 Mac instructions                                          */
478
    PPC_405_MAC       = 0x0000000000100000ULL,
479
    /* PowerPC 440 specific instructions                                     */
480
    PPC_440_SPEC      = 0x0000000000200000ULL,
481
    /* Power-to-PowerPC bridge (601)                                         */
482
    PPC_POWER_BR      = 0x0000000000400000ULL,
483
    /* PowerPC 602 specific                                                  */
484
    PPC_602_SPEC      = 0x0000000000800000ULL,
485
    /* Deprecated instructions                                               */
486
    /* Original POWER instruction set                                        */
487
    PPC_POWER         = 0x0000000001000000ULL,
488
    /* POWER2 instruction set extension                                      */
489
    PPC_POWER2        = 0x0000000002000000ULL,
490
    /* Power RTC support                                                     */
491
    PPC_POWER_RTC     = 0x0000000004000000ULL,
492
    /* 64 bits PowerPC instruction set                                       */
493
    PPC_64B           = 0x0000000008000000ULL,
494
    /* 64 bits hypervisor extensions                                         */
495
    PPC_64H           = 0x0000000010000000ULL,
496
    /* segment register access instructions for PowerPC 64 "bridge"          */
497
    PPC_SEGMENT_64B   = 0x0000000020000000ULL,
498
    /* BookE (embedded) PowerPC specification                                */
499
    PPC_BOOKE         = 0x0000000040000000ULL,
500
    /* eieio                                                                 */
501
    PPC_MEM_EIEIO     = 0x0000000080000000ULL,
502
    /* e500 vector instructions                                              */
503
    PPC_E500_VECTOR   = 0x0000000100000000ULL,
504
    /* PowerPC 4xx dedicated instructions                                    */
505
    PPC_4xx_COMMON    = 0x0000000200000000ULL,
506
    /* PowerPC 2.03 specification extensions                                 */
507
    PPC_203           = 0x0000000400000000ULL,
508
    /* PowerPC 2.03 SPE extension                                            */
509
    PPC_SPE           = 0x0000000800000000ULL,
510
    /* PowerPC 2.03 SPE floating-point extension                             */
511
    PPC_SPEFPU        = 0x0000001000000000ULL,
512
    /* SLB management                                                        */
513
    PPC_SLBI          = 0x0000002000000000ULL,
514
    /* PowerPC 40x ibct instructions                                         */
515
    PPC_40x_ICBT      = 0x0000004000000000ULL,
516
    /* PowerPC 74xx TLB management instructions                              */
517
    PPC_74xx_TLB      = 0x0000008000000000ULL,
518
    /* More BookE (embedded) instructions...                                 */
519
    PPC_BOOKE_EXT     = 0x0000010000000000ULL,
520
    /* rfmci is not implemented in all BookE PowerPC                         */
521
    PPC_RFMCI         = 0x0000020000000000ULL,
522
    /* user-mode DCR access, implemented in PowerPC 460                      */
523
    PPC_DCRUX         = 0x0000040000000000ULL,
524
    /* New floating-point extensions (PowerPC 2.0x)                          */
525
    PPC_FLOAT_EXT     = 0x0000080000000000ULL,
526
    /* New wait instruction (PowerPC 2.0x)                                   */
527
    PPC_WAIT          = 0x0000100000000000ULL,
528
    /* New 64 bits extensions (PowerPC 2.0x)                                 */
529
    PPC_64BX          = 0x0000200000000000ULL,
530
    /* dcbz instruction with fixed cache line size                           */
531
    PPC_CACHE_DCBZ    = 0x0000400000000000ULL,
532
    /* dcbz instruction with tunable cache line size                         */
533
    PPC_CACHE_DCBZT   = 0x0000800000000000ULL,
534
    /* frsqrtes extension                                                    */
535
    PPC_FLOAT_FRSQRTES = 0x0001000000000000ULL,
536
};
537

    
538
/*****************************************************************************/
539
/* PowerPC instructions table                                                */
540
#if HOST_LONG_BITS == 64
541
#define OPC_ALIGN 8
542
#else
543
#define OPC_ALIGN 4
544
#endif
545
#if defined(__APPLE__)
546
#define OPCODES_SECTION                                                       \
547
    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
548
#else
549
#define OPCODES_SECTION                                                       \
550
    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
551
#endif
552

    
553
#if defined(DO_PPC_STATISTICS)
554
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
555
OPCODES_SECTION opcode_t opc_##name = {                                       \
556
    .opc1 = op1,                                                              \
557
    .opc2 = op2,                                                              \
558
    .opc3 = op3,                                                              \
559
    .pad  = { 0, },                                                           \
560
    .handler = {                                                              \
561
        .inval   = invl,                                                      \
562
        .type = _typ,                                                         \
563
        .handler = &gen_##name,                                               \
564
        .oname = stringify(name),                                             \
565
    },                                                                        \
566
    .oname = stringify(name),                                                 \
567
}
568
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
569
OPCODES_SECTION opcode_t opc_##name = {                                       \
570
    .opc1 = op1,                                                              \
571
    .opc2 = op2,                                                              \
572
    .opc3 = op3,                                                              \
573
    .pad  = { 0, },                                                           \
574
    .handler = {                                                              \
575
        .inval   = invl,                                                      \
576
        .type = _typ,                                                         \
577
        .handler = &gen_##name,                                               \
578
        .oname = onam,                                                        \
579
    },                                                                        \
580
    .oname = onam,                                                            \
581
}
582
#else
583
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \
584
OPCODES_SECTION opcode_t opc_##name = {                                       \
585
    .opc1 = op1,                                                              \
586
    .opc2 = op2,                                                              \
587
    .opc3 = op3,                                                              \
588
    .pad  = { 0, },                                                           \
589
    .handler = {                                                              \
590
        .inval   = invl,                                                      \
591
        .type = _typ,                                                         \
592
        .handler = &gen_##name,                                               \
593
    },                                                                        \
594
    .oname = stringify(name),                                                 \
595
}
596
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \
597
OPCODES_SECTION opcode_t opc_##name = {                                       \
598
    .opc1 = op1,                                                              \
599
    .opc2 = op2,                                                              \
600
    .opc3 = op3,                                                              \
601
    .pad  = { 0, },                                                           \
602
    .handler = {                                                              \
603
        .inval   = invl,                                                      \
604
        .type = _typ,                                                         \
605
        .handler = &gen_##name,                                               \
606
    },                                                                        \
607
    .oname = onam,                                                            \
608
}
609
#endif
610

    
611
#define GEN_OPCODE_MARK(name)                                                 \
612
OPCODES_SECTION opcode_t opc_##name = {                                       \
613
    .opc1 = 0xFF,                                                             \
614
    .opc2 = 0xFF,                                                             \
615
    .opc3 = 0xFF,                                                             \
616
    .pad  = { 0, },                                                           \
617
    .handler = {                                                              \
618
        .inval   = 0x00000000,                                                \
619
        .type = 0x00,                                                         \
620
        .handler = NULL,                                                      \
621
    },                                                                        \
622
    .oname = stringify(name),                                                 \
623
}
624

    
625
/* Start opcode list */
626
GEN_OPCODE_MARK(start);
627

    
628
/* Invalid instruction */
629
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
630
{
631
    GEN_EXCP_INVAL(ctx);
632
}
633

    
634
static opc_handler_t invalid_handler = {
635
    .inval   = 0xFFFFFFFF,
636
    .type    = PPC_NONE,
637
    .handler = gen_invalid,
638
};
639

    
640
/***                           Integer arithmetic                          ***/
641
#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type)                 \
642
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
643
{                                                                             \
644
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
645
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
646
    gen_op_##name();                                                          \
647
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
648
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
649
        gen_set_Rc0(ctx);                                                     \
650
}
651

    
652
#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type)               \
653
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
654
{                                                                             \
655
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
656
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
657
    gen_op_##name();                                                          \
658
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
659
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
660
        gen_set_Rc0(ctx);                                                     \
661
}
662

    
663
#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                        \
664
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
665
{                                                                             \
666
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
667
    gen_op_##name();                                                          \
668
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
669
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
670
        gen_set_Rc0(ctx);                                                     \
671
}
672
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type)                      \
673
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
674
{                                                                             \
675
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
676
    gen_op_##name();                                                          \
677
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
678
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
679
        gen_set_Rc0(ctx);                                                     \
680
}
681

    
682
/* Two operands arithmetic functions */
683
#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type)                          \
684
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type)                    \
685
__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
686

    
687
/* Two operands arithmetic functions with no overflow allowed */
688
#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type)                          \
689
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
690

    
691
/* One operand arithmetic functions */
692
#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                          \
693
__GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                                \
694
__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
695

    
696
#if defined(TARGET_PPC64)
697
#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type)              \
698
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
699
{                                                                             \
700
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
701
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
702
    if (ctx->sf_mode)                                                         \
703
        gen_op_##name##_64();                                                 \
704
    else                                                                      \
705
        gen_op_##name();                                                      \
706
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
707
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
708
        gen_set_Rc0(ctx);                                                     \
709
}
710

    
711
#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type)            \
712
GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
713
{                                                                             \
714
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
715
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
716
    if (ctx->sf_mode)                                                         \
717
        gen_op_##name##_64();                                                 \
718
    else                                                                      \
719
        gen_op_##name();                                                      \
720
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
721
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
722
        gen_set_Rc0(ctx);                                                     \
723
}
724

    
725
#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                     \
726
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
727
{                                                                             \
728
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
729
    if (ctx->sf_mode)                                                         \
730
        gen_op_##name##_64();                                                 \
731
    else                                                                      \
732
        gen_op_##name();                                                      \
733
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
734
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
735
        gen_set_Rc0(ctx);                                                     \
736
}
737
#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type)                   \
738
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
739
{                                                                             \
740
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
741
    if (ctx->sf_mode)                                                         \
742
        gen_op_##name##_64();                                                 \
743
    else                                                                      \
744
        gen_op_##name();                                                      \
745
    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
746
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
747
        gen_set_Rc0(ctx);                                                     \
748
}
749

    
750
/* Two operands arithmetic functions */
751
#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type)                       \
752
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type)                 \
753
__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
754

    
755
/* Two operands arithmetic functions with no overflow allowed */
756
#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type)                       \
757
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
758

    
759
/* One operand arithmetic functions */
760
#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                       \
761
__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                             \
762
__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
763
#else
764
#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
765
#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
766
#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
767
#endif
768

    
769
/* add    add.    addo    addo.    */
770
static always_inline void gen_op_addo (void)
771
{
772
    gen_op_move_T2_T0();
773
    gen_op_add();
774
    gen_op_check_addo();
775
}
776
#if defined(TARGET_PPC64)
777
#define gen_op_add_64 gen_op_add
778
static always_inline void gen_op_addo_64 (void)
779
{
780
    gen_op_move_T2_T0();
781
    gen_op_add();
782
    gen_op_check_addo_64();
783
}
784
#endif
785
GEN_INT_ARITH2_64 (add,    0x1F, 0x0A, 0x08, PPC_INTEGER);
786
/* addc   addc.   addco   addco.   */
787
static always_inline void gen_op_addc (void)
788
{
789
    gen_op_move_T2_T0();
790
    gen_op_add();
791
    gen_op_check_addc();
792
}
793
static always_inline void gen_op_addco (void)
794
{
795
    gen_op_move_T2_T0();
796
    gen_op_add();
797
    gen_op_check_addc();
798
    gen_op_check_addo();
799
}
800
#if defined(TARGET_PPC64)
801
static always_inline void gen_op_addc_64 (void)
802
{
803
    gen_op_move_T2_T0();
804
    gen_op_add();
805
    gen_op_check_addc_64();
806
}
807
static always_inline void gen_op_addco_64 (void)
808
{
809
    gen_op_move_T2_T0();
810
    gen_op_add();
811
    gen_op_check_addc_64();
812
    gen_op_check_addo_64();
813
}
814
#endif
815
GEN_INT_ARITH2_64 (addc,   0x1F, 0x0A, 0x00, PPC_INTEGER);
816
/* adde   adde.   addeo   addeo.   */
817
static always_inline void gen_op_addeo (void)
818
{
819
    gen_op_move_T2_T0();
820
    gen_op_adde();
821
    gen_op_check_addo();
822
}
823
#if defined(TARGET_PPC64)
824
static always_inline void gen_op_addeo_64 (void)
825
{
826
    gen_op_move_T2_T0();
827
    gen_op_adde_64();
828
    gen_op_check_addo_64();
829
}
830
#endif
831
GEN_INT_ARITH2_64 (adde,   0x1F, 0x0A, 0x04, PPC_INTEGER);
832
/* addme  addme.  addmeo  addmeo.  */
833
static always_inline void gen_op_addme (void)
834
{
835
    gen_op_move_T1_T0();
836
    gen_op_add_me();
837
}
838
#if defined(TARGET_PPC64)
839
static always_inline void gen_op_addme_64 (void)
840
{
841
    gen_op_move_T1_T0();
842
    gen_op_add_me_64();
843
}
844
#endif
845
GEN_INT_ARITH1_64 (addme,  0x1F, 0x0A, 0x07, PPC_INTEGER);
846
/* addze  addze.  addzeo  addzeo.  */
847
static always_inline void gen_op_addze (void)
848
{
849
    gen_op_move_T2_T0();
850
    gen_op_add_ze();
851
    gen_op_check_addc();
852
}
853
static always_inline void gen_op_addzeo (void)
854
{
855
    gen_op_move_T2_T0();
856
    gen_op_add_ze();
857
    gen_op_check_addc();
858
    gen_op_check_addo();
859
}
860
#if defined(TARGET_PPC64)
861
static always_inline void gen_op_addze_64 (void)
862
{
863
    gen_op_move_T2_T0();
864
    gen_op_add_ze();
865
    gen_op_check_addc_64();
866
}
867
static always_inline void gen_op_addzeo_64 (void)
868
{
869
    gen_op_move_T2_T0();
870
    gen_op_add_ze();
871
    gen_op_check_addc_64();
872
    gen_op_check_addo_64();
873
}
874
#endif
875
GEN_INT_ARITH1_64 (addze,  0x1F, 0x0A, 0x06, PPC_INTEGER);
876
/* divw   divw.   divwo   divwo.   */
877
GEN_INT_ARITH2 (divw,   0x1F, 0x0B, 0x0F, PPC_INTEGER);
878
/* divwu  divwu.  divwuo  divwuo.  */
879
GEN_INT_ARITH2 (divwu,  0x1F, 0x0B, 0x0E, PPC_INTEGER);
880
/* mulhw  mulhw.                   */
881
GEN_INT_ARITHN (mulhw,  0x1F, 0x0B, 0x02, PPC_INTEGER);
882
/* mulhwu mulhwu.                  */
883
GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
884
/* mullw  mullw.  mullwo  mullwo.  */
885
GEN_INT_ARITH2 (mullw,  0x1F, 0x0B, 0x07, PPC_INTEGER);
886
/* neg    neg.    nego    nego.    */
887
GEN_INT_ARITH1_64 (neg,    0x1F, 0x08, 0x03, PPC_INTEGER);
888
/* subf   subf.   subfo   subfo.   */
889
static always_inline void gen_op_subfo (void)
890
{
891
    gen_op_move_T2_T0();
892
    gen_op_subf();
893
    gen_op_check_subfo();
894
}
895
#if defined(TARGET_PPC64)
896
#define gen_op_subf_64 gen_op_subf
897
static always_inline void gen_op_subfo_64 (void)
898
{
899
    gen_op_move_T2_T0();
900
    gen_op_subf();
901
    gen_op_check_subfo_64();
902
}
903
#endif
904
GEN_INT_ARITH2_64 (subf,   0x1F, 0x08, 0x01, PPC_INTEGER);
905
/* subfc  subfc.  subfco  subfco.  */
906
static always_inline void gen_op_subfc (void)
907
{
908
    gen_op_subf();
909
    gen_op_check_subfc();
910
}
911
static always_inline void gen_op_subfco (void)
912
{
913
    gen_op_move_T2_T0();
914
    gen_op_subf();
915
    gen_op_check_subfc();
916
    gen_op_check_subfo();
917
}
918
#if defined(TARGET_PPC64)
919
static always_inline void gen_op_subfc_64 (void)
920
{
921
    gen_op_subf();
922
    gen_op_check_subfc_64();
923
}
924
static always_inline void gen_op_subfco_64 (void)
925
{
926
    gen_op_move_T2_T0();
927
    gen_op_subf();
928
    gen_op_check_subfc_64();
929
    gen_op_check_subfo_64();
930
}
931
#endif
932
GEN_INT_ARITH2_64 (subfc,  0x1F, 0x08, 0x00, PPC_INTEGER);
933
/* subfe  subfe.  subfeo  subfeo.  */
934
static always_inline void gen_op_subfeo (void)
935
{
936
    gen_op_move_T2_T0();
937
    gen_op_subfe();
938
    gen_op_check_subfo();
939
}
940
#if defined(TARGET_PPC64)
941
#define gen_op_subfe_64 gen_op_subfe
942
static always_inline void gen_op_subfeo_64 (void)
943
{
944
    gen_op_move_T2_T0();
945
    gen_op_subfe_64();
946
    gen_op_check_subfo_64();
947
}
948
#endif
949
GEN_INT_ARITH2_64 (subfe,  0x1F, 0x08, 0x04, PPC_INTEGER);
950
/* subfme subfme. subfmeo subfmeo. */
951
GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
952
/* subfze subfze. subfzeo subfzeo. */
953
GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
954
/* addi */
955
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
956
{
957
    target_long simm = SIMM(ctx->opcode);
958

    
959
    if (rA(ctx->opcode) == 0) {
960
        /* li case */
961
        gen_set_T0(simm);
962
    } else {
963
        gen_op_load_gpr_T0(rA(ctx->opcode));
964
        if (likely(simm != 0))
965
            gen_op_addi(simm);
966
    }
967
    gen_op_store_T0_gpr(rD(ctx->opcode));
968
}
969
/* addic */
970
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
971
{
972
    target_long simm = SIMM(ctx->opcode);
973

    
974
    gen_op_load_gpr_T0(rA(ctx->opcode));
975
    if (likely(simm != 0)) {
976
        gen_op_move_T2_T0();
977
        gen_op_addi(simm);
978
#if defined(TARGET_PPC64)
979
        if (ctx->sf_mode)
980
            gen_op_check_addc_64();
981
        else
982
#endif
983
            gen_op_check_addc();
984
    } else {
985
        gen_op_clear_xer_ca();
986
    }
987
    gen_op_store_T0_gpr(rD(ctx->opcode));
988
}
989
/* addic. */
990
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
991
{
992
    target_long simm = SIMM(ctx->opcode);
993

    
994
    gen_op_load_gpr_T0(rA(ctx->opcode));
995
    if (likely(simm != 0)) {
996
        gen_op_move_T2_T0();
997
        gen_op_addi(simm);
998
#if defined(TARGET_PPC64)
999
        if (ctx->sf_mode)
1000
            gen_op_check_addc_64();
1001
        else
1002
#endif
1003
            gen_op_check_addc();
1004
    } else {
1005
        gen_op_clear_xer_ca();
1006
    }
1007
    gen_op_store_T0_gpr(rD(ctx->opcode));
1008
    gen_set_Rc0(ctx);
1009
}
1010
/* addis */
1011
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1012
{
1013
    target_long simm = SIMM(ctx->opcode);
1014

    
1015
    if (rA(ctx->opcode) == 0) {
1016
        /* lis case */
1017
        gen_set_T0(simm << 16);
1018
    } else {
1019
        gen_op_load_gpr_T0(rA(ctx->opcode));
1020
        if (likely(simm != 0))
1021
            gen_op_addi(simm << 16);
1022
    }
1023
    gen_op_store_T0_gpr(rD(ctx->opcode));
1024
}
1025
/* mulli */
1026
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1027
{
1028
    gen_op_load_gpr_T0(rA(ctx->opcode));
1029
    gen_op_mulli(SIMM(ctx->opcode));
1030
    gen_op_store_T0_gpr(rD(ctx->opcode));
1031
}
1032
/* subfic */
1033
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1034
{
1035
    gen_op_load_gpr_T0(rA(ctx->opcode));
1036
#if defined(TARGET_PPC64)
1037
    if (ctx->sf_mode)
1038
        gen_op_subfic_64(SIMM(ctx->opcode));
1039
    else
1040
#endif
1041
        gen_op_subfic(SIMM(ctx->opcode));
1042
    gen_op_store_T0_gpr(rD(ctx->opcode));
1043
}
1044

    
1045
#if defined(TARGET_PPC64)
1046
/* mulhd  mulhd.                   */
1047
GEN_INT_ARITHN (mulhd,  0x1F, 0x09, 0x02, PPC_64B);
1048
/* mulhdu mulhdu.                  */
1049
GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
1050
/* mulld  mulld.  mulldo  mulldo.  */
1051
GEN_INT_ARITH2 (mulld,  0x1F, 0x09, 0x07, PPC_64B);
1052
/* divd   divd.   divdo   divdo.   */
1053
GEN_INT_ARITH2 (divd,   0x1F, 0x09, 0x0F, PPC_64B);
1054
/* divdu  divdu.  divduo  divduo.  */
1055
GEN_INT_ARITH2 (divdu,  0x1F, 0x09, 0x0E, PPC_64B);
1056
#endif
1057

    
1058
/***                           Integer comparison                          ***/
1059
#if defined(TARGET_PPC64)
1060
#define GEN_CMP(name, opc, type)                                              \
1061
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1062
{                                                                             \
1063
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1064
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1065
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))                           \
1066
        gen_op_##name##_64();                                                 \
1067
    else                                                                      \
1068
        gen_op_##name();                                                      \
1069
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
1070
}
1071
#else
1072
#define GEN_CMP(name, opc, type)                                              \
1073
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
1074
{                                                                             \
1075
    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
1076
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1077
    gen_op_##name();                                                          \
1078
    gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
1079
}
1080
#endif
1081

    
1082
/* cmp */
1083
GEN_CMP(cmp, 0x00, PPC_INTEGER);
1084
/* cmpi */
1085
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1086
{
1087
    gen_op_load_gpr_T0(rA(ctx->opcode));
1088
#if defined(TARGET_PPC64)
1089
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1090
        gen_op_cmpi_64(SIMM(ctx->opcode));
1091
    else
1092
#endif
1093
        gen_op_cmpi(SIMM(ctx->opcode));
1094
    gen_op_store_T0_crf(crfD(ctx->opcode));
1095
}
1096
/* cmpl */
1097
GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1098
/* cmpli */
1099
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1100
{
1101
    gen_op_load_gpr_T0(rA(ctx->opcode));
1102
#if defined(TARGET_PPC64)
1103
    if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1104
        gen_op_cmpli_64(UIMM(ctx->opcode));
1105
    else
1106
#endif
1107
        gen_op_cmpli(UIMM(ctx->opcode));
1108
    gen_op_store_T0_crf(crfD(ctx->opcode));
1109
}
1110

    
1111
/* isel (PowerPC 2.03 specification) */
1112
GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1113
{
1114
    uint32_t bi = rC(ctx->opcode);
1115
    uint32_t mask;
1116

    
1117
    if (rA(ctx->opcode) == 0) {
1118
        gen_set_T0(0);
1119
    } else {
1120
        gen_op_load_gpr_T1(rA(ctx->opcode));
1121
    }
1122
    gen_op_load_gpr_T2(rB(ctx->opcode));
1123
    mask = 1 << (3 - (bi & 0x03));
1124
    gen_op_load_crf_T0(bi >> 2);
1125
    gen_op_test_true(mask);
1126
    gen_op_isel();
1127
    gen_op_store_T0_gpr(rD(ctx->opcode));
1128
}
1129

    
1130
/***                            Integer logical                            ***/
1131
#define __GEN_LOGICAL2(name, opc2, opc3, type)                                \
1132
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type)                         \
1133
{                                                                             \
1134
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
1135
    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
1136
    gen_op_##name();                                                          \
1137
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1138
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1139
        gen_set_Rc0(ctx);                                                     \
1140
}
1141
#define GEN_LOGICAL2(name, opc, type)                                         \
1142
__GEN_LOGICAL2(name, 0x1C, opc, type)
1143

    
1144
#define GEN_LOGICAL1(name, opc, type)                                         \
1145
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)                          \
1146
{                                                                             \
1147
    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
1148
    gen_op_##name();                                                          \
1149
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
1150
    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1151
        gen_set_Rc0(ctx);                                                     \
1152
}
1153

    
1154
/* and & and. */
1155
GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1156
/* andc & andc. */
1157
GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1158
/* andi. */
1159
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1160
{
1161
    gen_op_load_gpr_T0(rS(ctx->opcode));
1162
    gen_op_andi_T0(UIMM(ctx->opcode));
1163
    gen_op_store_T0_gpr(rA(ctx->opcode));
1164
    gen_set_Rc0(ctx);
1165
}
1166
/* andis. */
1167
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1168
{
1169
    gen_op_load_gpr_T0(rS(ctx->opcode));
1170
    gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1171
    gen_op_store_T0_gpr(rA(ctx->opcode));
1172
    gen_set_Rc0(ctx);
1173
}
1174

    
1175
/* cntlzw */
1176
GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1177
/* eqv & eqv. */
1178
GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1179
/* extsb & extsb. */
1180
GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1181
/* extsh & extsh. */
1182
GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1183
/* nand & nand. */
1184
GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1185
/* nor & nor. */
1186
GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1187

    
1188
/* or & or. */
1189
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1190
{
1191
    int rs, ra, rb;
1192

    
1193
    rs = rS(ctx->opcode);
1194
    ra = rA(ctx->opcode);
1195
    rb = rB(ctx->opcode);
1196
    /* Optimisation for mr. ri case */
1197
    if (rs != ra || rs != rb) {
1198
        gen_op_load_gpr_T0(rs);
1199
        if (rs != rb) {
1200
            gen_op_load_gpr_T1(rb);
1201
            gen_op_or();
1202
        }
1203
        gen_op_store_T0_gpr(ra);
1204
        if (unlikely(Rc(ctx->opcode) != 0))
1205
            gen_set_Rc0(ctx);
1206
    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1207
        gen_op_load_gpr_T0(rs);
1208
        gen_set_Rc0(ctx);
1209
#if defined(TARGET_PPC64)
1210
    } else {
1211
        switch (rs) {
1212
        case 1:
1213
            /* Set process priority to low */
1214
            gen_op_store_pri(2);
1215
            break;
1216
        case 6:
1217
            /* Set process priority to medium-low */
1218
            gen_op_store_pri(3);
1219
            break;
1220
        case 2:
1221
            /* Set process priority to normal */
1222
            gen_op_store_pri(4);
1223
            break;
1224
#if !defined(CONFIG_USER_ONLY)
1225
        case 31:
1226
            if (ctx->supervisor > 0) {
1227
                /* Set process priority to very low */
1228
                gen_op_store_pri(1);
1229
            }
1230
            break;
1231
        case 5:
1232
            if (ctx->supervisor > 0) {
1233
                /* Set process priority to medium-hight */
1234
                gen_op_store_pri(5);
1235
            }
1236
            break;
1237
        case 3:
1238
            if (ctx->supervisor > 0) {
1239
                /* Set process priority to high */
1240
                gen_op_store_pri(6);
1241
            }
1242
            break;
1243
#if defined(TARGET_PPC64H)
1244
        case 7:
1245
            if (ctx->supervisor > 1) {
1246
                /* Set process priority to very high */
1247
                gen_op_store_pri(7);
1248
            }
1249
            break;
1250
#endif
1251
#endif
1252
        default:
1253
            /* nop */
1254
            break;
1255
        }
1256
#endif
1257
    }
1258
}
1259

    
1260
/* orc & orc. */
1261
GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1262
/* xor & xor. */
1263
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1264
{
1265
    gen_op_load_gpr_T0(rS(ctx->opcode));
1266
    /* Optimisation for "set to zero" case */
1267
    if (rS(ctx->opcode) != rB(ctx->opcode)) {
1268
        gen_op_load_gpr_T1(rB(ctx->opcode));
1269
        gen_op_xor();
1270
    } else {
1271
        gen_op_reset_T0();
1272
    }
1273
    gen_op_store_T0_gpr(rA(ctx->opcode));
1274
    if (unlikely(Rc(ctx->opcode) != 0))
1275
        gen_set_Rc0(ctx);
1276
}
1277
/* ori */
1278
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1279
{
1280
    target_ulong uimm = UIMM(ctx->opcode);
1281

    
1282
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1283
        /* NOP */
1284
        /* XXX: should handle special NOPs for POWER series */
1285
        return;
1286
    }
1287
    gen_op_load_gpr_T0(rS(ctx->opcode));
1288
    if (likely(uimm != 0))
1289
        gen_op_ori(uimm);
1290
    gen_op_store_T0_gpr(rA(ctx->opcode));
1291
}
1292
/* oris */
1293
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1294
{
1295
    target_ulong uimm = UIMM(ctx->opcode);
1296

    
1297
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1298
        /* NOP */
1299
        return;
1300
    }
1301
    gen_op_load_gpr_T0(rS(ctx->opcode));
1302
    if (likely(uimm != 0))
1303
        gen_op_ori(uimm << 16);
1304
    gen_op_store_T0_gpr(rA(ctx->opcode));
1305
}
1306
/* xori */
1307
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1308
{
1309
    target_ulong uimm = UIMM(ctx->opcode);
1310

    
1311
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1312
        /* NOP */
1313
        return;
1314
    }
1315
    gen_op_load_gpr_T0(rS(ctx->opcode));
1316
    if (likely(uimm != 0))
1317
        gen_op_xori(uimm);
1318
    gen_op_store_T0_gpr(rA(ctx->opcode));
1319
}
1320

    
1321
/* xoris */
1322
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1323
{
1324
    target_ulong uimm = UIMM(ctx->opcode);
1325

    
1326
    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1327
        /* NOP */
1328
        return;
1329
    }
1330
    gen_op_load_gpr_T0(rS(ctx->opcode));
1331
    if (likely(uimm != 0))
1332
        gen_op_xori(uimm << 16);
1333
    gen_op_store_T0_gpr(rA(ctx->opcode));
1334
}
1335

    
1336
/* popcntb : PowerPC 2.03 specification */
1337
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1338
{
1339
    gen_op_load_gpr_T0(rS(ctx->opcode));
1340
#if defined(TARGET_PPC64)
1341
    if (ctx->sf_mode)
1342
        gen_op_popcntb_64();
1343
    else
1344
#endif
1345
        gen_op_popcntb();
1346
    gen_op_store_T0_gpr(rA(ctx->opcode));
1347
}
1348

    
1349
#if defined(TARGET_PPC64)
1350
/* extsw & extsw. */
1351
GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1352
/* cntlzd */
1353
GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1354
#endif
1355

    
1356
/***                             Integer rotate                            ***/
1357
/* rlwimi & rlwimi. */
1358
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1359
{
1360
    target_ulong mask;
1361
    uint32_t mb, me, sh;
1362

    
1363
    mb = MB(ctx->opcode);
1364
    me = ME(ctx->opcode);
1365
    sh = SH(ctx->opcode);
1366
    if (likely(sh == 0)) {
1367
        if (likely(mb == 0 && me == 31)) {
1368
            gen_op_load_gpr_T0(rS(ctx->opcode));
1369
            goto do_store;
1370
        } else if (likely(mb == 31 && me == 0)) {
1371
            gen_op_load_gpr_T0(rA(ctx->opcode));
1372
            goto do_store;
1373
        }
1374
        gen_op_load_gpr_T0(rS(ctx->opcode));
1375
        gen_op_load_gpr_T1(rA(ctx->opcode));
1376
        goto do_mask;
1377
    }
1378
    gen_op_load_gpr_T0(rS(ctx->opcode));
1379
    gen_op_load_gpr_T1(rA(ctx->opcode));
1380
    gen_op_rotli32_T0(SH(ctx->opcode));
1381
 do_mask:
1382
#if defined(TARGET_PPC64)
1383
    mb += 32;
1384
    me += 32;
1385
#endif
1386
    mask = MASK(mb, me);
1387
    gen_op_andi_T0(mask);
1388
    gen_op_andi_T1(~mask);
1389
    gen_op_or();
1390
 do_store:
1391
    gen_op_store_T0_gpr(rA(ctx->opcode));
1392
    if (unlikely(Rc(ctx->opcode) != 0))
1393
        gen_set_Rc0(ctx);
1394
}
1395
/* rlwinm & rlwinm. */
1396
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1397
{
1398
    uint32_t mb, me, sh;
1399

    
1400
    sh = SH(ctx->opcode);
1401
    mb = MB(ctx->opcode);
1402
    me = ME(ctx->opcode);
1403
    gen_op_load_gpr_T0(rS(ctx->opcode));
1404
    if (likely(sh == 0)) {
1405
        goto do_mask;
1406
    }
1407
    if (likely(mb == 0)) {
1408
        if (likely(me == 31)) {
1409
            gen_op_rotli32_T0(sh);
1410
            goto do_store;
1411
        } else if (likely(me == (31 - sh))) {
1412
            gen_op_sli_T0(sh);
1413
            goto do_store;
1414
        }
1415
    } else if (likely(me == 31)) {
1416
        if (likely(sh == (32 - mb))) {
1417
            gen_op_srli_T0(mb);
1418
            goto do_store;
1419
        }
1420
    }
1421
    gen_op_rotli32_T0(sh);
1422
 do_mask:
1423
#if defined(TARGET_PPC64)
1424
    mb += 32;
1425
    me += 32;
1426
#endif
1427
    gen_op_andi_T0(MASK(mb, me));
1428
 do_store:
1429
    gen_op_store_T0_gpr(rA(ctx->opcode));
1430
    if (unlikely(Rc(ctx->opcode) != 0))
1431
        gen_set_Rc0(ctx);
1432
}
1433
/* rlwnm & rlwnm. */
1434
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1435
{
1436
    uint32_t mb, me;
1437

    
1438
    mb = MB(ctx->opcode);
1439
    me = ME(ctx->opcode);
1440
    gen_op_load_gpr_T0(rS(ctx->opcode));
1441
    gen_op_load_gpr_T1(rB(ctx->opcode));
1442
    gen_op_rotl32_T0_T1();
1443
    if (unlikely(mb != 0 || me != 31)) {
1444
#if defined(TARGET_PPC64)
1445
        mb += 32;
1446
        me += 32;
1447
#endif
1448
        gen_op_andi_T0(MASK(mb, me));
1449
    }
1450
    gen_op_store_T0_gpr(rA(ctx->opcode));
1451
    if (unlikely(Rc(ctx->opcode) != 0))
1452
        gen_set_Rc0(ctx);
1453
}
1454

    
1455
#if defined(TARGET_PPC64)
1456
#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1457
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1458
{                                                                             \
1459
    gen_##name(ctx, 0);                                                       \
1460
}                                                                             \
1461
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1462
             PPC_64B)                                                         \
1463
{                                                                             \
1464
    gen_##name(ctx, 1);                                                       \
1465
}
1466
#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1467
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1468
{                                                                             \
1469
    gen_##name(ctx, 0, 0);                                                    \
1470
}                                                                             \
1471
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000,   \
1472
             PPC_64B)                                                         \
1473
{                                                                             \
1474
    gen_##name(ctx, 0, 1);                                                    \
1475
}                                                                             \
1476
GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000,   \
1477
             PPC_64B)                                                         \
1478
{                                                                             \
1479
    gen_##name(ctx, 1, 0);                                                    \
1480
}                                                                             \
1481
GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000,   \
1482
             PPC_64B)                                                         \
1483
{                                                                             \
1484
    gen_##name(ctx, 1, 1);                                                    \
1485
}
1486

    
1487
static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1488
{
1489
    if (mask >> 32)
1490
        gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1491
    else
1492
        gen_op_andi_T0(mask);
1493
}
1494

    
1495
static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1496
{
1497
    if (mask >> 32)
1498
        gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1499
    else
1500
        gen_op_andi_T1(mask);
1501
}
1502

    
1503
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1504
                                      uint32_t me, uint32_t sh)
1505
{
1506
    gen_op_load_gpr_T0(rS(ctx->opcode));
1507
    if (likely(sh == 0)) {
1508
        goto do_mask;
1509
    }
1510
    if (likely(mb == 0)) {
1511
        if (likely(me == 63)) {
1512
            gen_op_rotli64_T0(sh);
1513
            goto do_store;
1514
        } else if (likely(me == (63 - sh))) {
1515
            gen_op_sli_T0(sh);
1516
            goto do_store;
1517
        }
1518
    } else if (likely(me == 63)) {
1519
        if (likely(sh == (64 - mb))) {
1520
            gen_op_srli_T0_64(mb);
1521
            goto do_store;
1522
        }
1523
    }
1524
    gen_op_rotli64_T0(sh);
1525
 do_mask:
1526
    gen_andi_T0_64(ctx, MASK(mb, me));
1527
 do_store:
1528
    gen_op_store_T0_gpr(rA(ctx->opcode));
1529
    if (unlikely(Rc(ctx->opcode) != 0))
1530
        gen_set_Rc0(ctx);
1531
}
1532
/* rldicl - rldicl. */
1533
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1534
{
1535
    uint32_t sh, mb;
1536

    
1537
    sh = SH(ctx->opcode) | (shn << 5);
1538
    mb = MB(ctx->opcode) | (mbn << 5);
1539
    gen_rldinm(ctx, mb, 63, sh);
1540
}
1541
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1542
/* rldicr - rldicr. */
1543
static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1544
{
1545
    uint32_t sh, me;
1546

    
1547
    sh = SH(ctx->opcode) | (shn << 5);
1548
    me = MB(ctx->opcode) | (men << 5);
1549
    gen_rldinm(ctx, 0, me, sh);
1550
}
1551
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1552
/* rldic - rldic. */
1553
static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1554
{
1555
    uint32_t sh, mb;
1556

    
1557
    sh = SH(ctx->opcode) | (shn << 5);
1558
    mb = MB(ctx->opcode) | (mbn << 5);
1559
    gen_rldinm(ctx, mb, 63 - sh, sh);
1560
}
1561
GEN_PPC64_R4(rldic, 0x1E, 0x04);
1562

    
1563
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1564
                                     uint32_t me)
1565
{
1566
    gen_op_load_gpr_T0(rS(ctx->opcode));
1567
    gen_op_load_gpr_T1(rB(ctx->opcode));
1568
    gen_op_rotl64_T0_T1();
1569
    if (unlikely(mb != 0 || me != 63)) {
1570
        gen_andi_T0_64(ctx, MASK(mb, me));
1571
    }
1572
    gen_op_store_T0_gpr(rA(ctx->opcode));
1573
    if (unlikely(Rc(ctx->opcode) != 0))
1574
        gen_set_Rc0(ctx);
1575
}
1576

    
1577
/* rldcl - rldcl. */
1578
static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1579
{
1580
    uint32_t mb;
1581

    
1582
    mb = MB(ctx->opcode) | (mbn << 5);
1583
    gen_rldnm(ctx, mb, 63);
1584
}
1585
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1586
/* rldcr - rldcr. */
1587
static always_inline void gen_rldcr (DisasContext *ctx, int men)
1588
{
1589
    uint32_t me;
1590

    
1591
    me = MB(ctx->opcode) | (men << 5);
1592
    gen_rldnm(ctx, 0, me);
1593
}
1594
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1595
/* rldimi - rldimi. */
1596
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1597
{
1598
    uint64_t mask;
1599
    uint32_t sh, mb;
1600

    
1601
    sh = SH(ctx->opcode) | (shn << 5);
1602
    mb = MB(ctx->opcode) | (mbn << 5);
1603
    if (likely(sh == 0)) {
1604
        if (likely(mb == 0)) {
1605
            gen_op_load_gpr_T0(rS(ctx->opcode));
1606
            goto do_store;
1607
        } else if (likely(mb == 63)) {
1608
            gen_op_load_gpr_T0(rA(ctx->opcode));
1609
            goto do_store;
1610
        }
1611
        gen_op_load_gpr_T0(rS(ctx->opcode));
1612
        gen_op_load_gpr_T1(rA(ctx->opcode));
1613
        goto do_mask;
1614
    }
1615
    gen_op_load_gpr_T0(rS(ctx->opcode));
1616
    gen_op_load_gpr_T1(rA(ctx->opcode));
1617
    gen_op_rotli64_T0(sh);
1618
 do_mask:
1619
    mask = MASK(mb, 63 - sh);
1620
    gen_andi_T0_64(ctx, mask);
1621
    gen_andi_T1_64(ctx, ~mask);
1622
    gen_op_or();
1623
 do_store:
1624
    gen_op_store_T0_gpr(rA(ctx->opcode));
1625
    if (unlikely(Rc(ctx->opcode) != 0))
1626
        gen_set_Rc0(ctx);
1627
}
1628
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1629
#endif
1630

    
1631
/***                             Integer shift                             ***/
1632
/* slw & slw. */
1633
__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1634
/* sraw & sraw. */
1635
__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1636
/* srawi & srawi. */
1637
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1638
{
1639
    int mb, me;
1640
    gen_op_load_gpr_T0(rS(ctx->opcode));
1641
    if (SH(ctx->opcode) != 0) {
1642
        gen_op_move_T1_T0();
1643
        mb = 32 - SH(ctx->opcode);
1644
        me = 31;
1645
#if defined(TARGET_PPC64)
1646
        mb += 32;
1647
        me += 32;
1648
#endif
1649
        gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1650
    }
1651
    gen_op_store_T0_gpr(rA(ctx->opcode));
1652
    if (unlikely(Rc(ctx->opcode) != 0))
1653
        gen_set_Rc0(ctx);
1654
}
1655
/* srw & srw. */
1656
__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1657

    
1658
#if defined(TARGET_PPC64)
1659
/* sld & sld. */
1660
__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1661
/* srad & srad. */
1662
__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1663
/* sradi & sradi. */
1664
static always_inline void gen_sradi (DisasContext *ctx, int n)
1665
{
1666
    uint64_t mask;
1667
    int sh, mb, me;
1668

    
1669
    gen_op_load_gpr_T0(rS(ctx->opcode));
1670
    sh = SH(ctx->opcode) + (n << 5);
1671
    if (sh != 0) {
1672
        gen_op_move_T1_T0();
1673
        mb = 64 - SH(ctx->opcode);
1674
        me = 63;
1675
        mask = MASK(mb, me);
1676
        gen_op_sradi(sh, mask >> 32, mask);
1677
    }
1678
    gen_op_store_T0_gpr(rA(ctx->opcode));
1679
    if (unlikely(Rc(ctx->opcode) != 0))
1680
        gen_set_Rc0(ctx);
1681
}
1682
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1683
{
1684
    gen_sradi(ctx, 0);
1685
}
1686
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1687
{
1688
    gen_sradi(ctx, 1);
1689
}
1690
/* srd & srd. */
1691
__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1692
#endif
1693

    
1694
/***                       Floating-Point arithmetic                       ***/
1695
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
1696
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)                        \
1697
{                                                                             \
1698
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1699
        GEN_EXCP_NO_FP(ctx);                                                  \
1700
        return;                                                               \
1701
    }                                                                         \
1702
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1703
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
1704
    gen_op_load_fpr_FT2(rB(ctx->opcode));                                     \
1705
    gen_reset_fpstatus();                                                     \
1706
    gen_op_f##op();                                                           \
1707
    if (isfloat) {                                                            \
1708
        gen_op_frsp();                                                        \
1709
    }                                                                         \
1710
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1711
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1712
}
1713

    
1714
#define GEN_FLOAT_ACB(name, op2, set_fprf, type)                              \
1715
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type);                     \
1716
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1717

    
1718
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
1719
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
1720
{                                                                             \
1721
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1722
        GEN_EXCP_NO_FP(ctx);                                                  \
1723
        return;                                                               \
1724
    }                                                                         \
1725
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1726
    gen_op_load_fpr_FT1(rB(ctx->opcode));                                     \
1727
    gen_reset_fpstatus();                                                     \
1728
    gen_op_f##op();                                                           \
1729
    if (isfloat) {                                                            \
1730
        gen_op_frsp();                                                        \
1731
    }                                                                         \
1732
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1733
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1734
}
1735
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type)                        \
1736
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
1737
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1738

    
1739
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
1740
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)                             \
1741
{                                                                             \
1742
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1743
        GEN_EXCP_NO_FP(ctx);                                                  \
1744
        return;                                                               \
1745
    }                                                                         \
1746
    gen_op_load_fpr_FT0(rA(ctx->opcode));                                     \
1747
    gen_op_load_fpr_FT1(rC(ctx->opcode));                                     \
1748
    gen_reset_fpstatus();                                                     \
1749
    gen_op_f##op();                                                           \
1750
    if (isfloat) {                                                            \
1751
        gen_op_frsp();                                                        \
1752
    }                                                                         \
1753
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1754
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1755
}
1756
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
1757
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
1758
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1759

    
1760
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
1761
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)                        \
1762
{                                                                             \
1763
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1764
        GEN_EXCP_NO_FP(ctx);                                                  \
1765
        return;                                                               \
1766
    }                                                                         \
1767
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
1768
    gen_reset_fpstatus();                                                     \
1769
    gen_op_f##name();                                                         \
1770
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1771
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1772
}
1773

    
1774
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type)                          \
1775
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)                        \
1776
{                                                                             \
1777
    if (unlikely(!ctx->fpu_enabled)) {                                        \
1778
        GEN_EXCP_NO_FP(ctx);                                                  \
1779
        return;                                                               \
1780
    }                                                                         \
1781
    gen_op_load_fpr_FT0(rB(ctx->opcode));                                     \
1782
    gen_reset_fpstatus();                                                     \
1783
    gen_op_f##name();                                                         \
1784
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
1785
    gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0);                         \
1786
}
1787

    
1788
/* fadd - fadds */
1789
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1790
/* fdiv - fdivs */
1791
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
1792
/* fmul - fmuls */
1793
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
1794

    
1795
/* fre */
1796
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
1797

    
1798
/* fres */
1799
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
1800

    
1801
/* frsqrte */
1802
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1803

    
1804
/* frsqrtes */
1805
static always_inline void gen_op_frsqrtes (void)
1806
{
1807
    gen_op_frsqrte();
1808
    gen_op_frsp();
1809
}
1810
GEN_FLOAT_BS(rsqrtes, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTES);
1811

    
1812
/* fsel */
1813
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
1814
/* fsub - fsubs */
1815
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
1816
/* Optional: */
1817
/* fsqrt */
1818
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1819
{
1820
    if (unlikely(!ctx->fpu_enabled)) {
1821
        GEN_EXCP_NO_FP(ctx);
1822
        return;
1823
    }
1824
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1825
    gen_reset_fpstatus();
1826
    gen_op_fsqrt();
1827
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1828
    gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1829
}
1830

    
1831
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1832
{
1833
    if (unlikely(!ctx->fpu_enabled)) {
1834
        GEN_EXCP_NO_FP(ctx);
1835
        return;
1836
    }
1837
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1838
    gen_reset_fpstatus();
1839
    gen_op_fsqrt();
1840
    gen_op_frsp();
1841
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1842
    gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1843
}
1844

    
1845
/***                     Floating-Point multiply-and-add                   ***/
1846
/* fmadd - fmadds */
1847
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
1848
/* fmsub - fmsubs */
1849
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
1850
/* fnmadd - fnmadds */
1851
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
1852
/* fnmsub - fnmsubs */
1853
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
1854

    
1855
/***                     Floating-Point round & convert                    ***/
1856
/* fctiw */
1857
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
1858
/* fctiwz */
1859
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
1860
/* frsp */
1861
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
1862
#if defined(TARGET_PPC64)
1863
/* fcfid */
1864
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
1865
/* fctid */
1866
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
1867
/* fctidz */
1868
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
1869
#endif
1870

    
1871
/* frin */
1872
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
1873
/* friz */
1874
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
1875
/* frip */
1876
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
1877
/* frim */
1878
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
1879

    
1880
/***                         Floating-Point compare                        ***/
1881
/* fcmpo */
1882
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1883
{
1884
    if (unlikely(!ctx->fpu_enabled)) {
1885
        GEN_EXCP_NO_FP(ctx);
1886
        return;
1887
    }
1888
    gen_op_load_fpr_FT0(rA(ctx->opcode));
1889
    gen_op_load_fpr_FT1(rB(ctx->opcode));
1890
    gen_reset_fpstatus();
1891
    gen_op_fcmpo();
1892
    gen_op_store_T0_crf(crfD(ctx->opcode));
1893
    gen_op_float_check_status();
1894
}
1895

    
1896
/* fcmpu */
1897
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1898
{
1899
    if (unlikely(!ctx->fpu_enabled)) {
1900
        GEN_EXCP_NO_FP(ctx);
1901
        return;
1902
    }
1903
    gen_op_load_fpr_FT0(rA(ctx->opcode));
1904
    gen_op_load_fpr_FT1(rB(ctx->opcode));
1905
    gen_reset_fpstatus();
1906
    gen_op_fcmpu();
1907
    gen_op_store_T0_crf(crfD(ctx->opcode));
1908
    gen_op_float_check_status();
1909
}
1910

    
1911
/***                         Floating-point move                           ***/
1912
/* fabs */
1913
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1914
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
1915

    
1916
/* fmr  - fmr. */
1917
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1918
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1919
{
1920
    if (unlikely(!ctx->fpu_enabled)) {
1921
        GEN_EXCP_NO_FP(ctx);
1922
        return;
1923
    }
1924
    gen_op_load_fpr_FT0(rB(ctx->opcode));
1925
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1926
    gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1927
}
1928

    
1929
/* fnabs */
1930
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1931
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
1932
/* fneg */
1933
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1934
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
1935

    
1936
/***                  Floating-Point status & ctrl register                ***/
1937
/* mcrfs */
1938
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1939
{
1940
    int bfa;
1941

    
1942
    if (unlikely(!ctx->fpu_enabled)) {
1943
        GEN_EXCP_NO_FP(ctx);
1944
        return;
1945
    }
1946
    gen_optimize_fprf();
1947
    bfa = 4 * (7 - crfS(ctx->opcode));
1948
    gen_op_load_fpscr_T0(bfa);
1949
    gen_op_store_T0_crf(crfD(ctx->opcode));
1950
    gen_op_fpscr_resetbit(~(0xF << bfa));
1951
}
1952

    
1953
/* mffs */
1954
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1955
{
1956
    if (unlikely(!ctx->fpu_enabled)) {
1957
        GEN_EXCP_NO_FP(ctx);
1958
        return;
1959
    }
1960
    gen_optimize_fprf();
1961
    gen_reset_fpstatus();
1962
    gen_op_load_fpscr_FT0();
1963
    gen_op_store_FT0_fpr(rD(ctx->opcode));
1964
    gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1965
}
1966

    
1967
/* mtfsb0 */
1968
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1969
{
1970
    uint8_t crb;
1971

    
1972
    if (unlikely(!ctx->fpu_enabled)) {
1973
        GEN_EXCP_NO_FP(ctx);
1974
        return;
1975
    }
1976
    crb = 32 - (crbD(ctx->opcode) >> 2);
1977
    gen_optimize_fprf();
1978
    gen_reset_fpstatus();
1979
    if (likely(crb != 30 && crb != 29))
1980
        gen_op_fpscr_resetbit(~(1 << crb));
1981
    if (unlikely(Rc(ctx->opcode) != 0)) {
1982
        gen_op_load_fpcc();
1983
        gen_op_set_Rc0();
1984
    }
1985
}
1986

    
1987
/* mtfsb1 */
1988
GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1989
{
1990
    uint8_t crb;
1991

    
1992
    if (unlikely(!ctx->fpu_enabled)) {
1993
        GEN_EXCP_NO_FP(ctx);
1994
        return;
1995
    }
1996
    crb = 32 - (crbD(ctx->opcode) >> 2);
1997
    gen_optimize_fprf();
1998
    gen_reset_fpstatus();
1999
    /* XXX: we pretend we can only do IEEE floating-point computations */
2000
    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2001
        gen_op_fpscr_setbit(crb);
2002
    if (unlikely(Rc(ctx->opcode) != 0)) {
2003
        gen_op_load_fpcc();
2004
        gen_op_set_Rc0();
2005
    }
2006
    /* We can raise a differed exception */
2007
    gen_op_float_check_status();
2008
}
2009

    
2010
/* mtfsf */
2011
GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2012
{
2013
    if (unlikely(!ctx->fpu_enabled)) {
2014
        GEN_EXCP_NO_FP(ctx);
2015
        return;
2016
    }
2017
    gen_optimize_fprf();
2018
    gen_op_load_fpr_FT0(rB(ctx->opcode));
2019
    gen_reset_fpstatus();
2020
    gen_op_store_fpscr(FM(ctx->opcode));
2021
    if (unlikely(Rc(ctx->opcode) != 0)) {
2022
        gen_op_load_fpcc();
2023
        gen_op_set_Rc0();
2024
    }
2025
    /* We can raise a differed exception */
2026
    gen_op_float_check_status();
2027
}
2028

    
2029
/* mtfsfi */
2030
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2031
{
2032
    int bf, sh;
2033

    
2034
    if (unlikely(!ctx->fpu_enabled)) {
2035
        GEN_EXCP_NO_FP(ctx);
2036
        return;
2037
    }
2038
    bf = crbD(ctx->opcode) >> 2;
2039
    sh = 7 - bf;
2040
    gen_optimize_fprf();
2041
    gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2042
    gen_reset_fpstatus();
2043
    gen_op_store_fpscr(1 << sh);
2044
    if (unlikely(Rc(ctx->opcode) != 0)) {
2045
        gen_op_load_fpcc();
2046
        gen_op_set_Rc0();
2047
    }
2048
    /* We can raise a differed exception */
2049
    gen_op_float_check_status();
2050
}
2051

    
2052
/***                           Addressing modes                            ***/
2053
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2054
static always_inline void gen_addr_imm_index (DisasContext *ctx,
2055
                                              target_long maskl)
2056
{
2057
    target_long simm = SIMM(ctx->opcode);
2058

    
2059
    simm &= ~maskl;
2060
    if (rA(ctx->opcode) == 0) {
2061
        gen_set_T0(simm);
2062
    } else {
2063
        gen_op_load_gpr_T0(rA(ctx->opcode));
2064
        if (likely(simm != 0))
2065
            gen_op_addi(simm);
2066
    }
2067
#ifdef DEBUG_MEMORY_ACCESSES
2068
    gen_op_print_mem_EA();
2069
#endif
2070
}
2071

    
2072
static always_inline void gen_addr_reg_index (DisasContext *ctx)
2073
{
2074
    if (rA(ctx->opcode) == 0) {
2075
        gen_op_load_gpr_T0(rB(ctx->opcode));
2076
    } else {
2077
        gen_op_load_gpr_T0(rA(ctx->opcode));
2078
        gen_op_load_gpr_T1(rB(ctx->opcode));
2079
        gen_op_add();
2080
    }
2081
#ifdef DEBUG_MEMORY_ACCESSES
2082
    gen_op_print_mem_EA();
2083
#endif
2084
}
2085

    
2086
static always_inline void gen_addr_register (DisasContext *ctx)
2087
{
2088
    if (rA(ctx->opcode) == 0) {
2089
        gen_op_reset_T0();
2090
    } else {
2091
        gen_op_load_gpr_T0(rA(ctx->opcode));
2092
    }
2093
#ifdef DEBUG_MEMORY_ACCESSES
2094
    gen_op_print_mem_EA();
2095
#endif
2096
}
2097

    
2098
/***                             Integer load                              ***/
2099
#define op_ldst(name)        (*gen_op_##name[ctx->mem_idx])()
2100
#if defined(CONFIG_USER_ONLY)
2101
#if defined(TARGET_PPC64)
2102
/* User mode only - 64 bits */
2103
#define OP_LD_TABLE(width)                                                    \
2104
static GenOpFunc *gen_op_l##width[] = {                                       \
2105
    &gen_op_l##width##_raw,                                                   \
2106
    &gen_op_l##width##_le_raw,                                                \
2107
    &gen_op_l##width##_64_raw,                                                \
2108
    &gen_op_l##width##_le_64_raw,                                             \
2109
};
2110
#define OP_ST_TABLE(width)                                                    \
2111
static GenOpFunc *gen_op_st##width[] = {                                      \
2112
    &gen_op_st##width##_raw,                                                  \
2113
    &gen_op_st##width##_le_raw,                                               \
2114
    &gen_op_st##width##_64_raw,                                               \
2115
    &gen_op_st##width##_le_64_raw,                                            \
2116
};
2117
/* Byte access routine are endian safe */
2118
#define gen_op_stb_le_64_raw gen_op_stb_64_raw
2119
#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2120
#else
2121
/* User mode only - 32 bits */
2122
#define OP_LD_TABLE(width)                                                    \
2123
static GenOpFunc *gen_op_l##width[] = {                                       \
2124
    &gen_op_l##width##_raw,                                                   \
2125
    &gen_op_l##width##_le_raw,                                                \
2126
};
2127
#define OP_ST_TABLE(width)                                                    \
2128
static GenOpFunc *gen_op_st##width[] = {                                      \
2129
    &gen_op_st##width##_raw,                                                  \
2130
    &gen_op_st##width##_le_raw,                                               \
2131
};
2132
#endif
2133
/* Byte access routine are endian safe */
2134
#define gen_op_stb_le_raw gen_op_stb_raw
2135
#define gen_op_lbz_le_raw gen_op_lbz_raw
2136
#else
2137
#if defined(TARGET_PPC64)
2138
#if defined(TARGET_PPC64H)
2139
/* Full system - 64 bits with hypervisor mode */
2140
#define OP_LD_TABLE(width)                                                    \
2141
static GenOpFunc *gen_op_l##width[] = {                                       \
2142
    &gen_op_l##width##_user,                                                  \
2143
    &gen_op_l##width##_le_user,                                               \
2144
    &gen_op_l##width##_64_user,                                               \
2145
    &gen_op_l##width##_le_64_user,                                            \
2146
    &gen_op_l##width##_kernel,                                                \
2147
    &gen_op_l##width##_le_kernel,                                             \
2148
    &gen_op_l##width##_64_kernel,                                             \
2149
    &gen_op_l##width##_le_64_kernel,                                          \
2150
    &gen_op_l##width##_hypv,                                                  \
2151
    &gen_op_l##width##_le_hypv,                                               \
2152
    &gen_op_l##width##_64_hypv,                                               \
2153
    &gen_op_l##width##_le_64_hypv,                                            \
2154
};
2155
#define OP_ST_TABLE(width)                                                    \
2156
static GenOpFunc *gen_op_st##width[] = {                                      \
2157
    &gen_op_st##width##_user,                                                 \
2158
    &gen_op_st##width##_le_user,                                              \
2159
    &gen_op_st##width##_64_user,                                              \
2160
    &gen_op_st##width##_le_64_user,                                           \
2161
    &gen_op_st##width##_kernel,                                               \
2162
    &gen_op_st##width##_le_kernel,                                            \
2163
    &gen_op_st##width##_64_kernel,                                            \
2164
    &gen_op_st##width##_le_64_kernel,                                         \
2165
    &gen_op_st##width##_hypv,                                                 \
2166
    &gen_op_st##width##_le_hypv,                                              \
2167
    &gen_op_st##width##_64_hypv,                                              \
2168
    &gen_op_st##width##_le_64_hypv,                                           \
2169
};
2170
/* Byte access routine are endian safe */
2171
#define gen_op_stb_le_hypv      gen_op_stb_64_hypv
2172
#define gen_op_lbz_le_hypv      gen_op_lbz_64_hypv
2173
#define gen_op_stb_le_64_hypv   gen_op_stb_64_hypv
2174
#define gen_op_lbz_le_64_hypv   gen_op_lbz_64_hypv
2175
#else
2176
/* Full system - 64 bits */
2177
#define OP_LD_TABLE(width)                                                    \
2178
static GenOpFunc *gen_op_l##width[] = {                                       \
2179
    &gen_op_l##width##_user,                                                  \
2180
    &gen_op_l##width##_le_user,                                               \
2181
    &gen_op_l##width##_64_user,                                               \
2182
    &gen_op_l##width##_le_64_user,                                            \
2183
    &gen_op_l##width##_kernel,                                                \
2184
    &gen_op_l##width##_le_kernel,                                             \
2185
    &gen_op_l##width##_64_kernel,                                             \
2186
    &gen_op_l##width##_le_64_kernel,                                          \
2187
};
2188
#define OP_ST_TABLE(width)                                                    \
2189
static GenOpFunc *gen_op_st##width[] = {                                      \
2190
    &gen_op_st##width##_user,                                                 \
2191
    &gen_op_st##width##_le_user,                                              \
2192
    &gen_op_st##width##_64_user,                                              \
2193
    &gen_op_st##width##_le_64_user,                                           \
2194
    &gen_op_st##width##_kernel,                                               \
2195
    &gen_op_st##width##_le_kernel,                                            \
2196
    &gen_op_st##width##_64_kernel,                                            \
2197
    &gen_op_st##width##_le_64_kernel,                                         \
2198
};
2199
#endif
2200
/* Byte access routine are endian safe */
2201
#define gen_op_stb_le_64_user   gen_op_stb_64_user
2202
#define gen_op_lbz_le_64_user   gen_op_lbz_64_user
2203
#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2204
#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2205
#else
2206
/* Full system - 32 bits */
2207
#define OP_LD_TABLE(width)                                                    \
2208
static GenOpFunc *gen_op_l##width[] = {                                       \
2209
    &gen_op_l##width##_user,                                                  \
2210
    &gen_op_l##width##_le_user,                                               \
2211
    &gen_op_l##width##_kernel,                                                \
2212
    &gen_op_l##width##_le_kernel,                                             \
2213
};
2214
#define OP_ST_TABLE(width)                                                    \
2215
static GenOpFunc *gen_op_st##width[] = {                                      \
2216
    &gen_op_st##width##_user,                                                 \
2217
    &gen_op_st##width##_le_user,                                              \
2218
    &gen_op_st##width##_kernel,                                               \
2219
    &gen_op_st##width##_le_kernel,                                            \
2220
};
2221
#endif
2222
/* Byte access routine are endian safe */
2223
#define gen_op_stb_le_user   gen_op_stb_user
2224
#define gen_op_lbz_le_user   gen_op_lbz_user
2225
#define gen_op_stb_le_kernel gen_op_stb_kernel
2226
#define gen_op_lbz_le_kernel gen_op_lbz_kernel
2227
#endif
2228

    
2229
#define GEN_LD(width, opc, type)                                              \
2230
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
2231
{                                                                             \
2232
    gen_addr_imm_index(ctx, 0);                                               \
2233
    op_ldst(l##width);                                                        \
2234
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2235
}
2236

    
2237
#define GEN_LDU(width, opc, type)                                             \
2238
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
2239
{                                                                             \
2240
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2241
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2242
        GEN_EXCP_INVAL(ctx);                                                  \
2243
        return;                                                               \
2244
    }                                                                         \
2245
    if (type == PPC_64B)                                                      \
2246
        gen_addr_imm_index(ctx, 0x03);                                        \
2247
    else                                                                      \
2248
        gen_addr_imm_index(ctx, 0);                                           \
2249
    op_ldst(l##width);                                                        \
2250
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2251
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2252
}
2253

    
2254
#define GEN_LDUX(width, opc2, opc3, type)                                     \
2255
GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                 \
2256
{                                                                             \
2257
    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2258
                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2259
        GEN_EXCP_INVAL(ctx);                                                  \
2260
        return;                                                               \
2261
    }                                                                         \
2262
    gen_addr_reg_index(ctx);                                                  \
2263
    op_ldst(l##width);                                                        \
2264
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2265
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2266
}
2267

    
2268
#define GEN_LDX(width, opc2, opc3, type)                                      \
2269
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
2270
{                                                                             \
2271
    gen_addr_reg_index(ctx);                                                  \
2272
    op_ldst(l##width);                                                        \
2273
    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
2274
}
2275

    
2276
#define GEN_LDS(width, op, type)                                              \
2277
OP_LD_TABLE(width);                                                           \
2278
GEN_LD(width, op | 0x20, type);                                               \
2279
GEN_LDU(width, op | 0x21, type);                                              \
2280
GEN_LDUX(width, 0x17, op | 0x01, type);                                       \
2281
GEN_LDX(width, 0x17, op | 0x00, type)
2282

    
2283
/* lbz lbzu lbzux lbzx */
2284
GEN_LDS(bz, 0x02, PPC_INTEGER);
2285
/* lha lhau lhaux lhax */
2286
GEN_LDS(ha, 0x0A, PPC_INTEGER);
2287
/* lhz lhzu lhzux lhzx */
2288
GEN_LDS(hz, 0x08, PPC_INTEGER);
2289
/* lwz lwzu lwzux lwzx */
2290
GEN_LDS(wz, 0x00, PPC_INTEGER);
2291
#if defined(TARGET_PPC64)
2292
OP_LD_TABLE(wa);
2293
OP_LD_TABLE(d);
2294
/* lwaux */
2295
GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2296
/* lwax */
2297
GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2298
/* ldux */
2299
GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2300
/* ldx */
2301
GEN_LDX(d, 0x15, 0x00, PPC_64B);
2302
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2303
{
2304
    if (Rc(ctx->opcode)) {
2305
        if (unlikely(rA(ctx->opcode) == 0 ||
2306
                     rA(ctx->opcode) == rD(ctx->opcode))) {
2307
            GEN_EXCP_INVAL(ctx);
2308
            return;
2309
        }
2310
    }
2311
    gen_addr_imm_index(ctx, 0x03);
2312
    if (ctx->opcode & 0x02) {
2313
        /* lwa (lwau is undefined) */
2314
        op_ldst(lwa);
2315
    } else {
2316
        /* ld - ldu */
2317
        op_ldst(ld);
2318
    }
2319
    gen_op_store_T1_gpr(rD(ctx->opcode));
2320
    if (Rc(ctx->opcode))
2321
        gen_op_store_T0_gpr(rA(ctx->opcode));
2322
}
2323
/* lq */
2324
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2325
{
2326
#if defined(CONFIG_USER_ONLY)
2327
    GEN_EXCP_PRIVOPC(ctx);
2328
#else
2329
    int ra, rd;
2330

    
2331
    /* Restore CPU state */
2332
    if (unlikely(ctx->supervisor == 0)) {
2333
        GEN_EXCP_PRIVOPC(ctx);
2334
        return;
2335
    }
2336
    ra = rA(ctx->opcode);
2337
    rd = rD(ctx->opcode);
2338
    if (unlikely((rd & 1) || rd == ra)) {
2339
        GEN_EXCP_INVAL(ctx);
2340
        return;
2341
    }
2342
    if (unlikely(ctx->mem_idx & 1)) {
2343
        /* Little-endian mode is not handled */
2344
        GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2345
        return;
2346
    }
2347
    gen_addr_imm_index(ctx, 0x0F);
2348
    op_ldst(ld);
2349
    gen_op_store_T1_gpr(rd);
2350
    gen_op_addi(8);
2351
    op_ldst(ld);
2352
    gen_op_store_T1_gpr(rd + 1);
2353
#endif
2354
}
2355
#endif
2356

    
2357
/***                              Integer store                            ***/
2358
#define GEN_ST(width, opc, type)                                              \
2359
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
2360
{                                                                             \
2361
    gen_addr_imm_index(ctx, 0);                                               \
2362
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2363
    op_ldst(st##width);                                                       \
2364
}
2365

    
2366
#define GEN_STU(width, opc, type)                                             \
2367
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
2368
{                                                                             \
2369
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2370
        GEN_EXCP_INVAL(ctx);                                                  \
2371
        return;                                                               \
2372
    }                                                                         \
2373
    if (type == PPC_64B)                                                      \
2374
        gen_addr_imm_index(ctx, 0x03);                                        \
2375
    else                                                                      \
2376
        gen_addr_imm_index(ctx, 0);                                           \
2377
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2378
    op_ldst(st##width);                                                       \
2379
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2380
}
2381

    
2382
#define GEN_STUX(width, opc2, opc3, type)                                     \
2383
GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                \
2384
{                                                                             \
2385
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2386
        GEN_EXCP_INVAL(ctx);                                                  \
2387
        return;                                                               \
2388
    }                                                                         \
2389
    gen_addr_reg_index(ctx);                                                  \
2390
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2391
    op_ldst(st##width);                                                       \
2392
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2393
}
2394

    
2395
#define GEN_STX(width, opc2, opc3, type)                                      \
2396
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
2397
{                                                                             \
2398
    gen_addr_reg_index(ctx);                                                  \
2399
    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
2400
    op_ldst(st##width);                                                       \
2401
}
2402

    
2403
#define GEN_STS(width, op, type)                                              \
2404
OP_ST_TABLE(width);                                                           \
2405
GEN_ST(width, op | 0x20, type);                                               \
2406
GEN_STU(width, op | 0x21, type);                                              \
2407
GEN_STUX(width, 0x17, op | 0x01, type);                                       \
2408
GEN_STX(width, 0x17, op | 0x00, type)
2409

    
2410
/* stb stbu stbux stbx */
2411
GEN_STS(b, 0x06, PPC_INTEGER);
2412
/* sth sthu sthux sthx */
2413
GEN_STS(h, 0x0C, PPC_INTEGER);
2414
/* stw stwu stwux stwx */
2415
GEN_STS(w, 0x04, PPC_INTEGER);
2416
#if defined(TARGET_PPC64)
2417
OP_ST_TABLE(d);
2418
GEN_STUX(d, 0x15, 0x05, PPC_64B);
2419
GEN_STX(d, 0x15, 0x04, PPC_64B);
2420
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2421
{
2422
    int rs;
2423

    
2424
    rs = rS(ctx->opcode);
2425
    if ((ctx->opcode & 0x3) == 0x2) {
2426
#if defined(CONFIG_USER_ONLY)
2427
        GEN_EXCP_PRIVOPC(ctx);
2428
#else
2429
        /* stq */
2430
        if (unlikely(ctx->supervisor == 0)) {
2431
            GEN_EXCP_PRIVOPC(ctx);
2432
            return;
2433
        }
2434
        if (unlikely(rs & 1)) {
2435
            GEN_EXCP_INVAL(ctx);
2436
            return;
2437
        }
2438
        if (unlikely(ctx->mem_idx & 1)) {
2439
            /* Little-endian mode is not handled */
2440
            GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2441
            return;
2442
        }
2443
        gen_addr_imm_index(ctx, 0x03);
2444
        gen_op_load_gpr_T1(rs);
2445
        op_ldst(std);
2446
        gen_op_addi(8);
2447
        gen_op_load_gpr_T1(rs + 1);
2448
        op_ldst(std);
2449
#endif
2450
    } else {
2451
        /* std / stdu */
2452
        if (Rc(ctx->opcode)) {
2453
            if (unlikely(rA(ctx->opcode) == 0)) {
2454
                GEN_EXCP_INVAL(ctx);
2455
                return;
2456
            }
2457
        }
2458
        gen_addr_imm_index(ctx, 0x03);
2459
        gen_op_load_gpr_T1(rs);
2460
        op_ldst(std);
2461
        if (Rc(ctx->opcode))
2462
            gen_op_store_T0_gpr(rA(ctx->opcode));
2463
    }
2464
}
2465
#endif
2466
/***                Integer load and store with byte reverse               ***/
2467
/* lhbrx */
2468
OP_LD_TABLE(hbr);
2469
GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2470
/* lwbrx */
2471
OP_LD_TABLE(wbr);
2472
GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2473
/* sthbrx */
2474
OP_ST_TABLE(hbr);
2475
GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2476
/* stwbrx */
2477
OP_ST_TABLE(wbr);
2478
GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2479

    
2480
/***                    Integer load and store multiple                    ***/
2481
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2482
#if defined(CONFIG_USER_ONLY)
2483
/* User-mode only */
2484
static GenOpFunc1 *gen_op_lmw[] = {
2485
    &gen_op_lmw_raw,
2486
    &gen_op_lmw_le_raw,
2487
#if defined(TARGET_PPC64)
2488
    &gen_op_lmw_64_raw,
2489
    &gen_op_lmw_le_64_raw,
2490
#endif
2491
};
2492
static GenOpFunc1 *gen_op_stmw[] = {
2493
    &gen_op_stmw_raw,
2494
    &gen_op_stmw_le_raw,
2495
#if defined(TARGET_PPC64)
2496
    &gen_op_stmw_64_raw,
2497
    &gen_op_stmw_le_64_raw,
2498
#endif
2499
};
2500
#else
2501
#if defined(TARGET_PPC64)
2502
/* Full system - 64 bits mode */
2503
static GenOpFunc1 *gen_op_lmw[] = {
2504
    &gen_op_lmw_user,
2505
    &gen_op_lmw_le_user,
2506
    &gen_op_lmw_64_user,
2507
    &gen_op_lmw_le_64_user,
2508
    &gen_op_lmw_kernel,
2509
    &gen_op_lmw_le_kernel,
2510
    &gen_op_lmw_64_kernel,
2511
    &gen_op_lmw_le_64_kernel,
2512
#if defined(TARGET_PPC64H)
2513
    &gen_op_lmw_hypv,
2514
    &gen_op_lmw_le_hypv,
2515
    &gen_op_lmw_64_hypv,
2516
    &gen_op_lmw_le_64_hypv,
2517
#endif
2518
};
2519
static GenOpFunc1 *gen_op_stmw[] = {
2520
    &gen_op_stmw_user,
2521
    &gen_op_stmw_le_user,
2522
    &gen_op_stmw_64_user,
2523
    &gen_op_stmw_le_64_user,
2524
    &gen_op_stmw_kernel,
2525
    &gen_op_stmw_le_kernel,
2526
    &gen_op_stmw_64_kernel,
2527
    &gen_op_stmw_le_64_kernel,
2528
#if defined(TARGET_PPC64H)
2529
    &gen_op_stmw_hypv,
2530
    &gen_op_stmw_le_hypv,
2531
    &gen_op_stmw_64_hypv,
2532
    &gen_op_stmw_le_64_hypv,
2533
#endif
2534
};
2535
#else
2536
/* Full system - 32 bits mode */
2537
static GenOpFunc1 *gen_op_lmw[] = {
2538
    &gen_op_lmw_user,
2539
    &gen_op_lmw_le_user,
2540
    &gen_op_lmw_kernel,
2541
    &gen_op_lmw_le_kernel,
2542
};
2543
static GenOpFunc1 *gen_op_stmw[] = {
2544
    &gen_op_stmw_user,
2545
    &gen_op_stmw_le_user,
2546
    &gen_op_stmw_kernel,
2547
    &gen_op_stmw_le_kernel,
2548
};
2549
#endif
2550
#endif
2551

    
2552
/* lmw */
2553
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2554
{
2555
    /* NIP cannot be restored if the memory exception comes from an helper */
2556
    gen_update_nip(ctx, ctx->nip - 4);
2557
    gen_addr_imm_index(ctx, 0);
2558
    op_ldstm(lmw, rD(ctx->opcode));
2559
}
2560

    
2561
/* stmw */
2562
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2563
{
2564
    /* NIP cannot be restored if the memory exception comes from an helper */
2565
    gen_update_nip(ctx, ctx->nip - 4);
2566
    gen_addr_imm_index(ctx, 0);
2567
    op_ldstm(stmw, rS(ctx->opcode));
2568
}
2569

    
2570
/***                    Integer load and store strings                     ***/
2571
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2572
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2573
#if defined(CONFIG_USER_ONLY)
2574
/* User-mode only */
2575
static GenOpFunc1 *gen_op_lswi[] = {
2576
    &gen_op_lswi_raw,
2577
    &gen_op_lswi_le_raw,
2578
#if defined(TARGET_PPC64)
2579
    &gen_op_lswi_64_raw,
2580
    &gen_op_lswi_le_64_raw,
2581
#endif
2582
};
2583
static GenOpFunc3 *gen_op_lswx[] = {
2584
    &gen_op_lswx_raw,
2585
    &gen_op_lswx_le_raw,
2586
#if defined(TARGET_PPC64)
2587
    &gen_op_lswx_64_raw,
2588
    &gen_op_lswx_le_64_raw,
2589
#endif
2590
};
2591
static GenOpFunc1 *gen_op_stsw[] = {
2592
    &gen_op_stsw_raw,
2593
    &gen_op_stsw_le_raw,
2594
#if defined(TARGET_PPC64)
2595
    &gen_op_stsw_64_raw,
2596
    &gen_op_stsw_le_64_raw,
2597
#endif
2598
};
2599
#else
2600
#if defined(TARGET_PPC64)
2601
/* Full system - 64 bits mode */
2602
static GenOpFunc1 *gen_op_lswi[] = {
2603
    &gen_op_lswi_user,
2604
    &gen_op_lswi_le_user,
2605
    &gen_op_lswi_64_user,
2606
    &gen_op_lswi_le_64_user,
2607
    &gen_op_lswi_kernel,
2608
    &gen_op_lswi_le_kernel,
2609
    &gen_op_lswi_64_kernel,
2610
    &gen_op_lswi_le_64_kernel,
2611
#if defined(TARGET_PPC64H)
2612
    &gen_op_lswi_hypv,
2613
    &gen_op_lswi_le_hypv,
2614
    &gen_op_lswi_64_hypv,
2615
    &gen_op_lswi_le_64_hypv,
2616
#endif
2617
};
2618
static GenOpFunc3 *gen_op_lswx[] = {
2619
    &gen_op_lswx_user,
2620
    &gen_op_lswx_le_user,
2621
    &gen_op_lswx_64_user,
2622
    &gen_op_lswx_le_64_user,
2623
    &gen_op_lswx_kernel,
2624
    &gen_op_lswx_le_kernel,
2625
    &gen_op_lswx_64_kernel,
2626
    &gen_op_lswx_le_64_kernel,
2627
#if defined(TARGET_PPC64H)
2628
    &gen_op_lswx_hypv,
2629
    &gen_op_lswx_le_hypv,
2630
    &gen_op_lswx_64_hypv,
2631
    &gen_op_lswx_le_64_hypv,
2632
#endif
2633
};
2634
static GenOpFunc1 *gen_op_stsw[] = {
2635
    &gen_op_stsw_user,
2636
    &gen_op_stsw_le_user,
2637
    &gen_op_stsw_64_user,
2638
    &gen_op_stsw_le_64_user,
2639
    &gen_op_stsw_kernel,
2640
    &gen_op_stsw_le_kernel,
2641
    &gen_op_stsw_64_kernel,
2642
    &gen_op_stsw_le_64_kernel,
2643
#if defined(TARGET_PPC64H)
2644
    &gen_op_stsw_hypv,
2645
    &gen_op_stsw_le_hypv,
2646
    &gen_op_stsw_64_hypv,
2647
    &gen_op_stsw_le_64_hypv,
2648
#endif
2649
};
2650
#else
2651
/* Full system - 32 bits mode */
2652
static GenOpFunc1 *gen_op_lswi[] = {
2653
    &gen_op_lswi_user,
2654
    &gen_op_lswi_le_user,
2655
    &gen_op_lswi_kernel,
2656
    &gen_op_lswi_le_kernel,
2657
};
2658
static GenOpFunc3 *gen_op_lswx[] = {
2659
    &gen_op_lswx_user,
2660
    &gen_op_lswx_le_user,
2661
    &gen_op_lswx_kernel,
2662
    &gen_op_lswx_le_kernel,
2663
};
2664
static GenOpFunc1 *gen_op_stsw[] = {
2665
    &gen_op_stsw_user,
2666
    &gen_op_stsw_le_user,
2667
    &gen_op_stsw_kernel,
2668
    &gen_op_stsw_le_kernel,
2669
};
2670
#endif
2671
#endif
2672

    
2673
/* lswi */
2674
/* PowerPC32 specification says we must generate an exception if
2675
 * rA is in the range of registers to be loaded.
2676
 * In an other hand, IBM says this is valid, but rA won't be loaded.
2677
 * For now, I'll follow the spec...
2678
 */
2679
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2680
{
2681
    int nb = NB(ctx->opcode);
2682
    int start = rD(ctx->opcode);
2683
    int ra = rA(ctx->opcode);
2684
    int nr;
2685

    
2686
    if (nb == 0)
2687
        nb = 32;
2688
    nr = nb / 4;
2689
    if (unlikely(((start + nr) > 32  &&
2690
                  start <= ra && (start + nr - 32) > ra) ||
2691
                 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2692
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2693
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2694
        return;
2695
    }
2696
    /* NIP cannot be restored if the memory exception comes from an helper */
2697
    gen_update_nip(ctx, ctx->nip - 4);
2698
    gen_addr_register(ctx);
2699
    gen_op_set_T1(nb);
2700
    op_ldsts(lswi, start);
2701
}
2702

    
2703
/* lswx */
2704
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2705
{
2706
    int ra = rA(ctx->opcode);
2707
    int rb = rB(ctx->opcode);
2708

    
2709
    /* NIP cannot be restored if the memory exception comes from an helper */
2710
    gen_update_nip(ctx, ctx->nip - 4);
2711
    gen_addr_reg_index(ctx);
2712
    if (ra == 0) {
2713
        ra = rb;
2714
    }
2715
    gen_op_load_xer_bc();
2716
    op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2717
}
2718

    
2719
/* stswi */
2720
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2721
{
2722
    int nb = NB(ctx->opcode);
2723

    
2724
    /* NIP cannot be restored if the memory exception comes from an helper */
2725
    gen_update_nip(ctx, ctx->nip - 4);
2726
    gen_addr_register(ctx);
2727
    if (nb == 0)
2728
        nb = 32;
2729
    gen_op_set_T1(nb);
2730
    op_ldsts(stsw, rS(ctx->opcode));
2731
}
2732

    
2733
/* stswx */
2734
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
2735
{
2736
    /* NIP cannot be restored if the memory exception comes from an helper */
2737
    gen_update_nip(ctx, ctx->nip - 4);
2738
    gen_addr_reg_index(ctx);
2739
    gen_op_load_xer_bc();
2740
    op_ldsts(stsw, rS(ctx->opcode));
2741
}
2742

    
2743
/***                        Memory synchronisation                         ***/
2744
/* eieio */
2745
GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2746
{
2747
}
2748

    
2749
/* isync */
2750
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2751
{
2752
    GEN_STOP(ctx);
2753
}
2754

    
2755
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2756
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2757
#if defined(CONFIG_USER_ONLY)
2758
/* User-mode only */
2759
static GenOpFunc *gen_op_lwarx[] = {
2760
    &gen_op_lwarx_raw,
2761
    &gen_op_lwarx_le_raw,
2762
#if defined(TARGET_PPC64)
2763
    &gen_op_lwarx_64_raw,
2764
    &gen_op_lwarx_le_64_raw,
2765
#endif
2766
};
2767
static GenOpFunc *gen_op_stwcx[] = {
2768
    &gen_op_stwcx_raw,
2769
    &gen_op_stwcx_le_raw,
2770
#if defined(TARGET_PPC64)
2771
    &gen_op_stwcx_64_raw,
2772
    &gen_op_stwcx_le_64_raw,
2773
#endif
2774
};
2775
#else
2776
#if defined(TARGET_PPC64)
2777
/* Full system - 64 bits mode */
2778
static GenOpFunc *gen_op_lwarx[] = {
2779
    &gen_op_lwarx_user,
2780
    &gen_op_lwarx_le_user,
2781
    &gen_op_lwarx_64_user,
2782
    &gen_op_lwarx_le_64_user,
2783
    &gen_op_lwarx_kernel,
2784
    &gen_op_lwarx_le_kernel,
2785
    &gen_op_lwarx_64_kernel,
2786
    &gen_op_lwarx_le_64_kernel,
2787
#if defined(TARGET_PPC64H)
2788
    &gen_op_lwarx_hypv,
2789
    &gen_op_lwarx_le_hypv,
2790
    &gen_op_lwarx_64_hypv,
2791
    &gen_op_lwarx_le_64_hypv,
2792
#endif
2793
};
2794
static GenOpFunc *gen_op_stwcx[] = {
2795
    &gen_op_stwcx_user,
2796
    &gen_op_stwcx_le_user,
2797
    &gen_op_stwcx_64_user,
2798
    &gen_op_stwcx_le_64_user,
2799
    &gen_op_stwcx_kernel,
2800
    &gen_op_stwcx_le_kernel,
2801
    &gen_op_stwcx_64_kernel,
2802
    &gen_op_stwcx_le_64_kernel,
2803
#if defined(TARGET_PPC64H)
2804
    &gen_op_stwcx_hypv,
2805
    &gen_op_stwcx_le_hypv,
2806
    &gen_op_stwcx_64_hypv,
2807
    &gen_op_stwcx_le_64_hypv,
2808
#endif
2809
};
2810
#else
2811
/* Full system - 32 bits mode */
2812
static GenOpFunc *gen_op_lwarx[] = {
2813
    &gen_op_lwarx_user,
2814
    &gen_op_lwarx_le_user,
2815
    &gen_op_lwarx_kernel,
2816
    &gen_op_lwarx_le_kernel,
2817
};
2818
static GenOpFunc *gen_op_stwcx[] = {
2819
    &gen_op_stwcx_user,
2820
    &gen_op_stwcx_le_user,
2821
    &gen_op_stwcx_kernel,
2822
    &gen_op_stwcx_le_kernel,
2823
};
2824
#endif
2825
#endif
2826

    
2827
/* lwarx */
2828
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2829
{
2830
    /* NIP cannot be restored if the memory exception comes from an helper */
2831
    gen_update_nip(ctx, ctx->nip - 4);
2832
    gen_addr_reg_index(ctx);
2833
    op_lwarx();
2834
    gen_op_store_T1_gpr(rD(ctx->opcode));
2835
}
2836

    
2837
/* stwcx. */
2838
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2839
{
2840
    /* NIP cannot be restored if the memory exception comes from an helper */
2841
    gen_update_nip(ctx, ctx->nip - 4);
2842
    gen_addr_reg_index(ctx);
2843
    gen_op_load_gpr_T1(rS(ctx->opcode));
2844
    op_stwcx();
2845
}
2846

    
2847
#if defined(TARGET_PPC64)
2848
#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2849
#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2850
#if defined(CONFIG_USER_ONLY)
2851
/* User-mode only */
2852
static GenOpFunc *gen_op_ldarx[] = {
2853
    &gen_op_ldarx_raw,
2854
    &gen_op_ldarx_le_raw,
2855
    &gen_op_ldarx_64_raw,
2856
    &gen_op_ldarx_le_64_raw,
2857
};
2858
static GenOpFunc *gen_op_stdcx[] = {
2859
    &gen_op_stdcx_raw,
2860
    &gen_op_stdcx_le_raw,
2861
    &gen_op_stdcx_64_raw,
2862
    &gen_op_stdcx_le_64_raw,
2863
};
2864
#else
2865
/* Full system */
2866
static GenOpFunc *gen_op_ldarx[] = {
2867
    &gen_op_ldarx_user,
2868
    &gen_op_ldarx_le_user,
2869
    &gen_op_ldarx_64_user,
2870
    &gen_op_ldarx_le_64_user,
2871
    &gen_op_ldarx_kernel,
2872
    &gen_op_ldarx_le_kernel,
2873
    &gen_op_ldarx_64_kernel,
2874
    &gen_op_ldarx_le_64_kernel,
2875
#if defined(TARGET_PPC64H)
2876
    &gen_op_ldarx_hypv,
2877
    &gen_op_ldarx_le_hypv,
2878
    &gen_op_ldarx_64_hypv,
2879
    &gen_op_ldarx_le_64_hypv,
2880
#endif
2881
};
2882
static GenOpFunc *gen_op_stdcx[] = {
2883
    &gen_op_stdcx_user,
2884
    &gen_op_stdcx_le_user,
2885
    &gen_op_stdcx_64_user,
2886
    &gen_op_stdcx_le_64_user,
2887
    &gen_op_stdcx_kernel,
2888
    &gen_op_stdcx_le_kernel,
2889
    &gen_op_stdcx_64_kernel,
2890
    &gen_op_stdcx_le_64_kernel,
2891
#if defined(TARGET_PPC64H)
2892
    &gen_op_stdcx_hypv,
2893
    &gen_op_stdcx_le_hypv,
2894
    &gen_op_stdcx_64_hypv,
2895
    &gen_op_stdcx_le_64_hypv,
2896
#endif
2897
};
2898
#endif
2899

    
2900
/* ldarx */
2901
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2902
{
2903
    /* NIP cannot be restored if the memory exception comes from an helper */
2904
    gen_update_nip(ctx, ctx->nip - 4);
2905
    gen_addr_reg_index(ctx);
2906
    op_ldarx();
2907
    gen_op_store_T1_gpr(rD(ctx->opcode));
2908
}
2909

    
2910
/* stdcx. */
2911
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2912
{
2913
    /* NIP cannot be restored if the memory exception comes from an helper */
2914
    gen_update_nip(ctx, ctx->nip - 4);
2915
    gen_addr_reg_index(ctx);
2916
    gen_op_load_gpr_T1(rS(ctx->opcode));
2917
    op_stdcx();
2918
}
2919
#endif /* defined(TARGET_PPC64) */
2920

    
2921
/* sync */
2922
GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2923
{
2924
}
2925

    
2926
/* wait */
2927
GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2928
{
2929
    /* Stop translation, as the CPU is supposed to sleep from now */
2930
    gen_op_wait();
2931
    GEN_EXCP(ctx, EXCP_HLT, 1);
2932
}
2933

    
2934
/***                         Floating-point load                           ***/
2935
#define GEN_LDF(width, opc, type)                                             \
2936
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
2937
{                                                                             \
2938
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2939
        GEN_EXCP_NO_FP(ctx);                                                  \
2940
        return;                                                               \
2941
    }                                                                         \
2942
    gen_addr_imm_index(ctx, 0);                                               \
2943
    op_ldst(l##width);                                                        \
2944
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2945
}
2946

    
2947
#define GEN_LDUF(width, opc, type)                                            \
2948
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
2949
{                                                                             \
2950
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2951
        GEN_EXCP_NO_FP(ctx);                                                  \
2952
        return;                                                               \
2953
    }                                                                         \
2954
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2955
        GEN_EXCP_INVAL(ctx);                                                  \
2956
        return;                                                               \
2957
    }                                                                         \
2958
    gen_addr_imm_index(ctx, 0);                                               \
2959
    op_ldst(l##width);                                                        \
2960
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2961
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2962
}
2963

    
2964
#define GEN_LDUXF(width, opc, type)                                           \
2965
GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                  \
2966
{                                                                             \
2967
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2968
        GEN_EXCP_NO_FP(ctx);                                                  \
2969
        return;                                                               \
2970
    }                                                                         \
2971
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
2972
        GEN_EXCP_INVAL(ctx);                                                  \
2973
        return;                                                               \
2974
    }                                                                         \
2975
    gen_addr_reg_index(ctx);                                                  \
2976
    op_ldst(l##width);                                                        \
2977
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2978
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
2979
}
2980

    
2981
#define GEN_LDXF(width, opc2, opc3, type)                                     \
2982
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
2983
{                                                                             \
2984
    if (unlikely(!ctx->fpu_enabled)) {                                        \
2985
        GEN_EXCP_NO_FP(ctx);                                                  \
2986
        return;                                                               \
2987
    }                                                                         \
2988
    gen_addr_reg_index(ctx);                                                  \
2989
    op_ldst(l##width);                                                        \
2990
    gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
2991
}
2992

    
2993
#define GEN_LDFS(width, op, type)                                             \
2994
OP_LD_TABLE(width);                                                           \
2995
GEN_LDF(width, op | 0x20, type);                                              \
2996
GEN_LDUF(width, op | 0x21, type);                                             \
2997
GEN_LDUXF(width, op | 0x01, type);                                            \
2998
GEN_LDXF(width, 0x17, op | 0x00, type)
2999

    
3000
/* lfd lfdu lfdux lfdx */
3001
GEN_LDFS(fd, 0x12, PPC_FLOAT);
3002
/* lfs lfsu lfsux lfsx */
3003
GEN_LDFS(fs, 0x10, PPC_FLOAT);
3004

    
3005
/***                         Floating-point store                          ***/
3006
#define GEN_STF(width, opc, type)                                             \
3007
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
3008
{                                                                             \
3009
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3010
        GEN_EXCP_NO_FP(ctx);                                                  \
3011
        return;                                                               \
3012
    }                                                                         \
3013
    gen_addr_imm_index(ctx, 0);                                               \
3014
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
3015
    op_ldst(st##width);                                                       \
3016
}
3017

    
3018
#define GEN_STUF(width, opc, type)                                            \
3019
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
3020
{                                                                             \
3021
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3022
        GEN_EXCP_NO_FP(ctx);                                                  \
3023
        return;                                                               \
3024
    }                                                                         \
3025
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3026
        GEN_EXCP_INVAL(ctx);                                                  \
3027
        return;                                                               \
3028
    }                                                                         \
3029
    gen_addr_imm_index(ctx, 0);                                               \
3030
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
3031
    op_ldst(st##width);                                                       \
3032
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
3033
}
3034

    
3035
#define GEN_STUXF(width, opc, type)                                           \
3036
GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                 \
3037
{                                                                             \
3038
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3039
        GEN_EXCP_NO_FP(ctx);                                                  \
3040
        return;                                                               \
3041
    }                                                                         \
3042
    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3043
        GEN_EXCP_INVAL(ctx);                                                  \
3044
        return;                                                               \
3045
    }                                                                         \
3046
    gen_addr_reg_index(ctx);                                                  \
3047
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
3048
    op_ldst(st##width);                                                       \
3049
    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
3050
}
3051

    
3052
#define GEN_STXF(width, opc2, opc3, type)                                     \
3053
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
3054
{                                                                             \
3055
    if (unlikely(!ctx->fpu_enabled)) {                                        \
3056
        GEN_EXCP_NO_FP(ctx);                                                  \
3057
        return;                                                               \
3058
    }                                                                         \
3059
    gen_addr_reg_index(ctx);                                                  \
3060
    gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
3061
    op_ldst(st##width);                                                       \
3062
}
3063

    
3064
#define GEN_STFS(width, op, type)                                             \
3065
OP_ST_TABLE(width);                                                           \
3066
GEN_STF(width, op | 0x20, type);                                              \
3067
GEN_STUF(width, op | 0x21, type);                                             \
3068
GEN_STUXF(width, op | 0x01, type);                                            \
3069
GEN_STXF(width, 0x17, op | 0x00, type)
3070

    
3071
/* stfd stfdu stfdux stfdx */
3072
GEN_STFS(fd, 0x16, PPC_FLOAT);
3073
/* stfs stfsu stfsux stfsx */
3074
GEN_STFS(fs, 0x14, PPC_FLOAT);
3075

    
3076
/* Optional: */
3077
/* stfiwx */
3078
OP_ST_TABLE(fiwx);
3079
GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3080

    
3081
/***                                Branch                                 ***/
3082
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3083
                                       target_ulong dest)
3084
{
3085
    TranslationBlock *tb;
3086
    tb = ctx->tb;
3087
    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3088
        if (n == 0)
3089
            gen_op_goto_tb0(TBPARAM(tb));
3090
        else
3091
            gen_op_goto_tb1(TBPARAM(tb));
3092
        gen_set_T1(dest);
3093
#if defined(TARGET_PPC64)
3094
        if (ctx->sf_mode)
3095
            gen_op_b_T1_64();
3096
        else
3097
#endif
3098
            gen_op_b_T1();
3099
        gen_op_set_T0((long)tb + n);
3100
        if (ctx->singlestep_enabled)
3101
            gen_op_debug();
3102
        gen_op_exit_tb();
3103
    } else {
3104
        gen_set_T1(dest);
3105
#if defined(TARGET_PPC64)
3106
        if (ctx->sf_mode)
3107
            gen_op_b_T1_64();
3108
        else
3109
#endif
3110
            gen_op_b_T1();
3111
        gen_op_reset_T0();
3112
        if (ctx->singlestep_enabled)
3113
            gen_op_debug();
3114
        gen_op_exit_tb();
3115
    }
3116
}
3117

    
3118
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3119
{
3120
#if defined(TARGET_PPC64)
3121
    if (ctx->sf_mode != 0 && (nip >> 32))
3122
        gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3123
    else
3124
#endif
3125
        gen_op_setlr(ctx->nip);
3126
}
3127

    
3128
/* b ba bl bla */
3129
GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3130
{
3131
    target_ulong li, target;
3132

    
3133
    /* sign extend LI */
3134
#if defined(TARGET_PPC64)
3135
    if (ctx->sf_mode)
3136
        li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3137
    else
3138
#endif
3139
        li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3140
    if (likely(AA(ctx->opcode) == 0))
3141
        target = ctx->nip + li - 4;
3142
    else
3143
        target = li;
3144
#if defined(TARGET_PPC64)
3145
    if (!ctx->sf_mode)
3146
        target = (uint32_t)target;
3147
#endif
3148
    if (LK(ctx->opcode))
3149
        gen_setlr(ctx, ctx->nip);
3150
    gen_goto_tb(ctx, 0, target);
3151
    ctx->exception = POWERPC_EXCP_BRANCH;
3152
}
3153

    
3154
#define BCOND_IM  0
3155
#define BCOND_LR  1
3156
#define BCOND_CTR 2
3157

    
3158
static always_inline void gen_bcond (DisasContext *ctx, int type)
3159
{
3160
    target_ulong target = 0;
3161
    target_ulong li;
3162
    uint32_t bo = BO(ctx->opcode);
3163
    uint32_t bi = BI(ctx->opcode);
3164
    uint32_t mask;
3165

    
3166
    if ((bo & 0x4) == 0)
3167
        gen_op_dec_ctr();
3168
    switch(type) {
3169
    case BCOND_IM:
3170
        li = (target_long)((int16_t)(BD(ctx->opcode)));
3171
        if (likely(AA(ctx->opcode) == 0)) {
3172
            target = ctx->nip + li - 4;
3173
        } else {
3174
            target = li;
3175
        }
3176
#if defined(TARGET_PPC64)
3177
        if (!ctx->sf_mode)
3178
            target = (uint32_t)target;
3179
#endif
3180
        break;
3181
    case BCOND_CTR:
3182
        gen_op_movl_T1_ctr();
3183
        break;
3184
    default:
3185
    case BCOND_LR:
3186
        gen_op_movl_T1_lr();
3187
        break;
3188
    }
3189
    if (LK(ctx->opcode))
3190
        gen_setlr(ctx, ctx->nip);
3191
    if (bo & 0x10) {
3192
        /* No CR condition */
3193
        switch (bo & 0x6) {
3194
        case 0:
3195
#if defined(TARGET_PPC64)
3196
            if (ctx->sf_mode)
3197
                gen_op_test_ctr_64();
3198
            else
3199
#endif
3200
                gen_op_test_ctr();
3201
            break;
3202
        case 2:
3203
#if defined(TARGET_PPC64)
3204
            if (ctx->sf_mode)
3205
                gen_op_test_ctrz_64();
3206
            else
3207
#endif
3208
                gen_op_test_ctrz();
3209
            break;
3210
        default:
3211
        case 4:
3212
        case 6:
3213
            if (type == BCOND_IM) {
3214
                gen_goto_tb(ctx, 0, target);
3215
                goto out;
3216
            } else {
3217
#if defined(TARGET_PPC64)
3218
                if (ctx->sf_mode)
3219
                    gen_op_b_T1_64();
3220
                else
3221
#endif
3222
                    gen_op_b_T1();
3223
                gen_op_reset_T0();
3224
                goto no_test;
3225
            }
3226
            break;
3227
        }
3228
    } else {
3229
        mask = 1 << (3 - (bi & 0x03));
3230
        gen_op_load_crf_T0(bi >> 2);
3231
        if (bo & 0x8) {
3232
            switch (bo & 0x6) {
3233
            case 0:
3234
#if defined(TARGET_PPC64)
3235
                if (ctx->sf_mode)
3236
                    gen_op_test_ctr_true_64(mask);
3237
                else
3238
#endif
3239
                    gen_op_test_ctr_true(mask);
3240
                break;
3241
            case 2:
3242
#if defined(TARGET_PPC64)
3243
                if (ctx->sf_mode)
3244
                    gen_op_test_ctrz_true_64(mask);
3245
                else
3246
#endif
3247
                    gen_op_test_ctrz_true(mask);
3248
                break;
3249
            default:
3250
            case 4:
3251
            case 6:
3252
                gen_op_test_true(mask);
3253
                break;
3254
            }
3255
        } else {
3256
            switch (bo & 0x6) {
3257
            case 0:
3258
#if defined(TARGET_PPC64)
3259
                if (ctx->sf_mode)
3260
                    gen_op_test_ctr_false_64(mask);
3261
                else
3262
#endif
3263
                    gen_op_test_ctr_false(mask);
3264
                break;
3265
            case 2:
3266
#if defined(TARGET_PPC64)
3267
                if (ctx->sf_mode)
3268
                    gen_op_test_ctrz_false_64(mask);
3269
                else
3270
#endif
3271
                    gen_op_test_ctrz_false(mask);
3272
                break;
3273
            default:
3274
            case 4:
3275
            case 6:
3276
                gen_op_test_false(mask);
3277
                break;
3278
            }
3279
        }
3280
    }
3281
    if (type == BCOND_IM) {
3282
        int l1 = gen_new_label();
3283
        gen_op_jz_T0(l1);
3284
        gen_goto_tb(ctx, 0, target);
3285
        gen_set_label(l1);
3286
        gen_goto_tb(ctx, 1, ctx->nip);
3287
    } else {
3288
#if defined(TARGET_PPC64)
3289
        if (ctx->sf_mode)
3290
            gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3291
        else
3292
#endif
3293
            gen_op_btest_T1(ctx->nip);
3294
        gen_op_reset_T0();
3295
    no_test:
3296
        if (ctx->singlestep_enabled)
3297
            gen_op_debug();
3298
        gen_op_exit_tb();
3299
    }
3300
 out:
3301
    ctx->exception = POWERPC_EXCP_BRANCH;
3302
}
3303

    
3304
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3305
{
3306
    gen_bcond(ctx, BCOND_IM);
3307
}
3308

    
3309
GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3310
{
3311
    gen_bcond(ctx, BCOND_CTR);
3312
}
3313

    
3314
GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3315
{
3316
    gen_bcond(ctx, BCOND_LR);
3317
}
3318

    
3319
/***                      Condition register logical                       ***/
3320
#define GEN_CRLOGIC(op, opc)                                                  \
3321
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)                 \
3322
{                                                                             \
3323
    uint8_t bitmask;                                                          \
3324
    int sh;                                                                   \
3325
    gen_op_load_crf_T0(crbA(ctx->opcode) >> 2);                               \
3326
    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
3327
    if (sh > 0)                                                               \
3328
        gen_op_srli_T0(sh);                                                   \
3329
    else if (sh < 0)                                                          \
3330
        gen_op_sli_T0(-sh);                                                   \
3331
    gen_op_load_crf_T1(crbB(ctx->opcode) >> 2);                               \
3332
    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
3333
    if (sh > 0)                                                               \
3334
        gen_op_srli_T1(sh);                                                   \
3335
    else if (sh < 0)                                                          \
3336
        gen_op_sli_T1(-sh);                                                   \
3337
    gen_op_##op();                                                            \
3338
    bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));                          \
3339
    gen_op_andi_T0(bitmask);                                                  \
3340
    gen_op_load_crf_T1(crbD(ctx->opcode) >> 2);                               \
3341
    gen_op_andi_T1(~bitmask);                                                 \
3342
    gen_op_or();                                                              \
3343
    gen_op_store_T0_crf(crbD(ctx->opcode) >> 2);                              \
3344
}
3345

    
3346
/* crand */
3347
GEN_CRLOGIC(and, 0x08);
3348
/* crandc */
3349
GEN_CRLOGIC(andc, 0x04);
3350
/* creqv */
3351
GEN_CRLOGIC(eqv, 0x09);
3352
/* crnand */
3353
GEN_CRLOGIC(nand, 0x07);
3354
/* crnor */
3355
GEN_CRLOGIC(nor, 0x01);
3356
/* cror */
3357
GEN_CRLOGIC(or, 0x0E);
3358
/* crorc */
3359
GEN_CRLOGIC(orc, 0x0D);
3360
/* crxor */
3361
GEN_CRLOGIC(xor, 0x06);
3362
/* mcrf */
3363
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3364
{
3365
    gen_op_load_crf_T0(crfS(ctx->opcode));
3366
    gen_op_store_T0_crf(crfD(ctx->opcode));
3367
}
3368

    
3369
/***                           System linkage                              ***/
3370
/* rfi (supervisor only) */
3371
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3372
{
3373
#if defined(CONFIG_USER_ONLY)
3374
    GEN_EXCP_PRIVOPC(ctx);
3375
#else
3376
    /* Restore CPU state */
3377
    if (unlikely(!ctx->supervisor)) {
3378
        GEN_EXCP_PRIVOPC(ctx);
3379
        return;
3380
    }
3381
    gen_op_rfi();
3382
    GEN_SYNC(ctx);
3383
#endif
3384
}
3385

    
3386
#if defined(TARGET_PPC64)
3387
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3388
{
3389
#if defined(CONFIG_USER_ONLY)
3390
    GEN_EXCP_PRIVOPC(ctx);
3391
#else
3392
    /* Restore CPU state */
3393
    if (unlikely(!ctx->supervisor)) {
3394
        GEN_EXCP_PRIVOPC(ctx);
3395
        return;
3396
    }
3397
    gen_op_rfid();
3398
    GEN_SYNC(ctx);
3399
#endif
3400
}
3401
#endif
3402

    
3403
#if defined(TARGET_PPC64H)
3404
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3405
{
3406
#if defined(CONFIG_USER_ONLY)
3407
    GEN_EXCP_PRIVOPC(ctx);
3408
#else
3409
    /* Restore CPU state */
3410
    if (unlikely(ctx->supervisor <= 1)) {
3411
        GEN_EXCP_PRIVOPC(ctx);
3412
        return;
3413
    }
3414
    gen_op_hrfid();
3415
    GEN_SYNC(ctx);
3416
#endif
3417
}
3418
#endif
3419

    
3420
/* sc */
3421
#if defined(CONFIG_USER_ONLY)
3422
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3423
#else
3424
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3425
#endif
3426
GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3427
{
3428
    uint32_t lev;
3429

    
3430
    lev = (ctx->opcode >> 5) & 0x7F;
3431
    GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3432
}
3433

    
3434
/***                                Trap                                   ***/
3435
/* tw */
3436
GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3437
{
3438
    gen_op_load_gpr_T0(rA(ctx->opcode));
3439
    gen_op_load_gpr_T1(rB(ctx->opcode));
3440
    /* Update the nip since this might generate a trap exception */
3441
    gen_update_nip(ctx, ctx->nip);
3442
    gen_op_tw(TO(ctx->opcode));
3443
}
3444

    
3445
/* twi */
3446
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3447
{
3448
    gen_op_load_gpr_T0(rA(ctx->opcode));
3449
    gen_set_T1(SIMM(ctx->opcode));
3450
    /* Update the nip since this might generate a trap exception */
3451
    gen_update_nip(ctx, ctx->nip);
3452
    gen_op_tw(TO(ctx->opcode));
3453
}
3454

    
3455
#if defined(TARGET_PPC64)
3456
/* td */
3457
GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3458
{
3459
    gen_op_load_gpr_T0(rA(ctx->opcode));
3460
    gen_op_load_gpr_T1(rB(ctx->opcode));
3461
    /* Update the nip since this might generate a trap exception */
3462
    gen_update_nip(ctx, ctx->nip);
3463
    gen_op_td(TO(ctx->opcode));
3464
}
3465

    
3466
/* tdi */
3467
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3468
{
3469
    gen_op_load_gpr_T0(rA(ctx->opcode));
3470
    gen_set_T1(SIMM(ctx->opcode));
3471
    /* Update the nip since this might generate a trap exception */
3472
    gen_update_nip(ctx, ctx->nip);
3473
    gen_op_td(TO(ctx->opcode));
3474
}
3475
#endif
3476

    
3477
/***                          Processor control                            ***/
3478
/* mcrxr */
3479
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3480
{
3481
    gen_op_load_xer_cr();
3482
    gen_op_store_T0_crf(crfD(ctx->opcode));
3483
    gen_op_clear_xer_ov();
3484
    gen_op_clear_xer_ca();
3485
}
3486

    
3487
/* mfcr */
3488
GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3489
{
3490
    uint32_t crm, crn;
3491

    
3492
    if (likely(ctx->opcode & 0x00100000)) {
3493
        crm = CRM(ctx->opcode);
3494
        if (likely((crm ^ (crm - 1)) == 0)) {
3495
            crn = ffs(crm);
3496
            gen_op_load_cro(7 - crn);
3497
        }
3498
    } else {
3499
        gen_op_load_cr();
3500
    }
3501
    gen_op_store_T0_gpr(rD(ctx->opcode));
3502
}
3503

    
3504
/* mfmsr */
3505
GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3506
{
3507
#if defined(CONFIG_USER_ONLY)
3508
    GEN_EXCP_PRIVREG(ctx);
3509
#else
3510
    if (unlikely(!ctx->supervisor)) {
3511
        GEN_EXCP_PRIVREG(ctx);
3512
        return;
3513
    }
3514
    gen_op_load_msr();
3515
    gen_op_store_T0_gpr(rD(ctx->opcode));
3516
#endif
3517
}
3518

    
3519
#if 1
3520
#define SPR_NOACCESS ((void *)(-1))
3521
#else
3522
static void spr_noaccess (void *opaque, int sprn)
3523
{
3524
    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3525
    printf("ERROR: try to access SPR %d !\n", sprn);
3526
}
3527
#define SPR_NOACCESS (&spr_noaccess)
3528
#endif
3529

    
3530
/* mfspr */
3531
static always_inline void gen_op_mfspr (DisasContext *ctx)
3532
{
3533
    void (*read_cb)(void *opaque, int sprn);
3534
    uint32_t sprn = SPR(ctx->opcode);
3535

    
3536
#if !defined(CONFIG_USER_ONLY)
3537
#if defined(TARGET_PPC64H)
3538
    if (ctx->supervisor == 2)
3539
        read_cb = ctx->spr_cb[sprn].hea_read;
3540
    else
3541
#endif
3542
    if (ctx->supervisor)
3543
        read_cb = ctx->spr_cb[sprn].oea_read;
3544
    else
3545
#endif
3546
        read_cb = ctx->spr_cb[sprn].uea_read;
3547
    if (likely(read_cb != NULL)) {
3548
        if (likely(read_cb != SPR_NOACCESS)) {
3549
            (*read_cb)(ctx, sprn);
3550
            gen_op_store_T0_gpr(rD(ctx->opcode));
3551
        } else {
3552
            /* Privilege exception */
3553
            /* This is a hack to avoid warnings when running Linux:
3554
             * this OS breaks the PowerPC virtualisation model,
3555
             * allowing userland application to read the PVR
3556
             */
3557
            if (sprn != SPR_PVR) {
3558
                if (loglevel != 0) {
3559
                    fprintf(logfile, "Trying to read privileged spr %d %03x at"
3560
                            ADDRX "\n", sprn, sprn, ctx->nip);
3561
                }
3562
                printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3563
                       sprn, sprn, ctx->nip);
3564
            }
3565
            GEN_EXCP_PRIVREG(ctx);
3566
        }
3567
    } else {
3568
        /* Not defined */
3569
        if (loglevel != 0) {
3570
            fprintf(logfile, "Trying to read invalid spr %d %03x at "
3571
                    ADDRX "\n", sprn, sprn, ctx->nip);
3572
        }
3573
        printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3574
               sprn, sprn, ctx->nip);
3575
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3576
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3577
    }
3578
}
3579

    
3580
GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3581
{
3582
    gen_op_mfspr(ctx);
3583
}
3584

    
3585
/* mftb */
3586
GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3587
{
3588
    gen_op_mfspr(ctx);
3589
}
3590

    
3591
/* mtcrf */
3592
GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3593
{
3594
    uint32_t crm, crn;
3595

    
3596
    gen_op_load_gpr_T0(rS(ctx->opcode));
3597
    crm = CRM(ctx->opcode);
3598
    if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3599
        crn = ffs(crm);
3600
        gen_op_srli_T0(crn * 4);
3601
        gen_op_andi_T0(0xF);
3602
        gen_op_store_cro(7 - crn);
3603
    } else {
3604
        gen_op_store_cr(crm);
3605
    }
3606
}
3607

    
3608
/* mtmsr */
3609
#if defined(TARGET_PPC64)
3610
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3611
{
3612
#if defined(CONFIG_USER_ONLY)
3613
    GEN_EXCP_PRIVREG(ctx);
3614
#else
3615
    if (unlikely(!ctx->supervisor)) {
3616
        GEN_EXCP_PRIVREG(ctx);
3617
        return;
3618
    }
3619
    gen_op_load_gpr_T0(rS(ctx->opcode));
3620
    if (ctx->opcode & 0x00010000) {
3621
        /* Special form that does not need any synchronisation */
3622
        gen_op_update_riee();
3623
    } else {
3624
        /* XXX: we need to update nip before the store
3625
         *      if we enter power saving mode, we will exit the loop
3626
         *      directly from ppc_store_msr
3627
         */
3628
        gen_update_nip(ctx, ctx->nip);
3629
        gen_op_store_msr();
3630
        /* Must stop the translation as machine state (may have) changed */
3631
        /* Note that mtmsr is not always defined as context-synchronizing */
3632
        ctx->exception = POWERPC_EXCP_STOP;
3633
    }
3634
#endif
3635
}
3636
#endif
3637

    
3638
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3639
{
3640
#if defined(CONFIG_USER_ONLY)
3641
    GEN_EXCP_PRIVREG(ctx);
3642
#else
3643
    if (unlikely(!ctx->supervisor)) {
3644
        GEN_EXCP_PRIVREG(ctx);
3645
        return;
3646
    }
3647
    gen_op_load_gpr_T0(rS(ctx->opcode));
3648
    if (ctx->opcode & 0x00010000) {
3649
        /* Special form that does not need any synchronisation */
3650
        gen_op_update_riee();
3651
    } else {
3652
        /* XXX: we need to update nip before the store
3653
         *      if we enter power saving mode, we will exit the loop
3654
         *      directly from ppc_store_msr
3655
         */
3656
        gen_update_nip(ctx, ctx->nip);
3657
#if defined(TARGET_PPC64)
3658
        if (!ctx->sf_mode)
3659
            gen_op_store_msr_32();
3660
        else
3661
#endif
3662
            gen_op_store_msr();
3663
        /* Must stop the translation as machine state (may have) changed */
3664
        /* Note that mtmsrd is not always defined as context-synchronizing */
3665
        ctx->exception = POWERPC_EXCP_STOP;
3666
    }
3667
#endif
3668
}
3669

    
3670
/* mtspr */
3671
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3672
{
3673
    void (*write_cb)(void *opaque, int sprn);
3674
    uint32_t sprn = SPR(ctx->opcode);
3675

    
3676
#if !defined(CONFIG_USER_ONLY)
3677
#if defined(TARGET_PPC64H)
3678
    if (ctx->supervisor == 2)
3679
        write_cb = ctx->spr_cb[sprn].hea_write;
3680
    else
3681
#endif
3682
    if (ctx->supervisor)
3683
        write_cb = ctx->spr_cb[sprn].oea_write;
3684
    else
3685
#endif
3686
        write_cb = ctx->spr_cb[sprn].uea_write;
3687
    if (likely(write_cb != NULL)) {
3688
        if (likely(write_cb != SPR_NOACCESS)) {
3689
            gen_op_load_gpr_T0(rS(ctx->opcode));
3690
            (*write_cb)(ctx, sprn);
3691
        } else {
3692
            /* Privilege exception */
3693
            if (loglevel != 0) {
3694
                fprintf(logfile, "Trying to write privileged spr %d %03x at "
3695
                        ADDRX "\n", sprn, sprn, ctx->nip);
3696
            }
3697
            printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3698
                   sprn, sprn, ctx->nip);
3699
            GEN_EXCP_PRIVREG(ctx);
3700
        }
3701
    } else {
3702
        /* Not defined */
3703
        if (loglevel != 0) {
3704
            fprintf(logfile, "Trying to write invalid spr %d %03x at "
3705
                    ADDRX "\n", sprn, sprn, ctx->nip);
3706
        }
3707
        printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3708
               sprn, sprn, ctx->nip);
3709
        GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3710
                 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3711
    }
3712
}
3713

    
3714
/***                         Cache management                              ***/
3715
/* dcbf */
3716
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3717
{
3718
    /* XXX: specification says this is treated as a load by the MMU */
3719
    gen_addr_reg_index(ctx);
3720
    op_ldst(lbz);
3721
}
3722

    
3723
/* dcbi (Supervisor only) */
3724
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3725
{
3726
#if defined(CONFIG_USER_ONLY)
3727
    GEN_EXCP_PRIVOPC(ctx);
3728
#else
3729
    if (unlikely(!ctx->supervisor)) {
3730
        GEN_EXCP_PRIVOPC(ctx);
3731
        return;
3732
    }
3733
    gen_addr_reg_index(ctx);
3734
    /* XXX: specification says this should be treated as a store by the MMU */
3735
    op_ldst(lbz);
3736
    op_ldst(stb);
3737
#endif
3738
}
3739

    
3740
/* dcdst */
3741
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3742
{
3743
    /* XXX: specification say this is treated as a load by the MMU */
3744
    gen_addr_reg_index(ctx);
3745
    op_ldst(lbz);
3746
}
3747

    
3748
/* dcbt */
3749
GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3750
{
3751
    /* interpreted as no-op */
3752
    /* XXX: specification say this is treated as a load by the MMU
3753
     *      but does not generate any exception
3754
     */
3755
}
3756

    
3757
/* dcbtst */
3758
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3759
{
3760
    /* interpreted as no-op */
3761
    /* XXX: specification say this is treated as a load by the MMU
3762
     *      but does not generate any exception
3763
     */
3764
}
3765

    
3766
/* dcbz */
3767
#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3768
#if defined(CONFIG_USER_ONLY)
3769
/* User-mode only */
3770
static GenOpFunc *gen_op_dcbz[4][4] = {
3771
    {
3772
        &gen_op_dcbz_l32_raw,
3773
        &gen_op_dcbz_l32_raw,
3774
#if defined(TARGET_PPC64)
3775
        &gen_op_dcbz_l32_64_raw,
3776
        &gen_op_dcbz_l32_64_raw,
3777
#endif
3778
    },
3779
    {
3780
        &gen_op_dcbz_l64_raw,
3781
        &gen_op_dcbz_l64_raw,
3782
#if defined(TARGET_PPC64)
3783
        &gen_op_dcbz_l64_64_raw,
3784
        &gen_op_dcbz_l64_64_raw,
3785
#endif
3786
    },
3787
    {
3788
        &gen_op_dcbz_l128_raw,
3789
        &gen_op_dcbz_l128_raw,
3790
#if defined(TARGET_PPC64)
3791
        &gen_op_dcbz_l128_64_raw,
3792
        &gen_op_dcbz_l128_64_raw,
3793
#endif
3794
    },
3795
    {
3796
        &gen_op_dcbz_raw,
3797
        &gen_op_dcbz_raw,
3798
#if defined(TARGET_PPC64)
3799
        &gen_op_dcbz_64_raw,
3800
        &gen_op_dcbz_64_raw,
3801
#endif
3802
    },
3803
};
3804
#else
3805
#if defined(TARGET_PPC64)
3806
/* Full system - 64 bits mode */
3807
static GenOpFunc *gen_op_dcbz[4][12] = {
3808
    {
3809
        &gen_op_dcbz_l32_user,
3810
        &gen_op_dcbz_l32_user,
3811
        &gen_op_dcbz_l32_64_user,
3812
        &gen_op_dcbz_l32_64_user,
3813
        &gen_op_dcbz_l32_kernel,
3814
        &gen_op_dcbz_l32_kernel,
3815
        &gen_op_dcbz_l32_64_kernel,
3816
        &gen_op_dcbz_l32_64_kernel,
3817
#if defined(TARGET_PPC64H)
3818
        &gen_op_dcbz_l32_hypv,
3819
        &gen_op_dcbz_l32_hypv,
3820
        &gen_op_dcbz_l32_64_hypv,
3821
        &gen_op_dcbz_l32_64_hypv,
3822
#endif
3823
    },
3824
    {
3825
        &gen_op_dcbz_l64_user,
3826
        &gen_op_dcbz_l64_user,
3827
        &gen_op_dcbz_l64_64_user,
3828
        &gen_op_dcbz_l64_64_user,
3829
        &gen_op_dcbz_l64_kernel,
3830
        &gen_op_dcbz_l64_kernel,
3831
        &gen_op_dcbz_l64_64_kernel,
3832
        &gen_op_dcbz_l64_64_kernel,
3833
#if defined(TARGET_PPC64H)
3834
        &gen_op_dcbz_l64_hypv,
3835
        &gen_op_dcbz_l64_hypv,
3836
        &gen_op_dcbz_l64_64_hypv,
3837
        &gen_op_dcbz_l64_64_hypv,
3838
#endif
3839
    },
3840
    {
3841
        &gen_op_dcbz_l128_user,
3842
        &gen_op_dcbz_l128_user,
3843
        &gen_op_dcbz_l128_64_user,
3844
        &gen_op_dcbz_l128_64_user,
3845
        &gen_op_dcbz_l128_kernel,
3846
        &gen_op_dcbz_l128_kernel,
3847
        &gen_op_dcbz_l128_64_kernel,
3848
        &gen_op_dcbz_l128_64_kernel,
3849
#if defined(TARGET_PPC64H)
3850
        &gen_op_dcbz_l128_hypv,
3851
        &gen_op_dcbz_l128_hypv,
3852
        &gen_op_dcbz_l128_64_hypv,
3853
        &gen_op_dcbz_l128_64_hypv,
3854
#endif
3855
    },
3856
    {
3857
        &gen_op_dcbz_user,
3858
        &gen_op_dcbz_user,
3859
        &gen_op_dcbz_64_user,
3860
        &gen_op_dcbz_64_user,
3861
        &gen_op_dcbz_kernel,
3862
        &gen_op_dcbz_kernel,
3863
        &gen_op_dcbz_64_kernel,
3864
        &gen_op_dcbz_64_kernel,
3865
#if defined(TARGET_PPC64H)
3866
        &gen_op_dcbz_hypv,
3867
        &gen_op_dcbz_hypv,
3868
        &gen_op_dcbz_64_hypv,
3869
        &gen_op_dcbz_64_hypv,
3870
#endif
3871
    },
3872
};
3873
#else
3874
/* Full system - 32 bits mode */
3875
static GenOpFunc *gen_op_dcbz[4][4] = {
3876
    {
3877
        &gen_op_dcbz_l32_user,
3878
        &gen_op_dcbz_l32_user,
3879
        &gen_op_dcbz_l32_kernel,
3880
        &gen_op_dcbz_l32_kernel,
3881
    },
3882
    {
3883
        &gen_op_dcbz_l64_user,
3884
        &gen_op_dcbz_l64_user,
3885
        &gen_op_dcbz_l64_kernel,
3886
        &gen_op_dcbz_l64_kernel,
3887
    },
3888
    {
3889
        &gen_op_dcbz_l128_user,
3890
        &gen_op_dcbz_l128_user,
3891
        &gen_op_dcbz_l128_kernel,
3892
        &gen_op_dcbz_l128_kernel,
3893
    },
3894
    {
3895
        &gen_op_dcbz_user,
3896
        &gen_op_dcbz_user,
3897
        &gen_op_dcbz_kernel,
3898
        &gen_op_dcbz_kernel,
3899
    },
3900
};
3901
#endif
3902
#endif
3903

    
3904
static always_inline void handler_dcbz (DisasContext *ctx,
3905
                                        int dcache_line_size)
3906
{
3907
    int n;
3908

    
3909
    switch (dcache_line_size) {
3910
    case 32:
3911
        n = 0;
3912
        break;
3913
    case 64:
3914
        n = 1;
3915
        break;
3916
    case 128:
3917
        n = 2;
3918
        break;
3919
    default:
3920
        n = 3;
3921
        break;
3922
    }
3923
    op_dcbz(n);
3924
}
3925

    
3926
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3927
{
3928
    gen_addr_reg_index(ctx);
3929
    handler_dcbz(ctx, ctx->dcache_line_size);
3930
    gen_op_check_reservation();
3931
}
3932

    
3933
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3934
{
3935
    gen_addr_reg_index(ctx);
3936
    if (ctx->opcode & 0x00200000)
3937
        handler_dcbz(ctx, ctx->dcache_line_size);
3938
    else
3939
        handler_dcbz(ctx, -1);
3940
    gen_op_check_reservation();
3941
}
3942

    
3943
/* icbi */
3944
#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3945
#if defined(CONFIG_USER_ONLY)
3946
/* User-mode only */
3947
static GenOpFunc *gen_op_icbi[] = {
3948
    &gen_op_icbi_raw,
3949
    &gen_op_icbi_raw,
3950
#if defined(TARGET_PPC64)
3951
    &gen_op_icbi_64_raw,
3952
    &gen_op_icbi_64_raw,
3953
#endif
3954
};
3955
#else
3956
/* Full system - 64 bits mode */
3957
#if defined(TARGET_PPC64)
3958
static GenOpFunc *gen_op_icbi[] = {
3959
    &gen_op_icbi_user,
3960
    &gen_op_icbi_user,
3961
    &gen_op_icbi_64_user,
3962
    &gen_op_icbi_64_user,
3963
    &gen_op_icbi_kernel,
3964
    &gen_op_icbi_kernel,
3965
    &gen_op_icbi_64_kernel,
3966
    &gen_op_icbi_64_kernel,
3967
#if defined(TARGET_PPC64H)
3968
    &gen_op_icbi_hypv,
3969
    &gen_op_icbi_hypv,
3970
    &gen_op_icbi_64_hypv,
3971
    &gen_op_icbi_64_hypv,
3972
#endif
3973
};
3974
#else
3975
/* Full system - 32 bits mode */
3976
static GenOpFunc *gen_op_icbi[] = {
3977
    &gen_op_icbi_user,
3978
    &gen_op_icbi_user,
3979
    &gen_op_icbi_kernel,
3980
    &gen_op_icbi_kernel,
3981
};
3982
#endif
3983
#endif
3984

    
3985
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
3986
{
3987
    /* NIP cannot be restored if the memory exception comes from an helper */
3988
    gen_update_nip(ctx, ctx->nip - 4);
3989
    gen_addr_reg_index(ctx);
3990
    op_icbi();
3991
}
3992

    
3993
/* Optional: */
3994
/* dcba */
3995
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3996
{
3997
    /* interpreted as no-op */
3998
    /* XXX: specification say this is treated as a store by the MMU
3999
     *      but does not generate any exception
4000
     */
4001
}
4002

    
4003
/***                    Segment register manipulation                      ***/
4004
/* Supervisor only: */
4005
/* mfsr */
4006
GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4007
{
4008
#if defined(CONFIG_USER_ONLY)
4009
    GEN_EXCP_PRIVREG(ctx);
4010
#else
4011
    if (unlikely(!ctx->supervisor)) {
4012
        GEN_EXCP_PRIVREG(ctx);
4013
        return;
4014
    }
4015
    gen_op_set_T1(SR(ctx->opcode));
4016
    gen_op_load_sr();
4017
    gen_op_store_T0_gpr(rD(ctx->opcode));
4018
#endif
4019
}
4020

    
4021
/* mfsrin */
4022
GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4023
{
4024
#if defined(CONFIG_USER_ONLY)
4025
    GEN_EXCP_PRIVREG(ctx);
4026
#else
4027
    if (unlikely(!ctx->supervisor)) {
4028
        GEN_EXCP_PRIVREG(ctx);
4029
        return;
4030
    }
4031
    gen_op_load_gpr_T1(rB(ctx->opcode));
4032
    gen_op_srli_T1(28);
4033
    gen_op_load_sr();
4034
    gen_op_store_T0_gpr(rD(ctx->opcode));
4035
#endif
4036
}
4037

    
4038
/* mtsr */
4039
GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4040
{
4041
#if defined(CONFIG_USER_ONLY)
4042
    GEN_EXCP_PRIVREG(ctx);
4043
#else
4044
    if (unlikely(!ctx->supervisor)) {
4045
        GEN_EXCP_PRIVREG(ctx);
4046
        return;
4047
    }
4048
    gen_op_load_gpr_T0(rS(ctx->opcode));
4049
    gen_op_set_T1(SR(ctx->opcode));
4050
    gen_op_store_sr();
4051
#endif
4052
}
4053

    
4054
/* mtsrin */
4055
GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4056
{
4057
#if defined(CONFIG_USER_ONLY)
4058
    GEN_EXCP_PRIVREG(ctx);
4059
#else
4060
    if (unlikely(!ctx->supervisor)) {
4061
        GEN_EXCP_PRIVREG(ctx);
4062
        return;
4063
    }
4064
    gen_op_load_gpr_T0(rS(ctx->opcode));
4065
    gen_op_load_gpr_T1(rB(ctx->opcode));
4066
    gen_op_srli_T1(28);
4067
    gen_op_store_sr();
4068
#endif
4069
}
4070

    
4071
#if defined(TARGET_PPC64)
4072
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4073
/* mfsr */
4074
GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4075
{
4076
#if defined(CONFIG_USER_ONLY)
4077
    GEN_EXCP_PRIVREG(ctx);
4078
#else
4079
    if (unlikely(!ctx->supervisor)) {
4080
        GEN_EXCP_PRIVREG(ctx);
4081
        return;
4082
    }
4083
    gen_op_set_T1(SR(ctx->opcode));
4084
    gen_op_load_slb();
4085
    gen_op_store_T0_gpr(rD(ctx->opcode));
4086
#endif
4087
}
4088

    
4089
/* mfsrin */
4090
GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4091
             PPC_SEGMENT_64B)
4092
{
4093
#if defined(CONFIG_USER_ONLY)
4094
    GEN_EXCP_PRIVREG(ctx);
4095
#else
4096
    if (unlikely(!ctx->supervisor)) {
4097
        GEN_EXCP_PRIVREG(ctx);
4098
        return;
4099
    }
4100
    gen_op_load_gpr_T1(rB(ctx->opcode));
4101
    gen_op_srli_T1(28);
4102
    gen_op_load_slb();
4103
    gen_op_store_T0_gpr(rD(ctx->opcode));
4104
#endif
4105
}
4106

    
4107
/* mtsr */
4108
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4109
{
4110
#if defined(CONFIG_USER_ONLY)
4111
    GEN_EXCP_PRIVREG(ctx);
4112
#else
4113
    if (unlikely(!ctx->supervisor)) {
4114
        GEN_EXCP_PRIVREG(ctx);
4115
        return;
4116
    }
4117
    gen_op_load_gpr_T0(rS(ctx->opcode));
4118
    gen_op_set_T1(SR(ctx->opcode));
4119
    gen_op_store_slb();
4120
#endif
4121
}
4122

    
4123
/* mtsrin */
4124
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4125
             PPC_SEGMENT_64B)
4126
{
4127
#if defined(CONFIG_USER_ONLY)
4128
    GEN_EXCP_PRIVREG(ctx);
4129
#else
4130
    if (unlikely(!ctx->supervisor)) {
4131
        GEN_EXCP_PRIVREG(ctx);
4132
        return;
4133
    }
4134
    gen_op_load_gpr_T0(rS(ctx->opcode));
4135
    gen_op_load_gpr_T1(rB(ctx->opcode));
4136
    gen_op_srli_T1(28);
4137
    gen_op_store_slb();
4138
#endif
4139
}
4140
#endif /* defined(TARGET_PPC64) */
4141

    
4142
/***                      Lookaside buffer management                      ***/
4143
/* Optional & supervisor only: */
4144
/* tlbia */
4145
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4146
{
4147
#if defined(CONFIG_USER_ONLY)
4148
    GEN_EXCP_PRIVOPC(ctx);
4149
#else
4150
    if (unlikely(!ctx->supervisor)) {
4151
        if (loglevel != 0)
4152
            fprintf(logfile, "%s: ! supervisor\n", __func__);
4153
        GEN_EXCP_PRIVOPC(ctx);
4154
        return;
4155
    }
4156
    gen_op_tlbia();
4157
#endif
4158
}
4159

    
4160
/* tlbie */
4161
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4162
{
4163
#if defined(CONFIG_USER_ONLY)
4164
    GEN_EXCP_PRIVOPC(ctx);
4165
#else
4166
    if (unlikely(!ctx->supervisor)) {
4167
        GEN_EXCP_PRIVOPC(ctx);
4168
        return;
4169
    }
4170
    gen_op_load_gpr_T0(rB(ctx->opcode));
4171
#if defined(TARGET_PPC64)
4172
    if (ctx->sf_mode)
4173
        gen_op_tlbie_64();
4174
    else
4175
#endif
4176
        gen_op_tlbie();
4177
#endif
4178
}
4179

    
4180
/* tlbsync */
4181
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4182
{
4183
#if defined(CONFIG_USER_ONLY)
4184
    GEN_EXCP_PRIVOPC(ctx);
4185
#else
4186
    if (unlikely(!ctx->supervisor)) {
4187
        GEN_EXCP_PRIVOPC(ctx);
4188
        return;
4189
    }
4190
    /* This has no effect: it should ensure that all previous
4191
     * tlbie have completed
4192
     */
4193
    GEN_STOP(ctx);
4194
#endif
4195
}
4196

    
4197
#if defined(TARGET_PPC64)
4198
/* slbia */
4199
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4200
{
4201
#if defined(CONFIG_USER_ONLY)
4202
    GEN_EXCP_PRIVOPC(ctx);
4203
#else
4204
    if (unlikely(!ctx->supervisor)) {
4205
        if (loglevel != 0)
4206
            fprintf(logfile, "%s: ! supervisor\n", __func__);
4207
        GEN_EXCP_PRIVOPC(ctx);
4208
        return;
4209
    }
4210
    gen_op_slbia();
4211
#endif
4212
}
4213

    
4214
/* slbie */
4215
GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4216
{
4217
#if defined(CONFIG_USER_ONLY)
4218
    GEN_EXCP_PRIVOPC(ctx);
4219
#else
4220
    if (unlikely(!ctx->supervisor)) {
4221
        GEN_EXCP_PRIVOPC(ctx);
4222
        return;
4223
    }
4224
    gen_op_load_gpr_T0(rB(ctx->opcode));
4225
    gen_op_slbie();
4226
#endif
4227
}
4228
#endif
4229

    
4230
/***                              External control                         ***/
4231
/* Optional: */
4232
#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4233
#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4234
#if defined(CONFIG_USER_ONLY)
4235
/* User-mode only */
4236
static GenOpFunc *gen_op_eciwx[] = {
4237
    &gen_op_eciwx_raw,
4238
    &gen_op_eciwx_le_raw,
4239
#if defined(TARGET_PPC64)
4240
    &gen_op_eciwx_64_raw,
4241
    &gen_op_eciwx_le_64_raw,
4242
#endif
4243
};
4244
static GenOpFunc *gen_op_ecowx[] = {
4245
    &gen_op_ecowx_raw,
4246
    &gen_op_ecowx_le_raw,
4247
#if defined(TARGET_PPC64)
4248
    &gen_op_ecowx_64_raw,
4249
    &gen_op_ecowx_le_64_raw,
4250
#endif
4251
};
4252
#else
4253
#if defined(TARGET_PPC64)
4254
/* Full system - 64 bits mode */
4255
static GenOpFunc *gen_op_eciwx[] = {
4256
    &gen_op_eciwx_user,
4257
    &gen_op_eciwx_le_user,
4258
    &gen_op_eciwx_64_user,
4259
    &gen_op_eciwx_le_64_user,
4260
    &gen_op_eciwx_kernel,
4261
    &gen_op_eciwx_le_kernel,
4262
    &gen_op_eciwx_64_kernel,
4263
    &gen_op_eciwx_le_64_kernel,
4264
#if defined(TARGET_PPC64H)
4265
    &gen_op_eciwx_hypv,
4266
    &gen_op_eciwx_le_hypv,
4267
    &gen_op_eciwx_64_hypv,
4268
    &gen_op_eciwx_le_64_hypv,
4269
#endif
4270
};
4271
static GenOpFunc *gen_op_ecowx[] = {
4272
    &gen_op_ecowx_user,
4273
    &gen_op_ecowx_le_user,
4274
    &gen_op_ecowx_64_user,
4275
    &gen_op_ecowx_le_64_user,
4276
    &gen_op_ecowx_kernel,
4277
    &gen_op_ecowx_le_kernel,
4278
    &gen_op_ecowx_64_kernel,
4279
    &gen_op_ecowx_le_64_kernel,
4280
#if defined(TARGET_PPC64H)
4281
    &gen_op_ecowx_hypv,
4282
    &gen_op_ecowx_le_hypv,
4283
    &gen_op_ecowx_64_hypv,
4284
    &gen_op_ecowx_le_64_hypv,
4285
#endif
4286
};
4287
#else
4288
/* Full system - 32 bits mode */
4289
static GenOpFunc *gen_op_eciwx[] = {
4290
    &gen_op_eciwx_user,
4291
    &gen_op_eciwx_le_user,
4292
    &gen_op_eciwx_kernel,
4293
    &gen_op_eciwx_le_kernel,
4294
};
4295
static GenOpFunc *gen_op_ecowx[] = {
4296
    &gen_op_ecowx_user,
4297
    &gen_op_ecowx_le_user,
4298
    &gen_op_ecowx_kernel,
4299
    &gen_op_ecowx_le_kernel,
4300
};
4301
#endif
4302
#endif
4303

    
4304
/* eciwx */
4305
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4306
{
4307
    /* Should check EAR[E] & alignment ! */
4308
    gen_addr_reg_index(ctx);
4309
    op_eciwx();
4310
    gen_op_store_T0_gpr(rD(ctx->opcode));
4311
}
4312

    
4313
/* ecowx */
4314
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4315
{
4316
    /* Should check EAR[E] & alignment ! */
4317
    gen_addr_reg_index(ctx);
4318
    gen_op_load_gpr_T1(rS(ctx->opcode));
4319
    op_ecowx();
4320
}
4321

    
4322
/* PowerPC 601 specific instructions */
4323
/* abs - abs. */
4324
GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4325
{
4326
    gen_op_load_gpr_T0(rA(ctx->opcode));
4327
    gen_op_POWER_abs();
4328
    gen_op_store_T0_gpr(rD(ctx->opcode));
4329
    if (unlikely(Rc(ctx->opcode) != 0))
4330
        gen_set_Rc0(ctx);
4331
}
4332

    
4333
/* abso - abso. */
4334
GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4335
{
4336
    gen_op_load_gpr_T0(rA(ctx->opcode));
4337
    gen_op_POWER_abso();
4338
    gen_op_store_T0_gpr(rD(ctx->opcode));
4339
    if (unlikely(Rc(ctx->opcode) != 0))
4340
        gen_set_Rc0(ctx);
4341
}
4342

    
4343
/* clcs */
4344
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4345
{
4346
    gen_op_load_gpr_T0(rA(ctx->opcode));
4347
    gen_op_POWER_clcs();
4348
    /* Rc=1 sets CR0 to an undefined state */
4349
    gen_op_store_T0_gpr(rD(ctx->opcode));
4350
}
4351

    
4352
/* div - div. */
4353
GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4354
{
4355
    gen_op_load_gpr_T0(rA(ctx->opcode));
4356
    gen_op_load_gpr_T1(rB(ctx->opcode));
4357
    gen_op_POWER_div();
4358
    gen_op_store_T0_gpr(rD(ctx->opcode));
4359
    if (unlikely(Rc(ctx->opcode) != 0))
4360
        gen_set_Rc0(ctx);
4361
}
4362

    
4363
/* divo - divo. */
4364
GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4365
{
4366
    gen_op_load_gpr_T0(rA(ctx->opcode));
4367
    gen_op_load_gpr_T1(rB(ctx->opcode));
4368
    gen_op_POWER_divo();
4369
    gen_op_store_T0_gpr(rD(ctx->opcode));
4370
    if (unlikely(Rc(ctx->opcode) != 0))
4371
        gen_set_Rc0(ctx);
4372
}
4373

    
4374
/* divs - divs. */
4375
GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4376
{
4377
    gen_op_load_gpr_T0(rA(ctx->opcode));
4378
    gen_op_load_gpr_T1(rB(ctx->opcode));
4379
    gen_op_POWER_divs();
4380
    gen_op_store_T0_gpr(rD(ctx->opcode));
4381
    if (unlikely(Rc(ctx->opcode) != 0))
4382
        gen_set_Rc0(ctx);
4383
}
4384

    
4385
/* divso - divso. */
4386
GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4387
{
4388
    gen_op_load_gpr_T0(rA(ctx->opcode));
4389
    gen_op_load_gpr_T1(rB(ctx->opcode));
4390
    gen_op_POWER_divso();
4391
    gen_op_store_T0_gpr(rD(ctx->opcode));
4392
    if (unlikely(Rc(ctx->opcode) != 0))
4393
        gen_set_Rc0(ctx);
4394
}
4395

    
4396
/* doz - doz. */
4397
GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4398
{
4399
    gen_op_load_gpr_T0(rA(ctx->opcode));
4400
    gen_op_load_gpr_T1(rB(ctx->opcode));
4401
    gen_op_POWER_doz();
4402
    gen_op_store_T0_gpr(rD(ctx->opcode));
4403
    if (unlikely(Rc(ctx->opcode) != 0))
4404
        gen_set_Rc0(ctx);
4405
}
4406

    
4407
/* dozo - dozo. */
4408
GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4409
{
4410
    gen_op_load_gpr_T0(rA(ctx->opcode));
4411
    gen_op_load_gpr_T1(rB(ctx->opcode));
4412
    gen_op_POWER_dozo();
4413
    gen_op_store_T0_gpr(rD(ctx->opcode));
4414
    if (unlikely(Rc(ctx->opcode) != 0))
4415
        gen_set_Rc0(ctx);
4416
}
4417

    
4418
/* dozi */
4419
GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4420
{
4421
    gen_op_load_gpr_T0(rA(ctx->opcode));
4422
    gen_op_set_T1(SIMM(ctx->opcode));
4423
    gen_op_POWER_doz();
4424
    gen_op_store_T0_gpr(rD(ctx->opcode));
4425
}
4426

    
4427
/* As lscbx load from memory byte after byte, it's always endian safe */
4428
#define op_POWER_lscbx(start, ra, rb)                                         \
4429
(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4430
#if defined(CONFIG_USER_ONLY)
4431
static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4432
    &gen_op_POWER_lscbx_raw,
4433
    &gen_op_POWER_lscbx_raw,
4434
};
4435
#else
4436
static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4437
    &gen_op_POWER_lscbx_user,
4438
    &gen_op_POWER_lscbx_user,
4439
    &gen_op_POWER_lscbx_kernel,
4440
    &gen_op_POWER_lscbx_kernel,
4441
};
4442
#endif
4443

    
4444
/* lscbx - lscbx. */
4445
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4446
{
4447
    int ra = rA(ctx->opcode);
4448
    int rb = rB(ctx->opcode);
4449

    
4450
    gen_addr_reg_index(ctx);
4451
    if (ra == 0) {
4452
        ra = rb;
4453
    }
4454
    /* NIP cannot be restored if the memory exception comes from an helper */
4455
    gen_update_nip(ctx, ctx->nip - 4);
4456
    gen_op_load_xer_bc();
4457
    gen_op_load_xer_cmp();
4458
    op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4459
    gen_op_store_xer_bc();
4460
    if (unlikely(Rc(ctx->opcode) != 0))
4461
        gen_set_Rc0(ctx);
4462
}
4463

    
4464
/* maskg - maskg. */
4465
GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4466
{
4467
    gen_op_load_gpr_T0(rS(ctx->opcode));
4468
    gen_op_load_gpr_T1(rB(ctx->opcode));
4469
    gen_op_POWER_maskg();
4470
    gen_op_store_T0_gpr(rA(ctx->opcode));
4471
    if (unlikely(Rc(ctx->opcode) != 0))
4472
        gen_set_Rc0(ctx);
4473
}
4474

    
4475
/* maskir - maskir. */
4476
GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4477
{
4478
    gen_op_load_gpr_T0(rA(ctx->opcode));
4479
    gen_op_load_gpr_T1(rS(ctx->opcode));
4480
    gen_op_load_gpr_T2(rB(ctx->opcode));
4481
    gen_op_POWER_maskir();
4482
    gen_op_store_T0_gpr(rA(ctx->opcode));
4483
    if (unlikely(Rc(ctx->opcode) != 0))
4484
        gen_set_Rc0(ctx);
4485
}
4486

    
4487
/* mul - mul. */
4488
GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4489
{
4490
    gen_op_load_gpr_T0(rA(ctx->opcode));
4491
    gen_op_load_gpr_T1(rB(ctx->opcode));
4492
    gen_op_POWER_mul();
4493
    gen_op_store_T0_gpr(rD(ctx->opcode));
4494
    if (unlikely(Rc(ctx->opcode) != 0))
4495
        gen_set_Rc0(ctx);
4496
}
4497

    
4498
/* mulo - mulo. */
4499
GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4500
{
4501
    gen_op_load_gpr_T0(rA(ctx->opcode));
4502
    gen_op_load_gpr_T1(rB(ctx->opcode));
4503
    gen_op_POWER_mulo();
4504
    gen_op_store_T0_gpr(rD(ctx->opcode));
4505
    if (unlikely(Rc(ctx->opcode) != 0))
4506
        gen_set_Rc0(ctx);
4507
}
4508

    
4509
/* nabs - nabs. */
4510
GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4511
{
4512
    gen_op_load_gpr_T0(rA(ctx->opcode));
4513
    gen_op_POWER_nabs();
4514
    gen_op_store_T0_gpr(rD(ctx->opcode));
4515
    if (unlikely(Rc(ctx->opcode) != 0))
4516
        gen_set_Rc0(ctx);
4517
}
4518

    
4519
/* nabso - nabso. */
4520
GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4521
{
4522
    gen_op_load_gpr_T0(rA(ctx->opcode));
4523
    gen_op_POWER_nabso();
4524
    gen_op_store_T0_gpr(rD(ctx->opcode));
4525
    if (unlikely(Rc(ctx->opcode) != 0))
4526
        gen_set_Rc0(ctx);
4527
}
4528

    
4529
/* rlmi - rlmi. */
4530
GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4531
{
4532
    uint32_t mb, me;
4533

    
4534
    mb = MB(ctx->opcode);
4535
    me = ME(ctx->opcode);
4536
    gen_op_load_gpr_T0(rS(ctx->opcode));
4537
    gen_op_load_gpr_T1(rA(ctx->opcode));
4538
    gen_op_load_gpr_T2(rB(ctx->opcode));
4539
    gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4540
    gen_op_store_T0_gpr(rA(ctx->opcode));
4541
    if (unlikely(Rc(ctx->opcode) != 0))
4542
        gen_set_Rc0(ctx);
4543
}
4544

    
4545
/* rrib - rrib. */
4546
GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4547
{
4548
    gen_op_load_gpr_T0(rS(ctx->opcode));
4549
    gen_op_load_gpr_T1(rA(ctx->opcode));
4550
    gen_op_load_gpr_T2(rB(ctx->opcode));
4551
    gen_op_POWER_rrib();
4552
    gen_op_store_T0_gpr(rA(ctx->opcode));
4553
    if (unlikely(Rc(ctx->opcode) != 0))
4554
        gen_set_Rc0(ctx);
4555
}
4556

    
4557
/* sle - sle. */
4558
GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4559
{
4560
    gen_op_load_gpr_T0(rS(ctx->opcode));
4561
    gen_op_load_gpr_T1(rB(ctx->opcode));
4562
    gen_op_POWER_sle();
4563
    gen_op_store_T0_gpr(rA(ctx->opcode));
4564
    if (unlikely(Rc(ctx->opcode) != 0))
4565
        gen_set_Rc0(ctx);
4566
}
4567

    
4568
/* sleq - sleq. */
4569
GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4570
{
4571
    gen_op_load_gpr_T0(rS(ctx->opcode));
4572
    gen_op_load_gpr_T1(rB(ctx->opcode));
4573
    gen_op_POWER_sleq();
4574
    gen_op_store_T0_gpr(rA(ctx->opcode));
4575
    if (unlikely(Rc(ctx->opcode) != 0))
4576
        gen_set_Rc0(ctx);
4577
}
4578

    
4579
/* sliq - sliq. */
4580
GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4581
{
4582
    gen_op_load_gpr_T0(rS(ctx->opcode));
4583
    gen_op_set_T1(SH(ctx->opcode));
4584
    gen_op_POWER_sle();
4585
    gen_op_store_T0_gpr(rA(ctx->opcode));
4586
    if (unlikely(Rc(ctx->opcode) != 0))
4587
        gen_set_Rc0(ctx);
4588
}
4589

    
4590
/* slliq - slliq. */
4591
GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4592
{
4593
    gen_op_load_gpr_T0(rS(ctx->opcode));
4594
    gen_op_set_T1(SH(ctx->opcode));
4595
    gen_op_POWER_sleq();
4596
    gen_op_store_T0_gpr(rA(ctx->opcode));
4597
    if (unlikely(Rc(ctx->opcode) != 0))
4598
        gen_set_Rc0(ctx);
4599
}
4600

    
4601
/* sllq - sllq. */
4602
GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4603
{
4604
    gen_op_load_gpr_T0(rS(ctx->opcode));
4605
    gen_op_load_gpr_T1(rB(ctx->opcode));
4606
    gen_op_POWER_sllq();
4607
    gen_op_store_T0_gpr(rA(ctx->opcode));
4608
    if (unlikely(Rc(ctx->opcode) != 0))
4609
        gen_set_Rc0(ctx);
4610
}
4611

    
4612
/* slq - slq. */
4613
GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4614
{
4615
    gen_op_load_gpr_T0(rS(ctx->opcode));
4616
    gen_op_load_gpr_T1(rB(ctx->opcode));
4617
    gen_op_POWER_slq();
4618
    gen_op_store_T0_gpr(rA(ctx->opcode));
4619
    if (unlikely(Rc(ctx->opcode) != 0))
4620
        gen_set_Rc0(ctx);
4621
}
4622

    
4623
/* sraiq - sraiq. */
4624
GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4625
{
4626
    gen_op_load_gpr_T0(rS(ctx->opcode));
4627
    gen_op_set_T1(SH(ctx->opcode));
4628
    gen_op_POWER_sraq();
4629
    gen_op_store_T0_gpr(rA(ctx->opcode));
4630
    if (unlikely(Rc(ctx->opcode) != 0))
4631
        gen_set_Rc0(ctx);
4632
}
4633

    
4634
/* sraq - sraq. */
4635
GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4636
{
4637
    gen_op_load_gpr_T0(rS(ctx->opcode));
4638
    gen_op_load_gpr_T1(rB(ctx->opcode));
4639
    gen_op_POWER_sraq();
4640
    gen_op_store_T0_gpr(rA(ctx->opcode));
4641
    if (unlikely(Rc(ctx->opcode) != 0))
4642
        gen_set_Rc0(ctx);
4643
}
4644

    
4645
/* sre - sre. */
4646
GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4647
{
4648
    gen_op_load_gpr_T0(rS(ctx->opcode));
4649
    gen_op_load_gpr_T1(rB(ctx->opcode));
4650
    gen_op_POWER_sre();
4651
    gen_op_store_T0_gpr(rA(ctx->opcode));
4652
    if (unlikely(Rc(ctx->opcode) != 0))
4653
        gen_set_Rc0(ctx);
4654
}
4655

    
4656
/* srea - srea. */
4657
GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4658
{
4659
    gen_op_load_gpr_T0(rS(ctx->opcode));
4660
    gen_op_load_gpr_T1(rB(ctx->opcode));
4661
    gen_op_POWER_srea();
4662
    gen_op_store_T0_gpr(rA(ctx->opcode));
4663
    if (unlikely(Rc(ctx->opcode) != 0))
4664
        gen_set_Rc0(ctx);
4665
}
4666

    
4667
/* sreq */
4668
GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4669
{
4670
    gen_op_load_gpr_T0(rS(ctx->opcode));
4671
    gen_op_load_gpr_T1(rB(ctx->opcode));
4672
    gen_op_POWER_sreq();
4673
    gen_op_store_T0_gpr(rA(ctx->opcode));
4674
    if (unlikely(Rc(ctx->opcode) != 0))
4675
        gen_set_Rc0(ctx);
4676
}
4677

    
4678
/* sriq */
4679
GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4680
{
4681
    gen_op_load_gpr_T0(rS(ctx->opcode));
4682
    gen_op_set_T1(SH(ctx->opcode));
4683
    gen_op_POWER_srq();
4684
    gen_op_store_T0_gpr(rA(ctx->opcode));
4685
    if (unlikely(Rc(ctx->opcode) != 0))
4686
        gen_set_Rc0(ctx);
4687
}
4688

    
4689
/* srliq */
4690
GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4691
{
4692
    gen_op_load_gpr_T0(rS(ctx->opcode));
4693
    gen_op_load_gpr_T1(rB(ctx->opcode));
4694
    gen_op_set_T1(SH(ctx->opcode));
4695
    gen_op_POWER_srlq();
4696
    gen_op_store_T0_gpr(rA(ctx->opcode));
4697
    if (unlikely(Rc(ctx->opcode) != 0))
4698
        gen_set_Rc0(ctx);
4699
}
4700

    
4701
/* srlq */
4702
GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4703
{
4704
    gen_op_load_gpr_T0(rS(ctx->opcode));
4705
    gen_op_load_gpr_T1(rB(ctx->opcode));
4706
    gen_op_POWER_srlq();
4707
    gen_op_store_T0_gpr(rA(ctx->opcode));
4708
    if (unlikely(Rc(ctx->opcode) != 0))
4709
        gen_set_Rc0(ctx);
4710
}
4711

    
4712
/* srq */
4713
GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4714
{
4715
    gen_op_load_gpr_T0(rS(ctx->opcode));
4716
    gen_op_load_gpr_T1(rB(ctx->opcode));
4717
    gen_op_POWER_srq();
4718
    gen_op_store_T0_gpr(rA(ctx->opcode));
4719
    if (unlikely(Rc(ctx->opcode) != 0))
4720
        gen_set_Rc0(ctx);
4721
}
4722

    
4723
/* PowerPC 602 specific instructions */
4724
/* dsa  */
4725
GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4726
{
4727
    /* XXX: TODO */
4728
    GEN_EXCP_INVAL(ctx);
4729
}
4730

    
4731
/* esa */
4732
GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4733
{
4734
    /* XXX: TODO */
4735
    GEN_EXCP_INVAL(ctx);
4736
}
4737

    
4738
/* mfrom */
4739
GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4740
{
4741
#if defined(CONFIG_USER_ONLY)
4742
    GEN_EXCP_PRIVOPC(ctx);
4743
#else
4744
    if (unlikely(!ctx->supervisor)) {
4745
        GEN_EXCP_PRIVOPC(ctx);
4746
        return;
4747
    }
4748
    gen_op_load_gpr_T0(rA(ctx->opcode));
4749
    gen_op_602_mfrom();
4750
    gen_op_store_T0_gpr(rD(ctx->opcode));
4751
#endif
4752
}
4753

    
4754
/* 602 - 603 - G2 TLB management */
4755
/* tlbld */
4756
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4757
{
4758
#if defined(CONFIG_USER_ONLY)
4759
    GEN_EXCP_PRIVOPC(ctx);
4760
#else
4761
    if (unlikely(!ctx->supervisor)) {
4762
        GEN_EXCP_PRIVOPC(ctx);
4763
        return;
4764
    }
4765
    gen_op_load_gpr_T0(rB(ctx->opcode));
4766
    gen_op_6xx_tlbld();
4767
#endif
4768
}
4769

    
4770
/* tlbli */
4771
GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4772
{
4773
#if defined(CONFIG_USER_ONLY)
4774
    GEN_EXCP_PRIVOPC(ctx);
4775
#else
4776
    if (unlikely(!ctx->supervisor)) {
4777
        GEN_EXCP_PRIVOPC(ctx);
4778
        return;
4779
    }
4780
    gen_op_load_gpr_T0(rB(ctx->opcode));
4781
    gen_op_6xx_tlbli();
4782
#endif
4783
}
4784

    
4785
/* 74xx TLB management */
4786
/* tlbld */
4787
GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4788
{
4789
#if defined(CONFIG_USER_ONLY)
4790
    GEN_EXCP_PRIVOPC(ctx);
4791
#else
4792
    if (unlikely(!ctx->supervisor)) {
4793
        GEN_EXCP_PRIVOPC(ctx);
4794
        return;
4795
    }
4796
    gen_op_load_gpr_T0(rB(ctx->opcode));
4797
    gen_op_74xx_tlbld();
4798
#endif
4799
}
4800

    
4801
/* tlbli */
4802
GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4803
{
4804
#if defined(CONFIG_USER_ONLY)
4805
    GEN_EXCP_PRIVOPC(ctx);
4806
#else
4807
    if (unlikely(!ctx->supervisor)) {
4808
        GEN_EXCP_PRIVOPC(ctx);
4809
        return;
4810
    }
4811
    gen_op_load_gpr_T0(rB(ctx->opcode));
4812
    gen_op_74xx_tlbli();
4813
#endif
4814
}
4815

    
4816
/* POWER instructions not in PowerPC 601 */
4817
/* clf */
4818
GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4819
{
4820
    /* Cache line flush: implemented as no-op */
4821
}
4822

    
4823
/* cli */
4824
GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4825
{
4826
    /* Cache line invalidate: privileged and treated as no-op */
4827
#if defined(CONFIG_USER_ONLY)
4828
    GEN_EXCP_PRIVOPC(ctx);
4829
#else
4830
    if (unlikely(!ctx->supervisor)) {
4831
        GEN_EXCP_PRIVOPC(ctx);
4832
        return;
4833
    }
4834
#endif
4835
}
4836

    
4837
/* dclst */
4838
GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4839
{
4840
    /* Data cache line store: treated as no-op */
4841
}
4842

    
4843
GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4844
{
4845
#if defined(CONFIG_USER_ONLY)
4846
    GEN_EXCP_PRIVOPC(ctx);
4847
#else
4848
    if (unlikely(!ctx->supervisor)) {
4849
        GEN_EXCP_PRIVOPC(ctx);
4850
        return;
4851
    }
4852
    int ra = rA(ctx->opcode);
4853
    int rd = rD(ctx->opcode);
4854

    
4855
    gen_addr_reg_index(ctx);
4856
    gen_op_POWER_mfsri();
4857
    gen_op_store_T0_gpr(rd);
4858
    if (ra != 0 && ra != rd)
4859
        gen_op_store_T1_gpr(ra);
4860
#endif
4861
}
4862

    
4863
GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4864
{
4865
#if defined(CONFIG_USER_ONLY)
4866
    GEN_EXCP_PRIVOPC(ctx);
4867
#else
4868
    if (unlikely(!ctx->supervisor)) {
4869
        GEN_EXCP_PRIVOPC(ctx);
4870
        return;
4871
    }
4872
    gen_addr_reg_index(ctx);
4873
    gen_op_POWER_rac();
4874
    gen_op_store_T0_gpr(rD(ctx->opcode));
4875
#endif
4876
}
4877

    
4878
GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4879
{
4880
#if defined(CONFIG_USER_ONLY)
4881
    GEN_EXCP_PRIVOPC(ctx);
4882
#else
4883
    if (unlikely(!ctx->supervisor)) {
4884
        GEN_EXCP_PRIVOPC(ctx);
4885
        return;
4886
    }
4887
    gen_op_POWER_rfsvc();
4888
    GEN_SYNC(ctx);
4889
#endif
4890
}
4891

    
4892
/* svc is not implemented for now */
4893

    
4894
/* POWER2 specific instructions */
4895
/* Quad manipulation (load/store two floats at a time) */
4896
#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4897
#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4898
#if defined(CONFIG_USER_ONLY)
4899
static GenOpFunc *gen_op_POWER2_lfq[] = {
4900
    &gen_op_POWER2_lfq_le_raw,
4901
    &gen_op_POWER2_lfq_raw,
4902
};
4903
static GenOpFunc *gen_op_POWER2_stfq[] = {
4904
    &gen_op_POWER2_stfq_le_raw,
4905
    &gen_op_POWER2_stfq_raw,
4906
};
4907
#else
4908
static GenOpFunc *gen_op_POWER2_lfq[] = {
4909
    &gen_op_POWER2_lfq_le_user,
4910
    &gen_op_POWER2_lfq_user,
4911
    &gen_op_POWER2_lfq_le_kernel,
4912
    &gen_op_POWER2_lfq_kernel,
4913
};
4914
static GenOpFunc *gen_op_POWER2_stfq[] = {
4915
    &gen_op_POWER2_stfq_le_user,
4916
    &gen_op_POWER2_stfq_user,
4917
    &gen_op_POWER2_stfq_le_kernel,
4918
    &gen_op_POWER2_stfq_kernel,
4919
};
4920
#endif
4921

    
4922
/* lfq */
4923
GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4924
{
4925
    /* NIP cannot be restored if the memory exception comes from an helper */
4926
    gen_update_nip(ctx, ctx->nip - 4);
4927
    gen_addr_imm_index(ctx, 0);