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1
/*
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 * QEMU USB OHCI Emulation
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 * Copyright (c) 2004 Gianni Tedesco
4
 * Copyright (c) 2006 CodeSourcery
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 * Copyright (c) 2006 Openedhand Ltd.
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 *
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 * TODO:
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 *  o Isochronous transfers
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 *  o Allocate bandwidth in frames properly
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 *  o Disable timers when nothing needs to be done, or remove timer usage
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 *    all together.
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 *  o Handle unrecoverable errors properly
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 *  o BIOS work to boot from USB storage
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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#include "usb.h"
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#include "pci.h"
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#include "usb-ohci.h"
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#include "sysbus.h"
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#include "qdev-addr.h"
36

    
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//#define DEBUG_OHCI
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/* Dump packet contents.  */
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//#define DEBUG_PACKET
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//#define DEBUG_ISOCH
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/* This causes frames to occur 1000x slower */
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//#define OHCI_TIME_WARP 1
43

    
44
#ifdef DEBUG_OHCI
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
49

    
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/* Number of Downstream Ports on the root hub.  */
51

    
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#define OHCI_MAX_PORTS 15
53

    
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static int64_t usb_frame_time;
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static int64_t usb_bit_time;
56

    
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typedef struct OHCIPort {
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    USBPort port;
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    uint32_t ctrl;
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} OHCIPort;
61

    
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typedef struct {
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    USBBus bus;
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    qemu_irq irq;
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    MemoryRegion mem;
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    int num_ports;
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    const char *name;
68

    
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    QEMUTimer *eof_timer;
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    int64_t sof_time;
71

    
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    /* OHCI state */
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    /* Control partition */
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    uint32_t ctl, status;
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    uint32_t intr_status;
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    uint32_t intr;
77

    
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    /* memory pointer partition */
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    uint32_t hcca;
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    uint32_t ctrl_head, ctrl_cur;
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    uint32_t bulk_head, bulk_cur;
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    uint32_t per_cur;
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    uint32_t done;
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    int done_count;
85

    
86
    /* Frame counter partition */
87
    uint32_t fsmps:15;
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    uint32_t fit:1;
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    uint32_t fi:14;
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    uint32_t frt:1;
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    uint16_t frame_number;
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    uint16_t padding;
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    uint32_t pstart;
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    uint32_t lst;
95

    
96
    /* Root Hub partition */
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    uint32_t rhdesc_a, rhdesc_b;
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    uint32_t rhstatus;
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    OHCIPort rhport[OHCI_MAX_PORTS];
100

    
101
    /* PXA27x Non-OHCI events */
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    uint32_t hstatus;
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    uint32_t hmask;
104
    uint32_t hreset;
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    uint32_t htest;
106

    
107
    /* SM501 local memory offset */
108
    target_phys_addr_t localmem_base;
109

    
110
    /* Active packets.  */
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    uint32_t old_ctl;
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    USBPacket usb_packet;
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    uint8_t usb_buf[8192];
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    uint32_t async_td;
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    int async_complete;
116

    
117
} OHCIState;
118

    
119
/* Host Controller Communications Area */
120
struct ohci_hcca {
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    uint32_t intr[32];
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    uint16_t frame, pad;
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    uint32_t done;
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};
125

    
126
static void ohci_bus_stop(OHCIState *ohci);
127
static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev);
128

    
129
/* Bitfields for the first word of an Endpoint Desciptor.  */
130
#define OHCI_ED_FA_SHIFT  0
131
#define OHCI_ED_FA_MASK   (0x7f<<OHCI_ED_FA_SHIFT)
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#define OHCI_ED_EN_SHIFT  7
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#define OHCI_ED_EN_MASK   (0xf<<OHCI_ED_EN_SHIFT)
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#define OHCI_ED_D_SHIFT   11
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#define OHCI_ED_D_MASK    (3<<OHCI_ED_D_SHIFT)
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#define OHCI_ED_S         (1<<13)
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#define OHCI_ED_K         (1<<14)
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#define OHCI_ED_F         (1<<15)
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#define OHCI_ED_MPS_SHIFT 16
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#define OHCI_ED_MPS_MASK  (0x7ff<<OHCI_ED_MPS_SHIFT)
141

    
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/* Flags in the head field of an Endpoint Desciptor.  */
143
#define OHCI_ED_H         1
144
#define OHCI_ED_C         2
145

    
146
/* Bitfields for the first word of a Transfer Desciptor.  */
147
#define OHCI_TD_R         (1<<18)
148
#define OHCI_TD_DP_SHIFT  19
149
#define OHCI_TD_DP_MASK   (3<<OHCI_TD_DP_SHIFT)
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#define OHCI_TD_DI_SHIFT  21
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#define OHCI_TD_DI_MASK   (7<<OHCI_TD_DI_SHIFT)
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#define OHCI_TD_T0        (1<<24)
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#define OHCI_TD_T1        (1<<25)
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#define OHCI_TD_EC_SHIFT  26
155
#define OHCI_TD_EC_MASK   (3<<OHCI_TD_EC_SHIFT)
156
#define OHCI_TD_CC_SHIFT  28
157
#define OHCI_TD_CC_MASK   (0xf<<OHCI_TD_CC_SHIFT)
158

    
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/* Bitfields for the first word of an Isochronous Transfer Desciptor.  */
160
/* CC & DI - same as in the General Transfer Desciptor */
161
#define OHCI_TD_SF_SHIFT  0
162
#define OHCI_TD_SF_MASK   (0xffff<<OHCI_TD_SF_SHIFT)
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#define OHCI_TD_FC_SHIFT  24
164
#define OHCI_TD_FC_MASK   (7<<OHCI_TD_FC_SHIFT)
165

    
166
/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
167
#define OHCI_TD_PSW_CC_SHIFT 12
168
#define OHCI_TD_PSW_CC_MASK  (0xf<<OHCI_TD_PSW_CC_SHIFT)
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#define OHCI_TD_PSW_SIZE_SHIFT 0
170
#define OHCI_TD_PSW_SIZE_MASK  (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
171

    
172
#define OHCI_PAGE_MASK    0xfffff000
173
#define OHCI_OFFSET_MASK  0xfff
174

    
175
#define OHCI_DPTR_MASK    0xfffffff0
176

    
177
#define OHCI_BM(val, field) \
178
  (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
179

    
180
#define OHCI_SET_BM(val, field, newval) do { \
181
    val &= ~OHCI_##field##_MASK; \
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    val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
183
    } while(0)
184

    
185
/* endpoint descriptor */
186
struct ohci_ed {
187
    uint32_t flags;
188
    uint32_t tail;
189
    uint32_t head;
190
    uint32_t next;
191
};
192

    
193
/* General transfer descriptor */
194
struct ohci_td {
195
    uint32_t flags;
196
    uint32_t cbp;
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    uint32_t next;
198
    uint32_t be;
199
};
200

    
201
/* Isochronous transfer descriptor */
202
struct ohci_iso_td {
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    uint32_t flags;
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    uint32_t bp;
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    uint32_t next;
206
    uint32_t be;
207
    uint16_t offset[8];
208
};
209

    
210
#define USB_HZ                      12000000
211

    
212
/* OHCI Local stuff */
213
#define OHCI_CTL_CBSR         ((1<<0)|(1<<1))
214
#define OHCI_CTL_PLE          (1<<2)
215
#define OHCI_CTL_IE           (1<<3)
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#define OHCI_CTL_CLE          (1<<4)
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#define OHCI_CTL_BLE          (1<<5)
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#define OHCI_CTL_HCFS         ((1<<6)|(1<<7))
219
#define  OHCI_USB_RESET       0x00
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#define  OHCI_USB_RESUME      0x40
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#define  OHCI_USB_OPERATIONAL 0x80
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#define  OHCI_USB_SUSPEND     0xc0
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#define OHCI_CTL_IR           (1<<8)
224
#define OHCI_CTL_RWC          (1<<9)
225
#define OHCI_CTL_RWE          (1<<10)
226

    
227
#define OHCI_STATUS_HCR       (1<<0)
228
#define OHCI_STATUS_CLF       (1<<1)
229
#define OHCI_STATUS_BLF       (1<<2)
230
#define OHCI_STATUS_OCR       (1<<3)
231
#define OHCI_STATUS_SOC       ((1<<6)|(1<<7))
232

    
233
#define OHCI_INTR_SO          (1<<0) /* Scheduling overrun */
234
#define OHCI_INTR_WD          (1<<1) /* HcDoneHead writeback */
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#define OHCI_INTR_SF          (1<<2) /* Start of frame */
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#define OHCI_INTR_RD          (1<<3) /* Resume detect */
237
#define OHCI_INTR_UE          (1<<4) /* Unrecoverable error */
238
#define OHCI_INTR_FNO         (1<<5) /* Frame number overflow */
239
#define OHCI_INTR_RHSC        (1<<6) /* Root hub status change */
240
#define OHCI_INTR_OC          (1<<30) /* Ownership change */
241
#define OHCI_INTR_MIE         (1<<31) /* Master Interrupt Enable */
242

    
243
#define OHCI_HCCA_SIZE        0x100
244
#define OHCI_HCCA_MASK        0xffffff00
245

    
246
#define OHCI_EDPTR_MASK       0xfffffff0
247

    
248
#define OHCI_FMI_FI           0x00003fff
249
#define OHCI_FMI_FSMPS        0xffff0000
250
#define OHCI_FMI_FIT          0x80000000
251

    
252
#define OHCI_FR_RT            (1<<31)
253

    
254
#define OHCI_LS_THRESH        0x628
255

    
256
#define OHCI_RHA_RW_MASK      0x00000000 /* Mask of supported features.  */
257
#define OHCI_RHA_PSM          (1<<8)
258
#define OHCI_RHA_NPS          (1<<9)
259
#define OHCI_RHA_DT           (1<<10)
260
#define OHCI_RHA_OCPM         (1<<11)
261
#define OHCI_RHA_NOCP         (1<<12)
262
#define OHCI_RHA_POTPGT_MASK  0xff000000
263

    
264
#define OHCI_RHS_LPS          (1<<0)
265
#define OHCI_RHS_OCI          (1<<1)
266
#define OHCI_RHS_DRWE         (1<<15)
267
#define OHCI_RHS_LPSC         (1<<16)
268
#define OHCI_RHS_OCIC         (1<<17)
269
#define OHCI_RHS_CRWE         (1<<31)
270

    
271
#define OHCI_PORT_CCS         (1<<0)
272
#define OHCI_PORT_PES         (1<<1)
273
#define OHCI_PORT_PSS         (1<<2)
274
#define OHCI_PORT_POCI        (1<<3)
275
#define OHCI_PORT_PRS         (1<<4)
276
#define OHCI_PORT_PPS         (1<<8)
277
#define OHCI_PORT_LSDA        (1<<9)
278
#define OHCI_PORT_CSC         (1<<16)
279
#define OHCI_PORT_PESC        (1<<17)
280
#define OHCI_PORT_PSSC        (1<<18)
281
#define OHCI_PORT_OCIC        (1<<19)
282
#define OHCI_PORT_PRSC        (1<<20)
283
#define OHCI_PORT_WTC         (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
284
                               |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
285

    
286
#define OHCI_TD_DIR_SETUP     0x0
287
#define OHCI_TD_DIR_OUT       0x1
288
#define OHCI_TD_DIR_IN        0x2
289
#define OHCI_TD_DIR_RESERVED  0x3
290

    
291
#define OHCI_CC_NOERROR             0x0
292
#define OHCI_CC_CRC                 0x1
293
#define OHCI_CC_BITSTUFFING         0x2
294
#define OHCI_CC_DATATOGGLEMISMATCH  0x3
295
#define OHCI_CC_STALL               0x4
296
#define OHCI_CC_DEVICENOTRESPONDING 0x5
297
#define OHCI_CC_PIDCHECKFAILURE     0x6
298
#define OHCI_CC_UNDEXPETEDPID       0x7
299
#define OHCI_CC_DATAOVERRUN         0x8
300
#define OHCI_CC_DATAUNDERRUN        0x9
301
#define OHCI_CC_BUFFEROVERRUN       0xc
302
#define OHCI_CC_BUFFERUNDERRUN      0xd
303

    
304
#define OHCI_HRESET_FSBIR       (1 << 0)
305

    
306
/* Update IRQ levels */
307
static inline void ohci_intr_update(OHCIState *ohci)
308
{
309
    int level = 0;
310

    
311
    if ((ohci->intr & OHCI_INTR_MIE) &&
312
        (ohci->intr_status & ohci->intr))
313
        level = 1;
314

    
315
    qemu_set_irq(ohci->irq, level);
316
}
317

    
318
/* Set an interrupt */
319
static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
320
{
321
    ohci->intr_status |= intr;
322
    ohci_intr_update(ohci);
323
}
324

    
325
/* Attach or detach a device on a root hub port.  */
326
static void ohci_attach(USBPort *port1)
327
{
328
    OHCIState *s = port1->opaque;
329
    OHCIPort *port = &s->rhport[port1->index];
330
    uint32_t old_state = port->ctrl;
331

    
332
    /* set connect status */
333
    port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
334

    
335
    /* update speed */
336
    if (port->port.dev->speed == USB_SPEED_LOW) {
337
        port->ctrl |= OHCI_PORT_LSDA;
338
    } else {
339
        port->ctrl &= ~OHCI_PORT_LSDA;
340
    }
341

    
342
    /* notify of remote-wakeup */
343
    if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
344
        ohci_set_interrupt(s, OHCI_INTR_RD);
345
    }
346

    
347
    DPRINTF("usb-ohci: Attached port %d\n", port1->index);
348

    
349
    if (old_state != port->ctrl) {
350
        ohci_set_interrupt(s, OHCI_INTR_RHSC);
351
    }
352
}
353

    
354
static void ohci_detach(USBPort *port1)
355
{
356
    OHCIState *s = port1->opaque;
357
    OHCIPort *port = &s->rhport[port1->index];
358
    uint32_t old_state = port->ctrl;
359

    
360
    ohci_async_cancel_device(s, port1->dev);
361

    
362
    /* set connect status */
363
    if (port->ctrl & OHCI_PORT_CCS) {
364
        port->ctrl &= ~OHCI_PORT_CCS;
365
        port->ctrl |= OHCI_PORT_CSC;
366
    }
367
    /* disable port */
368
    if (port->ctrl & OHCI_PORT_PES) {
369
        port->ctrl &= ~OHCI_PORT_PES;
370
        port->ctrl |= OHCI_PORT_PESC;
371
    }
372
    DPRINTF("usb-ohci: Detached port %d\n", port1->index);
373

    
374
    if (old_state != port->ctrl) {
375
        ohci_set_interrupt(s, OHCI_INTR_RHSC);
376
    }
377
}
378

    
379
static void ohci_wakeup(USBPort *port1)
380
{
381
    OHCIState *s = port1->opaque;
382
    OHCIPort *port = &s->rhport[port1->index];
383
    uint32_t intr = 0;
384
    if (port->ctrl & OHCI_PORT_PSS) {
385
        DPRINTF("usb-ohci: port %d: wakeup\n", port1->index);
386
        port->ctrl |= OHCI_PORT_PSSC;
387
        port->ctrl &= ~OHCI_PORT_PSS;
388
        intr = OHCI_INTR_RHSC;
389
    }
390
    /* Note that the controller can be suspended even if this port is not */
391
    if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
392
        DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n");
393
        /* This is the one state transition the controller can do by itself */
394
        s->ctl &= ~OHCI_CTL_HCFS;
395
        s->ctl |= OHCI_USB_RESUME;
396
        /* In suspend mode only ResumeDetected is possible, not RHSC:
397
         * see the OHCI spec 5.1.2.3.
398
         */
399
        intr = OHCI_INTR_RD;
400
    }
401
    ohci_set_interrupt(s, intr);
402
}
403

    
404
static void ohci_child_detach(USBPort *port1, USBDevice *child)
405
{
406
    OHCIState *s = port1->opaque;
407

    
408
    ohci_async_cancel_device(s, child);
409
}
410

    
411
static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr)
412
{
413
    USBDevice *dev;
414
    int i;
415

    
416
    for (i = 0; i < ohci->num_ports; i++) {
417
        if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) {
418
            continue;
419
        }
420
        dev = usb_find_device(&ohci->rhport[i].port, addr);
421
        if (dev != NULL) {
422
            return dev;
423
        }
424
    }
425
    return NULL;
426
}
427

    
428
/* Reset the controller */
429
static void ohci_reset(void *opaque)
430
{
431
    OHCIState *ohci = opaque;
432
    OHCIPort *port;
433
    int i;
434

    
435
    ohci_bus_stop(ohci);
436
    ohci->ctl = 0;
437
    ohci->old_ctl = 0;
438
    ohci->status = 0;
439
    ohci->intr_status = 0;
440
    ohci->intr = OHCI_INTR_MIE;
441

    
442
    ohci->hcca = 0;
443
    ohci->ctrl_head = ohci->ctrl_cur = 0;
444
    ohci->bulk_head = ohci->bulk_cur = 0;
445
    ohci->per_cur = 0;
446
    ohci->done = 0;
447
    ohci->done_count = 7;
448

    
449
    /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
450
     * I took the value linux sets ...
451
     */
452
    ohci->fsmps = 0x2778;
453
    ohci->fi = 0x2edf;
454
    ohci->fit = 0;
455
    ohci->frt = 0;
456
    ohci->frame_number = 0;
457
    ohci->pstart = 0;
458
    ohci->lst = OHCI_LS_THRESH;
459

    
460
    ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
461
    ohci->rhdesc_b = 0x0; /* Impl. specific */
462
    ohci->rhstatus = 0;
463

    
464
    for (i = 0; i < ohci->num_ports; i++)
465
      {
466
        port = &ohci->rhport[i];
467
        port->ctrl = 0;
468
        if (port->port.dev && port->port.dev->attached) {
469
            usb_port_reset(&port->port);
470
        }
471
      }
472
    if (ohci->async_td) {
473
        usb_cancel_packet(&ohci->usb_packet);
474
        ohci->async_td = 0;
475
    }
476
    DPRINTF("usb-ohci: Reset %s\n", ohci->name);
477
}
478

    
479
/* Get an array of dwords from main memory */
480
static inline int get_dwords(OHCIState *ohci,
481
                             uint32_t addr, uint32_t *buf, int num)
482
{
483
    int i;
484

    
485
    addr += ohci->localmem_base;
486

    
487
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
488
        cpu_physical_memory_read(addr, buf, sizeof(*buf));
489
        *buf = le32_to_cpu(*buf);
490
    }
491

    
492
    return 1;
493
}
494

    
495
/* Put an array of dwords in to main memory */
496
static inline int put_dwords(OHCIState *ohci,
497
                             uint32_t addr, uint32_t *buf, int num)
498
{
499
    int i;
500

    
501
    addr += ohci->localmem_base;
502

    
503
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
504
        uint32_t tmp = cpu_to_le32(*buf);
505
        cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
506
    }
507

    
508
    return 1;
509
}
510

    
511
/* Get an array of words from main memory */
512
static inline int get_words(OHCIState *ohci,
513
                            uint32_t addr, uint16_t *buf, int num)
514
{
515
    int i;
516

    
517
    addr += ohci->localmem_base;
518

    
519
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
520
        cpu_physical_memory_read(addr, buf, sizeof(*buf));
521
        *buf = le16_to_cpu(*buf);
522
    }
523

    
524
    return 1;
525
}
526

    
527
/* Put an array of words in to main memory */
528
static inline int put_words(OHCIState *ohci,
529
                            uint32_t addr, uint16_t *buf, int num)
530
{
531
    int i;
532

    
533
    addr += ohci->localmem_base;
534

    
535
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
536
        uint16_t tmp = cpu_to_le16(*buf);
537
        cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
538
    }
539

    
540
    return 1;
541
}
542

    
543
static inline int ohci_read_ed(OHCIState *ohci,
544
                               uint32_t addr, struct ohci_ed *ed)
545
{
546
    return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
547
}
548

    
549
static inline int ohci_read_td(OHCIState *ohci,
550
                               uint32_t addr, struct ohci_td *td)
551
{
552
    return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
553
}
554

    
555
static inline int ohci_read_iso_td(OHCIState *ohci,
556
                                   uint32_t addr, struct ohci_iso_td *td)
557
{
558
    return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
559
            get_words(ohci, addr + 16, td->offset, 8));
560
}
561

    
562
static inline int ohci_read_hcca(OHCIState *ohci,
563
                                 uint32_t addr, struct ohci_hcca *hcca)
564
{
565
    cpu_physical_memory_read(addr + ohci->localmem_base, hcca, sizeof(*hcca));
566
    return 1;
567
}
568

    
569
static inline int ohci_put_ed(OHCIState *ohci,
570
                              uint32_t addr, struct ohci_ed *ed)
571
{
572
    return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
573
}
574

    
575
static inline int ohci_put_td(OHCIState *ohci,
576
                              uint32_t addr, struct ohci_td *td)
577
{
578
    return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
579
}
580

    
581
static inline int ohci_put_iso_td(OHCIState *ohci,
582
                                  uint32_t addr, struct ohci_iso_td *td)
583
{
584
    return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
585
            put_words(ohci, addr + 16, td->offset, 8));
586
}
587

    
588
static inline int ohci_put_hcca(OHCIState *ohci,
589
                                uint32_t addr, struct ohci_hcca *hcca)
590
{
591
    cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca));
592
    return 1;
593
}
594

    
595
/* Read/Write the contents of a TD from/to main memory.  */
596
static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
597
                         uint8_t *buf, int len, int write)
598
{
599
    uint32_t ptr;
600
    uint32_t n;
601

    
602
    ptr = td->cbp;
603
    n = 0x1000 - (ptr & 0xfff);
604
    if (n > len)
605
        n = len;
606
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
607
    if (n == len)
608
        return;
609
    ptr = td->be & ~0xfffu;
610
    buf += n;
611
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
612
}
613

    
614
/* Read/Write the contents of an ISO TD from/to main memory.  */
615
static void ohci_copy_iso_td(OHCIState *ohci,
616
                             uint32_t start_addr, uint32_t end_addr,
617
                             uint8_t *buf, int len, int write)
618
{
619
    uint32_t ptr;
620
    uint32_t n;
621

    
622
    ptr = start_addr;
623
    n = 0x1000 - (ptr & 0xfff);
624
    if (n > len)
625
        n = len;
626
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
627
    if (n == len)
628
        return;
629
    ptr = end_addr & ~0xfffu;
630
    buf += n;
631
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
632
}
633

    
634
static void ohci_process_lists(OHCIState *ohci, int completion);
635

    
636
static void ohci_async_complete_packet(USBPort *port, USBPacket *packet)
637
{
638
    OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
639
#ifdef DEBUG_PACKET
640
    DPRINTF("Async packet complete\n");
641
#endif
642
    ohci->async_complete = 1;
643
    ohci_process_lists(ohci, 1);
644
}
645

    
646
#define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
647

    
648
static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
649
                               int completion)
650
{
651
    int dir;
652
    size_t len = 0;
653
#ifdef DEBUG_ISOCH
654
    const char *str = NULL;
655
#endif
656
    int pid;
657
    int ret;
658
    int i;
659
    USBDevice *dev;
660
    USBEndpoint *ep;
661
    struct ohci_iso_td iso_td;
662
    uint32_t addr;
663
    uint16_t starting_frame;
664
    int16_t relative_frame_number;
665
    int frame_count;
666
    uint32_t start_offset, next_offset, end_offset = 0;
667
    uint32_t start_addr, end_addr;
668

    
669
    addr = ed->head & OHCI_DPTR_MASK;
670

    
671
    if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
672
        printf("usb-ohci: ISO_TD read error at %x\n", addr);
673
        return 0;
674
    }
675

    
676
    starting_frame = OHCI_BM(iso_td.flags, TD_SF);
677
    frame_count = OHCI_BM(iso_td.flags, TD_FC);
678
    relative_frame_number = USUB(ohci->frame_number, starting_frame); 
679

    
680
#ifdef DEBUG_ISOCH
681
    printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
682
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
683
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
684
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
685
           "frame_number 0x%.8x starting_frame 0x%.8x\n"
686
           "frame_count  0x%.8x relative %d\n"
687
           "di 0x%.8x cc 0x%.8x\n",
688
           ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
689
           iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
690
           iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
691
           iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
692
           ohci->frame_number, starting_frame, 
693
           frame_count, relative_frame_number,         
694
           OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
695
#endif
696

    
697
    if (relative_frame_number < 0) {
698
        DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
699
        return 1;
700
    } else if (relative_frame_number > frame_count) {
701
        /* ISO TD expired - retire the TD to the Done Queue and continue with
702
           the next ISO TD of the same ED */
703
        DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number, 
704
               frame_count);
705
        OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
706
        ed->head &= ~OHCI_DPTR_MASK;
707
        ed->head |= (iso_td.next & OHCI_DPTR_MASK);
708
        iso_td.next = ohci->done;
709
        ohci->done = addr;
710
        i = OHCI_BM(iso_td.flags, TD_DI);
711
        if (i < ohci->done_count)
712
            ohci->done_count = i;
713
        ohci_put_iso_td(ohci, addr, &iso_td);
714
        return 0;
715
    }
716

    
717
    dir = OHCI_BM(ed->flags, ED_D);
718
    switch (dir) {
719
    case OHCI_TD_DIR_IN:
720
#ifdef DEBUG_ISOCH
721
        str = "in";
722
#endif
723
        pid = USB_TOKEN_IN;
724
        break;
725
    case OHCI_TD_DIR_OUT:
726
#ifdef DEBUG_ISOCH
727
        str = "out";
728
#endif
729
        pid = USB_TOKEN_OUT;
730
        break;
731
    case OHCI_TD_DIR_SETUP:
732
#ifdef DEBUG_ISOCH
733
        str = "setup";
734
#endif
735
        pid = USB_TOKEN_SETUP;
736
        break;
737
    default:
738
        printf("usb-ohci: Bad direction %d\n", dir);
739
        return 1;
740
    }
741

    
742
    if (!iso_td.bp || !iso_td.be) {
743
        printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
744
        return 1;
745
    }
746

    
747
    start_offset = iso_td.offset[relative_frame_number];
748
    next_offset = iso_td.offset[relative_frame_number + 1];
749

    
750
    if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || 
751
        ((relative_frame_number < frame_count) && 
752
         !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
753
        printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
754
               start_offset, next_offset);
755
        return 1;
756
    }
757

    
758
    if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
759
        printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
760
                start_offset, next_offset);
761
        return 1;
762
    }
763

    
764
    if ((start_offset & 0x1000) == 0) {
765
        start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
766
            (start_offset & OHCI_OFFSET_MASK);
767
    } else {
768
        start_addr = (iso_td.be & OHCI_PAGE_MASK) |
769
            (start_offset & OHCI_OFFSET_MASK);
770
    }
771

    
772
    if (relative_frame_number < frame_count) {
773
        end_offset = next_offset - 1;
774
        if ((end_offset & 0x1000) == 0) {
775
            end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
776
                (end_offset & OHCI_OFFSET_MASK);
777
        } else {
778
            end_addr = (iso_td.be & OHCI_PAGE_MASK) |
779
                (end_offset & OHCI_OFFSET_MASK);
780
        }
781
    } else {
782
        /* Last packet in the ISO TD */
783
        end_addr = iso_td.be;
784
    }
785

    
786
    if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
787
        len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
788
            - (start_addr & OHCI_OFFSET_MASK);
789
    } else {
790
        len = end_addr - start_addr + 1;
791
    }
792

    
793
    if (len && dir != OHCI_TD_DIR_IN) {
794
        ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
795
    }
796

    
797
    if (completion) {
798
        ret = ohci->usb_packet.result;
799
    } else {
800
        dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA));
801
        ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
802
        usb_packet_setup(&ohci->usb_packet, pid, ep);
803
        usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len);
804
        ret = usb_handle_packet(dev, &ohci->usb_packet);
805
        if (ret == USB_RET_ASYNC) {
806
            return 1;
807
        }
808
    }
809

    
810
#ifdef DEBUG_ISOCH
811
    printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
812
           start_offset, end_offset, start_addr, end_addr, str, len, ret);
813
#endif
814

    
815
    /* Writeback */
816
    if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
817
        /* IN transfer succeeded */
818
        ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
819
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
820
                    OHCI_CC_NOERROR);
821
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
822
    } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
823
        /* OUT transfer succeeded */
824
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
825
                    OHCI_CC_NOERROR);
826
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
827
    } else {
828
        if (ret > (ssize_t) len) {
829
            printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
830
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
831
                        OHCI_CC_DATAOVERRUN);
832
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
833
                        len);
834
        } else if (ret >= 0) {
835
            printf("usb-ohci: DataUnderrun %d\n", ret);
836
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
837
                        OHCI_CC_DATAUNDERRUN);
838
        } else {
839
            switch (ret) {
840
            case USB_RET_NODEV:
841
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
842
                            OHCI_CC_DEVICENOTRESPONDING);
843
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
844
                            0);
845
                break;
846
            case USB_RET_NAK:
847
            case USB_RET_STALL:
848
                printf("usb-ohci: got NAK/STALL %d\n", ret);
849
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
850
                            OHCI_CC_STALL);
851
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
852
                            0);
853
                break;
854
            default:
855
                printf("usb-ohci: Bad device response %d\n", ret);
856
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
857
                            OHCI_CC_UNDEXPETEDPID);
858
                break;
859
            }
860
        }
861
    }
862

    
863
    if (relative_frame_number == frame_count) {
864
        /* Last data packet of ISO TD - retire the TD to the Done Queue */
865
        OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
866
        ed->head &= ~OHCI_DPTR_MASK;
867
        ed->head |= (iso_td.next & OHCI_DPTR_MASK);
868
        iso_td.next = ohci->done;
869
        ohci->done = addr;
870
        i = OHCI_BM(iso_td.flags, TD_DI);
871
        if (i < ohci->done_count)
872
            ohci->done_count = i;
873
    }
874
    ohci_put_iso_td(ohci, addr, &iso_td);
875
    return 1;
876
}
877

    
878
/* Service a transport descriptor.
879
   Returns nonzero to terminate processing of this endpoint.  */
880

    
881
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
882
{
883
    int dir;
884
    size_t len = 0, pktlen = 0;
885
#ifdef DEBUG_PACKET
886
    const char *str = NULL;
887
#endif
888
    int pid;
889
    int ret;
890
    int i;
891
    USBDevice *dev;
892
    USBEndpoint *ep;
893
    struct ohci_td td;
894
    uint32_t addr;
895
    int flag_r;
896
    int completion;
897

    
898
    addr = ed->head & OHCI_DPTR_MASK;
899
    /* See if this TD has already been submitted to the device.  */
900
    completion = (addr == ohci->async_td);
901
    if (completion && !ohci->async_complete) {
902
#ifdef DEBUG_PACKET
903
        DPRINTF("Skipping async TD\n");
904
#endif
905
        return 1;
906
    }
907
    if (!ohci_read_td(ohci, addr, &td)) {
908
        fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
909
        return 0;
910
    }
911

    
912
    dir = OHCI_BM(ed->flags, ED_D);
913
    switch (dir) {
914
    case OHCI_TD_DIR_OUT:
915
    case OHCI_TD_DIR_IN:
916
        /* Same value.  */
917
        break;
918
    default:
919
        dir = OHCI_BM(td.flags, TD_DP);
920
        break;
921
    }
922

    
923
    switch (dir) {
924
    case OHCI_TD_DIR_IN:
925
#ifdef DEBUG_PACKET
926
        str = "in";
927
#endif
928
        pid = USB_TOKEN_IN;
929
        break;
930
    case OHCI_TD_DIR_OUT:
931
#ifdef DEBUG_PACKET
932
        str = "out";
933
#endif
934
        pid = USB_TOKEN_OUT;
935
        break;
936
    case OHCI_TD_DIR_SETUP:
937
#ifdef DEBUG_PACKET
938
        str = "setup";
939
#endif
940
        pid = USB_TOKEN_SETUP;
941
        break;
942
    default:
943
        fprintf(stderr, "usb-ohci: Bad direction\n");
944
        return 1;
945
    }
946
    if (td.cbp && td.be) {
947
        if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
948
            len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
949
        } else {
950
            len = (td.be - td.cbp) + 1;
951
        }
952

    
953
        pktlen = len;
954
        if (len && dir != OHCI_TD_DIR_IN) {
955
            /* The endpoint may not allow us to transfer it all now */
956
            pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT;
957
            if (pktlen > len) {
958
                pktlen = len;
959
            }
960
            if (!completion) {
961
                ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, 0);
962
            }
963
        }
964
    }
965

    
966
    flag_r = (td.flags & OHCI_TD_R) != 0;
967
#ifdef DEBUG_PACKET
968
    DPRINTF(" TD @ 0x%.8x %" PRId64 " of %" PRId64
969
            " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
970
            addr, (int64_t)pktlen, (int64_t)len, str, flag_r, td.cbp, td.be);
971

    
972
    if (pktlen > 0 && dir != OHCI_TD_DIR_IN) {
973
        DPRINTF("  data:");
974
        for (i = 0; i < pktlen; i++) {
975
            printf(" %.2x", ohci->usb_buf[i]);
976
        }
977
        DPRINTF("\n");
978
    }
979
#endif
980
    if (completion) {
981
        ret = ohci->usb_packet.result;
982
        ohci->async_td = 0;
983
        ohci->async_complete = 0;
984
    } else {
985
        if (ohci->async_td) {
986
            /* ??? The hardware should allow one active packet per
987
               endpoint.  We only allow one active packet per controller.
988
               This should be sufficient as long as devices respond in a
989
               timely manner.
990
            */
991
#ifdef DEBUG_PACKET
992
            DPRINTF("Too many pending packets\n");
993
#endif
994
            return 1;
995
        }
996
        dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA));
997
        ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
998
        usb_packet_setup(&ohci->usb_packet, pid, ep);
999
        usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen);
1000
        ret = usb_handle_packet(dev, &ohci->usb_packet);
1001
#ifdef DEBUG_PACKET
1002
        DPRINTF("ret=%d\n", ret);
1003
#endif
1004
        if (ret == USB_RET_ASYNC) {
1005
            ohci->async_td = addr;
1006
            return 1;
1007
        }
1008
    }
1009
    if (ret >= 0) {
1010
        if (dir == OHCI_TD_DIR_IN) {
1011
            ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
1012
#ifdef DEBUG_PACKET
1013
            DPRINTF("  data:");
1014
            for (i = 0; i < ret; i++)
1015
                printf(" %.2x", ohci->usb_buf[i]);
1016
            DPRINTF("\n");
1017
#endif
1018
        } else {
1019
            ret = pktlen;
1020
        }
1021
    }
1022

    
1023
    /* Writeback */
1024
    if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
1025
        /* Transmission succeeded.  */
1026
        if (ret == len) {
1027
            td.cbp = 0;
1028
        } else {
1029
            if ((td.cbp & 0xfff) + ret > 0xfff) {
1030
                td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff);
1031
            } else {
1032
                td.cbp += ret;
1033
            }
1034
        }
1035
        td.flags |= OHCI_TD_T1;
1036
        td.flags ^= OHCI_TD_T0;
1037
        OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
1038
        OHCI_SET_BM(td.flags, TD_EC, 0);
1039

    
1040
        if ((dir != OHCI_TD_DIR_IN) && (ret != len)) {
1041
            /* Partial packet transfer: TD not ready to retire yet */
1042
            goto exit_no_retire;
1043
        }
1044

    
1045
        /* Setting ED_C is part of the TD retirement process */
1046
        ed->head &= ~OHCI_ED_C;
1047
        if (td.flags & OHCI_TD_T0)
1048
            ed->head |= OHCI_ED_C;
1049
    } else {
1050
        if (ret >= 0) {
1051
            DPRINTF("usb-ohci: Underrun\n");
1052
            OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1053
        } else {
1054
            switch (ret) {
1055
            case USB_RET_NODEV:
1056
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1057
            case USB_RET_NAK:
1058
                DPRINTF("usb-ohci: got NAK\n");
1059
                return 1;
1060
            case USB_RET_STALL:
1061
                DPRINTF("usb-ohci: got STALL\n");
1062
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1063
                break;
1064
            case USB_RET_BABBLE:
1065
                DPRINTF("usb-ohci: got BABBLE\n");
1066
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1067
                break;
1068
            default:
1069
                fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
1070
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1071
                OHCI_SET_BM(td.flags, TD_EC, 3);
1072
                break;
1073
            }
1074
        }
1075
        ed->head |= OHCI_ED_H;
1076
    }
1077

    
1078
    /* Retire this TD */
1079
    ed->head &= ~OHCI_DPTR_MASK;
1080
    ed->head |= td.next & OHCI_DPTR_MASK;
1081
    td.next = ohci->done;
1082
    ohci->done = addr;
1083
    i = OHCI_BM(td.flags, TD_DI);
1084
    if (i < ohci->done_count)
1085
        ohci->done_count = i;
1086
exit_no_retire:
1087
    ohci_put_td(ohci, addr, &td);
1088
    return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1089
}
1090

    
1091
/* Service an endpoint list.  Returns nonzero if active TD were found.  */
1092
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1093
{
1094
    struct ohci_ed ed;
1095
    uint32_t next_ed;
1096
    uint32_t cur;
1097
    int active;
1098

    
1099
    active = 0;
1100

    
1101
    if (head == 0)
1102
        return 0;
1103

    
1104
    for (cur = head; cur; cur = next_ed) {
1105
        if (!ohci_read_ed(ohci, cur, &ed)) {
1106
            fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1107
            return 0;
1108
        }
1109

    
1110
        next_ed = ed.next & OHCI_DPTR_MASK;
1111

    
1112
        if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1113
            uint32_t addr;
1114
            /* Cancel pending packets for ED that have been paused.  */
1115
            addr = ed.head & OHCI_DPTR_MASK;
1116
            if (ohci->async_td && addr == ohci->async_td) {
1117
                usb_cancel_packet(&ohci->usb_packet);
1118
                ohci->async_td = 0;
1119
            }
1120
            continue;
1121
        }
1122

    
1123
        while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1124
#ifdef DEBUG_PACKET
1125
            DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1126
                    "h=%u c=%u\n  head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1127
                    OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1128
                    OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1129
                    (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1130
                    OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1131
                    (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1132
                    ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1133
#endif
1134
            active = 1;
1135

    
1136
            if ((ed.flags & OHCI_ED_F) == 0) {
1137
                if (ohci_service_td(ohci, &ed))
1138
                    break;
1139
            } else {
1140
                /* Handle isochronous endpoints */
1141
                if (ohci_service_iso_td(ohci, &ed, completion))
1142
                    break;
1143
            }
1144
        }
1145

    
1146
        ohci_put_ed(ohci, cur, &ed);
1147
    }
1148

    
1149
    return active;
1150
}
1151

    
1152
/* Generate a SOF event, and set a timer for EOF */
1153
static void ohci_sof(OHCIState *ohci)
1154
{
1155
    ohci->sof_time = qemu_get_clock_ns(vm_clock);
1156
    qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1157
    ohci_set_interrupt(ohci, OHCI_INTR_SF);
1158
}
1159

    
1160
/* Process Control and Bulk lists.  */
1161
static void ohci_process_lists(OHCIState *ohci, int completion)
1162
{
1163
    if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1164
        if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1165
            DPRINTF("usb-ohci: head %x, cur %x\n",
1166
                    ohci->ctrl_head, ohci->ctrl_cur);
1167
        }
1168
        if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1169
            ohci->ctrl_cur = 0;
1170
            ohci->status &= ~OHCI_STATUS_CLF;
1171
        }
1172
    }
1173

    
1174
    if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1175
        if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1176
            ohci->bulk_cur = 0;
1177
            ohci->status &= ~OHCI_STATUS_BLF;
1178
        }
1179
    }
1180
}
1181

    
1182
/* Do frame processing on frame boundary */
1183
static void ohci_frame_boundary(void *opaque)
1184
{
1185
    OHCIState *ohci = opaque;
1186
    struct ohci_hcca hcca;
1187

    
1188
    ohci_read_hcca(ohci, ohci->hcca, &hcca);
1189

    
1190
    /* Process all the lists at the end of the frame */
1191
    if (ohci->ctl & OHCI_CTL_PLE) {
1192
        int n;
1193

    
1194
        n = ohci->frame_number & 0x1f;
1195
        ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1196
    }
1197

    
1198
    /* Cancel all pending packets if either of the lists has been disabled.  */
1199
    if (ohci->async_td &&
1200
        ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1201
        usb_cancel_packet(&ohci->usb_packet);
1202
        ohci->async_td = 0;
1203
    }
1204
    ohci->old_ctl = ohci->ctl;
1205
    ohci_process_lists(ohci, 0);
1206

    
1207
    /* Frame boundary, so do EOF stuf here */
1208
    ohci->frt = ohci->fit;
1209

    
1210
    /* Increment frame number and take care of endianness. */
1211
    ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1212
    hcca.frame = cpu_to_le16(ohci->frame_number);
1213

    
1214
    if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1215
        if (!ohci->done)
1216
            abort();
1217
        if (ohci->intr & ohci->intr_status)
1218
            ohci->done |= 1;
1219
        hcca.done = cpu_to_le32(ohci->done);
1220
        ohci->done = 0;
1221
        ohci->done_count = 7;
1222
        ohci_set_interrupt(ohci, OHCI_INTR_WD);
1223
    }
1224

    
1225
    if (ohci->done_count != 7 && ohci->done_count != 0)
1226
        ohci->done_count--;
1227

    
1228
    /* Do SOF stuff here */
1229
    ohci_sof(ohci);
1230

    
1231
    /* Writeback HCCA */
1232
    ohci_put_hcca(ohci, ohci->hcca, &hcca);
1233
}
1234

    
1235
/* Start sending SOF tokens across the USB bus, lists are processed in
1236
 * next frame
1237
 */
1238
static int ohci_bus_start(OHCIState *ohci)
1239
{
1240
    ohci->eof_timer = qemu_new_timer_ns(vm_clock,
1241
                    ohci_frame_boundary,
1242
                    ohci);
1243

    
1244
    if (ohci->eof_timer == NULL) {
1245
        fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
1246
        /* TODO: Signal unrecoverable error */
1247
        return 0;
1248
    }
1249

    
1250
    DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
1251

    
1252
    ohci_sof(ohci);
1253

    
1254
    return 1;
1255
}
1256

    
1257
/* Stop sending SOF tokens on the bus */
1258
static void ohci_bus_stop(OHCIState *ohci)
1259
{
1260
    if (ohci->eof_timer)
1261
        qemu_del_timer(ohci->eof_timer);
1262
    ohci->eof_timer = NULL;
1263
}
1264

    
1265
/* Sets a flag in a port status register but only set it if the port is
1266
 * connected, if not set ConnectStatusChange flag. If flag is enabled
1267
 * return 1.
1268
 */
1269
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1270
{
1271
    int ret = 1;
1272

    
1273
    /* writing a 0 has no effect */
1274
    if (val == 0)
1275
        return 0;
1276

    
1277
    /* If CurrentConnectStatus is cleared we set
1278
     * ConnectStatusChange
1279
     */
1280
    if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1281
        ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1282
        if (ohci->rhstatus & OHCI_RHS_DRWE) {
1283
            /* TODO: CSC is a wakeup event */
1284
        }
1285
        return 0;
1286
    }
1287

    
1288
    if (ohci->rhport[i].ctrl & val)
1289
        ret = 0;
1290

    
1291
    /* set the bit */
1292
    ohci->rhport[i].ctrl |= val;
1293

    
1294
    return ret;
1295
}
1296

    
1297
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1298
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1299
{
1300
    val &= OHCI_FMI_FI;
1301

    
1302
    if (val != ohci->fi) {
1303
        DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1304
            ohci->name, ohci->fi, ohci->fi);
1305
    }
1306

    
1307
    ohci->fi = val;
1308
}
1309

    
1310
static void ohci_port_power(OHCIState *ohci, int i, int p)
1311
{
1312
    if (p) {
1313
        ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1314
    } else {
1315
        ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1316
                    OHCI_PORT_CCS|
1317
                    OHCI_PORT_PSS|
1318
                    OHCI_PORT_PRS);
1319
    }
1320
}
1321

    
1322
/* Set HcControlRegister */
1323
static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1324
{
1325
    uint32_t old_state;
1326
    uint32_t new_state;
1327

    
1328
    old_state = ohci->ctl & OHCI_CTL_HCFS;
1329
    ohci->ctl = val;
1330
    new_state = ohci->ctl & OHCI_CTL_HCFS;
1331

    
1332
    /* no state change */
1333
    if (old_state == new_state)
1334
        return;
1335

    
1336
    switch (new_state) {
1337
    case OHCI_USB_OPERATIONAL:
1338
        ohci_bus_start(ohci);
1339
        break;
1340
    case OHCI_USB_SUSPEND:
1341
        ohci_bus_stop(ohci);
1342
        DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
1343
        break;
1344
    case OHCI_USB_RESUME:
1345
        DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
1346
        break;
1347
    case OHCI_USB_RESET:
1348
        ohci_reset(ohci);
1349
        DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
1350
        break;
1351
    }
1352
}
1353

    
1354
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1355
{
1356
    uint16_t fr;
1357
    int64_t tks;
1358

    
1359
    if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1360
        return (ohci->frt << 31);
1361

    
1362
    /* Being in USB operational state guarnatees sof_time was
1363
     * set already.
1364
     */
1365
    tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time;
1366

    
1367
    /* avoid muldiv if possible */
1368
    if (tks >= usb_frame_time)
1369
        return (ohci->frt << 31);
1370

    
1371
    tks = muldiv64(1, tks, usb_bit_time);
1372
    fr = (uint16_t)(ohci->fi - tks);
1373

    
1374
    return (ohci->frt << 31) | fr;
1375
}
1376

    
1377

    
1378
/* Set root hub status */
1379
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1380
{
1381
    uint32_t old_state;
1382

    
1383
    old_state = ohci->rhstatus;
1384

    
1385
    /* write 1 to clear OCIC */
1386
    if (val & OHCI_RHS_OCIC)
1387
        ohci->rhstatus &= ~OHCI_RHS_OCIC;
1388

    
1389
    if (val & OHCI_RHS_LPS) {
1390
        int i;
1391

    
1392
        for (i = 0; i < ohci->num_ports; i++)
1393
            ohci_port_power(ohci, i, 0);
1394
        DPRINTF("usb-ohci: powered down all ports\n");
1395
    }
1396

    
1397
    if (val & OHCI_RHS_LPSC) {
1398
        int i;
1399

    
1400
        for (i = 0; i < ohci->num_ports; i++)
1401
            ohci_port_power(ohci, i, 1);
1402
        DPRINTF("usb-ohci: powered up all ports\n");
1403
    }
1404

    
1405
    if (val & OHCI_RHS_DRWE)
1406
        ohci->rhstatus |= OHCI_RHS_DRWE;
1407

    
1408
    if (val & OHCI_RHS_CRWE)
1409
        ohci->rhstatus &= ~OHCI_RHS_DRWE;
1410

    
1411
    if (old_state != ohci->rhstatus)
1412
        ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1413
}
1414

    
1415
/* Set root hub port status */
1416
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1417
{
1418
    uint32_t old_state;
1419
    OHCIPort *port;
1420

    
1421
    port = &ohci->rhport[portnum];
1422
    old_state = port->ctrl;
1423

    
1424
    /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1425
    if (val & OHCI_PORT_WTC)
1426
        port->ctrl &= ~(val & OHCI_PORT_WTC);
1427

    
1428
    if (val & OHCI_PORT_CCS)
1429
        port->ctrl &= ~OHCI_PORT_PES;
1430

    
1431
    ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1432

    
1433
    if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1434
        DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
1435
    }
1436

    
1437
    if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1438
        DPRINTF("usb-ohci: port %d: RESET\n", portnum);
1439
        usb_device_reset(port->port.dev);
1440
        port->ctrl &= ~OHCI_PORT_PRS;
1441
        /* ??? Should this also set OHCI_PORT_PESC.  */
1442
        port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1443
    }
1444

    
1445
    /* Invert order here to ensure in ambiguous case, device is
1446
     * powered up...
1447
     */
1448
    if (val & OHCI_PORT_LSDA)
1449
        ohci_port_power(ohci, portnum, 0);
1450
    if (val & OHCI_PORT_PPS)
1451
        ohci_port_power(ohci, portnum, 1);
1452

    
1453
    if (old_state != port->ctrl)
1454
        ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1455

    
1456
    return;
1457
}
1458

    
1459
static uint64_t ohci_mem_read(void *opaque,
1460
                              target_phys_addr_t addr,
1461
                              unsigned size)
1462
{
1463
    OHCIState *ohci = opaque;
1464
    uint32_t retval;
1465

    
1466
    /* Only aligned reads are allowed on OHCI */
1467
    if (addr & 3) {
1468
        fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1469
        return 0xffffffff;
1470
    } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1471
        /* HcRhPortStatus */
1472
        retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1473
    } else {
1474
        switch (addr >> 2) {
1475
        case 0: /* HcRevision */
1476
            retval = 0x10;
1477
            break;
1478

    
1479
        case 1: /* HcControl */
1480
            retval = ohci->ctl;
1481
            break;
1482

    
1483
        case 2: /* HcCommandStatus */
1484
            retval = ohci->status;
1485
            break;
1486

    
1487
        case 3: /* HcInterruptStatus */
1488
            retval = ohci->intr_status;
1489
            break;
1490

    
1491
        case 4: /* HcInterruptEnable */
1492
        case 5: /* HcInterruptDisable */
1493
            retval = ohci->intr;
1494
            break;
1495

    
1496
        case 6: /* HcHCCA */
1497
            retval = ohci->hcca;
1498
            break;
1499

    
1500
        case 7: /* HcPeriodCurrentED */
1501
            retval = ohci->per_cur;
1502
            break;
1503

    
1504
        case 8: /* HcControlHeadED */
1505
            retval = ohci->ctrl_head;
1506
            break;
1507

    
1508
        case 9: /* HcControlCurrentED */
1509
            retval = ohci->ctrl_cur;
1510
            break;
1511

    
1512
        case 10: /* HcBulkHeadED */
1513
            retval = ohci->bulk_head;
1514
            break;
1515

    
1516
        case 11: /* HcBulkCurrentED */
1517
            retval = ohci->bulk_cur;
1518
            break;
1519

    
1520
        case 12: /* HcDoneHead */
1521
            retval = ohci->done;
1522
            break;
1523

    
1524
        case 13: /* HcFmInterretval */
1525
            retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1526
            break;
1527

    
1528
        case 14: /* HcFmRemaining */
1529
            retval = ohci_get_frame_remaining(ohci);
1530
            break;
1531

    
1532
        case 15: /* HcFmNumber */
1533
            retval = ohci->frame_number;
1534
            break;
1535

    
1536
        case 16: /* HcPeriodicStart */
1537
            retval = ohci->pstart;
1538
            break;
1539

    
1540
        case 17: /* HcLSThreshold */
1541
            retval = ohci->lst;
1542
            break;
1543

    
1544
        case 18: /* HcRhDescriptorA */
1545
            retval = ohci->rhdesc_a;
1546
            break;
1547

    
1548
        case 19: /* HcRhDescriptorB */
1549
            retval = ohci->rhdesc_b;
1550
            break;
1551

    
1552
        case 20: /* HcRhStatus */
1553
            retval = ohci->rhstatus;
1554
            break;
1555

    
1556
        /* PXA27x specific registers */
1557
        case 24: /* HcStatus */
1558
            retval = ohci->hstatus & ohci->hmask;
1559
            break;
1560

    
1561
        case 25: /* HcHReset */
1562
            retval = ohci->hreset;
1563
            break;
1564

    
1565
        case 26: /* HcHInterruptEnable */
1566
            retval = ohci->hmask;
1567
            break;
1568

    
1569
        case 27: /* HcHInterruptTest */
1570
            retval = ohci->htest;
1571
            break;
1572

    
1573
        default:
1574
            fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1575
            retval = 0xffffffff;
1576
        }
1577
    }
1578

    
1579
    return retval;
1580
}
1581

    
1582
static void ohci_mem_write(void *opaque,
1583
                           target_phys_addr_t addr,
1584
                           uint64_t val,
1585
                           unsigned size)
1586
{
1587
    OHCIState *ohci = opaque;
1588

    
1589
    /* Only aligned reads are allowed on OHCI */
1590
    if (addr & 3) {
1591
        fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1592
        return;
1593
    }
1594

    
1595
    if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1596
        /* HcRhPortStatus */
1597
        ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1598
        return;
1599
    }
1600

    
1601
    switch (addr >> 2) {
1602
    case 1: /* HcControl */
1603
        ohci_set_ctl(ohci, val);
1604
        break;
1605

    
1606
    case 2: /* HcCommandStatus */
1607
        /* SOC is read-only */
1608
        val = (val & ~OHCI_STATUS_SOC);
1609

    
1610
        /* Bits written as '0' remain unchanged in the register */
1611
        ohci->status |= val;
1612

    
1613
        if (ohci->status & OHCI_STATUS_HCR)
1614
            ohci_reset(ohci);
1615
        break;
1616

    
1617
    case 3: /* HcInterruptStatus */
1618
        ohci->intr_status &= ~val;
1619
        ohci_intr_update(ohci);
1620
        break;
1621

    
1622
    case 4: /* HcInterruptEnable */
1623
        ohci->intr |= val;
1624
        ohci_intr_update(ohci);
1625
        break;
1626

    
1627
    case 5: /* HcInterruptDisable */
1628
        ohci->intr &= ~val;
1629
        ohci_intr_update(ohci);
1630
        break;
1631

    
1632
    case 6: /* HcHCCA */
1633
        ohci->hcca = val & OHCI_HCCA_MASK;
1634
        break;
1635

    
1636
    case 7: /* HcPeriodCurrentED */
1637
        /* Ignore writes to this read-only register, Linux does them */
1638
        break;
1639

    
1640
    case 8: /* HcControlHeadED */
1641
        ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1642
        break;
1643

    
1644
    case 9: /* HcControlCurrentED */
1645
        ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1646
        break;
1647

    
1648
    case 10: /* HcBulkHeadED */
1649
        ohci->bulk_head = val & OHCI_EDPTR_MASK;
1650
        break;
1651

    
1652
    case 11: /* HcBulkCurrentED */
1653
        ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1654
        break;
1655

    
1656
    case 13: /* HcFmInterval */
1657
        ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1658
        ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1659
        ohci_set_frame_interval(ohci, val);
1660
        break;
1661

    
1662
    case 15: /* HcFmNumber */
1663
        break;
1664

    
1665
    case 16: /* HcPeriodicStart */
1666
        ohci->pstart = val & 0xffff;
1667
        break;
1668

    
1669
    case 17: /* HcLSThreshold */
1670
        ohci->lst = val & 0xffff;
1671
        break;
1672

    
1673
    case 18: /* HcRhDescriptorA */
1674
        ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1675
        ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1676
        break;
1677

    
1678
    case 19: /* HcRhDescriptorB */
1679
        break;
1680

    
1681
    case 20: /* HcRhStatus */
1682
        ohci_set_hub_status(ohci, val);
1683
        break;
1684

    
1685
    /* PXA27x specific registers */
1686
    case 24: /* HcStatus */
1687
        ohci->hstatus &= ~(val & ohci->hmask);
1688

    
1689
    case 25: /* HcHReset */
1690
        ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1691
        if (val & OHCI_HRESET_FSBIR)
1692
            ohci_reset(ohci);
1693
        break;
1694

    
1695
    case 26: /* HcHInterruptEnable */
1696
        ohci->hmask = val;
1697
        break;
1698

    
1699
    case 27: /* HcHInterruptTest */
1700
        ohci->htest = val;
1701
        break;
1702

    
1703
    default:
1704
        fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1705
        break;
1706
    }
1707
}
1708

    
1709
static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev)
1710
{
1711
    if (ohci->async_td &&
1712
        usb_packet_is_inflight(&ohci->usb_packet) &&
1713
        ohci->usb_packet.ep->dev == dev) {
1714
        usb_cancel_packet(&ohci->usb_packet);
1715
        ohci->async_td = 0;
1716
    }
1717
}
1718

    
1719
static const MemoryRegionOps ohci_mem_ops = {
1720
    .read = ohci_mem_read,
1721
    .write = ohci_mem_write,
1722
    .endianness = DEVICE_LITTLE_ENDIAN,
1723
};
1724

    
1725
static USBPortOps ohci_port_ops = {
1726
    .attach = ohci_attach,
1727
    .detach = ohci_detach,
1728
    .child_detach = ohci_child_detach,
1729
    .wakeup = ohci_wakeup,
1730
    .complete = ohci_async_complete_packet,
1731
};
1732

    
1733
static USBBusOps ohci_bus_ops = {
1734
};
1735

    
1736
static int usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1737
                         int num_ports, uint32_t localmem_base,
1738
                         char *masterbus, uint32_t firstport)
1739
{
1740
    int i;
1741

    
1742
    if (usb_frame_time == 0) {
1743
#ifdef OHCI_TIME_WARP
1744
        usb_frame_time = get_ticks_per_sec();
1745
        usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
1746
#else
1747
        usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
1748
        if (get_ticks_per_sec() >= USB_HZ) {
1749
            usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
1750
        } else {
1751
            usb_bit_time = 1;
1752
        }
1753
#endif
1754
        DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
1755
                usb_frame_time, usb_bit_time);
1756
    }
1757

    
1758
    ohci->num_ports = num_ports;
1759
    if (masterbus) {
1760
        USBPort *ports[OHCI_MAX_PORTS];
1761
        for(i = 0; i < num_ports; i++) {
1762
            ports[i] = &ohci->rhport[i].port;
1763
        }
1764
        if (usb_register_companion(masterbus, ports, num_ports,
1765
                firstport, ohci, &ohci_port_ops,
1766
                USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1767
            return -1;
1768
        }
1769
    } else {
1770
        usb_bus_new(&ohci->bus, &ohci_bus_ops, dev);
1771
        for (i = 0; i < num_ports; i++) {
1772
            usb_register_port(&ohci->bus, &ohci->rhport[i].port,
1773
                              ohci, i, &ohci_port_ops,
1774
                              USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1775
        }
1776
    }
1777

    
1778
    memory_region_init_io(&ohci->mem, &ohci_mem_ops, ohci, "ohci", 256);
1779
    ohci->localmem_base = localmem_base;
1780

    
1781
    ohci->name = object_get_typename(OBJECT(dev));
1782
    usb_packet_init(&ohci->usb_packet);
1783

    
1784
    ohci->async_td = 0;
1785
    qemu_register_reset(ohci_reset, ohci);
1786

    
1787
    return 0;
1788
}
1789

    
1790
typedef struct {
1791
    PCIDevice pci_dev;
1792
    OHCIState state;
1793
    char *masterbus;
1794
    uint32_t num_ports;
1795
    uint32_t firstport;
1796
} OHCIPCIState;
1797

    
1798
static int usb_ohci_initfn_pci(struct PCIDevice *dev)
1799
{
1800
    OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
1801

    
1802
    ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
1803
    ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
1804

    
1805
    if (usb_ohci_init(&ohci->state, &dev->qdev, ohci->num_ports, 0,
1806
                      ohci->masterbus, ohci->firstport) != 0) {
1807
        return -1;
1808
    }
1809
    ohci->state.irq = ohci->pci_dev.irq[0];
1810

    
1811
    /* TODO: avoid cast below by using dev */
1812
    pci_register_bar(&ohci->pci_dev, 0, 0, &ohci->state.mem);
1813
    return 0;
1814
}
1815

    
1816
void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1817
{
1818
    pci_create_simple(bus, devfn, "pci-ohci");
1819
}
1820

    
1821
typedef struct {
1822
    SysBusDevice busdev;
1823
    OHCIState ohci;
1824
    uint32_t num_ports;
1825
    target_phys_addr_t dma_offset;
1826
} OHCISysBusState;
1827

    
1828
static int ohci_init_pxa(SysBusDevice *dev)
1829
{
1830
    OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
1831

    
1832
    /* Cannot fail as we pass NULL for masterbus */
1833
    usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset, NULL, 0);
1834
    sysbus_init_irq(dev, &s->ohci.irq);
1835
    sysbus_init_mmio(dev, &s->ohci.mem);
1836

    
1837
    return 0;
1838
}
1839

    
1840
static Property ohci_pci_properties[] = {
1841
    DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
1842
    DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3),
1843
    DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0),
1844
    DEFINE_PROP_END_OF_LIST(),
1845
};
1846

    
1847
static void ohci_pci_class_init(ObjectClass *klass, void *data)
1848
{
1849
    DeviceClass *dc = DEVICE_CLASS(klass);
1850
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1851

    
1852
    k->init = usb_ohci_initfn_pci;
1853
    k->vendor_id = PCI_VENDOR_ID_APPLE;
1854
    k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB;
1855
    k->class_id = PCI_CLASS_SERIAL_USB;
1856
    dc->desc = "Apple USB Controller";
1857
    dc->props = ohci_pci_properties;
1858
}
1859

    
1860
static TypeInfo ohci_pci_info = {
1861
    .name          = "pci-ohci",
1862
    .parent        = TYPE_PCI_DEVICE,
1863
    .instance_size = sizeof(OHCIPCIState),
1864
    .class_init    = ohci_pci_class_init,
1865
};
1866

    
1867
static Property ohci_sysbus_properties[] = {
1868
    DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1869
    DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
1870
    DEFINE_PROP_END_OF_LIST(),
1871
};
1872

    
1873
static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
1874
{
1875
    DeviceClass *dc = DEVICE_CLASS(klass);
1876
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
1877

    
1878
    sbc->init = ohci_init_pxa;
1879
    dc->desc = "OHCI USB Controller";
1880
    dc->props = ohci_sysbus_properties;
1881
}
1882

    
1883
static TypeInfo ohci_sysbus_info = {
1884
    .name          = "sysbus-ohci",
1885
    .parent        = TYPE_SYS_BUS_DEVICE,
1886
    .instance_size = sizeof(OHCISysBusState),
1887
    .class_init    = ohci_sysbus_class_init,
1888
};
1889

    
1890
static void ohci_register(void)
1891
{
1892
    type_register_static(&ohci_pci_info);
1893
    type_register_static(&ohci_sysbus_info);
1894
}
1895
device_init(ohci_register);