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1
/*
2
 * USB UHCI controller emulation
3
 *
4
 * Copyright (c) 2005 Fabrice Bellard
5
 *
6
 * Copyright (c) 2008 Max Krasnyansky
7
 *     Magor rewrite of the UHCI data structures parser and frame processor
8
 *     Support for fully async operation and multiple outstanding transactions
9
 *
10
 * Permission is hereby granted, free of charge, to any person obtaining a copy
11
 * of this software and associated documentation files (the "Software"), to deal
12
 * in the Software without restriction, including without limitation the rights
13
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14
 * copies of the Software, and to permit persons to whom the Software is
15
 * furnished to do so, subject to the following conditions:
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 *
17
 * The above copyright notice and this permission notice shall be included in
18
 * all copies or substantial portions of the Software.
19
 *
20
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26
 * THE SOFTWARE.
27
 */
28
#include "hw.h"
29
#include "usb.h"
30
#include "pci.h"
31
#include "qemu-timer.h"
32
#include "usb-uhci.h"
33
#include "iov.h"
34
#include "dma.h"
35

    
36
//#define DEBUG
37
//#define DEBUG_DUMP_DATA
38

    
39
#define UHCI_CMD_FGR      (1 << 4)
40
#define UHCI_CMD_EGSM     (1 << 3)
41
#define UHCI_CMD_GRESET   (1 << 2)
42
#define UHCI_CMD_HCRESET  (1 << 1)
43
#define UHCI_CMD_RS       (1 << 0)
44

    
45
#define UHCI_STS_HCHALTED (1 << 5)
46
#define UHCI_STS_HCPERR   (1 << 4)
47
#define UHCI_STS_HSERR    (1 << 3)
48
#define UHCI_STS_RD       (1 << 2)
49
#define UHCI_STS_USBERR   (1 << 1)
50
#define UHCI_STS_USBINT   (1 << 0)
51

    
52
#define TD_CTRL_SPD     (1 << 29)
53
#define TD_CTRL_ERROR_SHIFT  27
54
#define TD_CTRL_IOS     (1 << 25)
55
#define TD_CTRL_IOC     (1 << 24)
56
#define TD_CTRL_ACTIVE  (1 << 23)
57
#define TD_CTRL_STALL   (1 << 22)
58
#define TD_CTRL_BABBLE  (1 << 20)
59
#define TD_CTRL_NAK     (1 << 19)
60
#define TD_CTRL_TIMEOUT (1 << 18)
61

    
62
#define UHCI_PORT_SUSPEND (1 << 12)
63
#define UHCI_PORT_RESET (1 << 9)
64
#define UHCI_PORT_LSDA  (1 << 8)
65
#define UHCI_PORT_RD    (1 << 6)
66
#define UHCI_PORT_ENC   (1 << 3)
67
#define UHCI_PORT_EN    (1 << 2)
68
#define UHCI_PORT_CSC   (1 << 1)
69
#define UHCI_PORT_CCS   (1 << 0)
70

    
71
#define UHCI_PORT_READ_ONLY    (0x1bb)
72
#define UHCI_PORT_WRITE_CLEAR  (UHCI_PORT_CSC | UHCI_PORT_ENC)
73

    
74
#define FRAME_TIMER_FREQ 1000
75

    
76
#define FRAME_MAX_LOOPS  256
77

    
78
#define NB_PORTS 2
79

    
80
#ifdef DEBUG
81
#define DPRINTF printf
82

    
83
static const char *pid2str(int pid)
84
{
85
    switch (pid) {
86
    case USB_TOKEN_SETUP: return "SETUP";
87
    case USB_TOKEN_IN:    return "IN";
88
    case USB_TOKEN_OUT:   return "OUT";
89
    }
90
    return "?";
91
}
92

    
93
#else
94
#define DPRINTF(...)
95
#endif
96

    
97
typedef struct UHCIState UHCIState;
98

    
99
/* 
100
 * Pending async transaction.
101
 * 'packet' must be the first field because completion
102
 * handler does "(UHCIAsync *) pkt" cast.
103
 */
104
typedef struct UHCIAsync {
105
    USBPacket packet;
106
    QEMUSGList sgl;
107
    UHCIState *uhci;
108
    QTAILQ_ENTRY(UHCIAsync) next;
109
    uint32_t  td;
110
    uint32_t  token;
111
    int8_t    valid;
112
    uint8_t   isoc;
113
    uint8_t   done;
114
} UHCIAsync;
115

    
116
typedef struct UHCIPort {
117
    USBPort port;
118
    uint16_t ctrl;
119
} UHCIPort;
120

    
121
struct UHCIState {
122
    PCIDevice dev;
123
    MemoryRegion io_bar;
124
    USBBus bus; /* Note unused when we're a companion controller */
125
    uint16_t cmd; /* cmd register */
126
    uint16_t status;
127
    uint16_t intr; /* interrupt enable register */
128
    uint16_t frnum; /* frame number */
129
    uint32_t fl_base_addr; /* frame list base address */
130
    uint8_t sof_timing;
131
    uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
132
    int64_t expire_time;
133
    QEMUTimer *frame_timer;
134
    UHCIPort ports[NB_PORTS];
135

    
136
    /* Interrupts that should be raised at the end of the current frame.  */
137
    uint32_t pending_int_mask;
138

    
139
    /* Active packets */
140
    QTAILQ_HEAD(,UHCIAsync) async_pending;
141
    uint8_t num_ports_vmstate;
142

    
143
    /* Properties */
144
    char *masterbus;
145
    uint32_t firstport;
146
};
147

    
148
typedef struct UHCI_TD {
149
    uint32_t link;
150
    uint32_t ctrl; /* see TD_CTRL_xxx */
151
    uint32_t token;
152
    uint32_t buffer;
153
} UHCI_TD;
154

    
155
typedef struct UHCI_QH {
156
    uint32_t link;
157
    uint32_t el_link;
158
} UHCI_QH;
159

    
160
static UHCIAsync *uhci_async_alloc(UHCIState *s)
161
{
162
    UHCIAsync *async = g_malloc(sizeof(UHCIAsync));
163

    
164
    memset(&async->packet, 0, sizeof(async->packet));
165
    async->uhci  = s;
166
    async->valid = 0;
167
    async->td    = 0;
168
    async->token = 0;
169
    async->done  = 0;
170
    async->isoc  = 0;
171
    usb_packet_init(&async->packet);
172
    pci_dma_sglist_init(&async->sgl, &s->dev, 1);
173

    
174
    return async;
175
}
176

    
177
static void uhci_async_free(UHCIState *s, UHCIAsync *async)
178
{
179
    usb_packet_cleanup(&async->packet);
180
    qemu_sglist_destroy(&async->sgl);
181
    g_free(async);
182
}
183

    
184
static void uhci_async_link(UHCIState *s, UHCIAsync *async)
185
{
186
    QTAILQ_INSERT_HEAD(&s->async_pending, async, next);
187
}
188

    
189
static void uhci_async_unlink(UHCIState *s, UHCIAsync *async)
190
{
191
    QTAILQ_REMOVE(&s->async_pending, async, next);
192
}
193

    
194
static void uhci_async_cancel(UHCIState *s, UHCIAsync *async)
195
{
196
    DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n",
197
           async->td, async->token, async->done);
198

    
199
    if (!async->done)
200
        usb_cancel_packet(&async->packet);
201
    uhci_async_free(s, async);
202
}
203

    
204
/*
205
 * Mark all outstanding async packets as invalid.
206
 * This is used for canceling them when TDs are removed by the HCD.
207
 */
208
static UHCIAsync *uhci_async_validate_begin(UHCIState *s)
209
{
210
    UHCIAsync *async;
211

    
212
    QTAILQ_FOREACH(async, &s->async_pending, next) {
213
        async->valid--;
214
    }
215
    return NULL;
216
}
217

    
218
/*
219
 * Cancel async packets that are no longer valid
220
 */
221
static void uhci_async_validate_end(UHCIState *s)
222
{
223
    UHCIAsync *curr, *n;
224

    
225
    QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) {
226
        if (curr->valid > 0) {
227
            continue;
228
        }
229
        uhci_async_unlink(s, curr);
230
        uhci_async_cancel(s, curr);
231
    }
232
}
233

    
234
static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
235
{
236
    UHCIAsync *curr, *n;
237

    
238
    QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) {
239
        if (!usb_packet_is_inflight(&curr->packet) ||
240
            curr->packet.ep->dev != dev) {
241
            continue;
242
        }
243
        uhci_async_unlink(s, curr);
244
        uhci_async_cancel(s, curr);
245
    }
246
}
247

    
248
static void uhci_async_cancel_all(UHCIState *s)
249
{
250
    UHCIAsync *curr, *n;
251

    
252
    QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) {
253
        uhci_async_unlink(s, curr);
254
        uhci_async_cancel(s, curr);
255
    }
256
}
257

    
258
static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token)
259
{
260
    UHCIAsync *async;
261
    UHCIAsync *match = NULL;
262
    int count = 0;
263

    
264
    /*
265
     * We're looking for the best match here. ie both td addr and token.
266
     * Otherwise we return last good match. ie just token.
267
     * It's ok to match just token because it identifies the transaction
268
     * rather well, token includes: device addr, endpoint, size, etc.
269
     *
270
     * Also since we queue async transactions in reverse order by returning
271
     * last good match we restores the order.
272
     *
273
     * It's expected that we wont have a ton of outstanding transactions.
274
     * If we ever do we'd want to optimize this algorithm.
275
     */
276

    
277
    QTAILQ_FOREACH(async, &s->async_pending, next) {
278
        if (async->token == token) {
279
            /* Good match */
280
            match = async;
281

    
282
            if (async->td == addr) {
283
                /* Best match */
284
                break;
285
            }
286
        }
287
        count++;
288
    }
289

    
290
    if (count > 64)
291
        fprintf(stderr, "uhci: warning lots of async transactions\n");
292

    
293
    return match;
294
}
295

    
296
static void uhci_update_irq(UHCIState *s)
297
{
298
    int level;
299
    if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
300
        ((s->status2 & 2) && (s->intr & (1 << 3))) ||
301
        ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
302
        ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
303
        (s->status & UHCI_STS_HSERR) ||
304
        (s->status & UHCI_STS_HCPERR)) {
305
        level = 1;
306
    } else {
307
        level = 0;
308
    }
309
    qemu_set_irq(s->dev.irq[3], level);
310
}
311

    
312
static void uhci_reset(void *opaque)
313
{
314
    UHCIState *s = opaque;
315
    uint8_t *pci_conf;
316
    int i;
317
    UHCIPort *port;
318

    
319
    DPRINTF("uhci: full reset\n");
320

    
321
    pci_conf = s->dev.config;
322

    
323
    pci_conf[0x6a] = 0x01; /* usb clock */
324
    pci_conf[0x6b] = 0x00;
325
    s->cmd = 0;
326
    s->status = 0;
327
    s->status2 = 0;
328
    s->intr = 0;
329
    s->fl_base_addr = 0;
330
    s->sof_timing = 64;
331

    
332
    for(i = 0; i < NB_PORTS; i++) {
333
        port = &s->ports[i];
334
        port->ctrl = 0x0080;
335
        if (port->port.dev && port->port.dev->attached) {
336
            usb_port_reset(&port->port);
337
        }
338
    }
339

    
340
    uhci_async_cancel_all(s);
341
}
342

    
343
static void uhci_pre_save(void *opaque)
344
{
345
    UHCIState *s = opaque;
346

    
347
    uhci_async_cancel_all(s);
348
}
349

    
350
static const VMStateDescription vmstate_uhci_port = {
351
    .name = "uhci port",
352
    .version_id = 1,
353
    .minimum_version_id = 1,
354
    .minimum_version_id_old = 1,
355
    .fields      = (VMStateField []) {
356
        VMSTATE_UINT16(ctrl, UHCIPort),
357
        VMSTATE_END_OF_LIST()
358
    }
359
};
360

    
361
static const VMStateDescription vmstate_uhci = {
362
    .name = "uhci",
363
    .version_id = 2,
364
    .minimum_version_id = 1,
365
    .minimum_version_id_old = 1,
366
    .pre_save = uhci_pre_save,
367
    .fields      = (VMStateField []) {
368
        VMSTATE_PCI_DEVICE(dev, UHCIState),
369
        VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState),
370
        VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
371
                             vmstate_uhci_port, UHCIPort),
372
        VMSTATE_UINT16(cmd, UHCIState),
373
        VMSTATE_UINT16(status, UHCIState),
374
        VMSTATE_UINT16(intr, UHCIState),
375
        VMSTATE_UINT16(frnum, UHCIState),
376
        VMSTATE_UINT32(fl_base_addr, UHCIState),
377
        VMSTATE_UINT8(sof_timing, UHCIState),
378
        VMSTATE_UINT8(status2, UHCIState),
379
        VMSTATE_TIMER(frame_timer, UHCIState),
380
        VMSTATE_INT64_V(expire_time, UHCIState, 2),
381
        VMSTATE_END_OF_LIST()
382
    }
383
};
384

    
385
static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
386
{
387
    UHCIState *s = opaque;
388

    
389
    addr &= 0x1f;
390
    switch(addr) {
391
    case 0x0c:
392
        s->sof_timing = val;
393
        break;
394
    }
395
}
396

    
397
static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)
398
{
399
    UHCIState *s = opaque;
400
    uint32_t val;
401

    
402
    addr &= 0x1f;
403
    switch(addr) {
404
    case 0x0c:
405
        val = s->sof_timing;
406
        break;
407
    default:
408
        val = 0xff;
409
        break;
410
    }
411
    return val;
412
}
413

    
414
static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
415
{
416
    UHCIState *s = opaque;
417

    
418
    addr &= 0x1f;
419
    DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
420

    
421
    switch(addr) {
422
    case 0x00:
423
        if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
424
            /* start frame processing */
425
            s->expire_time = qemu_get_clock_ns(vm_clock) +
426
                (get_ticks_per_sec() / FRAME_TIMER_FREQ);
427
            qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
428
            s->status &= ~UHCI_STS_HCHALTED;
429
        } else if (!(val & UHCI_CMD_RS)) {
430
            s->status |= UHCI_STS_HCHALTED;
431
        }
432
        if (val & UHCI_CMD_GRESET) {
433
            UHCIPort *port;
434
            int i;
435

    
436
            /* send reset on the USB bus */
437
            for(i = 0; i < NB_PORTS; i++) {
438
                port = &s->ports[i];
439
                usb_device_reset(port->port.dev);
440
            }
441
            uhci_reset(s);
442
            return;
443
        }
444
        if (val & UHCI_CMD_HCRESET) {
445
            uhci_reset(s);
446
            return;
447
        }
448
        s->cmd = val;
449
        break;
450
    case 0x02:
451
        s->status &= ~val;
452
        /* XXX: the chip spec is not coherent, so we add a hidden
453
           register to distinguish between IOC and SPD */
454
        if (val & UHCI_STS_USBINT)
455
            s->status2 = 0;
456
        uhci_update_irq(s);
457
        break;
458
    case 0x04:
459
        s->intr = val;
460
        uhci_update_irq(s);
461
        break;
462
    case 0x06:
463
        if (s->status & UHCI_STS_HCHALTED)
464
            s->frnum = val & 0x7ff;
465
        break;
466
    case 0x10 ... 0x1f:
467
        {
468
            UHCIPort *port;
469
            USBDevice *dev;
470
            int n;
471

    
472
            n = (addr >> 1) & 7;
473
            if (n >= NB_PORTS)
474
                return;
475
            port = &s->ports[n];
476
            dev = port->port.dev;
477
            if (dev && dev->attached) {
478
                /* port reset */
479
                if ( (val & UHCI_PORT_RESET) &&
480
                     !(port->ctrl & UHCI_PORT_RESET) ) {
481
                    usb_device_reset(dev);
482
                }
483
            }
484
            port->ctrl &= UHCI_PORT_READ_ONLY;
485
            port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
486
            /* some bits are reset when a '1' is written to them */
487
            port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
488
        }
489
        break;
490
    }
491
}
492

    
493
static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr)
494
{
495
    UHCIState *s = opaque;
496
    uint32_t val;
497

    
498
    addr &= 0x1f;
499
    switch(addr) {
500
    case 0x00:
501
        val = s->cmd;
502
        break;
503
    case 0x02:
504
        val = s->status;
505
        break;
506
    case 0x04:
507
        val = s->intr;
508
        break;
509
    case 0x06:
510
        val = s->frnum;
511
        break;
512
    case 0x10 ... 0x1f:
513
        {
514
            UHCIPort *port;
515
            int n;
516
            n = (addr >> 1) & 7;
517
            if (n >= NB_PORTS)
518
                goto read_default;
519
            port = &s->ports[n];
520
            val = port->ctrl;
521
        }
522
        break;
523
    default:
524
    read_default:
525
        val = 0xff7f; /* disabled port */
526
        break;
527
    }
528

    
529
    DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
530

    
531
    return val;
532
}
533

    
534
static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
535
{
536
    UHCIState *s = opaque;
537

    
538
    addr &= 0x1f;
539
    DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
540

    
541
    switch(addr) {
542
    case 0x08:
543
        s->fl_base_addr = val & ~0xfff;
544
        break;
545
    }
546
}
547

    
548
static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr)
549
{
550
    UHCIState *s = opaque;
551
    uint32_t val;
552

    
553
    addr &= 0x1f;
554
    switch(addr) {
555
    case 0x08:
556
        val = s->fl_base_addr;
557
        break;
558
    default:
559
        val = 0xffffffff;
560
        break;
561
    }
562
    return val;
563
}
564

    
565
/* signal resume if controller suspended */
566
static void uhci_resume (void *opaque)
567
{
568
    UHCIState *s = (UHCIState *)opaque;
569

    
570
    if (!s)
571
        return;
572

    
573
    if (s->cmd & UHCI_CMD_EGSM) {
574
        s->cmd |= UHCI_CMD_FGR;
575
        s->status |= UHCI_STS_RD;
576
        uhci_update_irq(s);
577
    }
578
}
579

    
580
static void uhci_attach(USBPort *port1)
581
{
582
    UHCIState *s = port1->opaque;
583
    UHCIPort *port = &s->ports[port1->index];
584

    
585
    /* set connect status */
586
    port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
587

    
588
    /* update speed */
589
    if (port->port.dev->speed == USB_SPEED_LOW) {
590
        port->ctrl |= UHCI_PORT_LSDA;
591
    } else {
592
        port->ctrl &= ~UHCI_PORT_LSDA;
593
    }
594

    
595
    uhci_resume(s);
596
}
597

    
598
static void uhci_detach(USBPort *port1)
599
{
600
    UHCIState *s = port1->opaque;
601
    UHCIPort *port = &s->ports[port1->index];
602

    
603
    uhci_async_cancel_device(s, port1->dev);
604

    
605
    /* set connect status */
606
    if (port->ctrl & UHCI_PORT_CCS) {
607
        port->ctrl &= ~UHCI_PORT_CCS;
608
        port->ctrl |= UHCI_PORT_CSC;
609
    }
610
    /* disable port */
611
    if (port->ctrl & UHCI_PORT_EN) {
612
        port->ctrl &= ~UHCI_PORT_EN;
613
        port->ctrl |= UHCI_PORT_ENC;
614
    }
615

    
616
    uhci_resume(s);
617
}
618

    
619
static void uhci_child_detach(USBPort *port1, USBDevice *child)
620
{
621
    UHCIState *s = port1->opaque;
622

    
623
    uhci_async_cancel_device(s, child);
624
}
625

    
626
static void uhci_wakeup(USBPort *port1)
627
{
628
    UHCIState *s = port1->opaque;
629
    UHCIPort *port = &s->ports[port1->index];
630

    
631
    if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
632
        port->ctrl |= UHCI_PORT_RD;
633
        uhci_resume(s);
634
    }
635
}
636

    
637
static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
638
{
639
    USBDevice *dev;
640
    int i;
641

    
642
    for (i = 0; i < NB_PORTS; i++) {
643
        UHCIPort *port = &s->ports[i];
644
        if (!(port->ctrl & UHCI_PORT_EN)) {
645
            continue;
646
        }
647
        dev = usb_find_device(&port->port, addr);
648
        if (dev != NULL) {
649
            return dev;
650
        }
651
    }
652
    return NULL;
653
}
654

    
655
static void uhci_async_complete(USBPort *port, USBPacket *packet);
656
static void uhci_process_frame(UHCIState *s);
657

    
658
/* return -1 if fatal error (frame must be stopped)
659
          0 if TD successful
660
          1 if TD unsuccessful or inactive
661
*/
662
static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
663
{
664
    int len = 0, max_len, err, ret;
665
    uint8_t pid;
666

    
667
    max_len = ((td->token >> 21) + 1) & 0x7ff;
668
    pid = td->token & 0xff;
669

    
670
    ret = async->packet.result;
671

    
672
    if (td->ctrl & TD_CTRL_IOS)
673
        td->ctrl &= ~TD_CTRL_ACTIVE;
674

    
675
    if (ret < 0)
676
        goto out;
677

    
678
    len = async->packet.result;
679
    td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
680

    
681
    /* The NAK bit may have been set by a previous frame, so clear it
682
       here.  The docs are somewhat unclear, but win2k relies on this
683
       behavior.  */
684
    td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
685
    if (td->ctrl & TD_CTRL_IOC)
686
        *int_mask |= 0x01;
687

    
688
    if (pid == USB_TOKEN_IN) {
689
        if (len > max_len) {
690
            ret = USB_RET_BABBLE;
691
            goto out;
692
        }
693

    
694
        if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
695
            *int_mask |= 0x02;
696
            /* short packet: do not update QH */
697
            DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
698
            return 1;
699
        }
700
    }
701

    
702
    /* success */
703
    return 0;
704

    
705
out:
706
    switch(ret) {
707
    case USB_RET_STALL:
708
        td->ctrl |= TD_CTRL_STALL;
709
        td->ctrl &= ~TD_CTRL_ACTIVE;
710
        s->status |= UHCI_STS_USBERR;
711
        if (td->ctrl & TD_CTRL_IOC) {
712
            *int_mask |= 0x01;
713
        }
714
        uhci_update_irq(s);
715
        return 1;
716

    
717
    case USB_RET_BABBLE:
718
        td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
719
        td->ctrl &= ~TD_CTRL_ACTIVE;
720
        s->status |= UHCI_STS_USBERR;
721
        if (td->ctrl & TD_CTRL_IOC) {
722
            *int_mask |= 0x01;
723
        }
724
        uhci_update_irq(s);
725
        /* frame interrupted */
726
        return -1;
727

    
728
    case USB_RET_NAK:
729
        td->ctrl |= TD_CTRL_NAK;
730
        if (pid == USB_TOKEN_SETUP)
731
            break;
732
        return 1;
733

    
734
    case USB_RET_NODEV:
735
    default:
736
        break;
737
    }
738

    
739
    /* Retry the TD if error count is not zero */
740

    
741
    td->ctrl |= TD_CTRL_TIMEOUT;
742
    err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
743
    if (err != 0) {
744
        err--;
745
        if (err == 0) {
746
            td->ctrl &= ~TD_CTRL_ACTIVE;
747
            s->status |= UHCI_STS_USBERR;
748
            if (td->ctrl & TD_CTRL_IOC)
749
                *int_mask |= 0x01;
750
            uhci_update_irq(s);
751
        }
752
    }
753
    td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
754
        (err << TD_CTRL_ERROR_SHIFT);
755
    return 1;
756
}
757

    
758
static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask)
759
{
760
    UHCIAsync *async;
761
    int len = 0, max_len;
762
    uint8_t pid, isoc;
763
    uint32_t token;
764
    USBDevice *dev;
765
    USBEndpoint *ep;
766

    
767
    /* Is active ? */
768
    if (!(td->ctrl & TD_CTRL_ACTIVE))
769
        return 1;
770

    
771
    /* token field is not unique for isochronous requests,
772
     * so use the destination buffer 
773
     */
774
    if (td->ctrl & TD_CTRL_IOS) {
775
        token = td->buffer;
776
        isoc = 1;
777
    } else {
778
        token = td->token;
779
        isoc = 0;
780
    }
781

    
782
    async = uhci_async_find_td(s, addr, token);
783
    if (async) {
784
        /* Already submitted */
785
        async->valid = 32;
786

    
787
        if (!async->done)
788
            return 1;
789

    
790
        uhci_async_unlink(s, async);
791
        goto done;
792
    }
793

    
794
    /* Allocate new packet */
795
    async = uhci_async_alloc(s);
796
    if (!async)
797
        return 1;
798

    
799
    /* valid needs to be large enough to handle 10 frame delay
800
     * for initial isochronous requests
801
     */
802
    async->valid = 32;
803
    async->td    = addr;
804
    async->token = token;
805
    async->isoc  = isoc;
806

    
807
    max_len = ((td->token >> 21) + 1) & 0x7ff;
808
    pid = td->token & 0xff;
809

    
810
    dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
811
    ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
812
    usb_packet_setup(&async->packet, pid, ep);
813
    qemu_sglist_add(&async->sgl, td->buffer, max_len);
814
    usb_packet_map(&async->packet, &async->sgl);
815

    
816
    switch(pid) {
817
    case USB_TOKEN_OUT:
818
    case USB_TOKEN_SETUP:
819
        len = usb_handle_packet(dev, &async->packet);
820
        if (len >= 0)
821
            len = max_len;
822
        break;
823

    
824
    case USB_TOKEN_IN:
825
        len = usb_handle_packet(dev, &async->packet);
826
        break;
827

    
828
    default:
829
        /* invalid pid : frame interrupted */
830
        uhci_async_free(s, async);
831
        s->status |= UHCI_STS_HCPERR;
832
        uhci_update_irq(s);
833
        return -1;
834
    }
835
 
836
    if (len == USB_RET_ASYNC) {
837
        uhci_async_link(s, async);
838
        return 2;
839
    }
840

    
841
    async->packet.result = len;
842

    
843
done:
844
    len = uhci_complete_td(s, td, async, int_mask);
845
    usb_packet_unmap(&async->packet);
846
    uhci_async_free(s, async);
847
    return len;
848
}
849

    
850
static void uhci_async_complete(USBPort *port, USBPacket *packet)
851
{
852
    UHCIAsync *async = container_of(packet, UHCIAsync, packet);
853
    UHCIState *s = async->uhci;
854

    
855
    DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
856

    
857
    if (async->isoc) {
858
        UHCI_TD td;
859
        uint32_t link = async->td;
860
        uint32_t int_mask = 0, val;
861

    
862
        pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
863
        le32_to_cpus(&td.link);
864
        le32_to_cpus(&td.ctrl);
865
        le32_to_cpus(&td.token);
866
        le32_to_cpus(&td.buffer);
867

    
868
        uhci_async_unlink(s, async);
869
        uhci_complete_td(s, &td, async, &int_mask);
870
        s->pending_int_mask |= int_mask;
871

    
872
        /* update the status bits of the TD */
873
        val = cpu_to_le32(td.ctrl);
874
        pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
875
        uhci_async_free(s, async);
876
    } else {
877
        async->done = 1;
878
        uhci_process_frame(s);
879
    }
880
}
881

    
882
static int is_valid(uint32_t link)
883
{
884
    return (link & 1) == 0;
885
}
886

    
887
static int is_qh(uint32_t link)
888
{
889
    return (link & 2) != 0;
890
}
891

    
892
static int depth_first(uint32_t link)
893
{
894
    return (link & 4) != 0;
895
}
896

    
897
/* QH DB used for detecting QH loops */
898
#define UHCI_MAX_QUEUES 128
899
typedef struct {
900
    uint32_t addr[UHCI_MAX_QUEUES];
901
    int      count;
902
} QhDb;
903

    
904
static void qhdb_reset(QhDb *db)
905
{
906
    db->count = 0;
907
}
908

    
909
/* Add QH to DB. Returns 1 if already present or DB is full. */
910
static int qhdb_insert(QhDb *db, uint32_t addr)
911
{
912
    int i;
913
    for (i = 0; i < db->count; i++)
914
        if (db->addr[i] == addr)
915
            return 1;
916

    
917
    if (db->count >= UHCI_MAX_QUEUES)
918
        return 1;
919

    
920
    db->addr[db->count++] = addr;
921
    return 0;
922
}
923

    
924
static void uhci_process_frame(UHCIState *s)
925
{
926
    uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
927
    uint32_t curr_qh, td_count = 0, bytes_count = 0;
928
    int cnt, ret;
929
    UHCI_TD td;
930
    UHCI_QH qh;
931
    QhDb qhdb;
932

    
933
    frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
934

    
935
    DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
936

    
937
    pci_dma_read(&s->dev, frame_addr, &link, 4);
938
    le32_to_cpus(&link);
939

    
940
    int_mask = 0;
941
    curr_qh  = 0;
942

    
943
    qhdb_reset(&qhdb);
944

    
945
    for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
946
        if (is_qh(link)) {
947
            /* QH */
948

    
949
            if (qhdb_insert(&qhdb, link)) {
950
                /*
951
                 * We're going in circles. Which is not a bug because
952
                 * HCD is allowed to do that as part of the BW management.
953
                 *
954
                 * Stop processing here if
955
                 *  (a) no transaction has been done since we've been
956
                 *      here last time, or
957
                 *  (b) we've reached the usb 1.1 bandwidth, which is
958
                 *      1280 bytes/frame.
959
                 */
960
                DPRINTF("uhci: detected loop. qh 0x%x\n", link);
961
                if (td_count == 0) {
962
                    DPRINTF("uhci: no transaction last round, stop\n");
963
                    break;
964
                } else if (bytes_count >= 1280) {
965
                    DPRINTF("uhci: bandwidth limit reached, stop\n");
966
                    break;
967
                } else {
968
                    td_count = 0;
969
                    qhdb_reset(&qhdb);
970
                    qhdb_insert(&qhdb, link);
971
                }
972
            }
973

    
974
            pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
975
            le32_to_cpus(&qh.link);
976
            le32_to_cpus(&qh.el_link);
977

    
978
            DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
979
                    link, qh.link, qh.el_link);
980

    
981
            if (!is_valid(qh.el_link)) {
982
                /* QH w/o elements */
983
                curr_qh = 0;
984
                link = qh.link;
985
            } else {
986
                /* QH with elements */
987
                    curr_qh = link;
988
                    link = qh.el_link;
989
            }
990
            continue;
991
        }
992

    
993
        /* TD */
994
        pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
995
        le32_to_cpus(&td.link);
996
        le32_to_cpus(&td.ctrl);
997
        le32_to_cpus(&td.token);
998
        le32_to_cpus(&td.buffer);
999

    
1000
        DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", 
1001
                link, td.link, td.ctrl, td.token, curr_qh);
1002

    
1003
        old_td_ctrl = td.ctrl;
1004
        ret = uhci_handle_td(s, link, &td, &int_mask);
1005
        if (old_td_ctrl != td.ctrl) {
1006
            /* update the status bits of the TD */
1007
            val = cpu_to_le32(td.ctrl);
1008
            pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1009
        }
1010

    
1011
        if (ret < 0) {
1012
            /* interrupted frame */
1013
            break;
1014
        }
1015

    
1016
        if (ret == 2 || ret == 1) {
1017
            DPRINTF("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1018
                    link, ret == 2 ? "pend" : "skip",
1019
                    td.link, td.ctrl, td.token, curr_qh);
1020

    
1021
            link = curr_qh ? qh.link : td.link;
1022
            continue;
1023
        }
1024

    
1025
        /* completed TD */
1026

    
1027
        DPRINTF("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", 
1028
                link, td.link, td.ctrl, td.token, curr_qh);
1029

    
1030
        link = td.link;
1031
        td_count++;
1032
        bytes_count += (td.ctrl & 0x7ff) + 1;
1033

    
1034
        if (curr_qh) {
1035
            /* update QH element link */
1036
            qh.el_link = link;
1037
            val = cpu_to_le32(qh.el_link);
1038
            pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1039

    
1040
            if (!depth_first(link)) {
1041
               /* done with this QH */
1042

    
1043
               DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
1044
                       curr_qh, qh.link, qh.el_link);
1045

    
1046
               curr_qh = 0;
1047
               link    = qh.link;
1048
            }
1049
        }
1050

    
1051
        /* go to the next entry */
1052
    }
1053

    
1054
    s->pending_int_mask |= int_mask;
1055
}
1056

    
1057
static void uhci_frame_timer(void *opaque)
1058
{
1059
    UHCIState *s = opaque;
1060

    
1061
    /* prepare the timer for the next frame */
1062
    s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1063

    
1064
    if (!(s->cmd & UHCI_CMD_RS)) {
1065
        /* Full stop */
1066
        qemu_del_timer(s->frame_timer);
1067
        /* set hchalted bit in status - UHCI11D 2.1.2 */
1068
        s->status |= UHCI_STS_HCHALTED;
1069

    
1070
        DPRINTF("uhci: halted\n");
1071
        return;
1072
    }
1073

    
1074
    /* Complete the previous frame */
1075
    if (s->pending_int_mask) {
1076
        s->status2 |= s->pending_int_mask;
1077
        s->status  |= UHCI_STS_USBINT;
1078
        uhci_update_irq(s);
1079
    }
1080
    s->pending_int_mask = 0;
1081

    
1082
    /* Start new frame */
1083
    s->frnum = (s->frnum + 1) & 0x7ff;
1084

    
1085
    DPRINTF("uhci: new frame #%u\n" , s->frnum);
1086

    
1087
    uhci_async_validate_begin(s);
1088

    
1089
    uhci_process_frame(s);
1090

    
1091
    uhci_async_validate_end(s);
1092

    
1093
    qemu_mod_timer(s->frame_timer, s->expire_time);
1094
}
1095

    
1096
static const MemoryRegionPortio uhci_portio[] = {
1097
    { 0, 32, 2, .write = uhci_ioport_writew, },
1098
    { 0, 32, 2, .read = uhci_ioport_readw, },
1099
    { 0, 32, 4, .write = uhci_ioport_writel, },
1100
    { 0, 32, 4, .read = uhci_ioport_readl, },
1101
    { 0, 32, 1, .write = uhci_ioport_writeb, },
1102
    { 0, 32, 1, .read = uhci_ioport_readb, },
1103
    PORTIO_END_OF_LIST()
1104
};
1105

    
1106
static const MemoryRegionOps uhci_ioport_ops = {
1107
    .old_portio = uhci_portio,
1108
};
1109

    
1110
static USBPortOps uhci_port_ops = {
1111
    .attach = uhci_attach,
1112
    .detach = uhci_detach,
1113
    .child_detach = uhci_child_detach,
1114
    .wakeup = uhci_wakeup,
1115
    .complete = uhci_async_complete,
1116
};
1117

    
1118
static USBBusOps uhci_bus_ops = {
1119
};
1120

    
1121
static int usb_uhci_common_initfn(PCIDevice *dev)
1122
{
1123
    UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1124
    uint8_t *pci_conf = s->dev.config;
1125
    int i;
1126

    
1127
    pci_conf[PCI_CLASS_PROG] = 0x00;
1128
    /* TODO: reset value should be 0. */
1129
    pci_conf[PCI_INTERRUPT_PIN] = 4; /* interrupt pin D */
1130
    pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1131

    
1132
    if (s->masterbus) {
1133
        USBPort *ports[NB_PORTS];
1134
        for(i = 0; i < NB_PORTS; i++) {
1135
            ports[i] = &s->ports[i].port;
1136
        }
1137
        if (usb_register_companion(s->masterbus, ports, NB_PORTS,
1138
                s->firstport, s, &uhci_port_ops,
1139
                USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1140
            return -1;
1141
        }
1142
    } else {
1143
        usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev);
1144
        for (i = 0; i < NB_PORTS; i++) {
1145
            usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1146
                              USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1147
        }
1148
    }
1149
    s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s);
1150
    s->num_ports_vmstate = NB_PORTS;
1151
    QTAILQ_INIT(&s->async_pending);
1152

    
1153
    qemu_register_reset(uhci_reset, s);
1154

    
1155
    memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20);
1156
    /* Use region 4 for consistency with real hardware.  BSD guests seem
1157
       to rely on this.  */
1158
    pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1159

    
1160
    return 0;
1161
}
1162

    
1163
static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
1164
{
1165
    UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1166
    uint8_t *pci_conf = s->dev.config;
1167

    
1168
    /* USB misc control 1/2 */
1169
    pci_set_long(pci_conf + 0x40,0x00001000);
1170
    /* PM capability */
1171
    pci_set_long(pci_conf + 0x80,0x00020001);
1172
    /* USB legacy support  */
1173
    pci_set_long(pci_conf + 0xc0,0x00002000);
1174

    
1175
    return usb_uhci_common_initfn(dev);
1176
}
1177

    
1178
static int usb_uhci_exit(PCIDevice *dev)
1179
{
1180
    UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1181

    
1182
    memory_region_destroy(&s->io_bar);
1183
    return 0;
1184
}
1185

    
1186
static Property uhci_properties[] = {
1187
    DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1188
    DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1189
    DEFINE_PROP_END_OF_LIST(),
1190
};
1191

    
1192
static void piix3_uhci_class_init(ObjectClass *klass, void *data)
1193
{
1194
    DeviceClass *dc = DEVICE_CLASS(klass);
1195
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1196

    
1197
    k->init = usb_uhci_common_initfn;
1198
    k->exit = usb_uhci_exit;
1199
    k->vendor_id = PCI_VENDOR_ID_INTEL;
1200
    k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2;
1201
    k->revision = 0x01;
1202
    k->class_id = PCI_CLASS_SERIAL_USB;
1203
    dc->vmsd = &vmstate_uhci;
1204
    dc->props = uhci_properties;
1205
}
1206

    
1207
static TypeInfo piix3_uhci_info = {
1208
    .name          = "piix3-usb-uhci",
1209
    .parent        = TYPE_PCI_DEVICE,
1210
    .instance_size = sizeof(UHCIState),
1211
    .class_init    = piix3_uhci_class_init,
1212
};
1213

    
1214
static void piix4_uhci_class_init(ObjectClass *klass, void *data)
1215
{
1216
    DeviceClass *dc = DEVICE_CLASS(klass);
1217
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1218

    
1219
    k->init = usb_uhci_common_initfn;
1220
    k->exit = usb_uhci_exit;
1221
    k->vendor_id = PCI_VENDOR_ID_INTEL;
1222
    k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2;
1223
    k->revision = 0x01;
1224
    k->class_id = PCI_CLASS_SERIAL_USB;
1225
    dc->vmsd = &vmstate_uhci;
1226
    dc->props = uhci_properties;
1227
}
1228

    
1229
static TypeInfo piix4_uhci_info = {
1230
    .name          = "piix4-usb-uhci",
1231
    .parent        = TYPE_PCI_DEVICE,
1232
    .instance_size = sizeof(UHCIState),
1233
    .class_init    = piix4_uhci_class_init,
1234
};
1235

    
1236
static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data)
1237
{
1238
    DeviceClass *dc = DEVICE_CLASS(klass);
1239
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1240

    
1241
    k->init = usb_uhci_vt82c686b_initfn;
1242
    k->exit = usb_uhci_exit;
1243
    k->vendor_id = PCI_VENDOR_ID_VIA;
1244
    k->device_id = PCI_DEVICE_ID_VIA_UHCI;
1245
    k->revision = 0x01;
1246
    k->class_id = PCI_CLASS_SERIAL_USB;
1247
    dc->vmsd = &vmstate_uhci;
1248
    dc->props = uhci_properties;
1249
}
1250

    
1251
static TypeInfo vt82c686b_uhci_info = {
1252
    .name          = "vt82c686b-usb-uhci",
1253
    .parent        = TYPE_PCI_DEVICE,
1254
    .instance_size = sizeof(UHCIState),
1255
    .class_init    = vt82c686b_uhci_class_init,
1256
};
1257

    
1258
static void ich9_uhci1_class_init(ObjectClass *klass, void *data)
1259
{
1260
    DeviceClass *dc = DEVICE_CLASS(klass);
1261
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1262

    
1263
    k->init = usb_uhci_common_initfn;
1264
    k->vendor_id = PCI_VENDOR_ID_INTEL;
1265
    k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1;
1266
    k->revision = 0x03;
1267
    k->class_id = PCI_CLASS_SERIAL_USB;
1268
    dc->vmsd = &vmstate_uhci;
1269
    dc->props = uhci_properties;
1270
}
1271

    
1272
static TypeInfo ich9_uhci1_info = {
1273
    .name          = "ich9-usb-uhci1",
1274
    .parent        = TYPE_PCI_DEVICE,
1275
    .instance_size = sizeof(UHCIState),
1276
    .class_init    = ich9_uhci1_class_init,
1277
};
1278

    
1279
static void ich9_uhci2_class_init(ObjectClass *klass, void *data)
1280
{
1281
    DeviceClass *dc = DEVICE_CLASS(klass);
1282
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1283

    
1284
    k->init = usb_uhci_common_initfn;
1285
    k->vendor_id = PCI_VENDOR_ID_INTEL;
1286
    k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2;
1287
    k->revision = 0x03;
1288
    k->class_id = PCI_CLASS_SERIAL_USB;
1289
    dc->vmsd = &vmstate_uhci;
1290
    dc->props = uhci_properties;
1291
}
1292

    
1293
static TypeInfo ich9_uhci2_info = {
1294
    .name          = "ich9-usb-uhci2",
1295
    .parent        = TYPE_PCI_DEVICE,
1296
    .instance_size = sizeof(UHCIState),
1297
    .class_init    = ich9_uhci2_class_init,
1298
};
1299

    
1300
static void ich9_uhci3_class_init(ObjectClass *klass, void *data)
1301
{
1302
    DeviceClass *dc = DEVICE_CLASS(klass);
1303
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1304

    
1305
    k->init = usb_uhci_common_initfn;
1306
    k->vendor_id = PCI_VENDOR_ID_INTEL;
1307
    k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3;
1308
    k->revision = 0x03;
1309
    k->class_id = PCI_CLASS_SERIAL_USB;
1310
    dc->vmsd = &vmstate_uhci;
1311
    dc->props = uhci_properties;
1312
}
1313

    
1314
static TypeInfo ich9_uhci3_info = {
1315
    .name          = "ich9-usb-uhci3",
1316
    .parent        = TYPE_PCI_DEVICE,
1317
    .instance_size = sizeof(UHCIState),
1318
    .class_init    = ich9_uhci3_class_init,
1319
};
1320

    
1321
static void uhci_register(void)
1322
{
1323
    type_register_static(&piix3_uhci_info);
1324
    type_register_static(&piix4_uhci_info);
1325
    type_register_static(&vt82c686b_uhci_info);
1326
    type_register_static(&ich9_uhci1_info);
1327
    type_register_static(&ich9_uhci2_info);
1328
    type_register_static(&ich9_uhci3_info);
1329
}
1330
device_init(uhci_register);
1331

    
1332
void usb_uhci_piix3_init(PCIBus *bus, int devfn)
1333
{
1334
    pci_create_simple(bus, devfn, "piix3-usb-uhci");
1335
}
1336

    
1337
void usb_uhci_piix4_init(PCIBus *bus, int devfn)
1338
{
1339
    pci_create_simple(bus, devfn, "piix4-usb-uhci");
1340
}
1341

    
1342
void usb_uhci_vt82c686b_init(PCIBus *bus, int devfn)
1343
{
1344
    pci_create_simple(bus, devfn, "vt82c686b-usb-uhci");
1345
}