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/*
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 *  Alpha emulation cpu helpers for qemu.
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 *
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 *  Copyright (c) 2007 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "softfloat.h"
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uint64_t cpu_alpha_load_fpcr (CPUState *env)
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{
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    uint64_t r = 0;
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    uint8_t t;
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    t = env->fpcr_exc_status;
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    if (t) {
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        r = FPCR_SUM;
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        if (t & float_flag_invalid) {
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            r |= FPCR_INV;
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        }
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        if (t & float_flag_divbyzero) {
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            r |= FPCR_DZE;
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        }
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        if (t & float_flag_overflow) {
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            r |= FPCR_OVF;
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        }
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        if (t & float_flag_underflow) {
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            r |= FPCR_UNF;
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        }
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        if (t & float_flag_inexact) {
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            r |= FPCR_INE;
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        }
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    }
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    t = env->fpcr_exc_mask;
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    if (t & float_flag_invalid) {
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        r |= FPCR_INVD;
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    }
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    if (t & float_flag_divbyzero) {
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        r |= FPCR_DZED;
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    }
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    if (t & float_flag_overflow) {
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        r |= FPCR_OVFD;
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    }
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    if (t & float_flag_underflow) {
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        r |= FPCR_UNFD;
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    }
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    if (t & float_flag_inexact) {
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        r |= FPCR_INED;
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    }
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    switch (env->fpcr_dyn_round) {
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    case float_round_nearest_even:
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        r |= FPCR_DYN_NORMAL;
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        break;
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    case float_round_down:
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        r |= FPCR_DYN_MINUS;
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        break;
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    case float_round_up:
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        r |= FPCR_DYN_PLUS;
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        break;
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    case float_round_to_zero:
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        r |= FPCR_DYN_CHOPPED;
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        break;
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    }
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    if (env->fpcr_dnz) {
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        r |= FPCR_DNZ;
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    }
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    if (env->fpcr_dnod) {
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        r |= FPCR_DNOD;
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    }
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    if (env->fpcr_undz) {
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        r |= FPCR_UNDZ;
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    }
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    return r;
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}
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void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
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{
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    uint8_t t;
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    t = 0;
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    if (val & FPCR_INV) {
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        t |= float_flag_invalid;
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    }
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    if (val & FPCR_DZE) {
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        t |= float_flag_divbyzero;
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    }
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    if (val & FPCR_OVF) {
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        t |= float_flag_overflow;
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    }
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    if (val & FPCR_UNF) {
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        t |= float_flag_underflow;
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    }
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    if (val & FPCR_INE) {
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        t |= float_flag_inexact;
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    }
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    env->fpcr_exc_status = t;
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    t = 0;
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    if (val & FPCR_INVD) {
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        t |= float_flag_invalid;
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    }
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    if (val & FPCR_DZED) {
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        t |= float_flag_divbyzero;
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    }
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    if (val & FPCR_OVFD) {
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        t |= float_flag_overflow;
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    }
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    if (val & FPCR_UNFD) {
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        t |= float_flag_underflow;
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    }
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    if (val & FPCR_INED) {
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        t |= float_flag_inexact;
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    }
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    env->fpcr_exc_mask = t;
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    switch (val & FPCR_DYN_MASK) {
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    case FPCR_DYN_CHOPPED:
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        t = float_round_to_zero;
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        break;
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    case FPCR_DYN_MINUS:
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        t = float_round_down;
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        break;
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    case FPCR_DYN_NORMAL:
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        t = float_round_nearest_even;
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        break;
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    case FPCR_DYN_PLUS:
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        t = float_round_up;
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        break;
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    }
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    env->fpcr_dyn_round = t;
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    env->fpcr_flush_to_zero
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      = (val & (FPCR_UNDZ|FPCR_UNFD)) == (FPCR_UNDZ|FPCR_UNFD);
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    env->fpcr_dnz = (val & FPCR_DNZ) != 0;
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    env->fpcr_dnod = (val & FPCR_DNOD) != 0;
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    env->fpcr_undz = (val & FPCR_UNDZ) != 0;
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}
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#if defined(CONFIG_USER_ONLY)
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int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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                                int mmu_idx, int is_softmmu)
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{
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    env->exception_index = EXCP_MMFAULT;
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    env->trap_arg0 = address;
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    return 1;
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}
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void do_interrupt (CPUState *env)
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{
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    env->exception_index = -1;
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}
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#else
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target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
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{
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    return -1;
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}
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int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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                                int mmu_idx, int is_softmmu)
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{
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    return 0;
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}
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void do_interrupt (CPUState *env)
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{
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    abort();
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}
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#endif
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void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
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                     int flags)
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{
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    static const char *linux_reg_names[] = {
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        "v0 ", "t0 ", "t1 ", "t2 ", "t3 ", "t4 ", "t5 ", "t6 ",
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        "t7 ", "s0 ", "s1 ", "s2 ", "s3 ", "s4 ", "s5 ", "fp ",
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        "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ",
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        "t10", "t11", "ra ", "t12", "at ", "gp ", "sp ", "zero",
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    };
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    int i;
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    cpu_fprintf(f, "     PC  " TARGET_FMT_lx "      PS  %02x\n",
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                env->pc, env->ps);
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    for (i = 0; i < 31; i++) {
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        cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i,
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                    linux_reg_names[i], env->ir[i]);
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        if ((i % 3) == 2)
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            cpu_fprintf(f, "\n");
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    }
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    cpu_fprintf(f, "lock_a   " TARGET_FMT_lx " lock_v   " TARGET_FMT_lx "\n",
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                env->lock_addr, env->lock_value);
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    for (i = 0; i < 31; i++) {
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        cpu_fprintf(f, "FIR%02d    " TARGET_FMT_lx " ", i,
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                    *((uint64_t *)(&env->fir[i])));
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        if ((i % 3) == 2)
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            cpu_fprintf(f, "\n");
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    }
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    cpu_fprintf(f, "\n");
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}