root / target-sparc / op_helper.c @ 09487205
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1 | e8af50a3 | bellard | #include "exec.h" |
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2 | eed152bb | blueswir1 | #include "host-utils.h" |
3 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
4 | e8af50a3 | bellard | |
5 | e80cfcfc | bellard | //#define DEBUG_MMU
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6 | 952a328f | blueswir1 | //#define DEBUG_MXCC
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7 | 94554550 | blueswir1 | //#define DEBUG_UNALIGNED
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8 | 6c36d3fa | blueswir1 | //#define DEBUG_UNASSIGNED
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9 | 8543e2cf | blueswir1 | //#define DEBUG_ASI
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10 | d81fd722 | blueswir1 | //#define DEBUG_PCALL
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11 | 7e8695ed | Igor V. Kovalenko | //#define DEBUG_PSTATE
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12 | e80cfcfc | bellard | |
13 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
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14 | 001faf32 | Blue Swirl | #define DPRINTF_MMU(fmt, ...) \
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15 | 001faf32 | Blue Swirl | do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) |
16 | 952a328f | blueswir1 | #else
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17 | 001faf32 | Blue Swirl | #define DPRINTF_MMU(fmt, ...) do {} while (0) |
18 | 952a328f | blueswir1 | #endif
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19 | 952a328f | blueswir1 | |
20 | 952a328f | blueswir1 | #ifdef DEBUG_MXCC
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21 | 001faf32 | Blue Swirl | #define DPRINTF_MXCC(fmt, ...) \
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22 | 001faf32 | Blue Swirl | do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) |
23 | 952a328f | blueswir1 | #else
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24 | 001faf32 | Blue Swirl | #define DPRINTF_MXCC(fmt, ...) do {} while (0) |
25 | 952a328f | blueswir1 | #endif
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26 | 952a328f | blueswir1 | |
27 | 8543e2cf | blueswir1 | #ifdef DEBUG_ASI
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28 | 001faf32 | Blue Swirl | #define DPRINTF_ASI(fmt, ...) \
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29 | 001faf32 | Blue Swirl | do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) |
30 | 8543e2cf | blueswir1 | #endif
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31 | 8543e2cf | blueswir1 | |
32 | 7e8695ed | Igor V. Kovalenko | #ifdef DEBUG_PSTATE
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33 | 7e8695ed | Igor V. Kovalenko | #define DPRINTF_PSTATE(fmt, ...) \
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34 | 7e8695ed | Igor V. Kovalenko | do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0) |
35 | 7e8695ed | Igor V. Kovalenko | #else
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36 | 7e8695ed | Igor V. Kovalenko | #define DPRINTF_PSTATE(fmt, ...) do {} while (0) |
37 | 7e8695ed | Igor V. Kovalenko | #endif
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38 | 7e8695ed | Igor V. Kovalenko | |
39 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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40 | 2cade6a3 | blueswir1 | #ifndef TARGET_ABI32
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41 | 2cade6a3 | blueswir1 | #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
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42 | c2bc0e38 | blueswir1 | #else
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43 | 2cade6a3 | blueswir1 | #define AM_CHECK(env1) (1) |
44 | 2cade6a3 | blueswir1 | #endif
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45 | c2bc0e38 | blueswir1 | #endif
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46 | c2bc0e38 | blueswir1 | |
47 | 21ffd181 | Blue Swirl | #define DT0 (env->dt0)
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48 | 21ffd181 | Blue Swirl | #define DT1 (env->dt1)
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49 | 21ffd181 | Blue Swirl | #define QT0 (env->qt0)
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50 | 21ffd181 | Blue Swirl | #define QT1 (env->qt1)
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51 | 21ffd181 | Blue Swirl | |
52 | 3c7b48b7 | Paul Brook | #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
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53 | 3c7b48b7 | Paul Brook | static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, |
54 | 3c7b48b7 | Paul Brook | int is_asi, int size); |
55 | 3c7b48b7 | Paul Brook | #endif
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56 | 3c7b48b7 | Paul Brook | |
57 | 9c22a623 | Blue Swirl | #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
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58 | 697a77e6 | Igor Kovalenko | // Calculates TSB pointer value for fault page size 8k or 64k
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59 | 697a77e6 | Igor Kovalenko | static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
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60 | 697a77e6 | Igor Kovalenko | uint64_t tag_access_register, |
61 | 697a77e6 | Igor Kovalenko | int page_size)
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62 | 697a77e6 | Igor Kovalenko | { |
63 | 697a77e6 | Igor Kovalenko | uint64_t tsb_base = tsb_register & ~0x1fffULL;
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64 | 6e8e7d4c | Igor Kovalenko | int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; |
65 | 6e8e7d4c | Igor Kovalenko | int tsb_size = tsb_register & 0xf; |
66 | 697a77e6 | Igor Kovalenko | |
67 | 697a77e6 | Igor Kovalenko | // discard lower 13 bits which hold tag access context
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68 | 697a77e6 | Igor Kovalenko | uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
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69 | 697a77e6 | Igor Kovalenko | |
70 | 697a77e6 | Igor Kovalenko | // now reorder bits
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71 | 697a77e6 | Igor Kovalenko | uint64_t tsb_base_mask = ~0x1fffULL;
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72 | 697a77e6 | Igor Kovalenko | uint64_t va = tag_access_va; |
73 | 697a77e6 | Igor Kovalenko | |
74 | 697a77e6 | Igor Kovalenko | // move va bits to correct position
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75 | 697a77e6 | Igor Kovalenko | if (page_size == 8*1024) { |
76 | 697a77e6 | Igor Kovalenko | va >>= 9;
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77 | 697a77e6 | Igor Kovalenko | } else if (page_size == 64*1024) { |
78 | 697a77e6 | Igor Kovalenko | va >>= 12;
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79 | 697a77e6 | Igor Kovalenko | } |
80 | 697a77e6 | Igor Kovalenko | |
81 | 697a77e6 | Igor Kovalenko | if (tsb_size) {
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82 | 697a77e6 | Igor Kovalenko | tsb_base_mask <<= tsb_size; |
83 | 697a77e6 | Igor Kovalenko | } |
84 | 697a77e6 | Igor Kovalenko | |
85 | 697a77e6 | Igor Kovalenko | // calculate tsb_base mask and adjust va if split is in use
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86 | 697a77e6 | Igor Kovalenko | if (tsb_split) {
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87 | 697a77e6 | Igor Kovalenko | if (page_size == 8*1024) { |
88 | 697a77e6 | Igor Kovalenko | va &= ~(1ULL << (13 + tsb_size)); |
89 | 697a77e6 | Igor Kovalenko | } else if (page_size == 64*1024) { |
90 | 697a77e6 | Igor Kovalenko | va |= (1ULL << (13 + tsb_size)); |
91 | 697a77e6 | Igor Kovalenko | } |
92 | 697a77e6 | Igor Kovalenko | tsb_base_mask <<= 1;
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93 | 697a77e6 | Igor Kovalenko | } |
94 | 697a77e6 | Igor Kovalenko | |
95 | 697a77e6 | Igor Kovalenko | return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; |
96 | 697a77e6 | Igor Kovalenko | } |
97 | 697a77e6 | Igor Kovalenko | |
98 | 697a77e6 | Igor Kovalenko | // Calculates tag target register value by reordering bits
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99 | 697a77e6 | Igor Kovalenko | // in tag access register
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100 | 697a77e6 | Igor Kovalenko | static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
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101 | 697a77e6 | Igor Kovalenko | { |
102 | 697a77e6 | Igor Kovalenko | return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); |
103 | 697a77e6 | Igor Kovalenko | } |
104 | 697a77e6 | Igor Kovalenko | |
105 | f707726e | Igor Kovalenko | static void replace_tlb_entry(SparcTLBEntry *tlb, |
106 | f707726e | Igor Kovalenko | uint64_t tlb_tag, uint64_t tlb_tte, |
107 | f707726e | Igor Kovalenko | CPUState *env1) |
108 | 6e8e7d4c | Igor Kovalenko | { |
109 | 6e8e7d4c | Igor Kovalenko | target_ulong mask, size, va, offset; |
110 | 6e8e7d4c | Igor Kovalenko | |
111 | 6e8e7d4c | Igor Kovalenko | // flush page range if translation is valid
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112 | f707726e | Igor Kovalenko | if (TTE_IS_VALID(tlb->tte)) {
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113 | 6e8e7d4c | Igor Kovalenko | |
114 | 6e8e7d4c | Igor Kovalenko | mask = 0xffffffffffffe000ULL;
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115 | 6e8e7d4c | Igor Kovalenko | mask <<= 3 * ((tlb->tte >> 61) & 3); |
116 | 6e8e7d4c | Igor Kovalenko | size = ~mask + 1;
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117 | 6e8e7d4c | Igor Kovalenko | |
118 | 6e8e7d4c | Igor Kovalenko | va = tlb->tag & mask; |
119 | 6e8e7d4c | Igor Kovalenko | |
120 | 6e8e7d4c | Igor Kovalenko | for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { |
121 | 6e8e7d4c | Igor Kovalenko | tlb_flush_page(env1, va + offset); |
122 | 6e8e7d4c | Igor Kovalenko | } |
123 | 6e8e7d4c | Igor Kovalenko | } |
124 | 6e8e7d4c | Igor Kovalenko | |
125 | 6e8e7d4c | Igor Kovalenko | tlb->tag = tlb_tag; |
126 | 6e8e7d4c | Igor Kovalenko | tlb->tte = tlb_tte; |
127 | 6e8e7d4c | Igor Kovalenko | } |
128 | 6e8e7d4c | Igor Kovalenko | |
129 | 6e8e7d4c | Igor Kovalenko | static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, |
130 | f707726e | Igor Kovalenko | const char* strmmu, CPUState *env1) |
131 | 6e8e7d4c | Igor Kovalenko | { |
132 | 6e8e7d4c | Igor Kovalenko | unsigned int i; |
133 | 6e8e7d4c | Igor Kovalenko | target_ulong mask; |
134 | 299b520c | Igor V. Kovalenko | uint64_t context; |
135 | 299b520c | Igor V. Kovalenko | |
136 | 299b520c | Igor V. Kovalenko | int is_demap_context = (demap_addr >> 6) & 1; |
137 | 299b520c | Igor V. Kovalenko | |
138 | 299b520c | Igor V. Kovalenko | // demap context
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139 | 299b520c | Igor V. Kovalenko | switch ((demap_addr >> 4) & 3) { |
140 | 299b520c | Igor V. Kovalenko | case 0: // primary |
141 | 299b520c | Igor V. Kovalenko | context = env1->dmmu.mmu_primary_context; |
142 | 299b520c | Igor V. Kovalenko | break;
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143 | 299b520c | Igor V. Kovalenko | case 1: // secondary |
144 | 299b520c | Igor V. Kovalenko | context = env1->dmmu.mmu_secondary_context; |
145 | 299b520c | Igor V. Kovalenko | break;
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146 | 299b520c | Igor V. Kovalenko | case 2: // nucleus |
147 | 299b520c | Igor V. Kovalenko | context = 0;
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148 | 299b520c | Igor V. Kovalenko | break;
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149 | 299b520c | Igor V. Kovalenko | case 3: // reserved |
150 | 299b520c | Igor V. Kovalenko | default:
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151 | 299b520c | Igor V. Kovalenko | return;
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152 | 299b520c | Igor V. Kovalenko | } |
153 | 6e8e7d4c | Igor Kovalenko | |
154 | 6e8e7d4c | Igor Kovalenko | for (i = 0; i < 64; i++) { |
155 | f707726e | Igor Kovalenko | if (TTE_IS_VALID(tlb[i].tte)) {
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156 | 6e8e7d4c | Igor Kovalenko | |
157 | 299b520c | Igor V. Kovalenko | if (is_demap_context) {
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158 | 299b520c | Igor V. Kovalenko | // will remove non-global entries matching context value
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159 | 299b520c | Igor V. Kovalenko | if (TTE_IS_GLOBAL(tlb[i].tte) ||
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160 | 299b520c | Igor V. Kovalenko | !tlb_compare_context(&tlb[i], context)) { |
161 | 299b520c | Igor V. Kovalenko | continue;
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162 | 299b520c | Igor V. Kovalenko | } |
163 | 299b520c | Igor V. Kovalenko | } else {
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164 | 299b520c | Igor V. Kovalenko | // demap page
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165 | 299b520c | Igor V. Kovalenko | // will remove any entry matching VA
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166 | 299b520c | Igor V. Kovalenko | mask = 0xffffffffffffe000ULL;
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167 | 299b520c | Igor V. Kovalenko | mask <<= 3 * ((tlb[i].tte >> 61) & 3); |
168 | 299b520c | Igor V. Kovalenko | |
169 | 299b520c | Igor V. Kovalenko | if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
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170 | 299b520c | Igor V. Kovalenko | continue;
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171 | 299b520c | Igor V. Kovalenko | } |
172 | 299b520c | Igor V. Kovalenko | |
173 | 299b520c | Igor V. Kovalenko | // entry should be global or matching context value
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174 | 299b520c | Igor V. Kovalenko | if (!TTE_IS_GLOBAL(tlb[i].tte) &&
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175 | 299b520c | Igor V. Kovalenko | !tlb_compare_context(&tlb[i], context)) { |
176 | 299b520c | Igor V. Kovalenko | continue;
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177 | 299b520c | Igor V. Kovalenko | } |
178 | 299b520c | Igor V. Kovalenko | } |
179 | 6e8e7d4c | Igor Kovalenko | |
180 | 299b520c | Igor V. Kovalenko | replace_tlb_entry(&tlb[i], 0, 0, env1); |
181 | 6e8e7d4c | Igor Kovalenko | #ifdef DEBUG_MMU
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182 | 299b520c | Igor V. Kovalenko | DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
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183 | 299b520c | Igor V. Kovalenko | dump_mmu(env1); |
184 | 6e8e7d4c | Igor Kovalenko | #endif
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185 | 6e8e7d4c | Igor Kovalenko | } |
186 | 6e8e7d4c | Igor Kovalenko | } |
187 | 6e8e7d4c | Igor Kovalenko | } |
188 | 6e8e7d4c | Igor Kovalenko | |
189 | f707726e | Igor Kovalenko | static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, |
190 | f707726e | Igor Kovalenko | uint64_t tlb_tag, uint64_t tlb_tte, |
191 | f707726e | Igor Kovalenko | const char* strmmu, CPUState *env1) |
192 | f707726e | Igor Kovalenko | { |
193 | f707726e | Igor Kovalenko | unsigned int i, replace_used; |
194 | f707726e | Igor Kovalenko | |
195 | f707726e | Igor Kovalenko | // Try replacing invalid entry
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196 | f707726e | Igor Kovalenko | for (i = 0; i < 64; i++) { |
197 | f707726e | Igor Kovalenko | if (!TTE_IS_VALID(tlb[i].tte)) {
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198 | f707726e | Igor Kovalenko | replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); |
199 | f707726e | Igor Kovalenko | #ifdef DEBUG_MMU
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200 | f707726e | Igor Kovalenko | DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
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201 | f707726e | Igor Kovalenko | dump_mmu(env1); |
202 | f707726e | Igor Kovalenko | #endif
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203 | f707726e | Igor Kovalenko | return;
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204 | f707726e | Igor Kovalenko | } |
205 | f707726e | Igor Kovalenko | } |
206 | f707726e | Igor Kovalenko | |
207 | f707726e | Igor Kovalenko | // All entries are valid, try replacing unlocked entry
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208 | f707726e | Igor Kovalenko | |
209 | f707726e | Igor Kovalenko | for (replace_used = 0; replace_used < 2; ++replace_used) { |
210 | f707726e | Igor Kovalenko | |
211 | f707726e | Igor Kovalenko | // Used entries are not replaced on first pass
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212 | f707726e | Igor Kovalenko | |
213 | f707726e | Igor Kovalenko | for (i = 0; i < 64; i++) { |
214 | f707726e | Igor Kovalenko | if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
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215 | f707726e | Igor Kovalenko | |
216 | f707726e | Igor Kovalenko | replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); |
217 | f707726e | Igor Kovalenko | #ifdef DEBUG_MMU
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218 | f707726e | Igor Kovalenko | DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
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219 | f707726e | Igor Kovalenko | strmmu, (replace_used?"used":"unused"), i); |
220 | f707726e | Igor Kovalenko | dump_mmu(env1); |
221 | f707726e | Igor Kovalenko | #endif
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222 | f707726e | Igor Kovalenko | return;
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223 | f707726e | Igor Kovalenko | } |
224 | f707726e | Igor Kovalenko | } |
225 | f707726e | Igor Kovalenko | |
226 | f707726e | Igor Kovalenko | // Now reset used bit and search for unused entries again
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227 | f707726e | Igor Kovalenko | |
228 | f707726e | Igor Kovalenko | for (i = 0; i < 64; i++) { |
229 | f707726e | Igor Kovalenko | TTE_SET_UNUSED(tlb[i].tte); |
230 | f707726e | Igor Kovalenko | } |
231 | f707726e | Igor Kovalenko | } |
232 | f707726e | Igor Kovalenko | |
233 | f707726e | Igor Kovalenko | #ifdef DEBUG_MMU
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234 | f707726e | Igor Kovalenko | DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
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235 | f707726e | Igor Kovalenko | #endif
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236 | f707726e | Igor Kovalenko | // error state?
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237 | f707726e | Igor Kovalenko | } |
238 | f707726e | Igor Kovalenko | |
239 | 697a77e6 | Igor Kovalenko | #endif
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240 | 697a77e6 | Igor Kovalenko | |
241 | 41db525e | Richard Henderson | static inline target_ulong address_mask(CPUState *env1, target_ulong addr) |
242 | 2cade6a3 | blueswir1 | { |
243 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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244 | 2cade6a3 | blueswir1 | if (AM_CHECK(env1))
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245 | 41db525e | Richard Henderson | addr &= 0xffffffffULL;
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246 | 2cade6a3 | blueswir1 | #endif
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247 | 41db525e | Richard Henderson | return addr;
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248 | 2cade6a3 | blueswir1 | } |
249 | 2cade6a3 | blueswir1 | |
250 | 1295001c | Igor V. Kovalenko | /* returns true if access using this ASI is to have address translated by MMU
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251 | 1295001c | Igor V. Kovalenko | otherwise access is to raw physical address */
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252 | 1295001c | Igor V. Kovalenko | static inline int is_translating_asi(int asi) |
253 | 1295001c | Igor V. Kovalenko | { |
254 | 1295001c | Igor V. Kovalenko | #ifdef TARGET_SPARC64
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255 | 1295001c | Igor V. Kovalenko | /* Ultrasparc IIi translating asi
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256 | 1295001c | Igor V. Kovalenko | - note this list is defined by cpu implementation
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257 | 1295001c | Igor V. Kovalenko | */
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258 | 1295001c | Igor V. Kovalenko | switch (asi) {
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259 | 1295001c | Igor V. Kovalenko | case 0x04 ... 0x11: |
260 | 1295001c | Igor V. Kovalenko | case 0x18 ... 0x19: |
261 | 1295001c | Igor V. Kovalenko | case 0x24 ... 0x2C: |
262 | 1295001c | Igor V. Kovalenko | case 0x70 ... 0x73: |
263 | 1295001c | Igor V. Kovalenko | case 0x78 ... 0x79: |
264 | 1295001c | Igor V. Kovalenko | case 0x80 ... 0xFF: |
265 | 1295001c | Igor V. Kovalenko | return 1; |
266 | 1295001c | Igor V. Kovalenko | |
267 | 1295001c | Igor V. Kovalenko | default:
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268 | 1295001c | Igor V. Kovalenko | return 0; |
269 | 1295001c | Igor V. Kovalenko | } |
270 | 1295001c | Igor V. Kovalenko | #else
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271 | 1295001c | Igor V. Kovalenko | /* TODO: check sparc32 bits */
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272 | 1295001c | Igor V. Kovalenko | return 0; |
273 | 1295001c | Igor V. Kovalenko | #endif
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274 | 1295001c | Igor V. Kovalenko | } |
275 | 1295001c | Igor V. Kovalenko | |
276 | 1295001c | Igor V. Kovalenko | static inline target_ulong asi_address_mask(CPUState *env1, |
277 | 1295001c | Igor V. Kovalenko | int asi, target_ulong addr)
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278 | 1295001c | Igor V. Kovalenko | { |
279 | 1295001c | Igor V. Kovalenko | if (is_translating_asi(asi)) {
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280 | 1295001c | Igor V. Kovalenko | return address_mask(env, addr);
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281 | 1295001c | Igor V. Kovalenko | } else {
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282 | 1295001c | Igor V. Kovalenko | return addr;
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283 | 1295001c | Igor V. Kovalenko | } |
284 | 1295001c | Igor V. Kovalenko | } |
285 | 1295001c | Igor V. Kovalenko | |
286 | f4a5a5ba | blueswir1 | static void raise_exception(int tt) |
287 | 9d893301 | bellard | { |
288 | 9d893301 | bellard | env->exception_index = tt; |
289 | 9d893301 | bellard | cpu_loop_exit(); |
290 | 3b46e624 | ths | } |
291 | 9d893301 | bellard | |
292 | a7812ae4 | pbrook | void HELPER(raise_exception)(int tt) |
293 | a7812ae4 | pbrook | { |
294 | a7812ae4 | pbrook | raise_exception(tt); |
295 | a7812ae4 | pbrook | } |
296 | a7812ae4 | pbrook | |
297 | 2b29924f | blueswir1 | void helper_check_align(target_ulong addr, uint32_t align)
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298 | 2b29924f | blueswir1 | { |
299 | c2bc0e38 | blueswir1 | if (addr & align) {
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300 | c2bc0e38 | blueswir1 | #ifdef DEBUG_UNALIGNED
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301 | c2bc0e38 | blueswir1 | printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx |
302 | c2bc0e38 | blueswir1 | "\n", addr, env->pc);
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303 | c2bc0e38 | blueswir1 | #endif
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304 | 2b29924f | blueswir1 | raise_exception(TT_UNALIGNED); |
305 | c2bc0e38 | blueswir1 | } |
306 | 2b29924f | blueswir1 | } |
307 | 2b29924f | blueswir1 | |
308 | 44e7757c | blueswir1 | #define F_HELPER(name, p) void helper_f##name##p(void) |
309 | 44e7757c | blueswir1 | |
310 | 44e7757c | blueswir1 | #define F_BINOP(name) \
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311 | 714547bb | blueswir1 | float32 helper_f ## name ## s (float32 src1, float32 src2) \ |
312 | 44e7757c | blueswir1 | { \ |
313 | 714547bb | blueswir1 | return float32_ ## name (src1, src2, &env->fp_status); \ |
314 | 44e7757c | blueswir1 | } \ |
315 | 44e7757c | blueswir1 | F_HELPER(name, d) \ |
316 | 44e7757c | blueswir1 | { \ |
317 | 44e7757c | blueswir1 | DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \ |
318 | 4e14008f | blueswir1 | } \ |
319 | 4e14008f | blueswir1 | F_HELPER(name, q) \ |
320 | 4e14008f | blueswir1 | { \ |
321 | 4e14008f | blueswir1 | QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \ |
322 | 44e7757c | blueswir1 | } |
323 | 44e7757c | blueswir1 | |
324 | 44e7757c | blueswir1 | F_BINOP(add); |
325 | 44e7757c | blueswir1 | F_BINOP(sub); |
326 | 44e7757c | blueswir1 | F_BINOP(mul); |
327 | 44e7757c | blueswir1 | F_BINOP(div); |
328 | 44e7757c | blueswir1 | #undef F_BINOP
|
329 | 44e7757c | blueswir1 | |
330 | d84763bc | blueswir1 | void helper_fsmuld(float32 src1, float32 src2)
|
331 | 1a2fb1c0 | blueswir1 | { |
332 | d84763bc | blueswir1 | DT0 = float64_mul(float32_to_float64(src1, &env->fp_status), |
333 | d84763bc | blueswir1 | float32_to_float64(src2, &env->fp_status), |
334 | 44e7757c | blueswir1 | &env->fp_status); |
335 | 44e7757c | blueswir1 | } |
336 | 1a2fb1c0 | blueswir1 | |
337 | 4e14008f | blueswir1 | void helper_fdmulq(void) |
338 | 4e14008f | blueswir1 | { |
339 | 4e14008f | blueswir1 | QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status), |
340 | 4e14008f | blueswir1 | float64_to_float128(DT1, &env->fp_status), |
341 | 4e14008f | blueswir1 | &env->fp_status); |
342 | 4e14008f | blueswir1 | } |
343 | 4e14008f | blueswir1 | |
344 | 714547bb | blueswir1 | float32 helper_fnegs(float32 src) |
345 | 44e7757c | blueswir1 | { |
346 | 714547bb | blueswir1 | return float32_chs(src);
|
347 | 417454b0 | blueswir1 | } |
348 | 417454b0 | blueswir1 | |
349 | 44e7757c | blueswir1 | #ifdef TARGET_SPARC64
|
350 | 44e7757c | blueswir1 | F_HELPER(neg, d) |
351 | 7e8c2b6c | blueswir1 | { |
352 | 44e7757c | blueswir1 | DT0 = float64_chs(DT1); |
353 | 7e8c2b6c | blueswir1 | } |
354 | 4e14008f | blueswir1 | |
355 | 4e14008f | blueswir1 | F_HELPER(neg, q) |
356 | 4e14008f | blueswir1 | { |
357 | 4e14008f | blueswir1 | QT0 = float128_chs(QT1); |
358 | 4e14008f | blueswir1 | } |
359 | 4e14008f | blueswir1 | #endif
|
360 | 44e7757c | blueswir1 | |
361 | 44e7757c | blueswir1 | /* Integer to float conversion. */
|
362 | 714547bb | blueswir1 | float32 helper_fitos(int32_t src) |
363 | a0c4cb4a | bellard | { |
364 | 714547bb | blueswir1 | return int32_to_float32(src, &env->fp_status);
|
365 | a0c4cb4a | bellard | } |
366 | a0c4cb4a | bellard | |
367 | d84763bc | blueswir1 | void helper_fitod(int32_t src)
|
368 | a0c4cb4a | bellard | { |
369 | d84763bc | blueswir1 | DT0 = int32_to_float64(src, &env->fp_status); |
370 | a0c4cb4a | bellard | } |
371 | 9c2b428e | blueswir1 | |
372 | c5d04e99 | blueswir1 | void helper_fitoq(int32_t src)
|
373 | 4e14008f | blueswir1 | { |
374 | c5d04e99 | blueswir1 | QT0 = int32_to_float128(src, &env->fp_status); |
375 | 4e14008f | blueswir1 | } |
376 | 4e14008f | blueswir1 | |
377 | 1e64e78d | blueswir1 | #ifdef TARGET_SPARC64
|
378 | d84763bc | blueswir1 | float32 helper_fxtos(void)
|
379 | 1e64e78d | blueswir1 | { |
380 | d84763bc | blueswir1 | return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
|
381 | 1e64e78d | blueswir1 | } |
382 | 1e64e78d | blueswir1 | |
383 | 44e7757c | blueswir1 | F_HELPER(xto, d) |
384 | 1e64e78d | blueswir1 | { |
385 | 1e64e78d | blueswir1 | DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); |
386 | 1e64e78d | blueswir1 | } |
387 | 64a88d5d | blueswir1 | |
388 | 4e14008f | blueswir1 | F_HELPER(xto, q) |
389 | 4e14008f | blueswir1 | { |
390 | 4e14008f | blueswir1 | QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status); |
391 | 4e14008f | blueswir1 | } |
392 | 4e14008f | blueswir1 | #endif
|
393 | 44e7757c | blueswir1 | #undef F_HELPER
|
394 | 44e7757c | blueswir1 | |
395 | 44e7757c | blueswir1 | /* floating point conversion */
|
396 | d84763bc | blueswir1 | float32 helper_fdtos(void)
|
397 | 44e7757c | blueswir1 | { |
398 | d84763bc | blueswir1 | return float64_to_float32(DT1, &env->fp_status);
|
399 | 44e7757c | blueswir1 | } |
400 | 44e7757c | blueswir1 | |
401 | d84763bc | blueswir1 | void helper_fstod(float32 src)
|
402 | 44e7757c | blueswir1 | { |
403 | d84763bc | blueswir1 | DT0 = float32_to_float64(src, &env->fp_status); |
404 | 44e7757c | blueswir1 | } |
405 | 9c2b428e | blueswir1 | |
406 | c5d04e99 | blueswir1 | float32 helper_fqtos(void)
|
407 | 4e14008f | blueswir1 | { |
408 | c5d04e99 | blueswir1 | return float128_to_float32(QT1, &env->fp_status);
|
409 | 4e14008f | blueswir1 | } |
410 | 4e14008f | blueswir1 | |
411 | c5d04e99 | blueswir1 | void helper_fstoq(float32 src)
|
412 | 4e14008f | blueswir1 | { |
413 | c5d04e99 | blueswir1 | QT0 = float32_to_float128(src, &env->fp_status); |
414 | 4e14008f | blueswir1 | } |
415 | 4e14008f | blueswir1 | |
416 | 4e14008f | blueswir1 | void helper_fqtod(void) |
417 | 4e14008f | blueswir1 | { |
418 | 4e14008f | blueswir1 | DT0 = float128_to_float64(QT1, &env->fp_status); |
419 | 4e14008f | blueswir1 | } |
420 | 4e14008f | blueswir1 | |
421 | 4e14008f | blueswir1 | void helper_fdtoq(void) |
422 | 4e14008f | blueswir1 | { |
423 | 4e14008f | blueswir1 | QT0 = float64_to_float128(DT1, &env->fp_status); |
424 | 4e14008f | blueswir1 | } |
425 | 4e14008f | blueswir1 | |
426 | 44e7757c | blueswir1 | /* Float to integer conversion. */
|
427 | 714547bb | blueswir1 | int32_t helper_fstoi(float32 src) |
428 | 44e7757c | blueswir1 | { |
429 | 714547bb | blueswir1 | return float32_to_int32_round_to_zero(src, &env->fp_status);
|
430 | 44e7757c | blueswir1 | } |
431 | 44e7757c | blueswir1 | |
432 | d84763bc | blueswir1 | int32_t helper_fdtoi(void)
|
433 | 44e7757c | blueswir1 | { |
434 | d84763bc | blueswir1 | return float64_to_int32_round_to_zero(DT1, &env->fp_status);
|
435 | 44e7757c | blueswir1 | } |
436 | 44e7757c | blueswir1 | |
437 | c5d04e99 | blueswir1 | int32_t helper_fqtoi(void)
|
438 | 4e14008f | blueswir1 | { |
439 | c5d04e99 | blueswir1 | return float128_to_int32_round_to_zero(QT1, &env->fp_status);
|
440 | 4e14008f | blueswir1 | } |
441 | 4e14008f | blueswir1 | |
442 | 44e7757c | blueswir1 | #ifdef TARGET_SPARC64
|
443 | d84763bc | blueswir1 | void helper_fstox(float32 src)
|
444 | 44e7757c | blueswir1 | { |
445 | d84763bc | blueswir1 | *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status); |
446 | 44e7757c | blueswir1 | } |
447 | 44e7757c | blueswir1 | |
448 | 44e7757c | blueswir1 | void helper_fdtox(void) |
449 | 44e7757c | blueswir1 | { |
450 | 44e7757c | blueswir1 | *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status); |
451 | 44e7757c | blueswir1 | } |
452 | 44e7757c | blueswir1 | |
453 | 4e14008f | blueswir1 | void helper_fqtox(void) |
454 | 4e14008f | blueswir1 | { |
455 | 4e14008f | blueswir1 | *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status); |
456 | 4e14008f | blueswir1 | } |
457 | 4e14008f | blueswir1 | |
458 | 44e7757c | blueswir1 | void helper_faligndata(void) |
459 | 44e7757c | blueswir1 | { |
460 | 44e7757c | blueswir1 | uint64_t tmp; |
461 | 44e7757c | blueswir1 | |
462 | 44e7757c | blueswir1 | tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8); |
463 | 06057e6f | blueswir1 | /* on many architectures a shift of 64 does nothing */
|
464 | 06057e6f | blueswir1 | if ((env->gsr & 7) != 0) { |
465 | 06057e6f | blueswir1 | tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8); |
466 | 06057e6f | blueswir1 | } |
467 | 44e7757c | blueswir1 | *((uint64_t *)&DT0) = tmp; |
468 | 44e7757c | blueswir1 | } |
469 | 44e7757c | blueswir1 | |
470 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
|
471 | 44e7757c | blueswir1 | #define VIS_B64(n) b[7 - (n)] |
472 | 44e7757c | blueswir1 | #define VIS_W64(n) w[3 - (n)] |
473 | 44e7757c | blueswir1 | #define VIS_SW64(n) sw[3 - (n)] |
474 | 44e7757c | blueswir1 | #define VIS_L64(n) l[1 - (n)] |
475 | 44e7757c | blueswir1 | #define VIS_B32(n) b[3 - (n)] |
476 | 44e7757c | blueswir1 | #define VIS_W32(n) w[1 - (n)] |
477 | 44e7757c | blueswir1 | #else
|
478 | 44e7757c | blueswir1 | #define VIS_B64(n) b[n]
|
479 | 44e7757c | blueswir1 | #define VIS_W64(n) w[n]
|
480 | 44e7757c | blueswir1 | #define VIS_SW64(n) sw[n]
|
481 | 44e7757c | blueswir1 | #define VIS_L64(n) l[n]
|
482 | 44e7757c | blueswir1 | #define VIS_B32(n) b[n]
|
483 | 44e7757c | blueswir1 | #define VIS_W32(n) w[n]
|
484 | 44e7757c | blueswir1 | #endif
|
485 | 44e7757c | blueswir1 | |
486 | 44e7757c | blueswir1 | typedef union { |
487 | 44e7757c | blueswir1 | uint8_t b[8];
|
488 | 44e7757c | blueswir1 | uint16_t w[4];
|
489 | 44e7757c | blueswir1 | int16_t sw[4];
|
490 | 44e7757c | blueswir1 | uint32_t l[2];
|
491 | 44e7757c | blueswir1 | float64 d; |
492 | 44e7757c | blueswir1 | } vis64; |
493 | 44e7757c | blueswir1 | |
494 | 44e7757c | blueswir1 | typedef union { |
495 | 44e7757c | blueswir1 | uint8_t b[4];
|
496 | 44e7757c | blueswir1 | uint16_t w[2];
|
497 | 44e7757c | blueswir1 | uint32_t l; |
498 | 44e7757c | blueswir1 | float32 f; |
499 | 44e7757c | blueswir1 | } vis32; |
500 | 44e7757c | blueswir1 | |
501 | 44e7757c | blueswir1 | void helper_fpmerge(void) |
502 | 44e7757c | blueswir1 | { |
503 | 44e7757c | blueswir1 | vis64 s, d; |
504 | 44e7757c | blueswir1 | |
505 | 44e7757c | blueswir1 | s.d = DT0; |
506 | 44e7757c | blueswir1 | d.d = DT1; |
507 | 44e7757c | blueswir1 | |
508 | 44e7757c | blueswir1 | // Reverse calculation order to handle overlap
|
509 | 44e7757c | blueswir1 | d.VIS_B64(7) = s.VIS_B64(3); |
510 | 44e7757c | blueswir1 | d.VIS_B64(6) = d.VIS_B64(3); |
511 | 44e7757c | blueswir1 | d.VIS_B64(5) = s.VIS_B64(2); |
512 | 44e7757c | blueswir1 | d.VIS_B64(4) = d.VIS_B64(2); |
513 | 44e7757c | blueswir1 | d.VIS_B64(3) = s.VIS_B64(1); |
514 | 44e7757c | blueswir1 | d.VIS_B64(2) = d.VIS_B64(1); |
515 | 44e7757c | blueswir1 | d.VIS_B64(1) = s.VIS_B64(0); |
516 | 44e7757c | blueswir1 | //d.VIS_B64(0) = d.VIS_B64(0);
|
517 | 44e7757c | blueswir1 | |
518 | 44e7757c | blueswir1 | DT0 = d.d; |
519 | 44e7757c | blueswir1 | } |
520 | 44e7757c | blueswir1 | |
521 | 44e7757c | blueswir1 | void helper_fmul8x16(void) |
522 | 44e7757c | blueswir1 | { |
523 | 44e7757c | blueswir1 | vis64 s, d; |
524 | 44e7757c | blueswir1 | uint32_t tmp; |
525 | 44e7757c | blueswir1 | |
526 | 44e7757c | blueswir1 | s.d = DT0; |
527 | 44e7757c | blueswir1 | d.d = DT1; |
528 | 44e7757c | blueswir1 | |
529 | 44e7757c | blueswir1 | #define PMUL(r) \
|
530 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \ |
531 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
532 | 44e7757c | blueswir1 | tmp += 0x100; \
|
533 | 44e7757c | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
534 | 44e7757c | blueswir1 | |
535 | 44e7757c | blueswir1 | PMUL(0);
|
536 | 44e7757c | blueswir1 | PMUL(1);
|
537 | 44e7757c | blueswir1 | PMUL(2);
|
538 | 44e7757c | blueswir1 | PMUL(3);
|
539 | 44e7757c | blueswir1 | #undef PMUL
|
540 | 44e7757c | blueswir1 | |
541 | 44e7757c | blueswir1 | DT0 = d.d; |
542 | 44e7757c | blueswir1 | } |
543 | 44e7757c | blueswir1 | |
544 | 44e7757c | blueswir1 | void helper_fmul8x16al(void) |
545 | 44e7757c | blueswir1 | { |
546 | 44e7757c | blueswir1 | vis64 s, d; |
547 | 44e7757c | blueswir1 | uint32_t tmp; |
548 | 44e7757c | blueswir1 | |
549 | 44e7757c | blueswir1 | s.d = DT0; |
550 | 44e7757c | blueswir1 | d.d = DT1; |
551 | 44e7757c | blueswir1 | |
552 | 44e7757c | blueswir1 | #define PMUL(r) \
|
553 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
|
554 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
555 | 44e7757c | blueswir1 | tmp += 0x100; \
|
556 | 44e7757c | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
557 | 44e7757c | blueswir1 | |
558 | 44e7757c | blueswir1 | PMUL(0);
|
559 | 44e7757c | blueswir1 | PMUL(1);
|
560 | 44e7757c | blueswir1 | PMUL(2);
|
561 | 44e7757c | blueswir1 | PMUL(3);
|
562 | 44e7757c | blueswir1 | #undef PMUL
|
563 | 44e7757c | blueswir1 | |
564 | 44e7757c | blueswir1 | DT0 = d.d; |
565 | 44e7757c | blueswir1 | } |
566 | 44e7757c | blueswir1 | |
567 | 44e7757c | blueswir1 | void helper_fmul8x16au(void) |
568 | 44e7757c | blueswir1 | { |
569 | 44e7757c | blueswir1 | vis64 s, d; |
570 | 44e7757c | blueswir1 | uint32_t tmp; |
571 | 44e7757c | blueswir1 | |
572 | 44e7757c | blueswir1 | s.d = DT0; |
573 | 44e7757c | blueswir1 | d.d = DT1; |
574 | 44e7757c | blueswir1 | |
575 | 44e7757c | blueswir1 | #define PMUL(r) \
|
576 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
|
577 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
578 | 44e7757c | blueswir1 | tmp += 0x100; \
|
579 | 44e7757c | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
580 | 44e7757c | blueswir1 | |
581 | 44e7757c | blueswir1 | PMUL(0);
|
582 | 44e7757c | blueswir1 | PMUL(1);
|
583 | 44e7757c | blueswir1 | PMUL(2);
|
584 | 44e7757c | blueswir1 | PMUL(3);
|
585 | 44e7757c | blueswir1 | #undef PMUL
|
586 | 44e7757c | blueswir1 | |
587 | 44e7757c | blueswir1 | DT0 = d.d; |
588 | 44e7757c | blueswir1 | } |
589 | 44e7757c | blueswir1 | |
590 | 44e7757c | blueswir1 | void helper_fmul8sux16(void) |
591 | 44e7757c | blueswir1 | { |
592 | 44e7757c | blueswir1 | vis64 s, d; |
593 | 44e7757c | blueswir1 | uint32_t tmp; |
594 | 44e7757c | blueswir1 | |
595 | 44e7757c | blueswir1 | s.d = DT0; |
596 | 44e7757c | blueswir1 | d.d = DT1; |
597 | 44e7757c | blueswir1 | |
598 | 44e7757c | blueswir1 | #define PMUL(r) \
|
599 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
|
600 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
601 | 44e7757c | blueswir1 | tmp += 0x100; \
|
602 | 44e7757c | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
603 | 44e7757c | blueswir1 | |
604 | 44e7757c | blueswir1 | PMUL(0);
|
605 | 44e7757c | blueswir1 | PMUL(1);
|
606 | 44e7757c | blueswir1 | PMUL(2);
|
607 | 44e7757c | blueswir1 | PMUL(3);
|
608 | 44e7757c | blueswir1 | #undef PMUL
|
609 | 44e7757c | blueswir1 | |
610 | 44e7757c | blueswir1 | DT0 = d.d; |
611 | 44e7757c | blueswir1 | } |
612 | 44e7757c | blueswir1 | |
613 | 44e7757c | blueswir1 | void helper_fmul8ulx16(void) |
614 | 44e7757c | blueswir1 | { |
615 | 44e7757c | blueswir1 | vis64 s, d; |
616 | 44e7757c | blueswir1 | uint32_t tmp; |
617 | 44e7757c | blueswir1 | |
618 | 44e7757c | blueswir1 | s.d = DT0; |
619 | 44e7757c | blueswir1 | d.d = DT1; |
620 | 44e7757c | blueswir1 | |
621 | 44e7757c | blueswir1 | #define PMUL(r) \
|
622 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
|
623 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
624 | 44e7757c | blueswir1 | tmp += 0x100; \
|
625 | 44e7757c | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
626 | 44e7757c | blueswir1 | |
627 | 44e7757c | blueswir1 | PMUL(0);
|
628 | 44e7757c | blueswir1 | PMUL(1);
|
629 | 44e7757c | blueswir1 | PMUL(2);
|
630 | 44e7757c | blueswir1 | PMUL(3);
|
631 | 44e7757c | blueswir1 | #undef PMUL
|
632 | 44e7757c | blueswir1 | |
633 | 44e7757c | blueswir1 | DT0 = d.d; |
634 | 44e7757c | blueswir1 | } |
635 | 44e7757c | blueswir1 | |
636 | 44e7757c | blueswir1 | void helper_fmuld8sux16(void) |
637 | 44e7757c | blueswir1 | { |
638 | 44e7757c | blueswir1 | vis64 s, d; |
639 | 44e7757c | blueswir1 | uint32_t tmp; |
640 | 44e7757c | blueswir1 | |
641 | 44e7757c | blueswir1 | s.d = DT0; |
642 | 44e7757c | blueswir1 | d.d = DT1; |
643 | 44e7757c | blueswir1 | |
644 | 44e7757c | blueswir1 | #define PMUL(r) \
|
645 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
|
646 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
647 | 44e7757c | blueswir1 | tmp += 0x100; \
|
648 | 44e7757c | blueswir1 | d.VIS_L64(r) = tmp; |
649 | 44e7757c | blueswir1 | |
650 | 44e7757c | blueswir1 | // Reverse calculation order to handle overlap
|
651 | 44e7757c | blueswir1 | PMUL(1);
|
652 | 44e7757c | blueswir1 | PMUL(0);
|
653 | 44e7757c | blueswir1 | #undef PMUL
|
654 | 44e7757c | blueswir1 | |
655 | 44e7757c | blueswir1 | DT0 = d.d; |
656 | 44e7757c | blueswir1 | } |
657 | 44e7757c | blueswir1 | |
658 | 44e7757c | blueswir1 | void helper_fmuld8ulx16(void) |
659 | 44e7757c | blueswir1 | { |
660 | 44e7757c | blueswir1 | vis64 s, d; |
661 | 44e7757c | blueswir1 | uint32_t tmp; |
662 | 44e7757c | blueswir1 | |
663 | 44e7757c | blueswir1 | s.d = DT0; |
664 | 44e7757c | blueswir1 | d.d = DT1; |
665 | 44e7757c | blueswir1 | |
666 | 44e7757c | blueswir1 | #define PMUL(r) \
|
667 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
|
668 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
669 | 44e7757c | blueswir1 | tmp += 0x100; \
|
670 | 44e7757c | blueswir1 | d.VIS_L64(r) = tmp; |
671 | 44e7757c | blueswir1 | |
672 | 44e7757c | blueswir1 | // Reverse calculation order to handle overlap
|
673 | 44e7757c | blueswir1 | PMUL(1);
|
674 | 44e7757c | blueswir1 | PMUL(0);
|
675 | 44e7757c | blueswir1 | #undef PMUL
|
676 | 44e7757c | blueswir1 | |
677 | 44e7757c | blueswir1 | DT0 = d.d; |
678 | 44e7757c | blueswir1 | } |
679 | 44e7757c | blueswir1 | |
680 | 44e7757c | blueswir1 | void helper_fexpand(void) |
681 | 44e7757c | blueswir1 | { |
682 | 44e7757c | blueswir1 | vis32 s; |
683 | 44e7757c | blueswir1 | vis64 d; |
684 | 44e7757c | blueswir1 | |
685 | 44e7757c | blueswir1 | s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
|
686 | 44e7757c | blueswir1 | d.d = DT1; |
687 | c55bda30 | blueswir1 | d.VIS_W64(0) = s.VIS_B32(0) << 4; |
688 | c55bda30 | blueswir1 | d.VIS_W64(1) = s.VIS_B32(1) << 4; |
689 | c55bda30 | blueswir1 | d.VIS_W64(2) = s.VIS_B32(2) << 4; |
690 | c55bda30 | blueswir1 | d.VIS_W64(3) = s.VIS_B32(3) << 4; |
691 | 44e7757c | blueswir1 | |
692 | 44e7757c | blueswir1 | DT0 = d.d; |
693 | 44e7757c | blueswir1 | } |
694 | 44e7757c | blueswir1 | |
695 | 44e7757c | blueswir1 | #define VIS_HELPER(name, F) \
|
696 | 44e7757c | blueswir1 | void name##16(void) \ |
697 | 44e7757c | blueswir1 | { \ |
698 | 44e7757c | blueswir1 | vis64 s, d; \ |
699 | 44e7757c | blueswir1 | \ |
700 | 44e7757c | blueswir1 | s.d = DT0; \ |
701 | 44e7757c | blueswir1 | d.d = DT1; \ |
702 | 44e7757c | blueswir1 | \ |
703 | 44e7757c | blueswir1 | d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \ |
704 | 44e7757c | blueswir1 | d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \ |
705 | 44e7757c | blueswir1 | d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \ |
706 | 44e7757c | blueswir1 | d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \ |
707 | 44e7757c | blueswir1 | \ |
708 | 44e7757c | blueswir1 | DT0 = d.d; \ |
709 | 44e7757c | blueswir1 | } \ |
710 | 44e7757c | blueswir1 | \ |
711 | 1d01299d | blueswir1 | uint32_t name##16s(uint32_t src1, uint32_t src2) \ |
712 | 44e7757c | blueswir1 | { \ |
713 | 44e7757c | blueswir1 | vis32 s, d; \ |
714 | 44e7757c | blueswir1 | \ |
715 | 1d01299d | blueswir1 | s.l = src1; \ |
716 | 1d01299d | blueswir1 | d.l = src2; \ |
717 | 44e7757c | blueswir1 | \ |
718 | 44e7757c | blueswir1 | d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \ |
719 | 44e7757c | blueswir1 | d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \ |
720 | 44e7757c | blueswir1 | \ |
721 | 1d01299d | blueswir1 | return d.l; \
|
722 | 44e7757c | blueswir1 | } \ |
723 | 44e7757c | blueswir1 | \ |
724 | 44e7757c | blueswir1 | void name##32(void) \ |
725 | 44e7757c | blueswir1 | { \ |
726 | 44e7757c | blueswir1 | vis64 s, d; \ |
727 | 44e7757c | blueswir1 | \ |
728 | 44e7757c | blueswir1 | s.d = DT0; \ |
729 | 44e7757c | blueswir1 | d.d = DT1; \ |
730 | 44e7757c | blueswir1 | \ |
731 | 44e7757c | blueswir1 | d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \ |
732 | 44e7757c | blueswir1 | d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \ |
733 | 44e7757c | blueswir1 | \ |
734 | 44e7757c | blueswir1 | DT0 = d.d; \ |
735 | 44e7757c | blueswir1 | } \ |
736 | 44e7757c | blueswir1 | \ |
737 | 1d01299d | blueswir1 | uint32_t name##32s(uint32_t src1, uint32_t src2) \ |
738 | 44e7757c | blueswir1 | { \ |
739 | 44e7757c | blueswir1 | vis32 s, d; \ |
740 | 44e7757c | blueswir1 | \ |
741 | 1d01299d | blueswir1 | s.l = src1; \ |
742 | 1d01299d | blueswir1 | d.l = src2; \ |
743 | 44e7757c | blueswir1 | \ |
744 | 44e7757c | blueswir1 | d.l = F(d.l, s.l); \ |
745 | 44e7757c | blueswir1 | \ |
746 | 1d01299d | blueswir1 | return d.l; \
|
747 | 44e7757c | blueswir1 | } |
748 | 44e7757c | blueswir1 | |
749 | 44e7757c | blueswir1 | #define FADD(a, b) ((a) + (b))
|
750 | 44e7757c | blueswir1 | #define FSUB(a, b) ((a) - (b))
|
751 | 44e7757c | blueswir1 | VIS_HELPER(helper_fpadd, FADD) |
752 | 44e7757c | blueswir1 | VIS_HELPER(helper_fpsub, FSUB) |
753 | 44e7757c | blueswir1 | |
754 | 44e7757c | blueswir1 | #define VIS_CMPHELPER(name, F) \
|
755 | 44e7757c | blueswir1 | void name##16(void) \ |
756 | 44e7757c | blueswir1 | { \ |
757 | 44e7757c | blueswir1 | vis64 s, d; \ |
758 | 44e7757c | blueswir1 | \ |
759 | 44e7757c | blueswir1 | s.d = DT0; \ |
760 | 44e7757c | blueswir1 | d.d = DT1; \ |
761 | 44e7757c | blueswir1 | \ |
762 | 44e7757c | blueswir1 | d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \ |
763 | 44e7757c | blueswir1 | d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \ |
764 | 44e7757c | blueswir1 | d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \ |
765 | 44e7757c | blueswir1 | d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \ |
766 | 44e7757c | blueswir1 | \ |
767 | 44e7757c | blueswir1 | DT0 = d.d; \ |
768 | 44e7757c | blueswir1 | } \ |
769 | 44e7757c | blueswir1 | \ |
770 | 44e7757c | blueswir1 | void name##32(void) \ |
771 | 44e7757c | blueswir1 | { \ |
772 | 44e7757c | blueswir1 | vis64 s, d; \ |
773 | 44e7757c | blueswir1 | \ |
774 | 44e7757c | blueswir1 | s.d = DT0; \ |
775 | 44e7757c | blueswir1 | d.d = DT1; \ |
776 | 44e7757c | blueswir1 | \ |
777 | 44e7757c | blueswir1 | d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \ |
778 | 44e7757c | blueswir1 | d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \ |
779 | 44e7757c | blueswir1 | \ |
780 | 44e7757c | blueswir1 | DT0 = d.d; \ |
781 | 44e7757c | blueswir1 | } |
782 | 44e7757c | blueswir1 | |
783 | 44e7757c | blueswir1 | #define FCMPGT(a, b) ((a) > (b))
|
784 | 44e7757c | blueswir1 | #define FCMPEQ(a, b) ((a) == (b))
|
785 | 44e7757c | blueswir1 | #define FCMPLE(a, b) ((a) <= (b))
|
786 | 44e7757c | blueswir1 | #define FCMPNE(a, b) ((a) != (b))
|
787 | 44e7757c | blueswir1 | |
788 | 44e7757c | blueswir1 | VIS_CMPHELPER(helper_fcmpgt, FCMPGT) |
789 | 44e7757c | blueswir1 | VIS_CMPHELPER(helper_fcmpeq, FCMPEQ) |
790 | 44e7757c | blueswir1 | VIS_CMPHELPER(helper_fcmple, FCMPLE) |
791 | 44e7757c | blueswir1 | VIS_CMPHELPER(helper_fcmpne, FCMPNE) |
792 | 44e7757c | blueswir1 | #endif
|
793 | 44e7757c | blueswir1 | |
794 | 44e7757c | blueswir1 | void helper_check_ieee_exceptions(void) |
795 | 44e7757c | blueswir1 | { |
796 | 44e7757c | blueswir1 | target_ulong status; |
797 | 44e7757c | blueswir1 | |
798 | 44e7757c | blueswir1 | status = get_float_exception_flags(&env->fp_status); |
799 | 44e7757c | blueswir1 | if (status) {
|
800 | 44e7757c | blueswir1 | /* Copy IEEE 754 flags into FSR */
|
801 | 44e7757c | blueswir1 | if (status & float_flag_invalid)
|
802 | 44e7757c | blueswir1 | env->fsr |= FSR_NVC; |
803 | 44e7757c | blueswir1 | if (status & float_flag_overflow)
|
804 | 44e7757c | blueswir1 | env->fsr |= FSR_OFC; |
805 | 44e7757c | blueswir1 | if (status & float_flag_underflow)
|
806 | 44e7757c | blueswir1 | env->fsr |= FSR_UFC; |
807 | 44e7757c | blueswir1 | if (status & float_flag_divbyzero)
|
808 | 44e7757c | blueswir1 | env->fsr |= FSR_DZC; |
809 | 44e7757c | blueswir1 | if (status & float_flag_inexact)
|
810 | 44e7757c | blueswir1 | env->fsr |= FSR_NXC; |
811 | 44e7757c | blueswir1 | |
812 | 44e7757c | blueswir1 | if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) { |
813 | 44e7757c | blueswir1 | /* Unmasked exception, generate a trap */
|
814 | 44e7757c | blueswir1 | env->fsr |= FSR_FTT_IEEE_EXCP; |
815 | 44e7757c | blueswir1 | raise_exception(TT_FP_EXCP); |
816 | 44e7757c | blueswir1 | } else {
|
817 | 44e7757c | blueswir1 | /* Accumulate exceptions */
|
818 | 44e7757c | blueswir1 | env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
|
819 | 44e7757c | blueswir1 | } |
820 | 44e7757c | blueswir1 | } |
821 | 44e7757c | blueswir1 | } |
822 | 44e7757c | blueswir1 | |
823 | 44e7757c | blueswir1 | void helper_clear_float_exceptions(void) |
824 | 44e7757c | blueswir1 | { |
825 | 44e7757c | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
826 | 44e7757c | blueswir1 | } |
827 | 44e7757c | blueswir1 | |
828 | 714547bb | blueswir1 | float32 helper_fabss(float32 src) |
829 | e8af50a3 | bellard | { |
830 | 714547bb | blueswir1 | return float32_abs(src);
|
831 | e8af50a3 | bellard | } |
832 | e8af50a3 | bellard | |
833 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
834 | 7e8c2b6c | blueswir1 | void helper_fabsd(void) |
835 | 3475187d | bellard | { |
836 | 3475187d | bellard | DT0 = float64_abs(DT1); |
837 | 3475187d | bellard | } |
838 | 4e14008f | blueswir1 | |
839 | 4e14008f | blueswir1 | void helper_fabsq(void) |
840 | 4e14008f | blueswir1 | { |
841 | 4e14008f | blueswir1 | QT0 = float128_abs(QT1); |
842 | 4e14008f | blueswir1 | } |
843 | 4e14008f | blueswir1 | #endif
|
844 | 3475187d | bellard | |
845 | 714547bb | blueswir1 | float32 helper_fsqrts(float32 src) |
846 | e8af50a3 | bellard | { |
847 | 714547bb | blueswir1 | return float32_sqrt(src, &env->fp_status);
|
848 | e8af50a3 | bellard | } |
849 | e8af50a3 | bellard | |
850 | 7e8c2b6c | blueswir1 | void helper_fsqrtd(void) |
851 | e8af50a3 | bellard | { |
852 | 7a0e1f41 | bellard | DT0 = float64_sqrt(DT1, &env->fp_status); |
853 | e8af50a3 | bellard | } |
854 | e8af50a3 | bellard | |
855 | 4e14008f | blueswir1 | void helper_fsqrtq(void) |
856 | 4e14008f | blueswir1 | { |
857 | 4e14008f | blueswir1 | QT0 = float128_sqrt(QT1, &env->fp_status); |
858 | 4e14008f | blueswir1 | } |
859 | 4e14008f | blueswir1 | |
860 | 417454b0 | blueswir1 | #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
|
861 | 7e8c2b6c | blueswir1 | void glue(helper_, name) (void) \ |
862 | 65ce8c2f | bellard | { \ |
863 | 1a2fb1c0 | blueswir1 | target_ulong new_fsr; \ |
864 | 1a2fb1c0 | blueswir1 | \ |
865 | 65ce8c2f | bellard | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
866 | 65ce8c2f | bellard | switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
|
867 | 65ce8c2f | bellard | case float_relation_unordered: \
|
868 | 1a2fb1c0 | blueswir1 | new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \ |
869 | 417454b0 | blueswir1 | if ((env->fsr & FSR_NVM) || TRAP) { \
|
870 | 1a2fb1c0 | blueswir1 | env->fsr |= new_fsr; \ |
871 | 417454b0 | blueswir1 | env->fsr |= FSR_NVC; \ |
872 | 417454b0 | blueswir1 | env->fsr |= FSR_FTT_IEEE_EXCP; \ |
873 | 65ce8c2f | bellard | raise_exception(TT_FP_EXCP); \ |
874 | 65ce8c2f | bellard | } else { \
|
875 | 65ce8c2f | bellard | env->fsr |= FSR_NVA; \ |
876 | 65ce8c2f | bellard | } \ |
877 | 65ce8c2f | bellard | break; \
|
878 | 65ce8c2f | bellard | case float_relation_less: \
|
879 | 1a2fb1c0 | blueswir1 | new_fsr = FSR_FCC0 << FS; \ |
880 | 65ce8c2f | bellard | break; \
|
881 | 65ce8c2f | bellard | case float_relation_greater: \
|
882 | 1a2fb1c0 | blueswir1 | new_fsr = FSR_FCC1 << FS; \ |
883 | 65ce8c2f | bellard | break; \
|
884 | 65ce8c2f | bellard | default: \
|
885 | 1a2fb1c0 | blueswir1 | new_fsr = 0; \
|
886 | 65ce8c2f | bellard | break; \
|
887 | 65ce8c2f | bellard | } \ |
888 | 1a2fb1c0 | blueswir1 | env->fsr |= new_fsr; \ |
889 | e8af50a3 | bellard | } |
890 | 714547bb | blueswir1 | #define GEN_FCMPS(name, size, FS, TRAP) \
|
891 | 714547bb | blueswir1 | void glue(helper_, name)(float32 src1, float32 src2) \
|
892 | 714547bb | blueswir1 | { \ |
893 | 714547bb | blueswir1 | target_ulong new_fsr; \ |
894 | 714547bb | blueswir1 | \ |
895 | 714547bb | blueswir1 | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
896 | 714547bb | blueswir1 | switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
|
897 | 714547bb | blueswir1 | case float_relation_unordered: \
|
898 | 714547bb | blueswir1 | new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \ |
899 | 714547bb | blueswir1 | if ((env->fsr & FSR_NVM) || TRAP) { \
|
900 | 714547bb | blueswir1 | env->fsr |= new_fsr; \ |
901 | 714547bb | blueswir1 | env->fsr |= FSR_NVC; \ |
902 | 714547bb | blueswir1 | env->fsr |= FSR_FTT_IEEE_EXCP; \ |
903 | 714547bb | blueswir1 | raise_exception(TT_FP_EXCP); \ |
904 | 714547bb | blueswir1 | } else { \
|
905 | 714547bb | blueswir1 | env->fsr |= FSR_NVA; \ |
906 | 714547bb | blueswir1 | } \ |
907 | 714547bb | blueswir1 | break; \
|
908 | 714547bb | blueswir1 | case float_relation_less: \
|
909 | 714547bb | blueswir1 | new_fsr = FSR_FCC0 << FS; \ |
910 | 714547bb | blueswir1 | break; \
|
911 | 714547bb | blueswir1 | case float_relation_greater: \
|
912 | 714547bb | blueswir1 | new_fsr = FSR_FCC1 << FS; \ |
913 | 714547bb | blueswir1 | break; \
|
914 | 714547bb | blueswir1 | default: \
|
915 | 714547bb | blueswir1 | new_fsr = 0; \
|
916 | 714547bb | blueswir1 | break; \
|
917 | 714547bb | blueswir1 | } \ |
918 | 714547bb | blueswir1 | env->fsr |= new_fsr; \ |
919 | 714547bb | blueswir1 | } |
920 | e8af50a3 | bellard | |
921 | 714547bb | blueswir1 | GEN_FCMPS(fcmps, float32, 0, 0); |
922 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
923 | 417454b0 | blueswir1 | |
924 | 714547bb | blueswir1 | GEN_FCMPS(fcmpes, float32, 0, 1); |
925 | 417454b0 | blueswir1 | GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
926 | 3475187d | bellard | |
927 | 4e14008f | blueswir1 | GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); |
928 | 4e14008f | blueswir1 | GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); |
929 | 4e14008f | blueswir1 | |
930 | 8393617c | Blue Swirl | static uint32_t compute_all_flags(void) |
931 | 8393617c | Blue Swirl | { |
932 | 8393617c | Blue Swirl | return env->psr & PSR_ICC;
|
933 | 8393617c | Blue Swirl | } |
934 | 8393617c | Blue Swirl | |
935 | 8393617c | Blue Swirl | static uint32_t compute_C_flags(void) |
936 | 8393617c | Blue Swirl | { |
937 | 8393617c | Blue Swirl | return env->psr & PSR_CARRY;
|
938 | 8393617c | Blue Swirl | } |
939 | 8393617c | Blue Swirl | |
940 | 5a4bb580 | Richard Henderson | static inline uint32_t get_NZ_icc(int32_t dst) |
941 | bdf9f35d | Blue Swirl | { |
942 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
943 | bdf9f35d | Blue Swirl | |
944 | 5a4bb580 | Richard Henderson | if (dst == 0) { |
945 | 5a4bb580 | Richard Henderson | ret = PSR_ZERO; |
946 | 5a4bb580 | Richard Henderson | } else if (dst < 0) { |
947 | 5a4bb580 | Richard Henderson | ret = PSR_NEG; |
948 | 5a4bb580 | Richard Henderson | } |
949 | bdf9f35d | Blue Swirl | return ret;
|
950 | bdf9f35d | Blue Swirl | } |
951 | bdf9f35d | Blue Swirl | |
952 | 8393617c | Blue Swirl | #ifdef TARGET_SPARC64
|
953 | 8393617c | Blue Swirl | static uint32_t compute_all_flags_xcc(void) |
954 | 8393617c | Blue Swirl | { |
955 | 8393617c | Blue Swirl | return env->xcc & PSR_ICC;
|
956 | 8393617c | Blue Swirl | } |
957 | 8393617c | Blue Swirl | |
958 | 8393617c | Blue Swirl | static uint32_t compute_C_flags_xcc(void) |
959 | 8393617c | Blue Swirl | { |
960 | 8393617c | Blue Swirl | return env->xcc & PSR_CARRY;
|
961 | 8393617c | Blue Swirl | } |
962 | 8393617c | Blue Swirl | |
963 | 5a4bb580 | Richard Henderson | static inline uint32_t get_NZ_xcc(target_long dst) |
964 | bdf9f35d | Blue Swirl | { |
965 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
966 | bdf9f35d | Blue Swirl | |
967 | 5a4bb580 | Richard Henderson | if (!dst) {
|
968 | 5a4bb580 | Richard Henderson | ret = PSR_ZERO; |
969 | 5a4bb580 | Richard Henderson | } else if (dst < 0) { |
970 | 5a4bb580 | Richard Henderson | ret = PSR_NEG; |
971 | 5a4bb580 | Richard Henderson | } |
972 | bdf9f35d | Blue Swirl | return ret;
|
973 | bdf9f35d | Blue Swirl | } |
974 | bdf9f35d | Blue Swirl | #endif
|
975 | bdf9f35d | Blue Swirl | |
976 | 6c78ea32 | Blue Swirl | static inline uint32_t get_V_div_icc(target_ulong src2) |
977 | 6c78ea32 | Blue Swirl | { |
978 | 6c78ea32 | Blue Swirl | uint32_t ret = 0;
|
979 | 6c78ea32 | Blue Swirl | |
980 | 5a4bb580 | Richard Henderson | if (src2 != 0) { |
981 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
982 | 5a4bb580 | Richard Henderson | } |
983 | 6c78ea32 | Blue Swirl | return ret;
|
984 | 6c78ea32 | Blue Swirl | } |
985 | 6c78ea32 | Blue Swirl | |
986 | 6c78ea32 | Blue Swirl | static uint32_t compute_all_div(void) |
987 | 6c78ea32 | Blue Swirl | { |
988 | 6c78ea32 | Blue Swirl | uint32_t ret; |
989 | 6c78ea32 | Blue Swirl | |
990 | 6c78ea32 | Blue Swirl | ret = get_NZ_icc(CC_DST); |
991 | 6c78ea32 | Blue Swirl | ret |= get_V_div_icc(CC_SRC2); |
992 | 6c78ea32 | Blue Swirl | return ret;
|
993 | 6c78ea32 | Blue Swirl | } |
994 | 6c78ea32 | Blue Swirl | |
995 | 6c78ea32 | Blue Swirl | static uint32_t compute_C_div(void) |
996 | 6c78ea32 | Blue Swirl | { |
997 | 6c78ea32 | Blue Swirl | return 0; |
998 | 6c78ea32 | Blue Swirl | } |
999 | 6c78ea32 | Blue Swirl | |
1000 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1) |
1001 | bdf9f35d | Blue Swirl | { |
1002 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
1003 | bdf9f35d | Blue Swirl | |
1004 | 5a4bb580 | Richard Henderson | if (dst < src1) {
|
1005 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1006 | 5a4bb580 | Richard Henderson | } |
1007 | bdf9f35d | Blue Swirl | return ret;
|
1008 | bdf9f35d | Blue Swirl | } |
1009 | bdf9f35d | Blue Swirl | |
1010 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_addx_icc(uint32_t dst, uint32_t src1, |
1011 | 5a4bb580 | Richard Henderson | uint32_t src2) |
1012 | bdf9f35d | Blue Swirl | { |
1013 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
1014 | bdf9f35d | Blue Swirl | |
1015 | 5a4bb580 | Richard Henderson | if (((src1 & src2) | (~dst & (src1 | src2))) & (1U << 31)) { |
1016 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1017 | 5a4bb580 | Richard Henderson | } |
1018 | 5a4bb580 | Richard Henderson | return ret;
|
1019 | 5a4bb580 | Richard Henderson | } |
1020 | 5a4bb580 | Richard Henderson | |
1021 | 5a4bb580 | Richard Henderson | static inline uint32_t get_V_add_icc(uint32_t dst, uint32_t src1, |
1022 | 5a4bb580 | Richard Henderson | uint32_t src2) |
1023 | 5a4bb580 | Richard Henderson | { |
1024 | 5a4bb580 | Richard Henderson | uint32_t ret = 0;
|
1025 | 5a4bb580 | Richard Henderson | |
1026 | 5a4bb580 | Richard Henderson | if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1U << 31)) { |
1027 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1028 | 5a4bb580 | Richard Henderson | } |
1029 | bdf9f35d | Blue Swirl | return ret;
|
1030 | bdf9f35d | Blue Swirl | } |
1031 | bdf9f35d | Blue Swirl | |
1032 | bdf9f35d | Blue Swirl | #ifdef TARGET_SPARC64
|
1033 | bdf9f35d | Blue Swirl | static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1) |
1034 | bdf9f35d | Blue Swirl | { |
1035 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
1036 | bdf9f35d | Blue Swirl | |
1037 | 5a4bb580 | Richard Henderson | if (dst < src1) {
|
1038 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1039 | 5a4bb580 | Richard Henderson | } |
1040 | 5a4bb580 | Richard Henderson | return ret;
|
1041 | 5a4bb580 | Richard Henderson | } |
1042 | 5a4bb580 | Richard Henderson | |
1043 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_addx_xcc(target_ulong dst, target_ulong src1, |
1044 | 5a4bb580 | Richard Henderson | target_ulong src2) |
1045 | 5a4bb580 | Richard Henderson | { |
1046 | 5a4bb580 | Richard Henderson | uint32_t ret = 0;
|
1047 | 5a4bb580 | Richard Henderson | |
1048 | 5a4bb580 | Richard Henderson | if (((src1 & src2) | (~dst & (src1 | src2))) & (1ULL << 63)) { |
1049 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1050 | 5a4bb580 | Richard Henderson | } |
1051 | bdf9f35d | Blue Swirl | return ret;
|
1052 | bdf9f35d | Blue Swirl | } |
1053 | bdf9f35d | Blue Swirl | |
1054 | bdf9f35d | Blue Swirl | static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1, |
1055 | bdf9f35d | Blue Swirl | target_ulong src2) |
1056 | bdf9f35d | Blue Swirl | { |
1057 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
1058 | bdf9f35d | Blue Swirl | |
1059 | 5a4bb580 | Richard Henderson | if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63)) { |
1060 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1061 | 5a4bb580 | Richard Henderson | } |
1062 | bdf9f35d | Blue Swirl | return ret;
|
1063 | bdf9f35d | Blue Swirl | } |
1064 | bdf9f35d | Blue Swirl | |
1065 | bdf9f35d | Blue Swirl | static uint32_t compute_all_add_xcc(void) |
1066 | bdf9f35d | Blue Swirl | { |
1067 | bdf9f35d | Blue Swirl | uint32_t ret; |
1068 | bdf9f35d | Blue Swirl | |
1069 | bdf9f35d | Blue Swirl | ret = get_NZ_xcc(CC_DST); |
1070 | bdf9f35d | Blue Swirl | ret |= get_C_add_xcc(CC_DST, CC_SRC); |
1071 | bdf9f35d | Blue Swirl | ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2); |
1072 | bdf9f35d | Blue Swirl | return ret;
|
1073 | bdf9f35d | Blue Swirl | } |
1074 | bdf9f35d | Blue Swirl | |
1075 | bdf9f35d | Blue Swirl | static uint32_t compute_C_add_xcc(void) |
1076 | bdf9f35d | Blue Swirl | { |
1077 | bdf9f35d | Blue Swirl | return get_C_add_xcc(CC_DST, CC_SRC);
|
1078 | bdf9f35d | Blue Swirl | } |
1079 | 8393617c | Blue Swirl | #endif
|
1080 | 8393617c | Blue Swirl | |
1081 | 3e6ba503 | Artyom Tarasenko | static uint32_t compute_all_add(void) |
1082 | 789c91ef | Blue Swirl | { |
1083 | 789c91ef | Blue Swirl | uint32_t ret; |
1084 | 789c91ef | Blue Swirl | |
1085 | 789c91ef | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1086 | 5a4bb580 | Richard Henderson | ret |= get_C_add_icc(CC_DST, CC_SRC); |
1087 | 789c91ef | Blue Swirl | ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1088 | 789c91ef | Blue Swirl | return ret;
|
1089 | 789c91ef | Blue Swirl | } |
1090 | 789c91ef | Blue Swirl | |
1091 | 3e6ba503 | Artyom Tarasenko | static uint32_t compute_C_add(void) |
1092 | 789c91ef | Blue Swirl | { |
1093 | 5a4bb580 | Richard Henderson | return get_C_add_icc(CC_DST, CC_SRC);
|
1094 | 789c91ef | Blue Swirl | } |
1095 | 789c91ef | Blue Swirl | |
1096 | 789c91ef | Blue Swirl | #ifdef TARGET_SPARC64
|
1097 | 789c91ef | Blue Swirl | static uint32_t compute_all_addx_xcc(void) |
1098 | 789c91ef | Blue Swirl | { |
1099 | 789c91ef | Blue Swirl | uint32_t ret; |
1100 | 789c91ef | Blue Swirl | |
1101 | 789c91ef | Blue Swirl | ret = get_NZ_xcc(CC_DST); |
1102 | 5a4bb580 | Richard Henderson | ret |= get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1103 | 789c91ef | Blue Swirl | ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2); |
1104 | 789c91ef | Blue Swirl | return ret;
|
1105 | 789c91ef | Blue Swirl | } |
1106 | 789c91ef | Blue Swirl | |
1107 | 789c91ef | Blue Swirl | static uint32_t compute_C_addx_xcc(void) |
1108 | 789c91ef | Blue Swirl | { |
1109 | 789c91ef | Blue Swirl | uint32_t ret; |
1110 | 789c91ef | Blue Swirl | |
1111 | 5a4bb580 | Richard Henderson | ret = get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1112 | 789c91ef | Blue Swirl | return ret;
|
1113 | 789c91ef | Blue Swirl | } |
1114 | 789c91ef | Blue Swirl | #endif
|
1115 | 789c91ef | Blue Swirl | |
1116 | 5a4bb580 | Richard Henderson | static uint32_t compute_all_addx(void) |
1117 | 5a4bb580 | Richard Henderson | { |
1118 | 5a4bb580 | Richard Henderson | uint32_t ret; |
1119 | 5a4bb580 | Richard Henderson | |
1120 | 5a4bb580 | Richard Henderson | ret = get_NZ_icc(CC_DST); |
1121 | 5a4bb580 | Richard Henderson | ret |= get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2); |
1122 | 5a4bb580 | Richard Henderson | ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1123 | 5a4bb580 | Richard Henderson | return ret;
|
1124 | 5a4bb580 | Richard Henderson | } |
1125 | 5a4bb580 | Richard Henderson | |
1126 | 5a4bb580 | Richard Henderson | static uint32_t compute_C_addx(void) |
1127 | 5a4bb580 | Richard Henderson | { |
1128 | 5a4bb580 | Richard Henderson | uint32_t ret; |
1129 | 5a4bb580 | Richard Henderson | |
1130 | 5a4bb580 | Richard Henderson | ret = get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2); |
1131 | 5a4bb580 | Richard Henderson | return ret;
|
1132 | 5a4bb580 | Richard Henderson | } |
1133 | 5a4bb580 | Richard Henderson | |
1134 | 3b2d1e92 | Blue Swirl | static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2) |
1135 | 3b2d1e92 | Blue Swirl | { |
1136 | 3b2d1e92 | Blue Swirl | uint32_t ret = 0;
|
1137 | 3b2d1e92 | Blue Swirl | |
1138 | 5a4bb580 | Richard Henderson | if ((src1 | src2) & 0x3) { |
1139 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1140 | 5a4bb580 | Richard Henderson | } |
1141 | 3b2d1e92 | Blue Swirl | return ret;
|
1142 | 3b2d1e92 | Blue Swirl | } |
1143 | 3b2d1e92 | Blue Swirl | |
1144 | 3b2d1e92 | Blue Swirl | static uint32_t compute_all_tadd(void) |
1145 | 3b2d1e92 | Blue Swirl | { |
1146 | 3b2d1e92 | Blue Swirl | uint32_t ret; |
1147 | 3b2d1e92 | Blue Swirl | |
1148 | 3b2d1e92 | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1149 | 5a4bb580 | Richard Henderson | ret |= get_C_add_icc(CC_DST, CC_SRC); |
1150 | 3b2d1e92 | Blue Swirl | ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1151 | 3b2d1e92 | Blue Swirl | ret |= get_V_tag_icc(CC_SRC, CC_SRC2); |
1152 | 3b2d1e92 | Blue Swirl | return ret;
|
1153 | 3b2d1e92 | Blue Swirl | } |
1154 | 3b2d1e92 | Blue Swirl | |
1155 | 3b2d1e92 | Blue Swirl | static uint32_t compute_all_taddtv(void) |
1156 | 3b2d1e92 | Blue Swirl | { |
1157 | 3b2d1e92 | Blue Swirl | uint32_t ret; |
1158 | 3b2d1e92 | Blue Swirl | |
1159 | 3b2d1e92 | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1160 | 5a4bb580 | Richard Henderson | ret |= get_C_add_icc(CC_DST, CC_SRC); |
1161 | 3b2d1e92 | Blue Swirl | return ret;
|
1162 | 3b2d1e92 | Blue Swirl | } |
1163 | 3b2d1e92 | Blue Swirl | |
1164 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_sub_icc(uint32_t src1, uint32_t src2) |
1165 | 3b2d1e92 | Blue Swirl | { |
1166 | 5a4bb580 | Richard Henderson | uint32_t ret = 0;
|
1167 | 5a4bb580 | Richard Henderson | |
1168 | 5a4bb580 | Richard Henderson | if (src1 < src2) {
|
1169 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1170 | 5a4bb580 | Richard Henderson | } |
1171 | 5a4bb580 | Richard Henderson | return ret;
|
1172 | 3b2d1e92 | Blue Swirl | } |
1173 | 3b2d1e92 | Blue Swirl | |
1174 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_subx_icc(uint32_t dst, uint32_t src1, |
1175 | 5a4bb580 | Richard Henderson | uint32_t src2) |
1176 | d4b0d468 | Blue Swirl | { |
1177 | d4b0d468 | Blue Swirl | uint32_t ret = 0;
|
1178 | d4b0d468 | Blue Swirl | |
1179 | 5a4bb580 | Richard Henderson | if (((~src1 & src2) | (dst & (~src1 | src2))) & (1U << 31)) { |
1180 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1181 | 5a4bb580 | Richard Henderson | } |
1182 | d4b0d468 | Blue Swirl | return ret;
|
1183 | d4b0d468 | Blue Swirl | } |
1184 | d4b0d468 | Blue Swirl | |
1185 | 5a4bb580 | Richard Henderson | static inline uint32_t get_V_sub_icc(uint32_t dst, uint32_t src1, |
1186 | 5a4bb580 | Richard Henderson | uint32_t src2) |
1187 | d4b0d468 | Blue Swirl | { |
1188 | d4b0d468 | Blue Swirl | uint32_t ret = 0;
|
1189 | d4b0d468 | Blue Swirl | |
1190 | 5a4bb580 | Richard Henderson | if (((src1 ^ src2) & (src1 ^ dst)) & (1U << 31)) { |
1191 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1192 | 5a4bb580 | Richard Henderson | } |
1193 | d4b0d468 | Blue Swirl | return ret;
|
1194 | d4b0d468 | Blue Swirl | } |
1195 | d4b0d468 | Blue Swirl | |
1196 | d4b0d468 | Blue Swirl | |
1197 | d4b0d468 | Blue Swirl | #ifdef TARGET_SPARC64
|
1198 | d4b0d468 | Blue Swirl | static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2) |
1199 | d4b0d468 | Blue Swirl | { |
1200 | d4b0d468 | Blue Swirl | uint32_t ret = 0;
|
1201 | d4b0d468 | Blue Swirl | |
1202 | 5a4bb580 | Richard Henderson | if (src1 < src2) {
|
1203 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1204 | 5a4bb580 | Richard Henderson | } |
1205 | 5a4bb580 | Richard Henderson | return ret;
|
1206 | 5a4bb580 | Richard Henderson | } |
1207 | 5a4bb580 | Richard Henderson | |
1208 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_subx_xcc(target_ulong dst, target_ulong src1, |
1209 | 5a4bb580 | Richard Henderson | target_ulong src2) |
1210 | 5a4bb580 | Richard Henderson | { |
1211 | 5a4bb580 | Richard Henderson | uint32_t ret = 0;
|
1212 | 5a4bb580 | Richard Henderson | |
1213 | 5a4bb580 | Richard Henderson | if (((~src1 & src2) | (dst & (~src1 | src2))) & (1ULL << 63)) { |
1214 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1215 | 5a4bb580 | Richard Henderson | } |
1216 | d4b0d468 | Blue Swirl | return ret;
|
1217 | d4b0d468 | Blue Swirl | } |
1218 | d4b0d468 | Blue Swirl | |
1219 | d4b0d468 | Blue Swirl | static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1, |
1220 | d4b0d468 | Blue Swirl | target_ulong src2) |
1221 | d4b0d468 | Blue Swirl | { |
1222 | d4b0d468 | Blue Swirl | uint32_t ret = 0;
|
1223 | d4b0d468 | Blue Swirl | |
1224 | 5a4bb580 | Richard Henderson | if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63)) { |
1225 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1226 | 5a4bb580 | Richard Henderson | } |
1227 | d4b0d468 | Blue Swirl | return ret;
|
1228 | d4b0d468 | Blue Swirl | } |
1229 | d4b0d468 | Blue Swirl | |
1230 | d4b0d468 | Blue Swirl | static uint32_t compute_all_sub_xcc(void) |
1231 | d4b0d468 | Blue Swirl | { |
1232 | d4b0d468 | Blue Swirl | uint32_t ret; |
1233 | d4b0d468 | Blue Swirl | |
1234 | d4b0d468 | Blue Swirl | ret = get_NZ_xcc(CC_DST); |
1235 | d4b0d468 | Blue Swirl | ret |= get_C_sub_xcc(CC_SRC, CC_SRC2); |
1236 | d4b0d468 | Blue Swirl | ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); |
1237 | d4b0d468 | Blue Swirl | return ret;
|
1238 | d4b0d468 | Blue Swirl | } |
1239 | d4b0d468 | Blue Swirl | |
1240 | d4b0d468 | Blue Swirl | static uint32_t compute_C_sub_xcc(void) |
1241 | d4b0d468 | Blue Swirl | { |
1242 | d4b0d468 | Blue Swirl | return get_C_sub_xcc(CC_SRC, CC_SRC2);
|
1243 | d4b0d468 | Blue Swirl | } |
1244 | d4b0d468 | Blue Swirl | #endif
|
1245 | d4b0d468 | Blue Swirl | |
1246 | 3e6ba503 | Artyom Tarasenko | static uint32_t compute_all_sub(void) |
1247 | 2ca1d92b | Blue Swirl | { |
1248 | 2ca1d92b | Blue Swirl | uint32_t ret; |
1249 | 2ca1d92b | Blue Swirl | |
1250 | 2ca1d92b | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1251 | 5a4bb580 | Richard Henderson | ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
1252 | 2ca1d92b | Blue Swirl | ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
1253 | 2ca1d92b | Blue Swirl | return ret;
|
1254 | 2ca1d92b | Blue Swirl | } |
1255 | 2ca1d92b | Blue Swirl | |
1256 | 3e6ba503 | Artyom Tarasenko | static uint32_t compute_C_sub(void) |
1257 | 2ca1d92b | Blue Swirl | { |
1258 | 5a4bb580 | Richard Henderson | return get_C_sub_icc(CC_SRC, CC_SRC2);
|
1259 | 2ca1d92b | Blue Swirl | } |
1260 | 2ca1d92b | Blue Swirl | |
1261 | 2ca1d92b | Blue Swirl | #ifdef TARGET_SPARC64
|
1262 | 2ca1d92b | Blue Swirl | static uint32_t compute_all_subx_xcc(void) |
1263 | 2ca1d92b | Blue Swirl | { |
1264 | 2ca1d92b | Blue Swirl | uint32_t ret; |
1265 | 2ca1d92b | Blue Swirl | |
1266 | 2ca1d92b | Blue Swirl | ret = get_NZ_xcc(CC_DST); |
1267 | 5a4bb580 | Richard Henderson | ret |= get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1268 | 2ca1d92b | Blue Swirl | ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); |
1269 | 2ca1d92b | Blue Swirl | return ret;
|
1270 | 2ca1d92b | Blue Swirl | } |
1271 | 2ca1d92b | Blue Swirl | |
1272 | 2ca1d92b | Blue Swirl | static uint32_t compute_C_subx_xcc(void) |
1273 | 2ca1d92b | Blue Swirl | { |
1274 | 2ca1d92b | Blue Swirl | uint32_t ret; |
1275 | 2ca1d92b | Blue Swirl | |
1276 | 5a4bb580 | Richard Henderson | ret = get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1277 | 2ca1d92b | Blue Swirl | return ret;
|
1278 | 2ca1d92b | Blue Swirl | } |
1279 | 2ca1d92b | Blue Swirl | #endif
|
1280 | 2ca1d92b | Blue Swirl | |
1281 | 5a4bb580 | Richard Henderson | static uint32_t compute_all_subx(void) |
1282 | 3b2d1e92 | Blue Swirl | { |
1283 | 3b2d1e92 | Blue Swirl | uint32_t ret; |
1284 | 3b2d1e92 | Blue Swirl | |
1285 | 3b2d1e92 | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1286 | 5a4bb580 | Richard Henderson | ret |= get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2); |
1287 | 3b2d1e92 | Blue Swirl | ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
1288 | 3b2d1e92 | Blue Swirl | return ret;
|
1289 | 3b2d1e92 | Blue Swirl | } |
1290 | 3b2d1e92 | Blue Swirl | |
1291 | 5a4bb580 | Richard Henderson | static uint32_t compute_C_subx(void) |
1292 | 3b2d1e92 | Blue Swirl | { |
1293 | 5a4bb580 | Richard Henderson | uint32_t ret; |
1294 | 5a4bb580 | Richard Henderson | |
1295 | 5a4bb580 | Richard Henderson | ret = get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2); |
1296 | 5a4bb580 | Richard Henderson | return ret;
|
1297 | 3b2d1e92 | Blue Swirl | } |
1298 | 3b2d1e92 | Blue Swirl | |
1299 | 5a4bb580 | Richard Henderson | static uint32_t compute_all_tsub(void) |
1300 | 3b2d1e92 | Blue Swirl | { |
1301 | 3b2d1e92 | Blue Swirl | uint32_t ret; |
1302 | 3b2d1e92 | Blue Swirl | |
1303 | 3b2d1e92 | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1304 | 5a4bb580 | Richard Henderson | ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
1305 | 5a4bb580 | Richard Henderson | ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
1306 | 5a4bb580 | Richard Henderson | ret |= get_V_tag_icc(CC_SRC, CC_SRC2); |
1307 | 3b2d1e92 | Blue Swirl | return ret;
|
1308 | 3b2d1e92 | Blue Swirl | } |
1309 | 3b2d1e92 | Blue Swirl | |
1310 | 5a4bb580 | Richard Henderson | static uint32_t compute_all_tsubtv(void) |
1311 | 3b2d1e92 | Blue Swirl | { |
1312 | 5a4bb580 | Richard Henderson | uint32_t ret; |
1313 | 5a4bb580 | Richard Henderson | |
1314 | 5a4bb580 | Richard Henderson | ret = get_NZ_icc(CC_DST); |
1315 | 5a4bb580 | Richard Henderson | ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
1316 | 5a4bb580 | Richard Henderson | return ret;
|
1317 | 3b2d1e92 | Blue Swirl | } |
1318 | 3b2d1e92 | Blue Swirl | |
1319 | 38482a77 | Blue Swirl | static uint32_t compute_all_logic(void) |
1320 | 38482a77 | Blue Swirl | { |
1321 | 38482a77 | Blue Swirl | return get_NZ_icc(CC_DST);
|
1322 | 38482a77 | Blue Swirl | } |
1323 | 38482a77 | Blue Swirl | |
1324 | 38482a77 | Blue Swirl | static uint32_t compute_C_logic(void) |
1325 | 38482a77 | Blue Swirl | { |
1326 | 38482a77 | Blue Swirl | return 0; |
1327 | 38482a77 | Blue Swirl | } |
1328 | 38482a77 | Blue Swirl | |
1329 | 38482a77 | Blue Swirl | #ifdef TARGET_SPARC64
|
1330 | 38482a77 | Blue Swirl | static uint32_t compute_all_logic_xcc(void) |
1331 | 38482a77 | Blue Swirl | { |
1332 | 38482a77 | Blue Swirl | return get_NZ_xcc(CC_DST);
|
1333 | 38482a77 | Blue Swirl | } |
1334 | 38482a77 | Blue Swirl | #endif
|
1335 | 38482a77 | Blue Swirl | |
1336 | 8393617c | Blue Swirl | typedef struct CCTable { |
1337 | 8393617c | Blue Swirl | uint32_t (*compute_all)(void); /* return all the flags */ |
1338 | 8393617c | Blue Swirl | uint32_t (*compute_c)(void); /* return the C flag */ |
1339 | 8393617c | Blue Swirl | } CCTable; |
1340 | 8393617c | Blue Swirl | |
1341 | 8393617c | Blue Swirl | static const CCTable icc_table[CC_OP_NB] = { |
1342 | 8393617c | Blue Swirl | /* CC_OP_DYNAMIC should never happen */
|
1343 | 8393617c | Blue Swirl | [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags }, |
1344 | 6c78ea32 | Blue Swirl | [CC_OP_DIV] = { compute_all_div, compute_C_div }, |
1345 | bdf9f35d | Blue Swirl | [CC_OP_ADD] = { compute_all_add, compute_C_add }, |
1346 | 5a4bb580 | Richard Henderson | [CC_OP_ADDX] = { compute_all_addx, compute_C_addx }, |
1347 | 5a4bb580 | Richard Henderson | [CC_OP_TADD] = { compute_all_tadd, compute_C_add }, |
1348 | 5a4bb580 | Richard Henderson | [CC_OP_TADDTV] = { compute_all_taddtv, compute_C_add }, |
1349 | d4b0d468 | Blue Swirl | [CC_OP_SUB] = { compute_all_sub, compute_C_sub }, |
1350 | 5a4bb580 | Richard Henderson | [CC_OP_SUBX] = { compute_all_subx, compute_C_subx }, |
1351 | 5a4bb580 | Richard Henderson | [CC_OP_TSUB] = { compute_all_tsub, compute_C_sub }, |
1352 | 5a4bb580 | Richard Henderson | [CC_OP_TSUBTV] = { compute_all_tsubtv, compute_C_sub }, |
1353 | 38482a77 | Blue Swirl | [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic }, |
1354 | 8393617c | Blue Swirl | }; |
1355 | 8393617c | Blue Swirl | |
1356 | 8393617c | Blue Swirl | #ifdef TARGET_SPARC64
|
1357 | 8393617c | Blue Swirl | static const CCTable xcc_table[CC_OP_NB] = { |
1358 | 8393617c | Blue Swirl | /* CC_OP_DYNAMIC should never happen */
|
1359 | 8393617c | Blue Swirl | [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc }, |
1360 | 6c78ea32 | Blue Swirl | [CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic }, |
1361 | bdf9f35d | Blue Swirl | [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc }, |
1362 | 789c91ef | Blue Swirl | [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc }, |
1363 | 3b2d1e92 | Blue Swirl | [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc }, |
1364 | 3b2d1e92 | Blue Swirl | [CC_OP_TADDTV] = { compute_all_add_xcc, compute_C_add_xcc }, |
1365 | d4b0d468 | Blue Swirl | [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
1366 | 2ca1d92b | Blue Swirl | [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc }, |
1367 | 3b2d1e92 | Blue Swirl | [CC_OP_TSUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
1368 | 3b2d1e92 | Blue Swirl | [CC_OP_TSUBTV] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
1369 | 38482a77 | Blue Swirl | [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic }, |
1370 | 8393617c | Blue Swirl | }; |
1371 | 8393617c | Blue Swirl | #endif
|
1372 | 8393617c | Blue Swirl | |
1373 | 8393617c | Blue Swirl | void helper_compute_psr(void) |
1374 | 8393617c | Blue Swirl | { |
1375 | 8393617c | Blue Swirl | uint32_t new_psr; |
1376 | 8393617c | Blue Swirl | |
1377 | 8393617c | Blue Swirl | new_psr = icc_table[CC_OP].compute_all(); |
1378 | 8393617c | Blue Swirl | env->psr = new_psr; |
1379 | 8393617c | Blue Swirl | #ifdef TARGET_SPARC64
|
1380 | 8393617c | Blue Swirl | new_psr = xcc_table[CC_OP].compute_all(); |
1381 | 8393617c | Blue Swirl | env->xcc = new_psr; |
1382 | 8393617c | Blue Swirl | #endif
|
1383 | 8393617c | Blue Swirl | CC_OP = CC_OP_FLAGS; |
1384 | 8393617c | Blue Swirl | } |
1385 | 8393617c | Blue Swirl | |
1386 | 70c48285 | Richard Henderson | uint32_t helper_compute_C_icc(void)
|
1387 | 8393617c | Blue Swirl | { |
1388 | 8393617c | Blue Swirl | uint32_t ret; |
1389 | 8393617c | Blue Swirl | |
1390 | 8393617c | Blue Swirl | ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT; |
1391 | 8393617c | Blue Swirl | return ret;
|
1392 | 8393617c | Blue Swirl | } |
1393 | 8393617c | Blue Swirl | |
1394 | 5a834bb4 | Blue Swirl | static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
1395 | 5a834bb4 | Blue Swirl | { |
1396 | 5a834bb4 | Blue Swirl | dst[0] = src[0]; |
1397 | 5a834bb4 | Blue Swirl | dst[1] = src[1]; |
1398 | 5a834bb4 | Blue Swirl | dst[2] = src[2]; |
1399 | 5a834bb4 | Blue Swirl | dst[3] = src[3]; |
1400 | 5a834bb4 | Blue Swirl | dst[4] = src[4]; |
1401 | 5a834bb4 | Blue Swirl | dst[5] = src[5]; |
1402 | 5a834bb4 | Blue Swirl | dst[6] = src[6]; |
1403 | 5a834bb4 | Blue Swirl | dst[7] = src[7]; |
1404 | 5a834bb4 | Blue Swirl | } |
1405 | 5a834bb4 | Blue Swirl | |
1406 | 5a834bb4 | Blue Swirl | static void set_cwp(int new_cwp) |
1407 | 5a834bb4 | Blue Swirl | { |
1408 | 5a834bb4 | Blue Swirl | /* put the modified wrap registers at their proper location */
|
1409 | 5a834bb4 | Blue Swirl | if (env->cwp == env->nwindows - 1) { |
1410 | 5a834bb4 | Blue Swirl | memcpy32(env->regbase, env->regbase + env->nwindows * 16);
|
1411 | 5a834bb4 | Blue Swirl | } |
1412 | 5a834bb4 | Blue Swirl | env->cwp = new_cwp; |
1413 | 5a834bb4 | Blue Swirl | |
1414 | 5a834bb4 | Blue Swirl | /* put the wrap registers at their temporary location */
|
1415 | 5a834bb4 | Blue Swirl | if (new_cwp == env->nwindows - 1) { |
1416 | 5a834bb4 | Blue Swirl | memcpy32(env->regbase + env->nwindows * 16, env->regbase);
|
1417 | 5a834bb4 | Blue Swirl | } |
1418 | 5a834bb4 | Blue Swirl | env->regwptr = env->regbase + (new_cwp * 16);
|
1419 | 5a834bb4 | Blue Swirl | } |
1420 | 5a834bb4 | Blue Swirl | |
1421 | 5a834bb4 | Blue Swirl | void cpu_set_cwp(CPUState *env1, int new_cwp) |
1422 | 5a834bb4 | Blue Swirl | { |
1423 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
1424 | 5a834bb4 | Blue Swirl | |
1425 | 5a834bb4 | Blue Swirl | saved_env = env; |
1426 | 5a834bb4 | Blue Swirl | env = env1; |
1427 | 5a834bb4 | Blue Swirl | set_cwp(new_cwp); |
1428 | 5a834bb4 | Blue Swirl | env = saved_env; |
1429 | 5a834bb4 | Blue Swirl | } |
1430 | 5a834bb4 | Blue Swirl | |
1431 | 5a834bb4 | Blue Swirl | static target_ulong get_psr(void) |
1432 | 5a834bb4 | Blue Swirl | { |
1433 | 5a834bb4 | Blue Swirl | helper_compute_psr(); |
1434 | 5a834bb4 | Blue Swirl | |
1435 | 5a834bb4 | Blue Swirl | #if !defined (TARGET_SPARC64)
|
1436 | 5a834bb4 | Blue Swirl | return env->version | (env->psr & PSR_ICC) |
|
1437 | 5a834bb4 | Blue Swirl | (env->psref? PSR_EF : 0) |
|
1438 | 5a834bb4 | Blue Swirl | (env->psrpil << 8) |
|
1439 | 5a834bb4 | Blue Swirl | (env->psrs? PSR_S : 0) |
|
1440 | 5a834bb4 | Blue Swirl | (env->psrps? PSR_PS : 0) |
|
1441 | 5a834bb4 | Blue Swirl | (env->psret? PSR_ET : 0) | env->cwp;
|
1442 | 5a834bb4 | Blue Swirl | #else
|
1443 | 2aae2b8e | Igor V. Kovalenko | return env->psr & PSR_ICC;
|
1444 | 5a834bb4 | Blue Swirl | #endif
|
1445 | 5a834bb4 | Blue Swirl | } |
1446 | 5a834bb4 | Blue Swirl | |
1447 | 5a834bb4 | Blue Swirl | target_ulong cpu_get_psr(CPUState *env1) |
1448 | 5a834bb4 | Blue Swirl | { |
1449 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
1450 | 5a834bb4 | Blue Swirl | target_ulong ret; |
1451 | 5a834bb4 | Blue Swirl | |
1452 | 5a834bb4 | Blue Swirl | saved_env = env; |
1453 | 5a834bb4 | Blue Swirl | env = env1; |
1454 | 5a834bb4 | Blue Swirl | ret = get_psr(); |
1455 | 5a834bb4 | Blue Swirl | env = saved_env; |
1456 | 5a834bb4 | Blue Swirl | return ret;
|
1457 | 5a834bb4 | Blue Swirl | } |
1458 | 5a834bb4 | Blue Swirl | |
1459 | 5a834bb4 | Blue Swirl | static void put_psr(target_ulong val) |
1460 | 5a834bb4 | Blue Swirl | { |
1461 | 5a834bb4 | Blue Swirl | env->psr = val & PSR_ICC; |
1462 | 2aae2b8e | Igor V. Kovalenko | #if !defined (TARGET_SPARC64)
|
1463 | 5a834bb4 | Blue Swirl | env->psref = (val & PSR_EF)? 1 : 0; |
1464 | 5a834bb4 | Blue Swirl | env->psrpil = (val & PSR_PIL) >> 8;
|
1465 | 2aae2b8e | Igor V. Kovalenko | #endif
|
1466 | 5a834bb4 | Blue Swirl | #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
|
1467 | 5a834bb4 | Blue Swirl | cpu_check_irqs(env); |
1468 | 5a834bb4 | Blue Swirl | #endif
|
1469 | 2aae2b8e | Igor V. Kovalenko | #if !defined (TARGET_SPARC64)
|
1470 | 5a834bb4 | Blue Swirl | env->psrs = (val & PSR_S)? 1 : 0; |
1471 | 5a834bb4 | Blue Swirl | env->psrps = (val & PSR_PS)? 1 : 0; |
1472 | 5a834bb4 | Blue Swirl | env->psret = (val & PSR_ET)? 1 : 0; |
1473 | 5a834bb4 | Blue Swirl | set_cwp(val & PSR_CWP); |
1474 | 2aae2b8e | Igor V. Kovalenko | #endif
|
1475 | 5a834bb4 | Blue Swirl | env->cc_op = CC_OP_FLAGS; |
1476 | 5a834bb4 | Blue Swirl | } |
1477 | 5a834bb4 | Blue Swirl | |
1478 | 5a834bb4 | Blue Swirl | void cpu_put_psr(CPUState *env1, target_ulong val)
|
1479 | 5a834bb4 | Blue Swirl | { |
1480 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
1481 | 5a834bb4 | Blue Swirl | |
1482 | 5a834bb4 | Blue Swirl | saved_env = env; |
1483 | 5a834bb4 | Blue Swirl | env = env1; |
1484 | 5a834bb4 | Blue Swirl | put_psr(val); |
1485 | 5a834bb4 | Blue Swirl | env = saved_env; |
1486 | 5a834bb4 | Blue Swirl | } |
1487 | 5a834bb4 | Blue Swirl | |
1488 | 5a834bb4 | Blue Swirl | static int cwp_inc(int cwp) |
1489 | 5a834bb4 | Blue Swirl | { |
1490 | 5a834bb4 | Blue Swirl | if (unlikely(cwp >= env->nwindows)) {
|
1491 | 5a834bb4 | Blue Swirl | cwp -= env->nwindows; |
1492 | 5a834bb4 | Blue Swirl | } |
1493 | 5a834bb4 | Blue Swirl | return cwp;
|
1494 | 5a834bb4 | Blue Swirl | } |
1495 | 5a834bb4 | Blue Swirl | |
1496 | 5a834bb4 | Blue Swirl | int cpu_cwp_inc(CPUState *env1, int cwp) |
1497 | 5a834bb4 | Blue Swirl | { |
1498 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
1499 | 5a834bb4 | Blue Swirl | target_ulong ret; |
1500 | 5a834bb4 | Blue Swirl | |
1501 | 5a834bb4 | Blue Swirl | saved_env = env; |
1502 | 5a834bb4 | Blue Swirl | env = env1; |
1503 | 5a834bb4 | Blue Swirl | ret = cwp_inc(cwp); |
1504 | 5a834bb4 | Blue Swirl | env = saved_env; |
1505 | 5a834bb4 | Blue Swirl | return ret;
|
1506 | 5a834bb4 | Blue Swirl | } |
1507 | 5a834bb4 | Blue Swirl | |
1508 | 5a834bb4 | Blue Swirl | static int cwp_dec(int cwp) |
1509 | 5a834bb4 | Blue Swirl | { |
1510 | 5a834bb4 | Blue Swirl | if (unlikely(cwp < 0)) { |
1511 | 5a834bb4 | Blue Swirl | cwp += env->nwindows; |
1512 | 5a834bb4 | Blue Swirl | } |
1513 | 5a834bb4 | Blue Swirl | return cwp;
|
1514 | 5a834bb4 | Blue Swirl | } |
1515 | 5a834bb4 | Blue Swirl | |
1516 | 5a834bb4 | Blue Swirl | int cpu_cwp_dec(CPUState *env1, int cwp) |
1517 | 5a834bb4 | Blue Swirl | { |
1518 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
1519 | 5a834bb4 | Blue Swirl | target_ulong ret; |
1520 | 5a834bb4 | Blue Swirl | |
1521 | 5a834bb4 | Blue Swirl | saved_env = env; |
1522 | 5a834bb4 | Blue Swirl | env = env1; |
1523 | 5a834bb4 | Blue Swirl | ret = cwp_dec(cwp); |
1524 | 5a834bb4 | Blue Swirl | env = saved_env; |
1525 | 5a834bb4 | Blue Swirl | return ret;
|
1526 | 5a834bb4 | Blue Swirl | } |
1527 | 5a834bb4 | Blue Swirl | |
1528 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1529 | 714547bb | blueswir1 | GEN_FCMPS(fcmps_fcc1, float32, 22, 0); |
1530 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
1531 | 64a88d5d | blueswir1 | GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); |
1532 | 417454b0 | blueswir1 | |
1533 | 714547bb | blueswir1 | GEN_FCMPS(fcmps_fcc2, float32, 24, 0); |
1534 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
1535 | 64a88d5d | blueswir1 | GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); |
1536 | 417454b0 | blueswir1 | |
1537 | 714547bb | blueswir1 | GEN_FCMPS(fcmps_fcc3, float32, 26, 0); |
1538 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
1539 | 64a88d5d | blueswir1 | GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); |
1540 | 417454b0 | blueswir1 | |
1541 | 714547bb | blueswir1 | GEN_FCMPS(fcmpes_fcc1, float32, 22, 1); |
1542 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
1543 | 64a88d5d | blueswir1 | GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); |
1544 | 3475187d | bellard | |
1545 | 714547bb | blueswir1 | GEN_FCMPS(fcmpes_fcc2, float32, 24, 1); |
1546 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); |
1547 | 64a88d5d | blueswir1 | GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); |
1548 | 3475187d | bellard | |
1549 | 714547bb | blueswir1 | GEN_FCMPS(fcmpes_fcc3, float32, 26, 1); |
1550 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); |
1551 | 4e14008f | blueswir1 | GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); |
1552 | 4e14008f | blueswir1 | #endif
|
1553 | 714547bb | blueswir1 | #undef GEN_FCMPS
|
1554 | 3475187d | bellard | |
1555 | 77f193da | blueswir1 | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
|
1556 | 77f193da | blueswir1 | defined(DEBUG_MXCC) |
1557 | 952a328f | blueswir1 | static void dump_mxcc(CPUState *env) |
1558 | 952a328f | blueswir1 | { |
1559 | 0bf9e31a | Blue Swirl | printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1560 | 0bf9e31a | Blue Swirl | "\n",
|
1561 | 77f193da | blueswir1 | env->mxccdata[0], env->mxccdata[1], |
1562 | 77f193da | blueswir1 | env->mxccdata[2], env->mxccdata[3]); |
1563 | 0bf9e31a | Blue Swirl | printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1564 | 0bf9e31a | Blue Swirl | "\n"
|
1565 | 0bf9e31a | Blue Swirl | " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1566 | 0bf9e31a | Blue Swirl | "\n",
|
1567 | 77f193da | blueswir1 | env->mxccregs[0], env->mxccregs[1], |
1568 | 77f193da | blueswir1 | env->mxccregs[2], env->mxccregs[3], |
1569 | 77f193da | blueswir1 | env->mxccregs[4], env->mxccregs[5], |
1570 | 77f193da | blueswir1 | env->mxccregs[6], env->mxccregs[7]); |
1571 | 952a328f | blueswir1 | } |
1572 | 952a328f | blueswir1 | #endif
|
1573 | 952a328f | blueswir1 | |
1574 | 1a2fb1c0 | blueswir1 | #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
|
1575 | 1a2fb1c0 | blueswir1 | && defined(DEBUG_ASI) |
1576 | 1a2fb1c0 | blueswir1 | static void dump_asi(const char *txt, target_ulong addr, int asi, int size, |
1577 | 1a2fb1c0 | blueswir1 | uint64_t r1) |
1578 | 8543e2cf | blueswir1 | { |
1579 | 8543e2cf | blueswir1 | switch (size)
|
1580 | 8543e2cf | blueswir1 | { |
1581 | 8543e2cf | blueswir1 | case 1: |
1582 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, |
1583 | 1a2fb1c0 | blueswir1 | addr, asi, r1 & 0xff);
|
1584 | 8543e2cf | blueswir1 | break;
|
1585 | 8543e2cf | blueswir1 | case 2: |
1586 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, |
1587 | 1a2fb1c0 | blueswir1 | addr, asi, r1 & 0xffff);
|
1588 | 8543e2cf | blueswir1 | break;
|
1589 | 8543e2cf | blueswir1 | case 4: |
1590 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, |
1591 | 1a2fb1c0 | blueswir1 | addr, asi, r1 & 0xffffffff);
|
1592 | 8543e2cf | blueswir1 | break;
|
1593 | 8543e2cf | blueswir1 | case 8: |
1594 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, |
1595 | 1a2fb1c0 | blueswir1 | addr, asi, r1); |
1596 | 8543e2cf | blueswir1 | break;
|
1597 | 8543e2cf | blueswir1 | } |
1598 | 8543e2cf | blueswir1 | } |
1599 | 8543e2cf | blueswir1 | #endif
|
1600 | 8543e2cf | blueswir1 | |
1601 | 1a2fb1c0 | blueswir1 | #ifndef TARGET_SPARC64
|
1602 | 1a2fb1c0 | blueswir1 | #ifndef CONFIG_USER_ONLY
|
1603 | 1a2fb1c0 | blueswir1 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
1604 | e8af50a3 | bellard | { |
1605 | 1a2fb1c0 | blueswir1 | uint64_t ret = 0;
|
1606 | 8543e2cf | blueswir1 | #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
|
1607 | 1a2fb1c0 | blueswir1 | uint32_t last_addr = addr; |
1608 | 952a328f | blueswir1 | #endif
|
1609 | e80cfcfc | bellard | |
1610 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
1611 | e80cfcfc | bellard | switch (asi) {
|
1612 | 6c36d3fa | blueswir1 | case 2: /* SuperSparc MXCC registers */ |
1613 | 1a2fb1c0 | blueswir1 | switch (addr) {
|
1614 | 952a328f | blueswir1 | case 0x01c00a00: /* MXCC control register */ |
1615 | 1a2fb1c0 | blueswir1 | if (size == 8) |
1616 | 1a2fb1c0 | blueswir1 | ret = env->mxccregs[3];
|
1617 | 1a2fb1c0 | blueswir1 | else
|
1618 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1619 | 77f193da | blueswir1 | size); |
1620 | 952a328f | blueswir1 | break;
|
1621 | 952a328f | blueswir1 | case 0x01c00a04: /* MXCC control register */ |
1622 | 952a328f | blueswir1 | if (size == 4) |
1623 | 952a328f | blueswir1 | ret = env->mxccregs[3];
|
1624 | 952a328f | blueswir1 | else
|
1625 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1626 | 77f193da | blueswir1 | size); |
1627 | 952a328f | blueswir1 | break;
|
1628 | 295db113 | blueswir1 | case 0x01c00c00: /* Module reset register */ |
1629 | 295db113 | blueswir1 | if (size == 8) { |
1630 | 1a2fb1c0 | blueswir1 | ret = env->mxccregs[5];
|
1631 | 295db113 | blueswir1 | // should we do something here?
|
1632 | 295db113 | blueswir1 | } else
|
1633 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1634 | 77f193da | blueswir1 | size); |
1635 | 295db113 | blueswir1 | break;
|
1636 | 952a328f | blueswir1 | case 0x01c00f00: /* MBus port address register */ |
1637 | 1a2fb1c0 | blueswir1 | if (size == 8) |
1638 | 1a2fb1c0 | blueswir1 | ret = env->mxccregs[7];
|
1639 | 1a2fb1c0 | blueswir1 | else
|
1640 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1641 | 77f193da | blueswir1 | size); |
1642 | 952a328f | blueswir1 | break;
|
1643 | 952a328f | blueswir1 | default:
|
1644 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
1645 | 77f193da | blueswir1 | size); |
1646 | 952a328f | blueswir1 | break;
|
1647 | 952a328f | blueswir1 | } |
1648 | 77f193da | blueswir1 | DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
|
1649 | 9827e450 | blueswir1 | "addr = %08x -> ret = %" PRIx64 "," |
1650 | 1a2fb1c0 | blueswir1 | "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
|
1651 | 952a328f | blueswir1 | #ifdef DEBUG_MXCC
|
1652 | 952a328f | blueswir1 | dump_mxcc(env); |
1653 | 952a328f | blueswir1 | #endif
|
1654 | 6c36d3fa | blueswir1 | break;
|
1655 | e8af50a3 | bellard | case 3: /* MMU probe */ |
1656 | 0f8a249a | blueswir1 | { |
1657 | 0f8a249a | blueswir1 | int mmulev;
|
1658 | 0f8a249a | blueswir1 | |
1659 | 1a2fb1c0 | blueswir1 | mmulev = (addr >> 8) & 15; |
1660 | 0f8a249a | blueswir1 | if (mmulev > 4) |
1661 | 0f8a249a | blueswir1 | ret = 0;
|
1662 | 1a2fb1c0 | blueswir1 | else
|
1663 | 1a2fb1c0 | blueswir1 | ret = mmu_probe(env, addr, mmulev); |
1664 | 1a2fb1c0 | blueswir1 | DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", |
1665 | 1a2fb1c0 | blueswir1 | addr, mmulev, ret); |
1666 | 0f8a249a | blueswir1 | } |
1667 | 0f8a249a | blueswir1 | break;
|
1668 | e8af50a3 | bellard | case 4: /* read MMU regs */ |
1669 | 0f8a249a | blueswir1 | { |
1670 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 8) & 0x1f; |
1671 | 3b46e624 | ths | |
1672 | 0f8a249a | blueswir1 | ret = env->mmuregs[reg]; |
1673 | 0f8a249a | blueswir1 | if (reg == 3) /* Fault status cleared on read */ |
1674 | 3dd9a152 | blueswir1 | env->mmuregs[3] = 0; |
1675 | 3dd9a152 | blueswir1 | else if (reg == 0x13) /* Fault status read */ |
1676 | 3dd9a152 | blueswir1 | ret = env->mmuregs[3];
|
1677 | 3dd9a152 | blueswir1 | else if (reg == 0x14) /* Fault address read */ |
1678 | 3dd9a152 | blueswir1 | ret = env->mmuregs[4];
|
1679 | 1a2fb1c0 | blueswir1 | DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); |
1680 | 0f8a249a | blueswir1 | } |
1681 | 0f8a249a | blueswir1 | break;
|
1682 | 045380be | blueswir1 | case 5: // Turbosparc ITLB Diagnostic |
1683 | 045380be | blueswir1 | case 6: // Turbosparc DTLB Diagnostic |
1684 | 045380be | blueswir1 | case 7: // Turbosparc IOTLB Diagnostic |
1685 | 045380be | blueswir1 | break;
|
1686 | 6c36d3fa | blueswir1 | case 9: /* Supervisor code access */ |
1687 | 6c36d3fa | blueswir1 | switch(size) {
|
1688 | 6c36d3fa | blueswir1 | case 1: |
1689 | 1a2fb1c0 | blueswir1 | ret = ldub_code(addr); |
1690 | 6c36d3fa | blueswir1 | break;
|
1691 | 6c36d3fa | blueswir1 | case 2: |
1692 | a4e7dd52 | blueswir1 | ret = lduw_code(addr); |
1693 | 6c36d3fa | blueswir1 | break;
|
1694 | 6c36d3fa | blueswir1 | default:
|
1695 | 6c36d3fa | blueswir1 | case 4: |
1696 | a4e7dd52 | blueswir1 | ret = ldl_code(addr); |
1697 | 6c36d3fa | blueswir1 | break;
|
1698 | 6c36d3fa | blueswir1 | case 8: |
1699 | a4e7dd52 | blueswir1 | ret = ldq_code(addr); |
1700 | 6c36d3fa | blueswir1 | break;
|
1701 | 6c36d3fa | blueswir1 | } |
1702 | 6c36d3fa | blueswir1 | break;
|
1703 | 81ad8ba2 | blueswir1 | case 0xa: /* User data access */ |
1704 | 81ad8ba2 | blueswir1 | switch(size) {
|
1705 | 81ad8ba2 | blueswir1 | case 1: |
1706 | 1a2fb1c0 | blueswir1 | ret = ldub_user(addr); |
1707 | 81ad8ba2 | blueswir1 | break;
|
1708 | 81ad8ba2 | blueswir1 | case 2: |
1709 | a4e7dd52 | blueswir1 | ret = lduw_user(addr); |
1710 | 81ad8ba2 | blueswir1 | break;
|
1711 | 81ad8ba2 | blueswir1 | default:
|
1712 | 81ad8ba2 | blueswir1 | case 4: |
1713 | a4e7dd52 | blueswir1 | ret = ldl_user(addr); |
1714 | 81ad8ba2 | blueswir1 | break;
|
1715 | 81ad8ba2 | blueswir1 | case 8: |
1716 | a4e7dd52 | blueswir1 | ret = ldq_user(addr); |
1717 | 81ad8ba2 | blueswir1 | break;
|
1718 | 81ad8ba2 | blueswir1 | } |
1719 | 81ad8ba2 | blueswir1 | break;
|
1720 | 81ad8ba2 | blueswir1 | case 0xb: /* Supervisor data access */ |
1721 | 81ad8ba2 | blueswir1 | switch(size) {
|
1722 | 81ad8ba2 | blueswir1 | case 1: |
1723 | 1a2fb1c0 | blueswir1 | ret = ldub_kernel(addr); |
1724 | 81ad8ba2 | blueswir1 | break;
|
1725 | 81ad8ba2 | blueswir1 | case 2: |
1726 | a4e7dd52 | blueswir1 | ret = lduw_kernel(addr); |
1727 | 81ad8ba2 | blueswir1 | break;
|
1728 | 81ad8ba2 | blueswir1 | default:
|
1729 | 81ad8ba2 | blueswir1 | case 4: |
1730 | a4e7dd52 | blueswir1 | ret = ldl_kernel(addr); |
1731 | 81ad8ba2 | blueswir1 | break;
|
1732 | 81ad8ba2 | blueswir1 | case 8: |
1733 | a4e7dd52 | blueswir1 | ret = ldq_kernel(addr); |
1734 | 81ad8ba2 | blueswir1 | break;
|
1735 | 81ad8ba2 | blueswir1 | } |
1736 | 81ad8ba2 | blueswir1 | break;
|
1737 | 6c36d3fa | blueswir1 | case 0xc: /* I-cache tag */ |
1738 | 6c36d3fa | blueswir1 | case 0xd: /* I-cache data */ |
1739 | 6c36d3fa | blueswir1 | case 0xe: /* D-cache tag */ |
1740 | 6c36d3fa | blueswir1 | case 0xf: /* D-cache data */ |
1741 | 6c36d3fa | blueswir1 | break;
|
1742 | 6c36d3fa | blueswir1 | case 0x20: /* MMU passthrough */ |
1743 | 02aab46a | bellard | switch(size) {
|
1744 | 02aab46a | bellard | case 1: |
1745 | 1a2fb1c0 | blueswir1 | ret = ldub_phys(addr); |
1746 | 02aab46a | bellard | break;
|
1747 | 02aab46a | bellard | case 2: |
1748 | a4e7dd52 | blueswir1 | ret = lduw_phys(addr); |
1749 | 02aab46a | bellard | break;
|
1750 | 02aab46a | bellard | default:
|
1751 | 02aab46a | bellard | case 4: |
1752 | a4e7dd52 | blueswir1 | ret = ldl_phys(addr); |
1753 | 02aab46a | bellard | break;
|
1754 | 9e61bde5 | bellard | case 8: |
1755 | a4e7dd52 | blueswir1 | ret = ldq_phys(addr); |
1756 | 0f8a249a | blueswir1 | break;
|
1757 | 02aab46a | bellard | } |
1758 | 0f8a249a | blueswir1 | break;
|
1759 | 7d85892b | blueswir1 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
1760 | 5dcb6b91 | blueswir1 | switch(size) {
|
1761 | 5dcb6b91 | blueswir1 | case 1: |
1762 | c227f099 | Anthony Liguori | ret = ldub_phys((target_phys_addr_t)addr |
1763 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
1764 | 5dcb6b91 | blueswir1 | break;
|
1765 | 5dcb6b91 | blueswir1 | case 2: |
1766 | c227f099 | Anthony Liguori | ret = lduw_phys((target_phys_addr_t)addr |
1767 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
1768 | 5dcb6b91 | blueswir1 | break;
|
1769 | 5dcb6b91 | blueswir1 | default:
|
1770 | 5dcb6b91 | blueswir1 | case 4: |
1771 | c227f099 | Anthony Liguori | ret = ldl_phys((target_phys_addr_t)addr |
1772 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
1773 | 5dcb6b91 | blueswir1 | break;
|
1774 | 5dcb6b91 | blueswir1 | case 8: |
1775 | c227f099 | Anthony Liguori | ret = ldq_phys((target_phys_addr_t)addr |
1776 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
1777 | 0f8a249a | blueswir1 | break;
|
1778 | 5dcb6b91 | blueswir1 | } |
1779 | 0f8a249a | blueswir1 | break;
|
1780 | 045380be | blueswir1 | case 0x30: // Turbosparc secondary cache diagnostic |
1781 | 045380be | blueswir1 | case 0x31: // Turbosparc RAM snoop |
1782 | 045380be | blueswir1 | case 0x32: // Turbosparc page table descriptor diagnostic |
1783 | 666c87aa | blueswir1 | case 0x39: /* data cache diagnostic register */ |
1784 | da7ed379 | Artyom Tarasenko | case 0x4c: /* SuperSPARC MMU Breakpoint Action register */ |
1785 | 666c87aa | blueswir1 | ret = 0;
|
1786 | 666c87aa | blueswir1 | break;
|
1787 | 4017190e | blueswir1 | case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ |
1788 | 4017190e | blueswir1 | { |
1789 | 4017190e | blueswir1 | int reg = (addr >> 8) & 3; |
1790 | 4017190e | blueswir1 | |
1791 | 4017190e | blueswir1 | switch(reg) {
|
1792 | 4017190e | blueswir1 | case 0: /* Breakpoint Value (Addr) */ |
1793 | 4017190e | blueswir1 | ret = env->mmubpregs[reg]; |
1794 | 4017190e | blueswir1 | break;
|
1795 | 4017190e | blueswir1 | case 1: /* Breakpoint Mask */ |
1796 | 4017190e | blueswir1 | ret = env->mmubpregs[reg]; |
1797 | 4017190e | blueswir1 | break;
|
1798 | 4017190e | blueswir1 | case 2: /* Breakpoint Control */ |
1799 | 4017190e | blueswir1 | ret = env->mmubpregs[reg]; |
1800 | 4017190e | blueswir1 | break;
|
1801 | 4017190e | blueswir1 | case 3: /* Breakpoint Status */ |
1802 | 4017190e | blueswir1 | ret = env->mmubpregs[reg]; |
1803 | 4017190e | blueswir1 | env->mmubpregs[reg] = 0ULL;
|
1804 | 4017190e | blueswir1 | break;
|
1805 | 4017190e | blueswir1 | } |
1806 | 0bf9e31a | Blue Swirl | DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, |
1807 | 0bf9e31a | Blue Swirl | ret); |
1808 | 4017190e | blueswir1 | } |
1809 | 4017190e | blueswir1 | break;
|
1810 | 045380be | blueswir1 | case 8: /* User code access, XXX */ |
1811 | e8af50a3 | bellard | default:
|
1812 | e18231a3 | blueswir1 | do_unassigned_access(addr, 0, 0, asi, size); |
1813 | 0f8a249a | blueswir1 | ret = 0;
|
1814 | 0f8a249a | blueswir1 | break;
|
1815 | e8af50a3 | bellard | } |
1816 | 81ad8ba2 | blueswir1 | if (sign) {
|
1817 | 81ad8ba2 | blueswir1 | switch(size) {
|
1818 | 81ad8ba2 | blueswir1 | case 1: |
1819 | 1a2fb1c0 | blueswir1 | ret = (int8_t) ret; |
1820 | e32664fb | blueswir1 | break;
|
1821 | 81ad8ba2 | blueswir1 | case 2: |
1822 | 1a2fb1c0 | blueswir1 | ret = (int16_t) ret; |
1823 | 1a2fb1c0 | blueswir1 | break;
|
1824 | 1a2fb1c0 | blueswir1 | case 4: |
1825 | 1a2fb1c0 | blueswir1 | ret = (int32_t) ret; |
1826 | e32664fb | blueswir1 | break;
|
1827 | 81ad8ba2 | blueswir1 | default:
|
1828 | 81ad8ba2 | blueswir1 | break;
|
1829 | 81ad8ba2 | blueswir1 | } |
1830 | 81ad8ba2 | blueswir1 | } |
1831 | 8543e2cf | blueswir1 | #ifdef DEBUG_ASI
|
1832 | 1a2fb1c0 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
1833 | 8543e2cf | blueswir1 | #endif
|
1834 | 1a2fb1c0 | blueswir1 | return ret;
|
1835 | e8af50a3 | bellard | } |
1836 | e8af50a3 | bellard | |
1837 | 1a2fb1c0 | blueswir1 | void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) |
1838 | e8af50a3 | bellard | { |
1839 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
1840 | e8af50a3 | bellard | switch(asi) {
|
1841 | 6c36d3fa | blueswir1 | case 2: /* SuperSparc MXCC registers */ |
1842 | 1a2fb1c0 | blueswir1 | switch (addr) {
|
1843 | 952a328f | blueswir1 | case 0x01c00000: /* MXCC stream data register 0 */ |
1844 | 952a328f | blueswir1 | if (size == 8) |
1845 | 1a2fb1c0 | blueswir1 | env->mxccdata[0] = val;
|
1846 | 952a328f | blueswir1 | else
|
1847 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1848 | 77f193da | blueswir1 | size); |
1849 | 952a328f | blueswir1 | break;
|
1850 | 952a328f | blueswir1 | case 0x01c00008: /* MXCC stream data register 1 */ |
1851 | 952a328f | blueswir1 | if (size == 8) |
1852 | 1a2fb1c0 | blueswir1 | env->mxccdata[1] = val;
|
1853 | 952a328f | blueswir1 | else
|
1854 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1855 | 77f193da | blueswir1 | size); |
1856 | 952a328f | blueswir1 | break;
|
1857 | 952a328f | blueswir1 | case 0x01c00010: /* MXCC stream data register 2 */ |
1858 | 952a328f | blueswir1 | if (size == 8) |
1859 | 1a2fb1c0 | blueswir1 | env->mxccdata[2] = val;
|
1860 | 952a328f | blueswir1 | else
|
1861 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1862 | 77f193da | blueswir1 | size); |
1863 | 952a328f | blueswir1 | break;
|
1864 | 952a328f | blueswir1 | case 0x01c00018: /* MXCC stream data register 3 */ |
1865 | 952a328f | blueswir1 | if (size == 8) |
1866 | 1a2fb1c0 | blueswir1 | env->mxccdata[3] = val;
|
1867 | 952a328f | blueswir1 | else
|
1868 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1869 | 77f193da | blueswir1 | size); |
1870 | 952a328f | blueswir1 | break;
|
1871 | 952a328f | blueswir1 | case 0x01c00100: /* MXCC stream source */ |
1872 | 952a328f | blueswir1 | if (size == 8) |
1873 | 1a2fb1c0 | blueswir1 | env->mxccregs[0] = val;
|
1874 | 952a328f | blueswir1 | else
|
1875 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1876 | 77f193da | blueswir1 | size); |
1877 | 77f193da | blueswir1 | env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
1878 | 77f193da | blueswir1 | 0);
|
1879 | 77f193da | blueswir1 | env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
1880 | 77f193da | blueswir1 | 8);
|
1881 | 77f193da | blueswir1 | env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
1882 | 77f193da | blueswir1 | 16);
|
1883 | 77f193da | blueswir1 | env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
1884 | 77f193da | blueswir1 | 24);
|
1885 | 952a328f | blueswir1 | break;
|
1886 | 952a328f | blueswir1 | case 0x01c00200: /* MXCC stream destination */ |
1887 | 952a328f | blueswir1 | if (size == 8) |
1888 | 1a2fb1c0 | blueswir1 | env->mxccregs[1] = val;
|
1889 | 952a328f | blueswir1 | else
|
1890 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1891 | 77f193da | blueswir1 | size); |
1892 | 77f193da | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, |
1893 | 77f193da | blueswir1 | env->mxccdata[0]);
|
1894 | 77f193da | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, |
1895 | 77f193da | blueswir1 | env->mxccdata[1]);
|
1896 | 77f193da | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, |
1897 | 77f193da | blueswir1 | env->mxccdata[2]);
|
1898 | 77f193da | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, |
1899 | 77f193da | blueswir1 | env->mxccdata[3]);
|
1900 | 952a328f | blueswir1 | break;
|
1901 | 952a328f | blueswir1 | case 0x01c00a00: /* MXCC control register */ |
1902 | 952a328f | blueswir1 | if (size == 8) |
1903 | 1a2fb1c0 | blueswir1 | env->mxccregs[3] = val;
|
1904 | 952a328f | blueswir1 | else
|
1905 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1906 | 77f193da | blueswir1 | size); |
1907 | 952a328f | blueswir1 | break;
|
1908 | 952a328f | blueswir1 | case 0x01c00a04: /* MXCC control register */ |
1909 | 952a328f | blueswir1 | if (size == 4) |
1910 | 9f4576f0 | blueswir1 | env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) |
1911 | 77f193da | blueswir1 | | val; |
1912 | 952a328f | blueswir1 | else
|
1913 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1914 | 77f193da | blueswir1 | size); |
1915 | 952a328f | blueswir1 | break;
|
1916 | 952a328f | blueswir1 | case 0x01c00e00: /* MXCC error register */ |
1917 | bbf7d96b | blueswir1 | // writing a 1 bit clears the error
|
1918 | 952a328f | blueswir1 | if (size == 8) |
1919 | 1a2fb1c0 | blueswir1 | env->mxccregs[6] &= ~val;
|
1920 | 952a328f | blueswir1 | else
|
1921 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1922 | 77f193da | blueswir1 | size); |
1923 | 952a328f | blueswir1 | break;
|
1924 | 952a328f | blueswir1 | case 0x01c00f00: /* MBus port address register */ |
1925 | 952a328f | blueswir1 | if (size == 8) |
1926 | 1a2fb1c0 | blueswir1 | env->mxccregs[7] = val;
|
1927 | 952a328f | blueswir1 | else
|
1928 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1929 | 77f193da | blueswir1 | size); |
1930 | 952a328f | blueswir1 | break;
|
1931 | 952a328f | blueswir1 | default:
|
1932 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
1933 | 77f193da | blueswir1 | size); |
1934 | 952a328f | blueswir1 | break;
|
1935 | 952a328f | blueswir1 | } |
1936 | 9827e450 | blueswir1 | DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", |
1937 | 9827e450 | blueswir1 | asi, size, addr, val); |
1938 | 952a328f | blueswir1 | #ifdef DEBUG_MXCC
|
1939 | 952a328f | blueswir1 | dump_mxcc(env); |
1940 | 952a328f | blueswir1 | #endif
|
1941 | 6c36d3fa | blueswir1 | break;
|
1942 | e8af50a3 | bellard | case 3: /* MMU flush */ |
1943 | 0f8a249a | blueswir1 | { |
1944 | 0f8a249a | blueswir1 | int mmulev;
|
1945 | e80cfcfc | bellard | |
1946 | 1a2fb1c0 | blueswir1 | mmulev = (addr >> 8) & 15; |
1947 | 952a328f | blueswir1 | DPRINTF_MMU("mmu flush level %d\n", mmulev);
|
1948 | 0f8a249a | blueswir1 | switch (mmulev) {
|
1949 | 0f8a249a | blueswir1 | case 0: // flush page |
1950 | 1a2fb1c0 | blueswir1 | tlb_flush_page(env, addr & 0xfffff000);
|
1951 | 0f8a249a | blueswir1 | break;
|
1952 | 0f8a249a | blueswir1 | case 1: // flush segment (256k) |
1953 | 0f8a249a | blueswir1 | case 2: // flush region (16M) |
1954 | 0f8a249a | blueswir1 | case 3: // flush context (4G) |
1955 | 0f8a249a | blueswir1 | case 4: // flush entire |
1956 | 0f8a249a | blueswir1 | tlb_flush(env, 1);
|
1957 | 0f8a249a | blueswir1 | break;
|
1958 | 0f8a249a | blueswir1 | default:
|
1959 | 0f8a249a | blueswir1 | break;
|
1960 | 0f8a249a | blueswir1 | } |
1961 | 55754d9e | bellard | #ifdef DEBUG_MMU
|
1962 | 0f8a249a | blueswir1 | dump_mmu(env); |
1963 | 55754d9e | bellard | #endif
|
1964 | 0f8a249a | blueswir1 | } |
1965 | 8543e2cf | blueswir1 | break;
|
1966 | e8af50a3 | bellard | case 4: /* write MMU regs */ |
1967 | 0f8a249a | blueswir1 | { |
1968 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 8) & 0x1f; |
1969 | 0f8a249a | blueswir1 | uint32_t oldreg; |
1970 | 3b46e624 | ths | |
1971 | 0f8a249a | blueswir1 | oldreg = env->mmuregs[reg]; |
1972 | 55754d9e | bellard | switch(reg) {
|
1973 | 3deaeab7 | blueswir1 | case 0: // Control Register |
1974 | 3dd9a152 | blueswir1 | env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
|
1975 | 1a2fb1c0 | blueswir1 | (val & 0x00ffffff);
|
1976 | 0f8a249a | blueswir1 | // Mappings generated during no-fault mode or MMU
|
1977 | 0f8a249a | blueswir1 | // disabled mode are invalid in normal mode
|
1978 | 5578ceab | blueswir1 | if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
|
1979 | 5578ceab | blueswir1 | (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) |
1980 | 55754d9e | bellard | tlb_flush(env, 1);
|
1981 | 55754d9e | bellard | break;
|
1982 | 3deaeab7 | blueswir1 | case 1: // Context Table Pointer Register |
1983 | 5578ceab | blueswir1 | env->mmuregs[reg] = val & env->def->mmu_ctpr_mask; |
1984 | 3deaeab7 | blueswir1 | break;
|
1985 | 3deaeab7 | blueswir1 | case 2: // Context Register |
1986 | 5578ceab | blueswir1 | env->mmuregs[reg] = val & env->def->mmu_cxr_mask; |
1987 | 55754d9e | bellard | if (oldreg != env->mmuregs[reg]) {
|
1988 | 55754d9e | bellard | /* we flush when the MMU context changes because
|
1989 | 55754d9e | bellard | QEMU has no MMU context support */
|
1990 | 55754d9e | bellard | tlb_flush(env, 1);
|
1991 | 55754d9e | bellard | } |
1992 | 55754d9e | bellard | break;
|
1993 | 3deaeab7 | blueswir1 | case 3: // Synchronous Fault Status Register with Clear |
1994 | 3deaeab7 | blueswir1 | case 4: // Synchronous Fault Address Register |
1995 | 3deaeab7 | blueswir1 | break;
|
1996 | 3deaeab7 | blueswir1 | case 0x10: // TLB Replacement Control Register |
1997 | 5578ceab | blueswir1 | env->mmuregs[reg] = val & env->def->mmu_trcr_mask; |
1998 | 55754d9e | bellard | break;
|
1999 | 3deaeab7 | blueswir1 | case 0x13: // Synchronous Fault Status Register with Read and Clear |
2000 | 5578ceab | blueswir1 | env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
|
2001 | 3dd9a152 | blueswir1 | break;
|
2002 | 3deaeab7 | blueswir1 | case 0x14: // Synchronous Fault Address Register |
2003 | 1a2fb1c0 | blueswir1 | env->mmuregs[4] = val;
|
2004 | 3dd9a152 | blueswir1 | break;
|
2005 | 55754d9e | bellard | default:
|
2006 | 1a2fb1c0 | blueswir1 | env->mmuregs[reg] = val; |
2007 | 55754d9e | bellard | break;
|
2008 | 55754d9e | bellard | } |
2009 | 55754d9e | bellard | if (oldreg != env->mmuregs[reg]) {
|
2010 | 77f193da | blueswir1 | DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
|
2011 | 77f193da | blueswir1 | reg, oldreg, env->mmuregs[reg]); |
2012 | 55754d9e | bellard | } |
2013 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
|
2014 | 0f8a249a | blueswir1 | dump_mmu(env); |
2015 | 55754d9e | bellard | #endif
|
2016 | 0f8a249a | blueswir1 | } |
2017 | 8543e2cf | blueswir1 | break;
|
2018 | 045380be | blueswir1 | case 5: // Turbosparc ITLB Diagnostic |
2019 | 045380be | blueswir1 | case 6: // Turbosparc DTLB Diagnostic |
2020 | 045380be | blueswir1 | case 7: // Turbosparc IOTLB Diagnostic |
2021 | 045380be | blueswir1 | break;
|
2022 | 81ad8ba2 | blueswir1 | case 0xa: /* User data access */ |
2023 | 81ad8ba2 | blueswir1 | switch(size) {
|
2024 | 81ad8ba2 | blueswir1 | case 1: |
2025 | 1a2fb1c0 | blueswir1 | stb_user(addr, val); |
2026 | 81ad8ba2 | blueswir1 | break;
|
2027 | 81ad8ba2 | blueswir1 | case 2: |
2028 | a4e7dd52 | blueswir1 | stw_user(addr, val); |
2029 | 81ad8ba2 | blueswir1 | break;
|
2030 | 81ad8ba2 | blueswir1 | default:
|
2031 | 81ad8ba2 | blueswir1 | case 4: |
2032 | a4e7dd52 | blueswir1 | stl_user(addr, val); |
2033 | 81ad8ba2 | blueswir1 | break;
|
2034 | 81ad8ba2 | blueswir1 | case 8: |
2035 | a4e7dd52 | blueswir1 | stq_user(addr, val); |
2036 | 81ad8ba2 | blueswir1 | break;
|
2037 | 81ad8ba2 | blueswir1 | } |
2038 | 81ad8ba2 | blueswir1 | break;
|
2039 | 81ad8ba2 | blueswir1 | case 0xb: /* Supervisor data access */ |
2040 | 81ad8ba2 | blueswir1 | switch(size) {
|
2041 | 81ad8ba2 | blueswir1 | case 1: |
2042 | 1a2fb1c0 | blueswir1 | stb_kernel(addr, val); |
2043 | 81ad8ba2 | blueswir1 | break;
|
2044 | 81ad8ba2 | blueswir1 | case 2: |
2045 | a4e7dd52 | blueswir1 | stw_kernel(addr, val); |
2046 | 81ad8ba2 | blueswir1 | break;
|
2047 | 81ad8ba2 | blueswir1 | default:
|
2048 | 81ad8ba2 | blueswir1 | case 4: |
2049 | a4e7dd52 | blueswir1 | stl_kernel(addr, val); |
2050 | 81ad8ba2 | blueswir1 | break;
|
2051 | 81ad8ba2 | blueswir1 | case 8: |
2052 | a4e7dd52 | blueswir1 | stq_kernel(addr, val); |
2053 | 81ad8ba2 | blueswir1 | break;
|
2054 | 81ad8ba2 | blueswir1 | } |
2055 | 81ad8ba2 | blueswir1 | break;
|
2056 | 6c36d3fa | blueswir1 | case 0xc: /* I-cache tag */ |
2057 | 6c36d3fa | blueswir1 | case 0xd: /* I-cache data */ |
2058 | 6c36d3fa | blueswir1 | case 0xe: /* D-cache tag */ |
2059 | 6c36d3fa | blueswir1 | case 0xf: /* D-cache data */ |
2060 | 6c36d3fa | blueswir1 | case 0x10: /* I/D-cache flush page */ |
2061 | 6c36d3fa | blueswir1 | case 0x11: /* I/D-cache flush segment */ |
2062 | 6c36d3fa | blueswir1 | case 0x12: /* I/D-cache flush region */ |
2063 | 6c36d3fa | blueswir1 | case 0x13: /* I/D-cache flush context */ |
2064 | 6c36d3fa | blueswir1 | case 0x14: /* I/D-cache flush user */ |
2065 | 6c36d3fa | blueswir1 | break;
|
2066 | e80cfcfc | bellard | case 0x17: /* Block copy, sta access */ |
2067 | 0f8a249a | blueswir1 | { |
2068 | 1a2fb1c0 | blueswir1 | // val = src
|
2069 | 1a2fb1c0 | blueswir1 | // addr = dst
|
2070 | 0f8a249a | blueswir1 | // copy 32 bytes
|
2071 | 6c36d3fa | blueswir1 | unsigned int i; |
2072 | 1a2fb1c0 | blueswir1 | uint32_t src = val & ~3, dst = addr & ~3, temp; |
2073 | 3b46e624 | ths | |
2074 | 6c36d3fa | blueswir1 | for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
2075 | 6c36d3fa | blueswir1 | temp = ldl_kernel(src); |
2076 | 6c36d3fa | blueswir1 | stl_kernel(dst, temp); |
2077 | 6c36d3fa | blueswir1 | } |
2078 | 0f8a249a | blueswir1 | } |
2079 | 8543e2cf | blueswir1 | break;
|
2080 | e80cfcfc | bellard | case 0x1f: /* Block fill, stda access */ |
2081 | 0f8a249a | blueswir1 | { |
2082 | 1a2fb1c0 | blueswir1 | // addr = dst
|
2083 | 1a2fb1c0 | blueswir1 | // fill 32 bytes with val
|
2084 | 6c36d3fa | blueswir1 | unsigned int i; |
2085 | 1a2fb1c0 | blueswir1 | uint32_t dst = addr & 7;
|
2086 | 6c36d3fa | blueswir1 | |
2087 | 6c36d3fa | blueswir1 | for (i = 0; i < 32; i += 8, dst += 8) |
2088 | 6c36d3fa | blueswir1 | stq_kernel(dst, val); |
2089 | 0f8a249a | blueswir1 | } |
2090 | 8543e2cf | blueswir1 | break;
|
2091 | 6c36d3fa | blueswir1 | case 0x20: /* MMU passthrough */ |
2092 | 0f8a249a | blueswir1 | { |
2093 | 02aab46a | bellard | switch(size) {
|
2094 | 02aab46a | bellard | case 1: |
2095 | 1a2fb1c0 | blueswir1 | stb_phys(addr, val); |
2096 | 02aab46a | bellard | break;
|
2097 | 02aab46a | bellard | case 2: |
2098 | a4e7dd52 | blueswir1 | stw_phys(addr, val); |
2099 | 02aab46a | bellard | break;
|
2100 | 02aab46a | bellard | case 4: |
2101 | 02aab46a | bellard | default:
|
2102 | a4e7dd52 | blueswir1 | stl_phys(addr, val); |
2103 | 02aab46a | bellard | break;
|
2104 | 9e61bde5 | bellard | case 8: |
2105 | a4e7dd52 | blueswir1 | stq_phys(addr, val); |
2106 | 9e61bde5 | bellard | break;
|
2107 | 02aab46a | bellard | } |
2108 | 0f8a249a | blueswir1 | } |
2109 | 8543e2cf | blueswir1 | break;
|
2110 | 045380be | blueswir1 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
2111 | 0f8a249a | blueswir1 | { |
2112 | 5dcb6b91 | blueswir1 | switch(size) {
|
2113 | 5dcb6b91 | blueswir1 | case 1: |
2114 | c227f099 | Anthony Liguori | stb_phys((target_phys_addr_t)addr |
2115 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2116 | 5dcb6b91 | blueswir1 | break;
|
2117 | 5dcb6b91 | blueswir1 | case 2: |
2118 | c227f099 | Anthony Liguori | stw_phys((target_phys_addr_t)addr |
2119 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2120 | 5dcb6b91 | blueswir1 | break;
|
2121 | 5dcb6b91 | blueswir1 | case 4: |
2122 | 5dcb6b91 | blueswir1 | default:
|
2123 | c227f099 | Anthony Liguori | stl_phys((target_phys_addr_t)addr |
2124 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2125 | 5dcb6b91 | blueswir1 | break;
|
2126 | 5dcb6b91 | blueswir1 | case 8: |
2127 | c227f099 | Anthony Liguori | stq_phys((target_phys_addr_t)addr |
2128 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2129 | 5dcb6b91 | blueswir1 | break;
|
2130 | 5dcb6b91 | blueswir1 | } |
2131 | 0f8a249a | blueswir1 | } |
2132 | 8543e2cf | blueswir1 | break;
|
2133 | 045380be | blueswir1 | case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic |
2134 | 045380be | blueswir1 | case 0x31: // store buffer data, Ross RT620 I-cache flush or |
2135 | 045380be | blueswir1 | // Turbosparc snoop RAM
|
2136 | 77f193da | blueswir1 | case 0x32: // store buffer control or Turbosparc page table |
2137 | 77f193da | blueswir1 | // descriptor diagnostic
|
2138 | 6c36d3fa | blueswir1 | case 0x36: /* I-cache flash clear */ |
2139 | 6c36d3fa | blueswir1 | case 0x37: /* D-cache flash clear */ |
2140 | 666c87aa | blueswir1 | case 0x4c: /* breakpoint action */ |
2141 | 6c36d3fa | blueswir1 | break;
|
2142 | 4017190e | blueswir1 | case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ |
2143 | 4017190e | blueswir1 | { |
2144 | 4017190e | blueswir1 | int reg = (addr >> 8) & 3; |
2145 | 4017190e | blueswir1 | |
2146 | 4017190e | blueswir1 | switch(reg) {
|
2147 | 4017190e | blueswir1 | case 0: /* Breakpoint Value (Addr) */ |
2148 | 4017190e | blueswir1 | env->mmubpregs[reg] = (val & 0xfffffffffULL);
|
2149 | 4017190e | blueswir1 | break;
|
2150 | 4017190e | blueswir1 | case 1: /* Breakpoint Mask */ |
2151 | 4017190e | blueswir1 | env->mmubpregs[reg] = (val & 0xfffffffffULL);
|
2152 | 4017190e | blueswir1 | break;
|
2153 | 4017190e | blueswir1 | case 2: /* Breakpoint Control */ |
2154 | 4017190e | blueswir1 | env->mmubpregs[reg] = (val & 0x7fULL);
|
2155 | 4017190e | blueswir1 | break;
|
2156 | 4017190e | blueswir1 | case 3: /* Breakpoint Status */ |
2157 | 4017190e | blueswir1 | env->mmubpregs[reg] = (val & 0xfULL);
|
2158 | 4017190e | blueswir1 | break;
|
2159 | 4017190e | blueswir1 | } |
2160 | 0bf9e31a | Blue Swirl | DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
|
2161 | 4017190e | blueswir1 | env->mmuregs[reg]); |
2162 | 4017190e | blueswir1 | } |
2163 | 4017190e | blueswir1 | break;
|
2164 | 045380be | blueswir1 | case 8: /* User code access, XXX */ |
2165 | 6c36d3fa | blueswir1 | case 9: /* Supervisor code access, XXX */ |
2166 | e8af50a3 | bellard | default:
|
2167 | e18231a3 | blueswir1 | do_unassigned_access(addr, 1, 0, asi, size); |
2168 | 8543e2cf | blueswir1 | break;
|
2169 | e8af50a3 | bellard | } |
2170 | 8543e2cf | blueswir1 | #ifdef DEBUG_ASI
|
2171 | 1a2fb1c0 | blueswir1 | dump_asi("write", addr, asi, size, val);
|
2172 | 8543e2cf | blueswir1 | #endif
|
2173 | e8af50a3 | bellard | } |
2174 | e8af50a3 | bellard | |
2175 | 81ad8ba2 | blueswir1 | #endif /* CONFIG_USER_ONLY */ |
2176 | 81ad8ba2 | blueswir1 | #else /* TARGET_SPARC64 */ |
2177 | 81ad8ba2 | blueswir1 | |
2178 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
|
2179 | 1a2fb1c0 | blueswir1 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
2180 | 81ad8ba2 | blueswir1 | { |
2181 | 81ad8ba2 | blueswir1 | uint64_t ret = 0;
|
2182 | 1a2fb1c0 | blueswir1 | #if defined(DEBUG_ASI)
|
2183 | 1a2fb1c0 | blueswir1 | target_ulong last_addr = addr; |
2184 | 1a2fb1c0 | blueswir1 | #endif
|
2185 | 81ad8ba2 | blueswir1 | |
2186 | 81ad8ba2 | blueswir1 | if (asi < 0x80) |
2187 | 81ad8ba2 | blueswir1 | raise_exception(TT_PRIV_ACT); |
2188 | 81ad8ba2 | blueswir1 | |
2189 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
2190 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
2191 | c2bc0e38 | blueswir1 | |
2192 | 81ad8ba2 | blueswir1 | switch (asi) {
|
2193 | 81ad8ba2 | blueswir1 | case 0x82: // Primary no-fault |
2194 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
2195 | e83ce550 | blueswir1 | if (page_check_range(addr, size, PAGE_READ) == -1) { |
2196 | e83ce550 | blueswir1 | #ifdef DEBUG_ASI
|
2197 | e83ce550 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
2198 | e83ce550 | blueswir1 | #endif
|
2199 | e83ce550 | blueswir1 | return 0; |
2200 | e83ce550 | blueswir1 | } |
2201 | e83ce550 | blueswir1 | // Fall through
|
2202 | e83ce550 | blueswir1 | case 0x80: // Primary |
2203 | e83ce550 | blueswir1 | case 0x88: // Primary LE |
2204 | 81ad8ba2 | blueswir1 | { |
2205 | 81ad8ba2 | blueswir1 | switch(size) {
|
2206 | 81ad8ba2 | blueswir1 | case 1: |
2207 | 1a2fb1c0 | blueswir1 | ret = ldub_raw(addr); |
2208 | 81ad8ba2 | blueswir1 | break;
|
2209 | 81ad8ba2 | blueswir1 | case 2: |
2210 | a4e7dd52 | blueswir1 | ret = lduw_raw(addr); |
2211 | 81ad8ba2 | blueswir1 | break;
|
2212 | 81ad8ba2 | blueswir1 | case 4: |
2213 | a4e7dd52 | blueswir1 | ret = ldl_raw(addr); |
2214 | 81ad8ba2 | blueswir1 | break;
|
2215 | 81ad8ba2 | blueswir1 | default:
|
2216 | 81ad8ba2 | blueswir1 | case 8: |
2217 | a4e7dd52 | blueswir1 | ret = ldq_raw(addr); |
2218 | 81ad8ba2 | blueswir1 | break;
|
2219 | 81ad8ba2 | blueswir1 | } |
2220 | 81ad8ba2 | blueswir1 | } |
2221 | 81ad8ba2 | blueswir1 | break;
|
2222 | 81ad8ba2 | blueswir1 | case 0x83: // Secondary no-fault |
2223 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
2224 | e83ce550 | blueswir1 | if (page_check_range(addr, size, PAGE_READ) == -1) { |
2225 | e83ce550 | blueswir1 | #ifdef DEBUG_ASI
|
2226 | e83ce550 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
2227 | e83ce550 | blueswir1 | #endif
|
2228 | e83ce550 | blueswir1 | return 0; |
2229 | e83ce550 | blueswir1 | } |
2230 | e83ce550 | blueswir1 | // Fall through
|
2231 | e83ce550 | blueswir1 | case 0x81: // Secondary |
2232 | e83ce550 | blueswir1 | case 0x89: // Secondary LE |
2233 | 81ad8ba2 | blueswir1 | // XXX
|
2234 | 81ad8ba2 | blueswir1 | break;
|
2235 | 81ad8ba2 | blueswir1 | default:
|
2236 | 81ad8ba2 | blueswir1 | break;
|
2237 | 81ad8ba2 | blueswir1 | } |
2238 | 81ad8ba2 | blueswir1 | |
2239 | 81ad8ba2 | blueswir1 | /* Convert from little endian */
|
2240 | 81ad8ba2 | blueswir1 | switch (asi) {
|
2241 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2242 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
2243 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
2244 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
2245 | 81ad8ba2 | blueswir1 | switch(size) {
|
2246 | 81ad8ba2 | blueswir1 | case 2: |
2247 | 81ad8ba2 | blueswir1 | ret = bswap16(ret); |
2248 | e32664fb | blueswir1 | break;
|
2249 | 81ad8ba2 | blueswir1 | case 4: |
2250 | 81ad8ba2 | blueswir1 | ret = bswap32(ret); |
2251 | e32664fb | blueswir1 | break;
|
2252 | 81ad8ba2 | blueswir1 | case 8: |
2253 | 81ad8ba2 | blueswir1 | ret = bswap64(ret); |
2254 | e32664fb | blueswir1 | break;
|
2255 | 81ad8ba2 | blueswir1 | default:
|
2256 | 81ad8ba2 | blueswir1 | break;
|
2257 | 81ad8ba2 | blueswir1 | } |
2258 | 81ad8ba2 | blueswir1 | default:
|
2259 | 81ad8ba2 | blueswir1 | break;
|
2260 | 81ad8ba2 | blueswir1 | } |
2261 | 81ad8ba2 | blueswir1 | |
2262 | 81ad8ba2 | blueswir1 | /* Convert to signed number */
|
2263 | 81ad8ba2 | blueswir1 | if (sign) {
|
2264 | 81ad8ba2 | blueswir1 | switch(size) {
|
2265 | 81ad8ba2 | blueswir1 | case 1: |
2266 | 81ad8ba2 | blueswir1 | ret = (int8_t) ret; |
2267 | e32664fb | blueswir1 | break;
|
2268 | 81ad8ba2 | blueswir1 | case 2: |
2269 | 81ad8ba2 | blueswir1 | ret = (int16_t) ret; |
2270 | e32664fb | blueswir1 | break;
|
2271 | 81ad8ba2 | blueswir1 | case 4: |
2272 | 81ad8ba2 | blueswir1 | ret = (int32_t) ret; |
2273 | e32664fb | blueswir1 | break;
|
2274 | 81ad8ba2 | blueswir1 | default:
|
2275 | 81ad8ba2 | blueswir1 | break;
|
2276 | 81ad8ba2 | blueswir1 | } |
2277 | 81ad8ba2 | blueswir1 | } |
2278 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
2279 | 1a2fb1c0 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
2280 | 1a2fb1c0 | blueswir1 | #endif
|
2281 | 1a2fb1c0 | blueswir1 | return ret;
|
2282 | 81ad8ba2 | blueswir1 | } |
2283 | 81ad8ba2 | blueswir1 | |
2284 | 1a2fb1c0 | blueswir1 | void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
2285 | 81ad8ba2 | blueswir1 | { |
2286 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
2287 | 1a2fb1c0 | blueswir1 | dump_asi("write", addr, asi, size, val);
|
2288 | 1a2fb1c0 | blueswir1 | #endif
|
2289 | 81ad8ba2 | blueswir1 | if (asi < 0x80) |
2290 | 81ad8ba2 | blueswir1 | raise_exception(TT_PRIV_ACT); |
2291 | 81ad8ba2 | blueswir1 | |
2292 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
2293 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
2294 | c2bc0e38 | blueswir1 | |
2295 | 81ad8ba2 | blueswir1 | /* Convert to little endian */
|
2296 | 81ad8ba2 | blueswir1 | switch (asi) {
|
2297 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2298 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
2299 | 81ad8ba2 | blueswir1 | switch(size) {
|
2300 | 81ad8ba2 | blueswir1 | case 2: |
2301 | 5b0f0bec | Igor Kovalenko | val = bswap16(val); |
2302 | e32664fb | blueswir1 | break;
|
2303 | 81ad8ba2 | blueswir1 | case 4: |
2304 | 5b0f0bec | Igor Kovalenko | val = bswap32(val); |
2305 | e32664fb | blueswir1 | break;
|
2306 | 81ad8ba2 | blueswir1 | case 8: |
2307 | 5b0f0bec | Igor Kovalenko | val = bswap64(val); |
2308 | e32664fb | blueswir1 | break;
|
2309 | 81ad8ba2 | blueswir1 | default:
|
2310 | 81ad8ba2 | blueswir1 | break;
|
2311 | 81ad8ba2 | blueswir1 | } |
2312 | 81ad8ba2 | blueswir1 | default:
|
2313 | 81ad8ba2 | blueswir1 | break;
|
2314 | 81ad8ba2 | blueswir1 | } |
2315 | 81ad8ba2 | blueswir1 | |
2316 | 81ad8ba2 | blueswir1 | switch(asi) {
|
2317 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
2318 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2319 | 81ad8ba2 | blueswir1 | { |
2320 | 81ad8ba2 | blueswir1 | switch(size) {
|
2321 | 81ad8ba2 | blueswir1 | case 1: |
2322 | 1a2fb1c0 | blueswir1 | stb_raw(addr, val); |
2323 | 81ad8ba2 | blueswir1 | break;
|
2324 | 81ad8ba2 | blueswir1 | case 2: |
2325 | a4e7dd52 | blueswir1 | stw_raw(addr, val); |
2326 | 81ad8ba2 | blueswir1 | break;
|
2327 | 81ad8ba2 | blueswir1 | case 4: |
2328 | a4e7dd52 | blueswir1 | stl_raw(addr, val); |
2329 | 81ad8ba2 | blueswir1 | break;
|
2330 | 81ad8ba2 | blueswir1 | case 8: |
2331 | 81ad8ba2 | blueswir1 | default:
|
2332 | a4e7dd52 | blueswir1 | stq_raw(addr, val); |
2333 | 81ad8ba2 | blueswir1 | break;
|
2334 | 81ad8ba2 | blueswir1 | } |
2335 | 81ad8ba2 | blueswir1 | } |
2336 | 81ad8ba2 | blueswir1 | break;
|
2337 | 81ad8ba2 | blueswir1 | case 0x81: // Secondary |
2338 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
2339 | 81ad8ba2 | blueswir1 | // XXX
|
2340 | 81ad8ba2 | blueswir1 | return;
|
2341 | 81ad8ba2 | blueswir1 | |
2342 | 81ad8ba2 | blueswir1 | case 0x82: // Primary no-fault, RO |
2343 | 81ad8ba2 | blueswir1 | case 0x83: // Secondary no-fault, RO |
2344 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE, RO |
2345 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE, RO |
2346 | 81ad8ba2 | blueswir1 | default:
|
2347 | e18231a3 | blueswir1 | do_unassigned_access(addr, 1, 0, 1, size); |
2348 | 81ad8ba2 | blueswir1 | return;
|
2349 | 81ad8ba2 | blueswir1 | } |
2350 | 81ad8ba2 | blueswir1 | } |
2351 | 81ad8ba2 | blueswir1 | |
2352 | 81ad8ba2 | blueswir1 | #else /* CONFIG_USER_ONLY */ |
2353 | 3475187d | bellard | |
2354 | 1a2fb1c0 | blueswir1 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
2355 | 3475187d | bellard | { |
2356 | 83469015 | bellard | uint64_t ret = 0;
|
2357 | 1a2fb1c0 | blueswir1 | #if defined(DEBUG_ASI)
|
2358 | 1a2fb1c0 | blueswir1 | target_ulong last_addr = addr; |
2359 | 1a2fb1c0 | blueswir1 | #endif
|
2360 | 3475187d | bellard | |
2361 | 01b5d4e5 | Igor V. Kovalenko | asi &= 0xff;
|
2362 | 01b5d4e5 | Igor V. Kovalenko | |
2363 | 6f27aba6 | blueswir1 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
2364 | 2aae2b8e | Igor V. Kovalenko | || (cpu_has_hypervisor(env) |
2365 | 5578ceab | blueswir1 | && asi >= 0x30 && asi < 0x80 |
2366 | fb79ceb9 | blueswir1 | && !(env->hpstate & HS_PRIV))) |
2367 | 0f8a249a | blueswir1 | raise_exception(TT_PRIV_ACT); |
2368 | 3475187d | bellard | |
2369 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
2370 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
2371 | 1295001c | Igor V. Kovalenko | |
2372 | 3475187d | bellard | switch (asi) {
|
2373 | e83ce550 | blueswir1 | case 0x82: // Primary no-fault |
2374 | e83ce550 | blueswir1 | case 0x8a: // Primary no-fault LE |
2375 | 2065061e | Igor V. Kovalenko | case 0x83: // Secondary no-fault |
2376 | 2065061e | Igor V. Kovalenko | case 0x8b: // Secondary no-fault LE |
2377 | 2065061e | Igor V. Kovalenko | { |
2378 | 2065061e | Igor V. Kovalenko | /* secondary space access has lowest asi bit equal to 1 */
|
2379 | 2065061e | Igor V. Kovalenko | int access_mmu_idx = ( asi & 1 ) ? MMU_KERNEL_IDX |
2380 | 2065061e | Igor V. Kovalenko | : MMU_KERNEL_SECONDARY_IDX; |
2381 | 2065061e | Igor V. Kovalenko | |
2382 | 2065061e | Igor V. Kovalenko | if (cpu_get_phys_page_nofault(env, addr, access_mmu_idx) == -1ULL) { |
2383 | e83ce550 | blueswir1 | #ifdef DEBUG_ASI
|
2384 | 2065061e | Igor V. Kovalenko | dump_asi("read ", last_addr, asi, size, ret);
|
2385 | e83ce550 | blueswir1 | #endif
|
2386 | 2065061e | Igor V. Kovalenko | return 0; |
2387 | 2065061e | Igor V. Kovalenko | } |
2388 | e83ce550 | blueswir1 | } |
2389 | e83ce550 | blueswir1 | // Fall through
|
2390 | 81ad8ba2 | blueswir1 | case 0x10: // As if user primary |
2391 | 2065061e | Igor V. Kovalenko | case 0x11: // As if user secondary |
2392 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
2393 | 2065061e | Igor V. Kovalenko | case 0x19: // As if user secondary LE |
2394 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
2395 | 2065061e | Igor V. Kovalenko | case 0x81: // Secondary |
2396 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2397 | 2065061e | Igor V. Kovalenko | case 0x89: // Secondary LE |
2398 | c99657d3 | blueswir1 | case 0xe2: // UA2007 Primary block init |
2399 | c99657d3 | blueswir1 | case 0xe3: // UA2007 Secondary block init |
2400 | 81ad8ba2 | blueswir1 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
2401 | 2aae2b8e | Igor V. Kovalenko | if (cpu_hypervisor_mode(env)) {
|
2402 | 6f27aba6 | blueswir1 | switch(size) {
|
2403 | 6f27aba6 | blueswir1 | case 1: |
2404 | 1a2fb1c0 | blueswir1 | ret = ldub_hypv(addr); |
2405 | 6f27aba6 | blueswir1 | break;
|
2406 | 6f27aba6 | blueswir1 | case 2: |
2407 | a4e7dd52 | blueswir1 | ret = lduw_hypv(addr); |
2408 | 6f27aba6 | blueswir1 | break;
|
2409 | 6f27aba6 | blueswir1 | case 4: |
2410 | a4e7dd52 | blueswir1 | ret = ldl_hypv(addr); |
2411 | 6f27aba6 | blueswir1 | break;
|
2412 | 6f27aba6 | blueswir1 | default:
|
2413 | 6f27aba6 | blueswir1 | case 8: |
2414 | a4e7dd52 | blueswir1 | ret = ldq_hypv(addr); |
2415 | 6f27aba6 | blueswir1 | break;
|
2416 | 6f27aba6 | blueswir1 | } |
2417 | 6f27aba6 | blueswir1 | } else {
|
2418 | 2065061e | Igor V. Kovalenko | /* secondary space access has lowest asi bit equal to 1 */
|
2419 | 2065061e | Igor V. Kovalenko | if (asi & 1) { |
2420 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2421 | 2065061e | Igor V. Kovalenko | case 1: |
2422 | 2065061e | Igor V. Kovalenko | ret = ldub_kernel_secondary(addr); |
2423 | 2065061e | Igor V. Kovalenko | break;
|
2424 | 2065061e | Igor V. Kovalenko | case 2: |
2425 | 2065061e | Igor V. Kovalenko | ret = lduw_kernel_secondary(addr); |
2426 | 2065061e | Igor V. Kovalenko | break;
|
2427 | 2065061e | Igor V. Kovalenko | case 4: |
2428 | 2065061e | Igor V. Kovalenko | ret = ldl_kernel_secondary(addr); |
2429 | 2065061e | Igor V. Kovalenko | break;
|
2430 | 2065061e | Igor V. Kovalenko | default:
|
2431 | 2065061e | Igor V. Kovalenko | case 8: |
2432 | 2065061e | Igor V. Kovalenko | ret = ldq_kernel_secondary(addr); |
2433 | 2065061e | Igor V. Kovalenko | break;
|
2434 | 2065061e | Igor V. Kovalenko | } |
2435 | 2065061e | Igor V. Kovalenko | } else {
|
2436 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2437 | 2065061e | Igor V. Kovalenko | case 1: |
2438 | 2065061e | Igor V. Kovalenko | ret = ldub_kernel(addr); |
2439 | 2065061e | Igor V. Kovalenko | break;
|
2440 | 2065061e | Igor V. Kovalenko | case 2: |
2441 | 2065061e | Igor V. Kovalenko | ret = lduw_kernel(addr); |
2442 | 2065061e | Igor V. Kovalenko | break;
|
2443 | 2065061e | Igor V. Kovalenko | case 4: |
2444 | 2065061e | Igor V. Kovalenko | ret = ldl_kernel(addr); |
2445 | 2065061e | Igor V. Kovalenko | break;
|
2446 | 2065061e | Igor V. Kovalenko | default:
|
2447 | 2065061e | Igor V. Kovalenko | case 8: |
2448 | 2065061e | Igor V. Kovalenko | ret = ldq_kernel(addr); |
2449 | 2065061e | Igor V. Kovalenko | break;
|
2450 | 2065061e | Igor V. Kovalenko | } |
2451 | 2065061e | Igor V. Kovalenko | } |
2452 | 2065061e | Igor V. Kovalenko | } |
2453 | 2065061e | Igor V. Kovalenko | } else {
|
2454 | 2065061e | Igor V. Kovalenko | /* secondary space access has lowest asi bit equal to 1 */
|
2455 | 2065061e | Igor V. Kovalenko | if (asi & 1) { |
2456 | 6f27aba6 | blueswir1 | switch(size) {
|
2457 | 6f27aba6 | blueswir1 | case 1: |
2458 | 2065061e | Igor V. Kovalenko | ret = ldub_user_secondary(addr); |
2459 | 6f27aba6 | blueswir1 | break;
|
2460 | 6f27aba6 | blueswir1 | case 2: |
2461 | 2065061e | Igor V. Kovalenko | ret = lduw_user_secondary(addr); |
2462 | 6f27aba6 | blueswir1 | break;
|
2463 | 6f27aba6 | blueswir1 | case 4: |
2464 | 2065061e | Igor V. Kovalenko | ret = ldl_user_secondary(addr); |
2465 | 6f27aba6 | blueswir1 | break;
|
2466 | 6f27aba6 | blueswir1 | default:
|
2467 | 6f27aba6 | blueswir1 | case 8: |
2468 | 2065061e | Igor V. Kovalenko | ret = ldq_user_secondary(addr); |
2469 | 2065061e | Igor V. Kovalenko | break;
|
2470 | 2065061e | Igor V. Kovalenko | } |
2471 | 2065061e | Igor V. Kovalenko | } else {
|
2472 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2473 | 2065061e | Igor V. Kovalenko | case 1: |
2474 | 2065061e | Igor V. Kovalenko | ret = ldub_user(addr); |
2475 | 2065061e | Igor V. Kovalenko | break;
|
2476 | 2065061e | Igor V. Kovalenko | case 2: |
2477 | 2065061e | Igor V. Kovalenko | ret = lduw_user(addr); |
2478 | 2065061e | Igor V. Kovalenko | break;
|
2479 | 2065061e | Igor V. Kovalenko | case 4: |
2480 | 2065061e | Igor V. Kovalenko | ret = ldl_user(addr); |
2481 | 2065061e | Igor V. Kovalenko | break;
|
2482 | 2065061e | Igor V. Kovalenko | default:
|
2483 | 2065061e | Igor V. Kovalenko | case 8: |
2484 | 2065061e | Igor V. Kovalenko | ret = ldq_user(addr); |
2485 | 6f27aba6 | blueswir1 | break;
|
2486 | 6f27aba6 | blueswir1 | } |
2487 | 81ad8ba2 | blueswir1 | } |
2488 | 81ad8ba2 | blueswir1 | } |
2489 | 81ad8ba2 | blueswir1 | break;
|
2490 | 3475187d | bellard | case 0x14: // Bypass |
2491 | 3475187d | bellard | case 0x15: // Bypass, non-cacheable |
2492 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
2493 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
2494 | 0f8a249a | blueswir1 | { |
2495 | 02aab46a | bellard | switch(size) {
|
2496 | 02aab46a | bellard | case 1: |
2497 | 1a2fb1c0 | blueswir1 | ret = ldub_phys(addr); |
2498 | 02aab46a | bellard | break;
|
2499 | 02aab46a | bellard | case 2: |
2500 | a4e7dd52 | blueswir1 | ret = lduw_phys(addr); |
2501 | 02aab46a | bellard | break;
|
2502 | 02aab46a | bellard | case 4: |
2503 | a4e7dd52 | blueswir1 | ret = ldl_phys(addr); |
2504 | 02aab46a | bellard | break;
|
2505 | 02aab46a | bellard | default:
|
2506 | 02aab46a | bellard | case 8: |
2507 | a4e7dd52 | blueswir1 | ret = ldq_phys(addr); |
2508 | 02aab46a | bellard | break;
|
2509 | 02aab46a | bellard | } |
2510 | 0f8a249a | blueswir1 | break;
|
2511 | 0f8a249a | blueswir1 | } |
2512 | db166940 | blueswir1 | case 0x24: // Nucleus quad LDD 128 bit atomic |
2513 | db166940 | blueswir1 | case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
2514 | db166940 | blueswir1 | // Only ldda allowed
|
2515 | db166940 | blueswir1 | raise_exception(TT_ILL_INSN); |
2516 | db166940 | blueswir1 | return 0; |
2517 | 83469015 | bellard | case 0x04: // Nucleus |
2518 | 83469015 | bellard | case 0x0c: // Nucleus Little Endian (LE) |
2519 | 2065061e | Igor V. Kovalenko | { |
2520 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2521 | 2065061e | Igor V. Kovalenko | case 1: |
2522 | 2065061e | Igor V. Kovalenko | ret = ldub_nucleus(addr); |
2523 | 2065061e | Igor V. Kovalenko | break;
|
2524 | 2065061e | Igor V. Kovalenko | case 2: |
2525 | 2065061e | Igor V. Kovalenko | ret = lduw_nucleus(addr); |
2526 | 2065061e | Igor V. Kovalenko | break;
|
2527 | 2065061e | Igor V. Kovalenko | case 4: |
2528 | 2065061e | Igor V. Kovalenko | ret = ldl_nucleus(addr); |
2529 | 2065061e | Igor V. Kovalenko | break;
|
2530 | 2065061e | Igor V. Kovalenko | default:
|
2531 | 2065061e | Igor V. Kovalenko | case 8: |
2532 | 2065061e | Igor V. Kovalenko | ret = ldq_nucleus(addr); |
2533 | 2065061e | Igor V. Kovalenko | break;
|
2534 | 2065061e | Igor V. Kovalenko | } |
2535 | 2065061e | Igor V. Kovalenko | break;
|
2536 | 2065061e | Igor V. Kovalenko | } |
2537 | 83469015 | bellard | case 0x4a: // UPA config |
2538 | 0f8a249a | blueswir1 | // XXX
|
2539 | 0f8a249a | blueswir1 | break;
|
2540 | 3475187d | bellard | case 0x45: // LSU |
2541 | 0f8a249a | blueswir1 | ret = env->lsu; |
2542 | 0f8a249a | blueswir1 | break;
|
2543 | 3475187d | bellard | case 0x50: // I-MMU regs |
2544 | 0f8a249a | blueswir1 | { |
2545 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
2546 | 3475187d | bellard | |
2547 | 697a77e6 | Igor Kovalenko | if (reg == 0) { |
2548 | 697a77e6 | Igor Kovalenko | // I-TSB Tag Target register
|
2549 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tag_target(env->immu.tag_access); |
2550 | 697a77e6 | Igor Kovalenko | } else {
|
2551 | 697a77e6 | Igor Kovalenko | ret = env->immuregs[reg]; |
2552 | 697a77e6 | Igor Kovalenko | } |
2553 | 697a77e6 | Igor Kovalenko | |
2554 | 0f8a249a | blueswir1 | break;
|
2555 | 0f8a249a | blueswir1 | } |
2556 | 3475187d | bellard | case 0x51: // I-MMU 8k TSB pointer |
2557 | 697a77e6 | Igor Kovalenko | { |
2558 | 697a77e6 | Igor Kovalenko | // env->immuregs[5] holds I-MMU TSB register value
|
2559 | 697a77e6 | Igor Kovalenko | // env->immuregs[6] holds I-MMU Tag Access register value
|
2560 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, |
2561 | 697a77e6 | Igor Kovalenko | 8*1024); |
2562 | 697a77e6 | Igor Kovalenko | break;
|
2563 | 697a77e6 | Igor Kovalenko | } |
2564 | 3475187d | bellard | case 0x52: // I-MMU 64k TSB pointer |
2565 | 697a77e6 | Igor Kovalenko | { |
2566 | 697a77e6 | Igor Kovalenko | // env->immuregs[5] holds I-MMU TSB register value
|
2567 | 697a77e6 | Igor Kovalenko | // env->immuregs[6] holds I-MMU Tag Access register value
|
2568 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, |
2569 | 697a77e6 | Igor Kovalenko | 64*1024); |
2570 | 697a77e6 | Igor Kovalenko | break;
|
2571 | 697a77e6 | Igor Kovalenko | } |
2572 | a5a52cf2 | blueswir1 | case 0x55: // I-MMU data access |
2573 | a5a52cf2 | blueswir1 | { |
2574 | a5a52cf2 | blueswir1 | int reg = (addr >> 3) & 0x3f; |
2575 | a5a52cf2 | blueswir1 | |
2576 | 6e8e7d4c | Igor Kovalenko | ret = env->itlb[reg].tte; |
2577 | a5a52cf2 | blueswir1 | break;
|
2578 | a5a52cf2 | blueswir1 | } |
2579 | 83469015 | bellard | case 0x56: // I-MMU tag read |
2580 | 0f8a249a | blueswir1 | { |
2581 | 43e9e742 | blueswir1 | int reg = (addr >> 3) & 0x3f; |
2582 | 0f8a249a | blueswir1 | |
2583 | 6e8e7d4c | Igor Kovalenko | ret = env->itlb[reg].tag; |
2584 | 0f8a249a | blueswir1 | break;
|
2585 | 0f8a249a | blueswir1 | } |
2586 | 3475187d | bellard | case 0x58: // D-MMU regs |
2587 | 0f8a249a | blueswir1 | { |
2588 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
2589 | 3475187d | bellard | |
2590 | 697a77e6 | Igor Kovalenko | if (reg == 0) { |
2591 | 697a77e6 | Igor Kovalenko | // D-TSB Tag Target register
|
2592 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tag_target(env->dmmu.tag_access); |
2593 | 697a77e6 | Igor Kovalenko | } else {
|
2594 | 697a77e6 | Igor Kovalenko | ret = env->dmmuregs[reg]; |
2595 | 697a77e6 | Igor Kovalenko | } |
2596 | 697a77e6 | Igor Kovalenko | break;
|
2597 | 697a77e6 | Igor Kovalenko | } |
2598 | 697a77e6 | Igor Kovalenko | case 0x59: // D-MMU 8k TSB pointer |
2599 | 697a77e6 | Igor Kovalenko | { |
2600 | 697a77e6 | Igor Kovalenko | // env->dmmuregs[5] holds D-MMU TSB register value
|
2601 | 697a77e6 | Igor Kovalenko | // env->dmmuregs[6] holds D-MMU Tag Access register value
|
2602 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, |
2603 | 697a77e6 | Igor Kovalenko | 8*1024); |
2604 | 697a77e6 | Igor Kovalenko | break;
|
2605 | 697a77e6 | Igor Kovalenko | } |
2606 | 697a77e6 | Igor Kovalenko | case 0x5a: // D-MMU 64k TSB pointer |
2607 | 697a77e6 | Igor Kovalenko | { |
2608 | 697a77e6 | Igor Kovalenko | // env->dmmuregs[5] holds D-MMU TSB register value
|
2609 | 697a77e6 | Igor Kovalenko | // env->dmmuregs[6] holds D-MMU Tag Access register value
|
2610 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, |
2611 | 697a77e6 | Igor Kovalenko | 64*1024); |
2612 | 0f8a249a | blueswir1 | break;
|
2613 | 0f8a249a | blueswir1 | } |
2614 | a5a52cf2 | blueswir1 | case 0x5d: // D-MMU data access |
2615 | a5a52cf2 | blueswir1 | { |
2616 | a5a52cf2 | blueswir1 | int reg = (addr >> 3) & 0x3f; |
2617 | a5a52cf2 | blueswir1 | |
2618 | 6e8e7d4c | Igor Kovalenko | ret = env->dtlb[reg].tte; |
2619 | a5a52cf2 | blueswir1 | break;
|
2620 | a5a52cf2 | blueswir1 | } |
2621 | 83469015 | bellard | case 0x5e: // D-MMU tag read |
2622 | 0f8a249a | blueswir1 | { |
2623 | 43e9e742 | blueswir1 | int reg = (addr >> 3) & 0x3f; |
2624 | 0f8a249a | blueswir1 | |
2625 | 6e8e7d4c | Igor Kovalenko | ret = env->dtlb[reg].tag; |
2626 | 0f8a249a | blueswir1 | break;
|
2627 | 0f8a249a | blueswir1 | } |
2628 | f7350b47 | blueswir1 | case 0x46: // D-cache data |
2629 | f7350b47 | blueswir1 | case 0x47: // D-cache tag access |
2630 | a5a52cf2 | blueswir1 | case 0x4b: // E-cache error enable |
2631 | a5a52cf2 | blueswir1 | case 0x4c: // E-cache asynchronous fault status |
2632 | a5a52cf2 | blueswir1 | case 0x4d: // E-cache asynchronous fault address |
2633 | f7350b47 | blueswir1 | case 0x4e: // E-cache tag data |
2634 | f7350b47 | blueswir1 | case 0x66: // I-cache instruction access |
2635 | f7350b47 | blueswir1 | case 0x67: // I-cache tag access |
2636 | f7350b47 | blueswir1 | case 0x6e: // I-cache predecode |
2637 | f7350b47 | blueswir1 | case 0x6f: // I-cache LRU etc. |
2638 | f7350b47 | blueswir1 | case 0x76: // E-cache tag |
2639 | f7350b47 | blueswir1 | case 0x7e: // E-cache tag |
2640 | f7350b47 | blueswir1 | break;
|
2641 | 3475187d | bellard | case 0x5b: // D-MMU data pointer |
2642 | 83469015 | bellard | case 0x48: // Interrupt dispatch, RO |
2643 | 83469015 | bellard | case 0x49: // Interrupt data receive |
2644 | 83469015 | bellard | case 0x7f: // Incoming interrupt vector, RO |
2645 | 0f8a249a | blueswir1 | // XXX
|
2646 | 0f8a249a | blueswir1 | break;
|
2647 | 3475187d | bellard | case 0x54: // I-MMU data in, WO |
2648 | 3475187d | bellard | case 0x57: // I-MMU demap, WO |
2649 | 3475187d | bellard | case 0x5c: // D-MMU data in, WO |
2650 | 3475187d | bellard | case 0x5f: // D-MMU demap, WO |
2651 | 83469015 | bellard | case 0x77: // Interrupt vector, WO |
2652 | 3475187d | bellard | default:
|
2653 | e18231a3 | blueswir1 | do_unassigned_access(addr, 0, 0, 1, size); |
2654 | 0f8a249a | blueswir1 | ret = 0;
|
2655 | 0f8a249a | blueswir1 | break;
|
2656 | 3475187d | bellard | } |
2657 | 81ad8ba2 | blueswir1 | |
2658 | 81ad8ba2 | blueswir1 | /* Convert from little endian */
|
2659 | 81ad8ba2 | blueswir1 | switch (asi) {
|
2660 | 81ad8ba2 | blueswir1 | case 0x0c: // Nucleus Little Endian (LE) |
2661 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
2662 | 81ad8ba2 | blueswir1 | case 0x19: // As if user secondary LE |
2663 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
2664 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
2665 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2666 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
2667 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
2668 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
2669 | 81ad8ba2 | blueswir1 | switch(size) {
|
2670 | 81ad8ba2 | blueswir1 | case 2: |
2671 | 81ad8ba2 | blueswir1 | ret = bswap16(ret); |
2672 | e32664fb | blueswir1 | break;
|
2673 | 81ad8ba2 | blueswir1 | case 4: |
2674 | 81ad8ba2 | blueswir1 | ret = bswap32(ret); |
2675 | e32664fb | blueswir1 | break;
|
2676 | 81ad8ba2 | blueswir1 | case 8: |
2677 | 81ad8ba2 | blueswir1 | ret = bswap64(ret); |
2678 | e32664fb | blueswir1 | break;
|
2679 | 81ad8ba2 | blueswir1 | default:
|
2680 | 81ad8ba2 | blueswir1 | break;
|
2681 | 81ad8ba2 | blueswir1 | } |
2682 | 81ad8ba2 | blueswir1 | default:
|
2683 | 81ad8ba2 | blueswir1 | break;
|
2684 | 81ad8ba2 | blueswir1 | } |
2685 | 81ad8ba2 | blueswir1 | |
2686 | 81ad8ba2 | blueswir1 | /* Convert to signed number */
|
2687 | 81ad8ba2 | blueswir1 | if (sign) {
|
2688 | 81ad8ba2 | blueswir1 | switch(size) {
|
2689 | 81ad8ba2 | blueswir1 | case 1: |
2690 | 81ad8ba2 | blueswir1 | ret = (int8_t) ret; |
2691 | e32664fb | blueswir1 | break;
|
2692 | 81ad8ba2 | blueswir1 | case 2: |
2693 | 81ad8ba2 | blueswir1 | ret = (int16_t) ret; |
2694 | e32664fb | blueswir1 | break;
|
2695 | 81ad8ba2 | blueswir1 | case 4: |
2696 | 81ad8ba2 | blueswir1 | ret = (int32_t) ret; |
2697 | e32664fb | blueswir1 | break;
|
2698 | 81ad8ba2 | blueswir1 | default:
|
2699 | 81ad8ba2 | blueswir1 | break;
|
2700 | 81ad8ba2 | blueswir1 | } |
2701 | 81ad8ba2 | blueswir1 | } |
2702 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
2703 | 1a2fb1c0 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
2704 | 1a2fb1c0 | blueswir1 | #endif
|
2705 | 1a2fb1c0 | blueswir1 | return ret;
|
2706 | 3475187d | bellard | } |
2707 | 3475187d | bellard | |
2708 | 1a2fb1c0 | blueswir1 | void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
2709 | 3475187d | bellard | { |
2710 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
2711 | 1a2fb1c0 | blueswir1 | dump_asi("write", addr, asi, size, val);
|
2712 | 1a2fb1c0 | blueswir1 | #endif
|
2713 | 01b5d4e5 | Igor V. Kovalenko | |
2714 | 01b5d4e5 | Igor V. Kovalenko | asi &= 0xff;
|
2715 | 01b5d4e5 | Igor V. Kovalenko | |
2716 | 6f27aba6 | blueswir1 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
2717 | 2aae2b8e | Igor V. Kovalenko | || (cpu_has_hypervisor(env) |
2718 | 5578ceab | blueswir1 | && asi >= 0x30 && asi < 0x80 |
2719 | fb79ceb9 | blueswir1 | && !(env->hpstate & HS_PRIV))) |
2720 | 0f8a249a | blueswir1 | raise_exception(TT_PRIV_ACT); |
2721 | 3475187d | bellard | |
2722 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
2723 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
2724 | 1295001c | Igor V. Kovalenko | |
2725 | 81ad8ba2 | blueswir1 | /* Convert to little endian */
|
2726 | 81ad8ba2 | blueswir1 | switch (asi) {
|
2727 | 81ad8ba2 | blueswir1 | case 0x0c: // Nucleus Little Endian (LE) |
2728 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
2729 | 81ad8ba2 | blueswir1 | case 0x19: // As if user secondary LE |
2730 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
2731 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
2732 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2733 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
2734 | 81ad8ba2 | blueswir1 | switch(size) {
|
2735 | 81ad8ba2 | blueswir1 | case 2: |
2736 | 5b0f0bec | Igor Kovalenko | val = bswap16(val); |
2737 | e32664fb | blueswir1 | break;
|
2738 | 81ad8ba2 | blueswir1 | case 4: |
2739 | 5b0f0bec | Igor Kovalenko | val = bswap32(val); |
2740 | e32664fb | blueswir1 | break;
|
2741 | 81ad8ba2 | blueswir1 | case 8: |
2742 | 5b0f0bec | Igor Kovalenko | val = bswap64(val); |
2743 | e32664fb | blueswir1 | break;
|
2744 | 81ad8ba2 | blueswir1 | default:
|
2745 | 81ad8ba2 | blueswir1 | break;
|
2746 | 81ad8ba2 | blueswir1 | } |
2747 | 81ad8ba2 | blueswir1 | default:
|
2748 | 81ad8ba2 | blueswir1 | break;
|
2749 | 81ad8ba2 | blueswir1 | } |
2750 | 81ad8ba2 | blueswir1 | |
2751 | 3475187d | bellard | switch(asi) {
|
2752 | 81ad8ba2 | blueswir1 | case 0x10: // As if user primary |
2753 | 2065061e | Igor V. Kovalenko | case 0x11: // As if user secondary |
2754 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
2755 | 2065061e | Igor V. Kovalenko | case 0x19: // As if user secondary LE |
2756 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
2757 | 2065061e | Igor V. Kovalenko | case 0x81: // Secondary |
2758 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2759 | 2065061e | Igor V. Kovalenko | case 0x89: // Secondary LE |
2760 | c99657d3 | blueswir1 | case 0xe2: // UA2007 Primary block init |
2761 | c99657d3 | blueswir1 | case 0xe3: // UA2007 Secondary block init |
2762 | 81ad8ba2 | blueswir1 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
2763 | 2aae2b8e | Igor V. Kovalenko | if (cpu_hypervisor_mode(env)) {
|
2764 | 6f27aba6 | blueswir1 | switch(size) {
|
2765 | 6f27aba6 | blueswir1 | case 1: |
2766 | 1a2fb1c0 | blueswir1 | stb_hypv(addr, val); |
2767 | 6f27aba6 | blueswir1 | break;
|
2768 | 6f27aba6 | blueswir1 | case 2: |
2769 | a4e7dd52 | blueswir1 | stw_hypv(addr, val); |
2770 | 6f27aba6 | blueswir1 | break;
|
2771 | 6f27aba6 | blueswir1 | case 4: |
2772 | a4e7dd52 | blueswir1 | stl_hypv(addr, val); |
2773 | 6f27aba6 | blueswir1 | break;
|
2774 | 6f27aba6 | blueswir1 | case 8: |
2775 | 6f27aba6 | blueswir1 | default:
|
2776 | a4e7dd52 | blueswir1 | stq_hypv(addr, val); |
2777 | 6f27aba6 | blueswir1 | break;
|
2778 | 6f27aba6 | blueswir1 | } |
2779 | 6f27aba6 | blueswir1 | } else {
|
2780 | 2065061e | Igor V. Kovalenko | /* secondary space access has lowest asi bit equal to 1 */
|
2781 | 2065061e | Igor V. Kovalenko | if (asi & 1) { |
2782 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2783 | 2065061e | Igor V. Kovalenko | case 1: |
2784 | 2065061e | Igor V. Kovalenko | stb_kernel_secondary(addr, val); |
2785 | 2065061e | Igor V. Kovalenko | break;
|
2786 | 2065061e | Igor V. Kovalenko | case 2: |
2787 | 2065061e | Igor V. Kovalenko | stw_kernel_secondary(addr, val); |
2788 | 2065061e | Igor V. Kovalenko | break;
|
2789 | 2065061e | Igor V. Kovalenko | case 4: |
2790 | 2065061e | Igor V. Kovalenko | stl_kernel_secondary(addr, val); |
2791 | 2065061e | Igor V. Kovalenko | break;
|
2792 | 2065061e | Igor V. Kovalenko | case 8: |
2793 | 2065061e | Igor V. Kovalenko | default:
|
2794 | 2065061e | Igor V. Kovalenko | stq_kernel_secondary(addr, val); |
2795 | 2065061e | Igor V. Kovalenko | break;
|
2796 | 2065061e | Igor V. Kovalenko | } |
2797 | 2065061e | Igor V. Kovalenko | } else {
|
2798 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2799 | 2065061e | Igor V. Kovalenko | case 1: |
2800 | 2065061e | Igor V. Kovalenko | stb_kernel(addr, val); |
2801 | 2065061e | Igor V. Kovalenko | break;
|
2802 | 2065061e | Igor V. Kovalenko | case 2: |
2803 | 2065061e | Igor V. Kovalenko | stw_kernel(addr, val); |
2804 | 2065061e | Igor V. Kovalenko | break;
|
2805 | 2065061e | Igor V. Kovalenko | case 4: |
2806 | 2065061e | Igor V. Kovalenko | stl_kernel(addr, val); |
2807 | 2065061e | Igor V. Kovalenko | break;
|
2808 | 2065061e | Igor V. Kovalenko | case 8: |
2809 | 2065061e | Igor V. Kovalenko | default:
|
2810 | 2065061e | Igor V. Kovalenko | stq_kernel(addr, val); |
2811 | 2065061e | Igor V. Kovalenko | break;
|
2812 | 2065061e | Igor V. Kovalenko | } |
2813 | 2065061e | Igor V. Kovalenko | } |
2814 | 2065061e | Igor V. Kovalenko | } |
2815 | 2065061e | Igor V. Kovalenko | } else {
|
2816 | 2065061e | Igor V. Kovalenko | /* secondary space access has lowest asi bit equal to 1 */
|
2817 | 2065061e | Igor V. Kovalenko | if (asi & 1) { |
2818 | 6f27aba6 | blueswir1 | switch(size) {
|
2819 | 6f27aba6 | blueswir1 | case 1: |
2820 | 2065061e | Igor V. Kovalenko | stb_user_secondary(addr, val); |
2821 | 6f27aba6 | blueswir1 | break;
|
2822 | 6f27aba6 | blueswir1 | case 2: |
2823 | 2065061e | Igor V. Kovalenko | stw_user_secondary(addr, val); |
2824 | 6f27aba6 | blueswir1 | break;
|
2825 | 6f27aba6 | blueswir1 | case 4: |
2826 | 2065061e | Igor V. Kovalenko | stl_user_secondary(addr, val); |
2827 | 6f27aba6 | blueswir1 | break;
|
2828 | 6f27aba6 | blueswir1 | case 8: |
2829 | 6f27aba6 | blueswir1 | default:
|
2830 | 2065061e | Igor V. Kovalenko | stq_user_secondary(addr, val); |
2831 | 2065061e | Igor V. Kovalenko | break;
|
2832 | 2065061e | Igor V. Kovalenko | } |
2833 | 2065061e | Igor V. Kovalenko | } else {
|
2834 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2835 | 2065061e | Igor V. Kovalenko | case 1: |
2836 | 2065061e | Igor V. Kovalenko | stb_user(addr, val); |
2837 | 2065061e | Igor V. Kovalenko | break;
|
2838 | 2065061e | Igor V. Kovalenko | case 2: |
2839 | 2065061e | Igor V. Kovalenko | stw_user(addr, val); |
2840 | 2065061e | Igor V. Kovalenko | break;
|
2841 | 2065061e | Igor V. Kovalenko | case 4: |
2842 | 2065061e | Igor V. Kovalenko | stl_user(addr, val); |
2843 | 2065061e | Igor V. Kovalenko | break;
|
2844 | 2065061e | Igor V. Kovalenko | case 8: |
2845 | 2065061e | Igor V. Kovalenko | default:
|
2846 | 2065061e | Igor V. Kovalenko | stq_user(addr, val); |
2847 | 6f27aba6 | blueswir1 | break;
|
2848 | 6f27aba6 | blueswir1 | } |
2849 | 81ad8ba2 | blueswir1 | } |
2850 | 81ad8ba2 | blueswir1 | } |
2851 | 81ad8ba2 | blueswir1 | break;
|
2852 | 3475187d | bellard | case 0x14: // Bypass |
2853 | 3475187d | bellard | case 0x15: // Bypass, non-cacheable |
2854 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
2855 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
2856 | 0f8a249a | blueswir1 | { |
2857 | 02aab46a | bellard | switch(size) {
|
2858 | 02aab46a | bellard | case 1: |
2859 | 1a2fb1c0 | blueswir1 | stb_phys(addr, val); |
2860 | 02aab46a | bellard | break;
|
2861 | 02aab46a | bellard | case 2: |
2862 | a4e7dd52 | blueswir1 | stw_phys(addr, val); |
2863 | 02aab46a | bellard | break;
|
2864 | 02aab46a | bellard | case 4: |
2865 | a4e7dd52 | blueswir1 | stl_phys(addr, val); |
2866 | 02aab46a | bellard | break;
|
2867 | 02aab46a | bellard | case 8: |
2868 | 02aab46a | bellard | default:
|
2869 | a4e7dd52 | blueswir1 | stq_phys(addr, val); |
2870 | 02aab46a | bellard | break;
|
2871 | 02aab46a | bellard | } |
2872 | 0f8a249a | blueswir1 | } |
2873 | 0f8a249a | blueswir1 | return;
|
2874 | db166940 | blueswir1 | case 0x24: // Nucleus quad LDD 128 bit atomic |
2875 | db166940 | blueswir1 | case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
2876 | db166940 | blueswir1 | // Only ldda allowed
|
2877 | db166940 | blueswir1 | raise_exception(TT_ILL_INSN); |
2878 | db166940 | blueswir1 | return;
|
2879 | 83469015 | bellard | case 0x04: // Nucleus |
2880 | 83469015 | bellard | case 0x0c: // Nucleus Little Endian (LE) |
2881 | 2065061e | Igor V. Kovalenko | { |
2882 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2883 | 2065061e | Igor V. Kovalenko | case 1: |
2884 | 2065061e | Igor V. Kovalenko | stb_nucleus(addr, val); |
2885 | 2065061e | Igor V. Kovalenko | break;
|
2886 | 2065061e | Igor V. Kovalenko | case 2: |
2887 | 2065061e | Igor V. Kovalenko | stw_nucleus(addr, val); |
2888 | 2065061e | Igor V. Kovalenko | break;
|
2889 | 2065061e | Igor V. Kovalenko | case 4: |
2890 | 2065061e | Igor V. Kovalenko | stl_nucleus(addr, val); |
2891 | 2065061e | Igor V. Kovalenko | break;
|
2892 | 2065061e | Igor V. Kovalenko | default:
|
2893 | 2065061e | Igor V. Kovalenko | case 8: |
2894 | 2065061e | Igor V. Kovalenko | stq_nucleus(addr, val); |
2895 | 2065061e | Igor V. Kovalenko | break;
|
2896 | 2065061e | Igor V. Kovalenko | } |
2897 | 2065061e | Igor V. Kovalenko | break;
|
2898 | 2065061e | Igor V. Kovalenko | } |
2899 | 2065061e | Igor V. Kovalenko | |
2900 | 83469015 | bellard | case 0x4a: // UPA config |
2901 | 0f8a249a | blueswir1 | // XXX
|
2902 | 0f8a249a | blueswir1 | return;
|
2903 | 3475187d | bellard | case 0x45: // LSU |
2904 | 0f8a249a | blueswir1 | { |
2905 | 0f8a249a | blueswir1 | uint64_t oldreg; |
2906 | 0f8a249a | blueswir1 | |
2907 | 0f8a249a | blueswir1 | oldreg = env->lsu; |
2908 | 1a2fb1c0 | blueswir1 | env->lsu = val & (DMMU_E | IMMU_E); |
2909 | 0f8a249a | blueswir1 | // Mappings generated during D/I MMU disabled mode are
|
2910 | 0f8a249a | blueswir1 | // invalid in normal mode
|
2911 | 0f8a249a | blueswir1 | if (oldreg != env->lsu) {
|
2912 | 77f193da | blueswir1 | DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", |
2913 | 77f193da | blueswir1 | oldreg, env->lsu); |
2914 | 83469015 | bellard | #ifdef DEBUG_MMU
|
2915 | 0f8a249a | blueswir1 | dump_mmu(env); |
2916 | 83469015 | bellard | #endif
|
2917 | 0f8a249a | blueswir1 | tlb_flush(env, 1);
|
2918 | 0f8a249a | blueswir1 | } |
2919 | 0f8a249a | blueswir1 | return;
|
2920 | 0f8a249a | blueswir1 | } |
2921 | 3475187d | bellard | case 0x50: // I-MMU regs |
2922 | 0f8a249a | blueswir1 | { |
2923 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
2924 | 0f8a249a | blueswir1 | uint64_t oldreg; |
2925 | 3b46e624 | ths | |
2926 | 0f8a249a | blueswir1 | oldreg = env->immuregs[reg]; |
2927 | 3475187d | bellard | switch(reg) {
|
2928 | 3475187d | bellard | case 0: // RO |
2929 | 3475187d | bellard | return;
|
2930 | 3475187d | bellard | case 1: // Not in I-MMU |
2931 | 3475187d | bellard | case 2: |
2932 | 3475187d | bellard | return;
|
2933 | 3475187d | bellard | case 3: // SFSR |
2934 | 1a2fb1c0 | blueswir1 | if ((val & 1) == 0) |
2935 | 1a2fb1c0 | blueswir1 | val = 0; // Clear SFSR |
2936 | 6e8e7d4c | Igor Kovalenko | env->immu.sfsr = val; |
2937 | 3475187d | bellard | break;
|
2938 | 6e8e7d4c | Igor Kovalenko | case 4: // RO |
2939 | 6e8e7d4c | Igor Kovalenko | return;
|
2940 | 3475187d | bellard | case 5: // TSB access |
2941 | 6e8e7d4c | Igor Kovalenko | DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" |
2942 | 6e8e7d4c | Igor Kovalenko | PRIx64 "\n", env->immu.tsb, val);
|
2943 | 6e8e7d4c | Igor Kovalenko | env->immu.tsb = val; |
2944 | 6e8e7d4c | Igor Kovalenko | break;
|
2945 | 3475187d | bellard | case 6: // Tag access |
2946 | 6e8e7d4c | Igor Kovalenko | env->immu.tag_access = val; |
2947 | 6e8e7d4c | Igor Kovalenko | break;
|
2948 | 6e8e7d4c | Igor Kovalenko | case 7: |
2949 | 6e8e7d4c | Igor Kovalenko | case 8: |
2950 | 6e8e7d4c | Igor Kovalenko | return;
|
2951 | 3475187d | bellard | default:
|
2952 | 3475187d | bellard | break;
|
2953 | 3475187d | bellard | } |
2954 | 6e8e7d4c | Igor Kovalenko | |
2955 | 3475187d | bellard | if (oldreg != env->immuregs[reg]) {
|
2956 | 6e8e7d4c | Igor Kovalenko | DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" |
2957 | 77f193da | blueswir1 | PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
|
2958 | 3475187d | bellard | } |
2959 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
|
2960 | 0f8a249a | blueswir1 | dump_mmu(env); |
2961 | 3475187d | bellard | #endif
|
2962 | 0f8a249a | blueswir1 | return;
|
2963 | 0f8a249a | blueswir1 | } |
2964 | 3475187d | bellard | case 0x54: // I-MMU data in |
2965 | f707726e | Igor Kovalenko | replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
|
2966 | f707726e | Igor Kovalenko | return;
|
2967 | 3475187d | bellard | case 0x55: // I-MMU data access |
2968 | 0f8a249a | blueswir1 | { |
2969 | cc6747f4 | blueswir1 | // TODO: auto demap
|
2970 | cc6747f4 | blueswir1 | |
2971 | 1a2fb1c0 | blueswir1 | unsigned int i = (addr >> 3) & 0x3f; |
2972 | 3475187d | bellard | |
2973 | f707726e | Igor Kovalenko | replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env); |
2974 | 6e8e7d4c | Igor Kovalenko | |
2975 | 6e8e7d4c | Igor Kovalenko | #ifdef DEBUG_MMU
|
2976 | f707726e | Igor Kovalenko | DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
|
2977 | 6e8e7d4c | Igor Kovalenko | dump_mmu(env); |
2978 | 6e8e7d4c | Igor Kovalenko | #endif
|
2979 | 0f8a249a | blueswir1 | return;
|
2980 | 0f8a249a | blueswir1 | } |
2981 | 3475187d | bellard | case 0x57: // I-MMU demap |
2982 | 170f4c55 | Igor V. Kovalenko | demap_tlb(env->itlb, addr, "immu", env);
|
2983 | 0f8a249a | blueswir1 | return;
|
2984 | 3475187d | bellard | case 0x58: // D-MMU regs |
2985 | 0f8a249a | blueswir1 | { |
2986 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
2987 | 0f8a249a | blueswir1 | uint64_t oldreg; |
2988 | 3b46e624 | ths | |
2989 | 0f8a249a | blueswir1 | oldreg = env->dmmuregs[reg]; |
2990 | 3475187d | bellard | switch(reg) {
|
2991 | 3475187d | bellard | case 0: // RO |
2992 | 3475187d | bellard | case 4: |
2993 | 3475187d | bellard | return;
|
2994 | 3475187d | bellard | case 3: // SFSR |
2995 | 1a2fb1c0 | blueswir1 | if ((val & 1) == 0) { |
2996 | 1a2fb1c0 | blueswir1 | val = 0; // Clear SFSR, Fault address |
2997 | 6e8e7d4c | Igor Kovalenko | env->dmmu.sfar = 0;
|
2998 | 0f8a249a | blueswir1 | } |
2999 | 6e8e7d4c | Igor Kovalenko | env->dmmu.sfsr = val; |
3000 | 3475187d | bellard | break;
|
3001 | 3475187d | bellard | case 1: // Primary context |
3002 | 6e8e7d4c | Igor Kovalenko | env->dmmu.mmu_primary_context = val; |
3003 | 664a65b0 | Igor V. Kovalenko | /* can be optimized to only flush MMU_USER_IDX
|
3004 | 664a65b0 | Igor V. Kovalenko | and MMU_KERNEL_IDX entries */
|
3005 | 664a65b0 | Igor V. Kovalenko | tlb_flush(env, 1);
|
3006 | 6e8e7d4c | Igor Kovalenko | break;
|
3007 | 3475187d | bellard | case 2: // Secondary context |
3008 | 6e8e7d4c | Igor Kovalenko | env->dmmu.mmu_secondary_context = val; |
3009 | 664a65b0 | Igor V. Kovalenko | /* can be optimized to only flush MMU_USER_SECONDARY_IDX
|
3010 | 664a65b0 | Igor V. Kovalenko | and MMU_KERNEL_SECONDARY_IDX entries */
|
3011 | 664a65b0 | Igor V. Kovalenko | tlb_flush(env, 1);
|
3012 | 6e8e7d4c | Igor Kovalenko | break;
|
3013 | 3475187d | bellard | case 5: // TSB access |
3014 | 6e8e7d4c | Igor Kovalenko | DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" |
3015 | 6e8e7d4c | Igor Kovalenko | PRIx64 "\n", env->dmmu.tsb, val);
|
3016 | 6e8e7d4c | Igor Kovalenko | env->dmmu.tsb = val; |
3017 | 6e8e7d4c | Igor Kovalenko | break;
|
3018 | 3475187d | bellard | case 6: // Tag access |
3019 | 6e8e7d4c | Igor Kovalenko | env->dmmu.tag_access = val; |
3020 | 6e8e7d4c | Igor Kovalenko | break;
|
3021 | 3475187d | bellard | case 7: // Virtual Watchpoint |
3022 | 3475187d | bellard | case 8: // Physical Watchpoint |
3023 | 3475187d | bellard | default:
|
3024 | 6e8e7d4c | Igor Kovalenko | env->dmmuregs[reg] = val; |
3025 | 3475187d | bellard | break;
|
3026 | 3475187d | bellard | } |
3027 | 6e8e7d4c | Igor Kovalenko | |
3028 | 3475187d | bellard | if (oldreg != env->dmmuregs[reg]) {
|
3029 | 6e8e7d4c | Igor Kovalenko | DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" |
3030 | 77f193da | blueswir1 | PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
|
3031 | 3475187d | bellard | } |
3032 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
|
3033 | 0f8a249a | blueswir1 | dump_mmu(env); |
3034 | 3475187d | bellard | #endif
|
3035 | 0f8a249a | blueswir1 | return;
|
3036 | 0f8a249a | blueswir1 | } |
3037 | 3475187d | bellard | case 0x5c: // D-MMU data in |
3038 | f707726e | Igor Kovalenko | replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
|
3039 | f707726e | Igor Kovalenko | return;
|
3040 | 3475187d | bellard | case 0x5d: // D-MMU data access |
3041 | 0f8a249a | blueswir1 | { |
3042 | 1a2fb1c0 | blueswir1 | unsigned int i = (addr >> 3) & 0x3f; |
3043 | 3475187d | bellard | |
3044 | f707726e | Igor Kovalenko | replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env); |
3045 | f707726e | Igor Kovalenko | |
3046 | 6e8e7d4c | Igor Kovalenko | #ifdef DEBUG_MMU
|
3047 | f707726e | Igor Kovalenko | DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
|
3048 | 6e8e7d4c | Igor Kovalenko | dump_mmu(env); |
3049 | 6e8e7d4c | Igor Kovalenko | #endif
|
3050 | 0f8a249a | blueswir1 | return;
|
3051 | 0f8a249a | blueswir1 | } |
3052 | 3475187d | bellard | case 0x5f: // D-MMU demap |
3053 | 170f4c55 | Igor V. Kovalenko | demap_tlb(env->dtlb, addr, "dmmu", env);
|
3054 | cc6747f4 | blueswir1 | return;
|
3055 | 83469015 | bellard | case 0x49: // Interrupt data receive |
3056 | 0f8a249a | blueswir1 | // XXX
|
3057 | 0f8a249a | blueswir1 | return;
|
3058 | f7350b47 | blueswir1 | case 0x46: // D-cache data |
3059 | f7350b47 | blueswir1 | case 0x47: // D-cache tag access |
3060 | a5a52cf2 | blueswir1 | case 0x4b: // E-cache error enable |
3061 | a5a52cf2 | blueswir1 | case 0x4c: // E-cache asynchronous fault status |
3062 | a5a52cf2 | blueswir1 | case 0x4d: // E-cache asynchronous fault address |
3063 | f7350b47 | blueswir1 | case 0x4e: // E-cache tag data |
3064 | f7350b47 | blueswir1 | case 0x66: // I-cache instruction access |
3065 | f7350b47 | blueswir1 | case 0x67: // I-cache tag access |
3066 | f7350b47 | blueswir1 | case 0x6e: // I-cache predecode |
3067 | f7350b47 | blueswir1 | case 0x6f: // I-cache LRU etc. |
3068 | f7350b47 | blueswir1 | case 0x76: // E-cache tag |
3069 | f7350b47 | blueswir1 | case 0x7e: // E-cache tag |
3070 | f7350b47 | blueswir1 | return;
|
3071 | 3475187d | bellard | case 0x51: // I-MMU 8k TSB pointer, RO |
3072 | 3475187d | bellard | case 0x52: // I-MMU 64k TSB pointer, RO |
3073 | 3475187d | bellard | case 0x56: // I-MMU tag read, RO |
3074 | 3475187d | bellard | case 0x59: // D-MMU 8k TSB pointer, RO |
3075 | 3475187d | bellard | case 0x5a: // D-MMU 64k TSB pointer, RO |
3076 | 3475187d | bellard | case 0x5b: // D-MMU data pointer, RO |
3077 | 3475187d | bellard | case 0x5e: // D-MMU tag read, RO |
3078 | 83469015 | bellard | case 0x48: // Interrupt dispatch, RO |
3079 | 83469015 | bellard | case 0x7f: // Incoming interrupt vector, RO |
3080 | 83469015 | bellard | case 0x82: // Primary no-fault, RO |
3081 | 83469015 | bellard | case 0x83: // Secondary no-fault, RO |
3082 | 83469015 | bellard | case 0x8a: // Primary no-fault LE, RO |
3083 | 83469015 | bellard | case 0x8b: // Secondary no-fault LE, RO |
3084 | 3475187d | bellard | default:
|
3085 | e18231a3 | blueswir1 | do_unassigned_access(addr, 1, 0, 1, size); |
3086 | 0f8a249a | blueswir1 | return;
|
3087 | 3475187d | bellard | } |
3088 | 3475187d | bellard | } |
3089 | 81ad8ba2 | blueswir1 | #endif /* CONFIG_USER_ONLY */ |
3090 | 3391c818 | blueswir1 | |
3091 | db166940 | blueswir1 | void helper_ldda_asi(target_ulong addr, int asi, int rd) |
3092 | db166940 | blueswir1 | { |
3093 | db166940 | blueswir1 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
3094 | 2aae2b8e | Igor V. Kovalenko | || (cpu_has_hypervisor(env) |
3095 | 5578ceab | blueswir1 | && asi >= 0x30 && asi < 0x80 |
3096 | fb79ceb9 | blueswir1 | && !(env->hpstate & HS_PRIV))) |
3097 | db166940 | blueswir1 | raise_exception(TT_PRIV_ACT); |
3098 | db166940 | blueswir1 | |
3099 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
3100 | 1295001c | Igor V. Kovalenko | |
3101 | db166940 | blueswir1 | switch (asi) {
|
3102 | 03ae77d6 | Blue Swirl | #if !defined(CONFIG_USER_ONLY)
|
3103 | db166940 | blueswir1 | case 0x24: // Nucleus quad LDD 128 bit atomic |
3104 | db166940 | blueswir1 | case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
3105 | db166940 | blueswir1 | helper_check_align(addr, 0xf);
|
3106 | db166940 | blueswir1 | if (rd == 0) { |
3107 | 54a3c0f0 | Igor V. Kovalenko | env->gregs[1] = ldq_nucleus(addr + 8); |
3108 | db166940 | blueswir1 | if (asi == 0x2c) |
3109 | db166940 | blueswir1 | bswap64s(&env->gregs[1]);
|
3110 | db166940 | blueswir1 | } else if (rd < 8) { |
3111 | 54a3c0f0 | Igor V. Kovalenko | env->gregs[rd] = ldq_nucleus(addr); |
3112 | 54a3c0f0 | Igor V. Kovalenko | env->gregs[rd + 1] = ldq_nucleus(addr + 8); |
3113 | db166940 | blueswir1 | if (asi == 0x2c) { |
3114 | db166940 | blueswir1 | bswap64s(&env->gregs[rd]); |
3115 | db166940 | blueswir1 | bswap64s(&env->gregs[rd + 1]);
|
3116 | db166940 | blueswir1 | } |
3117 | db166940 | blueswir1 | } else {
|
3118 | 54a3c0f0 | Igor V. Kovalenko | env->regwptr[rd] = ldq_nucleus(addr); |
3119 | 54a3c0f0 | Igor V. Kovalenko | env->regwptr[rd + 1] = ldq_nucleus(addr + 8); |
3120 | db166940 | blueswir1 | if (asi == 0x2c) { |
3121 | db166940 | blueswir1 | bswap64s(&env->regwptr[rd]); |
3122 | db166940 | blueswir1 | bswap64s(&env->regwptr[rd + 1]);
|
3123 | db166940 | blueswir1 | } |
3124 | db166940 | blueswir1 | } |
3125 | db166940 | blueswir1 | break;
|
3126 | 03ae77d6 | Blue Swirl | #endif
|
3127 | db166940 | blueswir1 | default:
|
3128 | db166940 | blueswir1 | helper_check_align(addr, 0x3);
|
3129 | db166940 | blueswir1 | if (rd == 0) |
3130 | db166940 | blueswir1 | env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0); |
3131 | db166940 | blueswir1 | else if (rd < 8) { |
3132 | db166940 | blueswir1 | env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0); |
3133 | db166940 | blueswir1 | env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0); |
3134 | db166940 | blueswir1 | } else {
|
3135 | db166940 | blueswir1 | env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0); |
3136 | db166940 | blueswir1 | env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0); |
3137 | db166940 | blueswir1 | } |
3138 | db166940 | blueswir1 | break;
|
3139 | db166940 | blueswir1 | } |
3140 | db166940 | blueswir1 | } |
3141 | db166940 | blueswir1 | |
3142 | 1a2fb1c0 | blueswir1 | void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) |
3143 | 3391c818 | blueswir1 | { |
3144 | 3391c818 | blueswir1 | unsigned int i; |
3145 | 1a2fb1c0 | blueswir1 | target_ulong val; |
3146 | 3391c818 | blueswir1 | |
3147 | c2bc0e38 | blueswir1 | helper_check_align(addr, 3);
|
3148 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
3149 | 1295001c | Igor V. Kovalenko | |
3150 | 3391c818 | blueswir1 | switch (asi) {
|
3151 | 3391c818 | blueswir1 | case 0xf0: // Block load primary |
3152 | 3391c818 | blueswir1 | case 0xf1: // Block load secondary |
3153 | 3391c818 | blueswir1 | case 0xf8: // Block load primary LE |
3154 | 3391c818 | blueswir1 | case 0xf9: // Block load secondary LE |
3155 | 51996525 | blueswir1 | if (rd & 7) { |
3156 | 51996525 | blueswir1 | raise_exception(TT_ILL_INSN); |
3157 | 51996525 | blueswir1 | return;
|
3158 | 51996525 | blueswir1 | } |
3159 | c2bc0e38 | blueswir1 | helper_check_align(addr, 0x3f);
|
3160 | 51996525 | blueswir1 | for (i = 0; i < 16; i++) { |
3161 | 77f193da | blueswir1 | *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, |
3162 | 77f193da | blueswir1 | 0);
|
3163 | 1a2fb1c0 | blueswir1 | addr += 4;
|
3164 | 3391c818 | blueswir1 | } |
3165 | 3391c818 | blueswir1 | |
3166 | 3391c818 | blueswir1 | return;
|
3167 | 0e2fa9ca | Igor V. Kovalenko | case 0x70: // Block load primary, user privilege |
3168 | 0e2fa9ca | Igor V. Kovalenko | case 0x71: // Block load secondary, user privilege |
3169 | 0e2fa9ca | Igor V. Kovalenko | if (rd & 7) { |
3170 | 0e2fa9ca | Igor V. Kovalenko | raise_exception(TT_ILL_INSN); |
3171 | 0e2fa9ca | Igor V. Kovalenko | return;
|
3172 | 0e2fa9ca | Igor V. Kovalenko | } |
3173 | 0e2fa9ca | Igor V. Kovalenko | helper_check_align(addr, 0x3f);
|
3174 | 0e2fa9ca | Igor V. Kovalenko | for (i = 0; i < 16; i++) { |
3175 | 0e2fa9ca | Igor V. Kovalenko | *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x1f, 4, |
3176 | 0e2fa9ca | Igor V. Kovalenko | 0);
|
3177 | 0e2fa9ca | Igor V. Kovalenko | addr += 4;
|
3178 | 0e2fa9ca | Igor V. Kovalenko | } |
3179 | 0e2fa9ca | Igor V. Kovalenko | |
3180 | 0e2fa9ca | Igor V. Kovalenko | return;
|
3181 | 3391c818 | blueswir1 | default:
|
3182 | 3391c818 | blueswir1 | break;
|
3183 | 3391c818 | blueswir1 | } |
3184 | 3391c818 | blueswir1 | |
3185 | 1a2fb1c0 | blueswir1 | val = helper_ld_asi(addr, asi, size, 0);
|
3186 | 3391c818 | blueswir1 | switch(size) {
|
3187 | 3391c818 | blueswir1 | default:
|
3188 | 3391c818 | blueswir1 | case 4: |
3189 | 714547bb | blueswir1 | *((uint32_t *)&env->fpr[rd]) = val; |
3190 | 3391c818 | blueswir1 | break;
|
3191 | 3391c818 | blueswir1 | case 8: |
3192 | 1a2fb1c0 | blueswir1 | *((int64_t *)&DT0) = val; |
3193 | 3391c818 | blueswir1 | break;
|
3194 | 1f587329 | blueswir1 | case 16: |
3195 | 1f587329 | blueswir1 | // XXX
|
3196 | 1f587329 | blueswir1 | break;
|
3197 | 3391c818 | blueswir1 | } |
3198 | 3391c818 | blueswir1 | } |
3199 | 3391c818 | blueswir1 | |
3200 | 1a2fb1c0 | blueswir1 | void helper_stf_asi(target_ulong addr, int asi, int size, int rd) |
3201 | 3391c818 | blueswir1 | { |
3202 | 3391c818 | blueswir1 | unsigned int i; |
3203 | 1a2fb1c0 | blueswir1 | target_ulong val = 0;
|
3204 | 3391c818 | blueswir1 | |
3205 | c2bc0e38 | blueswir1 | helper_check_align(addr, 3);
|
3206 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
3207 | 1295001c | Igor V. Kovalenko | |
3208 | 3391c818 | blueswir1 | switch (asi) {
|
3209 | c99657d3 | blueswir1 | case 0xe0: // UA2007 Block commit store primary (cache flush) |
3210 | c99657d3 | blueswir1 | case 0xe1: // UA2007 Block commit store secondary (cache flush) |
3211 | 3391c818 | blueswir1 | case 0xf0: // Block store primary |
3212 | 3391c818 | blueswir1 | case 0xf1: // Block store secondary |
3213 | 3391c818 | blueswir1 | case 0xf8: // Block store primary LE |
3214 | 3391c818 | blueswir1 | case 0xf9: // Block store secondary LE |
3215 | 51996525 | blueswir1 | if (rd & 7) { |
3216 | 51996525 | blueswir1 | raise_exception(TT_ILL_INSN); |
3217 | 51996525 | blueswir1 | return;
|
3218 | 51996525 | blueswir1 | } |
3219 | c2bc0e38 | blueswir1 | helper_check_align(addr, 0x3f);
|
3220 | 51996525 | blueswir1 | for (i = 0; i < 16; i++) { |
3221 | 1a2fb1c0 | blueswir1 | val = *(uint32_t *)&env->fpr[rd++]; |
3222 | 1a2fb1c0 | blueswir1 | helper_st_asi(addr, val, asi & 0x8f, 4); |
3223 | 1a2fb1c0 | blueswir1 | addr += 4;
|
3224 | 3391c818 | blueswir1 | } |
3225 | 3391c818 | blueswir1 | |
3226 | 3391c818 | blueswir1 | return;
|
3227 | 0e2fa9ca | Igor V. Kovalenko | case 0x70: // Block store primary, user privilege |
3228 | 0e2fa9ca | Igor V. Kovalenko | case 0x71: // Block store secondary, user privilege |
3229 | 0e2fa9ca | Igor V. Kovalenko | if (rd & 7) { |
3230 | 0e2fa9ca | Igor V. Kovalenko | raise_exception(TT_ILL_INSN); |
3231 | 0e2fa9ca | Igor V. Kovalenko | return;
|
3232 | 0e2fa9ca | Igor V. Kovalenko | } |
3233 | 0e2fa9ca | Igor V. Kovalenko | helper_check_align(addr, 0x3f);
|
3234 | 0e2fa9ca | Igor V. Kovalenko | for (i = 0; i < 16; i++) { |
3235 | 0e2fa9ca | Igor V. Kovalenko | val = *(uint32_t *)&env->fpr[rd++]; |
3236 | 0e2fa9ca | Igor V. Kovalenko | helper_st_asi(addr, val, asi & 0x1f, 4); |
3237 | 0e2fa9ca | Igor V. Kovalenko | addr += 4;
|
3238 | 0e2fa9ca | Igor V. Kovalenko | } |
3239 | 0e2fa9ca | Igor V. Kovalenko | |
3240 | 0e2fa9ca | Igor V. Kovalenko | return;
|
3241 | 3391c818 | blueswir1 | default:
|
3242 | 3391c818 | blueswir1 | break;
|
3243 | 3391c818 | blueswir1 | } |
3244 | 3391c818 | blueswir1 | |
3245 | 3391c818 | blueswir1 | switch(size) {
|
3246 | 3391c818 | blueswir1 | default:
|
3247 | 3391c818 | blueswir1 | case 4: |
3248 | 714547bb | blueswir1 | val = *((uint32_t *)&env->fpr[rd]); |
3249 | 3391c818 | blueswir1 | break;
|
3250 | 3391c818 | blueswir1 | case 8: |
3251 | 1a2fb1c0 | blueswir1 | val = *((int64_t *)&DT0); |
3252 | 3391c818 | blueswir1 | break;
|
3253 | 1f587329 | blueswir1 | case 16: |
3254 | 1f587329 | blueswir1 | // XXX
|
3255 | 1f587329 | blueswir1 | break;
|
3256 | 3391c818 | blueswir1 | } |
3257 | 1a2fb1c0 | blueswir1 | helper_st_asi(addr, val, asi, size); |
3258 | 1a2fb1c0 | blueswir1 | } |
3259 | 1a2fb1c0 | blueswir1 | |
3260 | 1a2fb1c0 | blueswir1 | target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, |
3261 | 1a2fb1c0 | blueswir1 | target_ulong val2, uint32_t asi) |
3262 | 1a2fb1c0 | blueswir1 | { |
3263 | 1a2fb1c0 | blueswir1 | target_ulong ret; |
3264 | 1a2fb1c0 | blueswir1 | |
3265 | 1121f879 | blueswir1 | val2 &= 0xffffffffUL;
|
3266 | 1a2fb1c0 | blueswir1 | ret = helper_ld_asi(addr, asi, 4, 0); |
3267 | 1a2fb1c0 | blueswir1 | ret &= 0xffffffffUL;
|
3268 | 1121f879 | blueswir1 | if (val2 == ret)
|
3269 | 1121f879 | blueswir1 | helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4); |
3270 | 1a2fb1c0 | blueswir1 | return ret;
|
3271 | 3391c818 | blueswir1 | } |
3272 | 3391c818 | blueswir1 | |
3273 | 1a2fb1c0 | blueswir1 | target_ulong helper_casx_asi(target_ulong addr, target_ulong val1, |
3274 | 1a2fb1c0 | blueswir1 | target_ulong val2, uint32_t asi) |
3275 | 1a2fb1c0 | blueswir1 | { |
3276 | 1a2fb1c0 | blueswir1 | target_ulong ret; |
3277 | 1a2fb1c0 | blueswir1 | |
3278 | 1a2fb1c0 | blueswir1 | ret = helper_ld_asi(addr, asi, 8, 0); |
3279 | 1121f879 | blueswir1 | if (val2 == ret)
|
3280 | 1121f879 | blueswir1 | helper_st_asi(addr, val1, asi, 8);
|
3281 | 1a2fb1c0 | blueswir1 | return ret;
|
3282 | 1a2fb1c0 | blueswir1 | } |
3283 | 81ad8ba2 | blueswir1 | #endif /* TARGET_SPARC64 */ |
3284 | 3475187d | bellard | |
3285 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3286 | 1a2fb1c0 | blueswir1 | void helper_rett(void) |
3287 | e8af50a3 | bellard | { |
3288 | af7bf89b | bellard | unsigned int cwp; |
3289 | af7bf89b | bellard | |
3290 | d4218d99 | blueswir1 | if (env->psret == 1) |
3291 | d4218d99 | blueswir1 | raise_exception(TT_ILL_INSN); |
3292 | d4218d99 | blueswir1 | |
3293 | e8af50a3 | bellard | env->psret = 1;
|
3294 | 5a834bb4 | Blue Swirl | cwp = cwp_inc(env->cwp + 1) ;
|
3295 | e8af50a3 | bellard | if (env->wim & (1 << cwp)) { |
3296 | e8af50a3 | bellard | raise_exception(TT_WIN_UNF); |
3297 | e8af50a3 | bellard | } |
3298 | e8af50a3 | bellard | set_cwp(cwp); |
3299 | e8af50a3 | bellard | env->psrs = env->psrps; |
3300 | e8af50a3 | bellard | } |
3301 | 3475187d | bellard | #endif
|
3302 | e8af50a3 | bellard | |
3303 | 3b89f26c | blueswir1 | target_ulong helper_udiv(target_ulong a, target_ulong b) |
3304 | 3b89f26c | blueswir1 | { |
3305 | 3b89f26c | blueswir1 | uint64_t x0; |
3306 | 3b89f26c | blueswir1 | uint32_t x1; |
3307 | 3b89f26c | blueswir1 | |
3308 | 7621a90d | blueswir1 | x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32); |
3309 | 09487205 | Igor V. Kovalenko | x1 = (b & 0xffffffff);
|
3310 | 3b89f26c | blueswir1 | |
3311 | 3b89f26c | blueswir1 | if (x1 == 0) { |
3312 | 3b89f26c | blueswir1 | raise_exception(TT_DIV_ZERO); |
3313 | 3b89f26c | blueswir1 | } |
3314 | 3b89f26c | blueswir1 | |
3315 | 3b89f26c | blueswir1 | x0 = x0 / x1; |
3316 | 3b89f26c | blueswir1 | if (x0 > 0xffffffff) { |
3317 | 3b89f26c | blueswir1 | env->cc_src2 = 1;
|
3318 | 3b89f26c | blueswir1 | return 0xffffffff; |
3319 | 3b89f26c | blueswir1 | } else {
|
3320 | 3b89f26c | blueswir1 | env->cc_src2 = 0;
|
3321 | 3b89f26c | blueswir1 | return x0;
|
3322 | 3b89f26c | blueswir1 | } |
3323 | 3b89f26c | blueswir1 | } |
3324 | 3b89f26c | blueswir1 | |
3325 | 3b89f26c | blueswir1 | target_ulong helper_sdiv(target_ulong a, target_ulong b) |
3326 | 3b89f26c | blueswir1 | { |
3327 | 3b89f26c | blueswir1 | int64_t x0; |
3328 | 3b89f26c | blueswir1 | int32_t x1; |
3329 | 3b89f26c | blueswir1 | |
3330 | 7621a90d | blueswir1 | x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32); |
3331 | 09487205 | Igor V. Kovalenko | x1 = (b & 0xffffffff);
|
3332 | 3b89f26c | blueswir1 | |
3333 | 3b89f26c | blueswir1 | if (x1 == 0) { |
3334 | 3b89f26c | blueswir1 | raise_exception(TT_DIV_ZERO); |
3335 | 3b89f26c | blueswir1 | } |
3336 | 3b89f26c | blueswir1 | |
3337 | 3b89f26c | blueswir1 | x0 = x0 / x1; |
3338 | 3b89f26c | blueswir1 | if ((int32_t) x0 != x0) {
|
3339 | 3b89f26c | blueswir1 | env->cc_src2 = 1;
|
3340 | 3b89f26c | blueswir1 | return x0 < 0? 0x80000000: 0x7fffffff; |
3341 | 3b89f26c | blueswir1 | } else {
|
3342 | 3b89f26c | blueswir1 | env->cc_src2 = 0;
|
3343 | 3b89f26c | blueswir1 | return x0;
|
3344 | 3b89f26c | blueswir1 | } |
3345 | 3b89f26c | blueswir1 | } |
3346 | 3b89f26c | blueswir1 | |
3347 | 7fa76c0b | blueswir1 | void helper_stdf(target_ulong addr, int mem_idx) |
3348 | 7fa76c0b | blueswir1 | { |
3349 | c2bc0e38 | blueswir1 | helper_check_align(addr, 7);
|
3350 | 7fa76c0b | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
3351 | 7fa76c0b | blueswir1 | switch (mem_idx) {
|
3352 | b219094a | Igor V. Kovalenko | case MMU_USER_IDX:
|
3353 | c2bc0e38 | blueswir1 | stfq_user(addr, DT0); |
3354 | 7fa76c0b | blueswir1 | break;
|
3355 | b219094a | Igor V. Kovalenko | case MMU_KERNEL_IDX:
|
3356 | c2bc0e38 | blueswir1 | stfq_kernel(addr, DT0); |
3357 | 7fa76c0b | blueswir1 | break;
|
3358 | 7fa76c0b | blueswir1 | #ifdef TARGET_SPARC64
|
3359 | b219094a | Igor V. Kovalenko | case MMU_HYPV_IDX:
|
3360 | c2bc0e38 | blueswir1 | stfq_hypv(addr, DT0); |
3361 | 7fa76c0b | blueswir1 | break;
|
3362 | 7fa76c0b | blueswir1 | #endif
|
3363 | 7fa76c0b | blueswir1 | default:
|
3364 | b219094a | Igor V. Kovalenko | DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx);
|
3365 | 7fa76c0b | blueswir1 | break;
|
3366 | 7fa76c0b | blueswir1 | } |
3367 | 7fa76c0b | blueswir1 | #else
|
3368 | 41db525e | Richard Henderson | stfq_raw(address_mask(env, addr), DT0); |
3369 | 7fa76c0b | blueswir1 | #endif
|
3370 | 7fa76c0b | blueswir1 | } |
3371 | 7fa76c0b | blueswir1 | |
3372 | 7fa76c0b | blueswir1 | void helper_lddf(target_ulong addr, int mem_idx) |
3373 | 7fa76c0b | blueswir1 | { |
3374 | c2bc0e38 | blueswir1 | helper_check_align(addr, 7);
|
3375 | 7fa76c0b | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
3376 | 7fa76c0b | blueswir1 | switch (mem_idx) {
|
3377 | b219094a | Igor V. Kovalenko | case MMU_USER_IDX:
|
3378 | c2bc0e38 | blueswir1 | DT0 = ldfq_user(addr); |
3379 | 7fa76c0b | blueswir1 | break;
|
3380 | b219094a | Igor V. Kovalenko | case MMU_KERNEL_IDX:
|
3381 | c2bc0e38 | blueswir1 | DT0 = ldfq_kernel(addr); |
3382 | 7fa76c0b | blueswir1 | break;
|
3383 | 7fa76c0b | blueswir1 | #ifdef TARGET_SPARC64
|
3384 | b219094a | Igor V. Kovalenko | case MMU_HYPV_IDX:
|
3385 | c2bc0e38 | blueswir1 | DT0 = ldfq_hypv(addr); |
3386 | 7fa76c0b | blueswir1 | break;
|
3387 | 7fa76c0b | blueswir1 | #endif
|
3388 | 7fa76c0b | blueswir1 | default:
|
3389 | b219094a | Igor V. Kovalenko | DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx);
|
3390 | 7fa76c0b | blueswir1 | break;
|
3391 | 7fa76c0b | blueswir1 | } |
3392 | 7fa76c0b | blueswir1 | #else
|
3393 | 41db525e | Richard Henderson | DT0 = ldfq_raw(address_mask(env, addr)); |
3394 | 7fa76c0b | blueswir1 | #endif
|
3395 | 7fa76c0b | blueswir1 | } |
3396 | 7fa76c0b | blueswir1 | |
3397 | 64a88d5d | blueswir1 | void helper_ldqf(target_ulong addr, int mem_idx) |
3398 | 7fa76c0b | blueswir1 | { |
3399 | 7fa76c0b | blueswir1 | // XXX add 128 bit load
|
3400 | 7fa76c0b | blueswir1 | CPU_QuadU u; |
3401 | 7fa76c0b | blueswir1 | |
3402 | c2bc0e38 | blueswir1 | helper_check_align(addr, 7);
|
3403 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
3404 | 64a88d5d | blueswir1 | switch (mem_idx) {
|
3405 | b219094a | Igor V. Kovalenko | case MMU_USER_IDX:
|
3406 | c2bc0e38 | blueswir1 | u.ll.upper = ldq_user(addr); |
3407 | c2bc0e38 | blueswir1 | u.ll.lower = ldq_user(addr + 8);
|
3408 | 64a88d5d | blueswir1 | QT0 = u.q; |
3409 | 64a88d5d | blueswir1 | break;
|
3410 | b219094a | Igor V. Kovalenko | case MMU_KERNEL_IDX:
|
3411 | c2bc0e38 | blueswir1 | u.ll.upper = ldq_kernel(addr); |
3412 | c2bc0e38 | blueswir1 | u.ll.lower = ldq_kernel(addr + 8);
|
3413 | 64a88d5d | blueswir1 | QT0 = u.q; |
3414 | 64a88d5d | blueswir1 | break;
|
3415 | 64a88d5d | blueswir1 | #ifdef TARGET_SPARC64
|
3416 | b219094a | Igor V. Kovalenko | case MMU_HYPV_IDX:
|
3417 | c2bc0e38 | blueswir1 | u.ll.upper = ldq_hypv(addr); |
3418 | c2bc0e38 | blueswir1 | u.ll.lower = ldq_hypv(addr + 8);
|
3419 | 64a88d5d | blueswir1 | QT0 = u.q; |
3420 | 64a88d5d | blueswir1 | break;
|
3421 | 64a88d5d | blueswir1 | #endif
|
3422 | 64a88d5d | blueswir1 | default:
|
3423 | b219094a | Igor V. Kovalenko | DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
|
3424 | 64a88d5d | blueswir1 | break;
|
3425 | 64a88d5d | blueswir1 | } |
3426 | 64a88d5d | blueswir1 | #else
|
3427 | 41db525e | Richard Henderson | u.ll.upper = ldq_raw(address_mask(env, addr)); |
3428 | 41db525e | Richard Henderson | u.ll.lower = ldq_raw(address_mask(env, addr + 8));
|
3429 | 7fa76c0b | blueswir1 | QT0 = u.q; |
3430 | 64a88d5d | blueswir1 | #endif
|
3431 | 7fa76c0b | blueswir1 | } |
3432 | 7fa76c0b | blueswir1 | |
3433 | 64a88d5d | blueswir1 | void helper_stqf(target_ulong addr, int mem_idx) |
3434 | 7fa76c0b | blueswir1 | { |
3435 | 7fa76c0b | blueswir1 | // XXX add 128 bit store
|
3436 | 7fa76c0b | blueswir1 | CPU_QuadU u; |
3437 | 7fa76c0b | blueswir1 | |
3438 | c2bc0e38 | blueswir1 | helper_check_align(addr, 7);
|
3439 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
3440 | 64a88d5d | blueswir1 | switch (mem_idx) {
|
3441 | b219094a | Igor V. Kovalenko | case MMU_USER_IDX:
|
3442 | 64a88d5d | blueswir1 | u.q = QT0; |
3443 | c2bc0e38 | blueswir1 | stq_user(addr, u.ll.upper); |
3444 | c2bc0e38 | blueswir1 | stq_user(addr + 8, u.ll.lower);
|
3445 | 64a88d5d | blueswir1 | break;
|
3446 | b219094a | Igor V. Kovalenko | case MMU_KERNEL_IDX:
|
3447 | 64a88d5d | blueswir1 | u.q = QT0; |
3448 | c2bc0e38 | blueswir1 | stq_kernel(addr, u.ll.upper); |
3449 | c2bc0e38 | blueswir1 | stq_kernel(addr + 8, u.ll.lower);
|
3450 | 64a88d5d | blueswir1 | break;
|
3451 | 64a88d5d | blueswir1 | #ifdef TARGET_SPARC64
|
3452 | b219094a | Igor V. Kovalenko | case MMU_HYPV_IDX:
|
3453 | 64a88d5d | blueswir1 | u.q = QT0; |
3454 | c2bc0e38 | blueswir1 | stq_hypv(addr, u.ll.upper); |
3455 | c2bc0e38 | blueswir1 | stq_hypv(addr + 8, u.ll.lower);
|
3456 | 64a88d5d | blueswir1 | break;
|
3457 | 64a88d5d | blueswir1 | #endif
|
3458 | 64a88d5d | blueswir1 | default:
|
3459 | b219094a | Igor V. Kovalenko | DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
|
3460 | 64a88d5d | blueswir1 | break;
|
3461 | 64a88d5d | blueswir1 | } |
3462 | 64a88d5d | blueswir1 | #else
|
3463 | 7fa76c0b | blueswir1 | u.q = QT0; |
3464 | 41db525e | Richard Henderson | stq_raw(address_mask(env, addr), u.ll.upper); |
3465 | 41db525e | Richard Henderson | stq_raw(address_mask(env, addr + 8), u.ll.lower);
|
3466 | 7fa76c0b | blueswir1 | #endif
|
3467 | 64a88d5d | blueswir1 | } |
3468 | 7fa76c0b | blueswir1 | |
3469 | 3a3b925d | blueswir1 | static inline void set_fsr(void) |
3470 | e8af50a3 | bellard | { |
3471 | 7a0e1f41 | bellard | int rnd_mode;
|
3472 | bb5529bb | blueswir1 | |
3473 | e8af50a3 | bellard | switch (env->fsr & FSR_RD_MASK) {
|
3474 | e8af50a3 | bellard | case FSR_RD_NEAREST:
|
3475 | 7a0e1f41 | bellard | rnd_mode = float_round_nearest_even; |
3476 | 0f8a249a | blueswir1 | break;
|
3477 | ed910241 | bellard | default:
|
3478 | e8af50a3 | bellard | case FSR_RD_ZERO:
|
3479 | 7a0e1f41 | bellard | rnd_mode = float_round_to_zero; |
3480 | 0f8a249a | blueswir1 | break;
|
3481 | e8af50a3 | bellard | case FSR_RD_POS:
|
3482 | 7a0e1f41 | bellard | rnd_mode = float_round_up; |
3483 | 0f8a249a | blueswir1 | break;
|
3484 | e8af50a3 | bellard | case FSR_RD_NEG:
|
3485 | 7a0e1f41 | bellard | rnd_mode = float_round_down; |
3486 | 0f8a249a | blueswir1 | break;
|
3487 | e8af50a3 | bellard | } |
3488 | 7a0e1f41 | bellard | set_float_rounding_mode(rnd_mode, &env->fp_status); |
3489 | e8af50a3 | bellard | } |
3490 | e80cfcfc | bellard | |
3491 | 3a3b925d | blueswir1 | void helper_ldfsr(uint32_t new_fsr)
|
3492 | bb5529bb | blueswir1 | { |
3493 | 3a3b925d | blueswir1 | env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK); |
3494 | 3a3b925d | blueswir1 | set_fsr(); |
3495 | bb5529bb | blueswir1 | } |
3496 | bb5529bb | blueswir1 | |
3497 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
3498 | 3a3b925d | blueswir1 | void helper_ldxfsr(uint64_t new_fsr)
|
3499 | 3a3b925d | blueswir1 | { |
3500 | 3a3b925d | blueswir1 | env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK); |
3501 | 3a3b925d | blueswir1 | set_fsr(); |
3502 | 3a3b925d | blueswir1 | } |
3503 | 3a3b925d | blueswir1 | #endif
|
3504 | 3a3b925d | blueswir1 | |
3505 | bb5529bb | blueswir1 | void helper_debug(void) |
3506 | e80cfcfc | bellard | { |
3507 | e80cfcfc | bellard | env->exception_index = EXCP_DEBUG; |
3508 | e80cfcfc | bellard | cpu_loop_exit(); |
3509 | e80cfcfc | bellard | } |
3510 | af7bf89b | bellard | |
3511 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3512 | 72a9747b | blueswir1 | /* XXX: use another pointer for %iN registers to avoid slow wrapping
|
3513 | 72a9747b | blueswir1 | handling ? */
|
3514 | 72a9747b | blueswir1 | void helper_save(void) |
3515 | 72a9747b | blueswir1 | { |
3516 | 72a9747b | blueswir1 | uint32_t cwp; |
3517 | 72a9747b | blueswir1 | |
3518 | 5a834bb4 | Blue Swirl | cwp = cwp_dec(env->cwp - 1);
|
3519 | 72a9747b | blueswir1 | if (env->wim & (1 << cwp)) { |
3520 | 72a9747b | blueswir1 | raise_exception(TT_WIN_OVF); |
3521 | 72a9747b | blueswir1 | } |
3522 | 72a9747b | blueswir1 | set_cwp(cwp); |
3523 | 72a9747b | blueswir1 | } |
3524 | 72a9747b | blueswir1 | |
3525 | 72a9747b | blueswir1 | void helper_restore(void) |
3526 | 72a9747b | blueswir1 | { |
3527 | 72a9747b | blueswir1 | uint32_t cwp; |
3528 | 72a9747b | blueswir1 | |
3529 | 5a834bb4 | Blue Swirl | cwp = cwp_inc(env->cwp + 1);
|
3530 | 72a9747b | blueswir1 | if (env->wim & (1 << cwp)) { |
3531 | 72a9747b | blueswir1 | raise_exception(TT_WIN_UNF); |
3532 | 72a9747b | blueswir1 | } |
3533 | 72a9747b | blueswir1 | set_cwp(cwp); |
3534 | 72a9747b | blueswir1 | } |
3535 | 72a9747b | blueswir1 | |
3536 | 1a2fb1c0 | blueswir1 | void helper_wrpsr(target_ulong new_psr)
|
3537 | af7bf89b | bellard | { |
3538 | 5a834bb4 | Blue Swirl | if ((new_psr & PSR_CWP) >= env->nwindows) {
|
3539 | d4218d99 | blueswir1 | raise_exception(TT_ILL_INSN); |
3540 | 5a834bb4 | Blue Swirl | } else {
|
3541 | 5a834bb4 | Blue Swirl | cpu_put_psr(env, new_psr); |
3542 | 5a834bb4 | Blue Swirl | } |
3543 | af7bf89b | bellard | } |
3544 | af7bf89b | bellard | |
3545 | 1a2fb1c0 | blueswir1 | target_ulong helper_rdpsr(void)
|
3546 | af7bf89b | bellard | { |
3547 | 5a834bb4 | Blue Swirl | return get_psr();
|
3548 | af7bf89b | bellard | } |
3549 | 3475187d | bellard | |
3550 | 3475187d | bellard | #else
|
3551 | 72a9747b | blueswir1 | /* XXX: use another pointer for %iN registers to avoid slow wrapping
|
3552 | 72a9747b | blueswir1 | handling ? */
|
3553 | 72a9747b | blueswir1 | void helper_save(void) |
3554 | 72a9747b | blueswir1 | { |
3555 | 72a9747b | blueswir1 | uint32_t cwp; |
3556 | 72a9747b | blueswir1 | |
3557 | 5a834bb4 | Blue Swirl | cwp = cwp_dec(env->cwp - 1);
|
3558 | 72a9747b | blueswir1 | if (env->cansave == 0) { |
3559 | 72a9747b | blueswir1 | raise_exception(TT_SPILL | (env->otherwin != 0 ?
|
3560 | 72a9747b | blueswir1 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
3561 | 72a9747b | blueswir1 | ((env->wstate & 0x7) << 2))); |
3562 | 72a9747b | blueswir1 | } else {
|
3563 | 72a9747b | blueswir1 | if (env->cleanwin - env->canrestore == 0) { |
3564 | 72a9747b | blueswir1 | // XXX Clean windows without trap
|
3565 | 72a9747b | blueswir1 | raise_exception(TT_CLRWIN); |
3566 | 72a9747b | blueswir1 | } else {
|
3567 | 72a9747b | blueswir1 | env->cansave--; |
3568 | 72a9747b | blueswir1 | env->canrestore++; |
3569 | 72a9747b | blueswir1 | set_cwp(cwp); |
3570 | 72a9747b | blueswir1 | } |
3571 | 72a9747b | blueswir1 | } |
3572 | 72a9747b | blueswir1 | } |
3573 | 72a9747b | blueswir1 | |
3574 | 72a9747b | blueswir1 | void helper_restore(void) |
3575 | 72a9747b | blueswir1 | { |
3576 | 72a9747b | blueswir1 | uint32_t cwp; |
3577 | 72a9747b | blueswir1 | |
3578 | 5a834bb4 | Blue Swirl | cwp = cwp_inc(env->cwp + 1);
|
3579 | 72a9747b | blueswir1 | if (env->canrestore == 0) { |
3580 | 72a9747b | blueswir1 | raise_exception(TT_FILL | (env->otherwin != 0 ?
|
3581 | 72a9747b | blueswir1 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
3582 | 72a9747b | blueswir1 | ((env->wstate & 0x7) << 2))); |
3583 | 72a9747b | blueswir1 | } else {
|
3584 | 72a9747b | blueswir1 | env->cansave++; |
3585 | 72a9747b | blueswir1 | env->canrestore--; |
3586 | 72a9747b | blueswir1 | set_cwp(cwp); |
3587 | 72a9747b | blueswir1 | } |
3588 | 72a9747b | blueswir1 | } |
3589 | 72a9747b | blueswir1 | |
3590 | 72a9747b | blueswir1 | void helper_flushw(void) |
3591 | 72a9747b | blueswir1 | { |
3592 | 1a14026e | blueswir1 | if (env->cansave != env->nwindows - 2) { |
3593 | 72a9747b | blueswir1 | raise_exception(TT_SPILL | (env->otherwin != 0 ?
|
3594 | 72a9747b | blueswir1 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
3595 | 72a9747b | blueswir1 | ((env->wstate & 0x7) << 2))); |
3596 | 72a9747b | blueswir1 | } |
3597 | 72a9747b | blueswir1 | } |
3598 | 72a9747b | blueswir1 | |
3599 | 72a9747b | blueswir1 | void helper_saved(void) |
3600 | 72a9747b | blueswir1 | { |
3601 | 72a9747b | blueswir1 | env->cansave++; |
3602 | 72a9747b | blueswir1 | if (env->otherwin == 0) |
3603 | 72a9747b | blueswir1 | env->canrestore--; |
3604 | 72a9747b | blueswir1 | else
|
3605 | 72a9747b | blueswir1 | env->otherwin--; |
3606 | 72a9747b | blueswir1 | } |
3607 | 72a9747b | blueswir1 | |
3608 | 72a9747b | blueswir1 | void helper_restored(void) |
3609 | 72a9747b | blueswir1 | { |
3610 | 72a9747b | blueswir1 | env->canrestore++; |
3611 | 1a14026e | blueswir1 | if (env->cleanwin < env->nwindows - 1) |
3612 | 72a9747b | blueswir1 | env->cleanwin++; |
3613 | 72a9747b | blueswir1 | if (env->otherwin == 0) |
3614 | 72a9747b | blueswir1 | env->cansave--; |
3615 | 72a9747b | blueswir1 | else
|
3616 | 72a9747b | blueswir1 | env->otherwin--; |
3617 | 72a9747b | blueswir1 | } |
3618 | 72a9747b | blueswir1 | |
3619 | 5a834bb4 | Blue Swirl | static target_ulong get_ccr(void) |
3620 | 5a834bb4 | Blue Swirl | { |
3621 | 5a834bb4 | Blue Swirl | target_ulong psr; |
3622 | 5a834bb4 | Blue Swirl | |
3623 | 5a834bb4 | Blue Swirl | psr = get_psr(); |
3624 | 5a834bb4 | Blue Swirl | |
3625 | 5a834bb4 | Blue Swirl | return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20); |
3626 | 5a834bb4 | Blue Swirl | } |
3627 | 5a834bb4 | Blue Swirl | |
3628 | 5a834bb4 | Blue Swirl | target_ulong cpu_get_ccr(CPUState *env1) |
3629 | 5a834bb4 | Blue Swirl | { |
3630 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
3631 | 5a834bb4 | Blue Swirl | target_ulong ret; |
3632 | 5a834bb4 | Blue Swirl | |
3633 | 5a834bb4 | Blue Swirl | saved_env = env; |
3634 | 5a834bb4 | Blue Swirl | env = env1; |
3635 | 5a834bb4 | Blue Swirl | ret = get_ccr(); |
3636 | 5a834bb4 | Blue Swirl | env = saved_env; |
3637 | 5a834bb4 | Blue Swirl | return ret;
|
3638 | 5a834bb4 | Blue Swirl | } |
3639 | 5a834bb4 | Blue Swirl | |
3640 | 5a834bb4 | Blue Swirl | static void put_ccr(target_ulong val) |
3641 | 5a834bb4 | Blue Swirl | { |
3642 | 5a834bb4 | Blue Swirl | target_ulong tmp = val; |
3643 | 5a834bb4 | Blue Swirl | |
3644 | 5a834bb4 | Blue Swirl | env->xcc = (tmp >> 4) << 20; |
3645 | 5a834bb4 | Blue Swirl | env->psr = (tmp & 0xf) << 20; |
3646 | 5a834bb4 | Blue Swirl | CC_OP = CC_OP_FLAGS; |
3647 | 5a834bb4 | Blue Swirl | } |
3648 | 5a834bb4 | Blue Swirl | |
3649 | 5a834bb4 | Blue Swirl | void cpu_put_ccr(CPUState *env1, target_ulong val)
|
3650 | 5a834bb4 | Blue Swirl | { |
3651 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
3652 | 5a834bb4 | Blue Swirl | |
3653 | 5a834bb4 | Blue Swirl | saved_env = env; |
3654 | 5a834bb4 | Blue Swirl | env = env1; |
3655 | 5a834bb4 | Blue Swirl | put_ccr(val); |
3656 | 5a834bb4 | Blue Swirl | env = saved_env; |
3657 | 5a834bb4 | Blue Swirl | } |
3658 | 5a834bb4 | Blue Swirl | |
3659 | 5a834bb4 | Blue Swirl | static target_ulong get_cwp64(void) |
3660 | 5a834bb4 | Blue Swirl | { |
3661 | 5a834bb4 | Blue Swirl | return env->nwindows - 1 - env->cwp; |
3662 | 5a834bb4 | Blue Swirl | } |
3663 | 5a834bb4 | Blue Swirl | |
3664 | 5a834bb4 | Blue Swirl | target_ulong cpu_get_cwp64(CPUState *env1) |
3665 | 5a834bb4 | Blue Swirl | { |
3666 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
3667 | 5a834bb4 | Blue Swirl | target_ulong ret; |
3668 | 5a834bb4 | Blue Swirl | |
3669 | 5a834bb4 | Blue Swirl | saved_env = env; |
3670 | 5a834bb4 | Blue Swirl | env = env1; |
3671 | 5a834bb4 | Blue Swirl | ret = get_cwp64(); |
3672 | 5a834bb4 | Blue Swirl | env = saved_env; |
3673 | 5a834bb4 | Blue Swirl | return ret;
|
3674 | 5a834bb4 | Blue Swirl | } |
3675 | 5a834bb4 | Blue Swirl | |
3676 | 5a834bb4 | Blue Swirl | static void put_cwp64(int cwp) |
3677 | 5a834bb4 | Blue Swirl | { |
3678 | 5a834bb4 | Blue Swirl | if (unlikely(cwp >= env->nwindows || cwp < 0)) { |
3679 | 5a834bb4 | Blue Swirl | cwp %= env->nwindows; |
3680 | 5a834bb4 | Blue Swirl | } |
3681 | 5a834bb4 | Blue Swirl | set_cwp(env->nwindows - 1 - cwp);
|
3682 | 5a834bb4 | Blue Swirl | } |
3683 | 5a834bb4 | Blue Swirl | |
3684 | 5a834bb4 | Blue Swirl | void cpu_put_cwp64(CPUState *env1, int cwp) |
3685 | 5a834bb4 | Blue Swirl | { |
3686 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
3687 | 5a834bb4 | Blue Swirl | |
3688 | 5a834bb4 | Blue Swirl | saved_env = env; |
3689 | 5a834bb4 | Blue Swirl | env = env1; |
3690 | 5a834bb4 | Blue Swirl | put_cwp64(cwp); |
3691 | 5a834bb4 | Blue Swirl | env = saved_env; |
3692 | 5a834bb4 | Blue Swirl | } |
3693 | 5a834bb4 | Blue Swirl | |
3694 | d35527d9 | blueswir1 | target_ulong helper_rdccr(void)
|
3695 | d35527d9 | blueswir1 | { |
3696 | 5a834bb4 | Blue Swirl | return get_ccr();
|
3697 | d35527d9 | blueswir1 | } |
3698 | d35527d9 | blueswir1 | |
3699 | d35527d9 | blueswir1 | void helper_wrccr(target_ulong new_ccr)
|
3700 | d35527d9 | blueswir1 | { |
3701 | 5a834bb4 | Blue Swirl | put_ccr(new_ccr); |
3702 | d35527d9 | blueswir1 | } |
3703 | d35527d9 | blueswir1 | |
3704 | d35527d9 | blueswir1 | // CWP handling is reversed in V9, but we still use the V8 register
|
3705 | d35527d9 | blueswir1 | // order.
|
3706 | d35527d9 | blueswir1 | target_ulong helper_rdcwp(void)
|
3707 | d35527d9 | blueswir1 | { |
3708 | 5a834bb4 | Blue Swirl | return get_cwp64();
|
3709 | d35527d9 | blueswir1 | } |
3710 | d35527d9 | blueswir1 | |
3711 | d35527d9 | blueswir1 | void helper_wrcwp(target_ulong new_cwp)
|
3712 | d35527d9 | blueswir1 | { |
3713 | 5a834bb4 | Blue Swirl | put_cwp64(new_cwp); |
3714 | d35527d9 | blueswir1 | } |
3715 | 3475187d | bellard | |
3716 | 1f5063fb | blueswir1 | // This function uses non-native bit order
|
3717 | 1f5063fb | blueswir1 | #define GET_FIELD(X, FROM, TO) \
|
3718 | 1f5063fb | blueswir1 | ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1)) |
3719 | 1f5063fb | blueswir1 | |
3720 | 1f5063fb | blueswir1 | // This function uses the order in the manuals, i.e. bit 0 is 2^0
|
3721 | 1f5063fb | blueswir1 | #define GET_FIELD_SP(X, FROM, TO) \
|
3722 | 1f5063fb | blueswir1 | GET_FIELD(X, 63 - (TO), 63 - (FROM)) |
3723 | 1f5063fb | blueswir1 | |
3724 | 1f5063fb | blueswir1 | target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) |
3725 | 1f5063fb | blueswir1 | { |
3726 | 1f5063fb | blueswir1 | return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) | |
3727 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) | |
3728 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) | |
3729 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 56, 59) << 13) | |
3730 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 35, 38) << 9) | |
3731 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 13, 16) << 5) | |
3732 | 1f5063fb | blueswir1 | (((pixel_addr >> 55) & 1) << 4) | |
3733 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 33, 34) << 2) | |
3734 | 1f5063fb | blueswir1 | GET_FIELD_SP(pixel_addr, 11, 12); |
3735 | 1f5063fb | blueswir1 | } |
3736 | 1f5063fb | blueswir1 | |
3737 | 1f5063fb | blueswir1 | target_ulong helper_alignaddr(target_ulong addr, target_ulong offset) |
3738 | 1f5063fb | blueswir1 | { |
3739 | 1f5063fb | blueswir1 | uint64_t tmp; |
3740 | 1f5063fb | blueswir1 | |
3741 | 1f5063fb | blueswir1 | tmp = addr + offset; |
3742 | 1f5063fb | blueswir1 | env->gsr &= ~7ULL;
|
3743 | 1f5063fb | blueswir1 | env->gsr |= tmp & 7ULL;
|
3744 | 1f5063fb | blueswir1 | return tmp & ~7ULL; |
3745 | 1f5063fb | blueswir1 | } |
3746 | 1f5063fb | blueswir1 | |
3747 | 1a2fb1c0 | blueswir1 | target_ulong helper_popc(target_ulong val) |
3748 | 3475187d | bellard | { |
3749 | 1a2fb1c0 | blueswir1 | return ctpop64(val);
|
3750 | 3475187d | bellard | } |
3751 | 83469015 | bellard | |
3752 | d780a466 | Igor V. Kovalenko | static inline uint64_t *get_gregset(uint32_t pstate) |
3753 | 83469015 | bellard | { |
3754 | 83469015 | bellard | switch (pstate) {
|
3755 | 83469015 | bellard | default:
|
3756 | 7e8695ed | Igor V. Kovalenko | DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
|
3757 | 7e8695ed | Igor V. Kovalenko | pstate, |
3758 | 7e8695ed | Igor V. Kovalenko | (pstate & PS_IG) ? " IG" : "", |
3759 | 7e8695ed | Igor V. Kovalenko | (pstate & PS_MG) ? " MG" : "", |
3760 | 7e8695ed | Igor V. Kovalenko | (pstate & PS_AG) ? " AG" : ""); |
3761 | 7e8695ed | Igor V. Kovalenko | /* pass through to normal set of global registers */
|
3762 | 83469015 | bellard | case 0: |
3763 | 0f8a249a | blueswir1 | return env->bgregs;
|
3764 | 83469015 | bellard | case PS_AG:
|
3765 | 0f8a249a | blueswir1 | return env->agregs;
|
3766 | 83469015 | bellard | case PS_MG:
|
3767 | 0f8a249a | blueswir1 | return env->mgregs;
|
3768 | 83469015 | bellard | case PS_IG:
|
3769 | 0f8a249a | blueswir1 | return env->igregs;
|
3770 | 83469015 | bellard | } |
3771 | 83469015 | bellard | } |
3772 | 83469015 | bellard | |
3773 | d780a466 | Igor V. Kovalenko | static inline void change_pstate(uint32_t new_pstate) |
3774 | 83469015 | bellard | { |
3775 | d780a466 | Igor V. Kovalenko | uint32_t pstate_regs, new_pstate_regs; |
3776 | 83469015 | bellard | uint64_t *src, *dst; |
3777 | 83469015 | bellard | |
3778 | 5210977a | Igor Kovalenko | if (env->def->features & CPU_FEATURE_GL) {
|
3779 | 5210977a | Igor Kovalenko | // PS_AG is not implemented in this case
|
3780 | 5210977a | Igor Kovalenko | new_pstate &= ~PS_AG; |
3781 | 5210977a | Igor Kovalenko | } |
3782 | 5210977a | Igor Kovalenko | |
3783 | 83469015 | bellard | pstate_regs = env->pstate & 0xc01;
|
3784 | 83469015 | bellard | new_pstate_regs = new_pstate & 0xc01;
|
3785 | 5210977a | Igor Kovalenko | |
3786 | 83469015 | bellard | if (new_pstate_regs != pstate_regs) {
|
3787 | 7e8695ed | Igor V. Kovalenko | DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
|
3788 | 7e8695ed | Igor V. Kovalenko | pstate_regs, new_pstate_regs); |
3789 | 0f8a249a | blueswir1 | // Switch global register bank
|
3790 | 0f8a249a | blueswir1 | src = get_gregset(new_pstate_regs); |
3791 | 0f8a249a | blueswir1 | dst = get_gregset(pstate_regs); |
3792 | 0f8a249a | blueswir1 | memcpy32(dst, env->gregs); |
3793 | 0f8a249a | blueswir1 | memcpy32(env->gregs, src); |
3794 | 83469015 | bellard | } |
3795 | 7e8695ed | Igor V. Kovalenko | else {
|
3796 | 7e8695ed | Igor V. Kovalenko | DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
|
3797 | 7e8695ed | Igor V. Kovalenko | new_pstate_regs); |
3798 | 7e8695ed | Igor V. Kovalenko | } |
3799 | 83469015 | bellard | env->pstate = new_pstate; |
3800 | 83469015 | bellard | } |
3801 | 83469015 | bellard | |
3802 | 1a2fb1c0 | blueswir1 | void helper_wrpstate(target_ulong new_state)
|
3803 | 8f1f22f6 | blueswir1 | { |
3804 | 5210977a | Igor Kovalenko | change_pstate(new_state & 0xf3f);
|
3805 | 4dc28134 | Igor V. Kovalenko | |
3806 | 4dc28134 | Igor V. Kovalenko | #if !defined(CONFIG_USER_ONLY)
|
3807 | 4dc28134 | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
|
3808 | 4dc28134 | Igor V. Kovalenko | cpu_check_irqs(env); |
3809 | 4dc28134 | Igor V. Kovalenko | } |
3810 | 4dc28134 | Igor V. Kovalenko | #endif
|
3811 | 8f1f22f6 | blueswir1 | } |
3812 | 8f1f22f6 | blueswir1 | |
3813 | 1fae7b70 | Igor V. Kovalenko | void helper_wrpil(target_ulong new_pil)
|
3814 | 1fae7b70 | Igor V. Kovalenko | { |
3815 | 1fae7b70 | Igor V. Kovalenko | #if !defined(CONFIG_USER_ONLY)
|
3816 | 1fae7b70 | Igor V. Kovalenko | DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
|
3817 | 1fae7b70 | Igor V. Kovalenko | env->psrpil, (uint32_t)new_pil); |
3818 | 1fae7b70 | Igor V. Kovalenko | |
3819 | 1fae7b70 | Igor V. Kovalenko | env->psrpil = new_pil; |
3820 | 1fae7b70 | Igor V. Kovalenko | |
3821 | 1fae7b70 | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
|
3822 | 1fae7b70 | Igor V. Kovalenko | cpu_check_irqs(env); |
3823 | 1fae7b70 | Igor V. Kovalenko | } |
3824 | 1fae7b70 | Igor V. Kovalenko | #endif
|
3825 | 1fae7b70 | Igor V. Kovalenko | } |
3826 | 1fae7b70 | Igor V. Kovalenko | |
3827 | 1a2fb1c0 | blueswir1 | void helper_done(void) |
3828 | 83469015 | bellard | { |
3829 | 8194f35a | Igor Kovalenko | trap_state* tsptr = cpu_tsptr(env); |
3830 | 8194f35a | Igor Kovalenko | |
3831 | 3723cd09 | Igor V. Kovalenko | env->pc = tsptr->tnpc; |
3832 | 8194f35a | Igor Kovalenko | env->npc = tsptr->tnpc + 4;
|
3833 | 5a834bb4 | Blue Swirl | put_ccr(tsptr->tstate >> 32);
|
3834 | 8194f35a | Igor Kovalenko | env->asi = (tsptr->tstate >> 24) & 0xff; |
3835 | 8194f35a | Igor Kovalenko | change_pstate((tsptr->tstate >> 8) & 0xf3f); |
3836 | 5a834bb4 | Blue Swirl | put_cwp64(tsptr->tstate & 0xff);
|
3837 | e6bf7d70 | blueswir1 | env->tl--; |
3838 | 4dc28134 | Igor V. Kovalenko | |
3839 | 4dc28134 | Igor V. Kovalenko | DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
|
3840 | 4dc28134 | Igor V. Kovalenko | |
3841 | 4dc28134 | Igor V. Kovalenko | #if !defined(CONFIG_USER_ONLY)
|
3842 | 4dc28134 | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
|
3843 | 4dc28134 | Igor V. Kovalenko | cpu_check_irqs(env); |
3844 | 4dc28134 | Igor V. Kovalenko | } |
3845 | 4dc28134 | Igor V. Kovalenko | #endif
|
3846 | 83469015 | bellard | } |
3847 | 83469015 | bellard | |
3848 | 1a2fb1c0 | blueswir1 | void helper_retry(void) |
3849 | 83469015 | bellard | { |
3850 | 8194f35a | Igor Kovalenko | trap_state* tsptr = cpu_tsptr(env); |
3851 | 8194f35a | Igor Kovalenko | |
3852 | 8194f35a | Igor Kovalenko | env->pc = tsptr->tpc; |
3853 | 8194f35a | Igor Kovalenko | env->npc = tsptr->tnpc; |
3854 | 5a834bb4 | Blue Swirl | put_ccr(tsptr->tstate >> 32);
|
3855 | 8194f35a | Igor Kovalenko | env->asi = (tsptr->tstate >> 24) & 0xff; |
3856 | 8194f35a | Igor Kovalenko | change_pstate((tsptr->tstate >> 8) & 0xf3f); |
3857 | 5a834bb4 | Blue Swirl | put_cwp64(tsptr->tstate & 0xff);
|
3858 | e6bf7d70 | blueswir1 | env->tl--; |
3859 | 4dc28134 | Igor V. Kovalenko | |
3860 | 4dc28134 | Igor V. Kovalenko | DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
|
3861 | 4dc28134 | Igor V. Kovalenko | |
3862 | 4dc28134 | Igor V. Kovalenko | #if !defined(CONFIG_USER_ONLY)
|
3863 | 4dc28134 | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
|
3864 | 4dc28134 | Igor V. Kovalenko | cpu_check_irqs(env); |
3865 | 4dc28134 | Igor V. Kovalenko | } |
3866 | 4dc28134 | Igor V. Kovalenko | #endif
|
3867 | 4dc28134 | Igor V. Kovalenko | } |
3868 | 4dc28134 | Igor V. Kovalenko | |
3869 | 4dc28134 | Igor V. Kovalenko | static void do_modify_softint(const char* operation, uint32_t value) |
3870 | 4dc28134 | Igor V. Kovalenko | { |
3871 | 4dc28134 | Igor V. Kovalenko | if (env->softint != value) {
|
3872 | 4dc28134 | Igor V. Kovalenko | env->softint = value; |
3873 | 4dc28134 | Igor V. Kovalenko | DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
|
3874 | 4dc28134 | Igor V. Kovalenko | #if !defined(CONFIG_USER_ONLY)
|
3875 | 4dc28134 | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
|
3876 | 4dc28134 | Igor V. Kovalenko | cpu_check_irqs(env); |
3877 | 4dc28134 | Igor V. Kovalenko | } |
3878 | 4dc28134 | Igor V. Kovalenko | #endif
|
3879 | 4dc28134 | Igor V. Kovalenko | } |
3880 | 83469015 | bellard | } |
3881 | 9d926598 | blueswir1 | |
3882 | 9d926598 | blueswir1 | void helper_set_softint(uint64_t value)
|
3883 | 9d926598 | blueswir1 | { |
3884 | 4dc28134 | Igor V. Kovalenko | do_modify_softint("helper_set_softint", env->softint | (uint32_t)value);
|
3885 | 9d926598 | blueswir1 | } |
3886 | 9d926598 | blueswir1 | |
3887 | 9d926598 | blueswir1 | void helper_clear_softint(uint64_t value)
|
3888 | 9d926598 | blueswir1 | { |
3889 | 4dc28134 | Igor V. Kovalenko | do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value);
|
3890 | 9d926598 | blueswir1 | } |
3891 | 9d926598 | blueswir1 | |
3892 | 9d926598 | blueswir1 | void helper_write_softint(uint64_t value)
|
3893 | 9d926598 | blueswir1 | { |
3894 | 4dc28134 | Igor V. Kovalenko | do_modify_softint("helper_write_softint", (uint32_t)value);
|
3895 | 9d926598 | blueswir1 | } |
3896 | 3475187d | bellard | #endif
|
3897 | ee5bbe38 | bellard | |
3898 | 91736d37 | blueswir1 | void helper_flush(target_ulong addr)
|
3899 | ee5bbe38 | bellard | { |
3900 | 91736d37 | blueswir1 | addr &= ~7;
|
3901 | 91736d37 | blueswir1 | tb_invalidate_page_range(addr, addr + 8);
|
3902 | ee5bbe38 | bellard | } |
3903 | ee5bbe38 | bellard | |
3904 | 91736d37 | blueswir1 | #ifdef TARGET_SPARC64
|
3905 | 91736d37 | blueswir1 | #ifdef DEBUG_PCALL
|
3906 | 91736d37 | blueswir1 | static const char * const excp_names[0x80] = { |
3907 | 91736d37 | blueswir1 | [TT_TFAULT] = "Instruction Access Fault",
|
3908 | 91736d37 | blueswir1 | [TT_TMISS] = "Instruction Access MMU Miss",
|
3909 | 91736d37 | blueswir1 | [TT_CODE_ACCESS] = "Instruction Access Error",
|
3910 | 91736d37 | blueswir1 | [TT_ILL_INSN] = "Illegal Instruction",
|
3911 | 91736d37 | blueswir1 | [TT_PRIV_INSN] = "Privileged Instruction",
|
3912 | 91736d37 | blueswir1 | [TT_NFPU_INSN] = "FPU Disabled",
|
3913 | 91736d37 | blueswir1 | [TT_FP_EXCP] = "FPU Exception",
|
3914 | 91736d37 | blueswir1 | [TT_TOVF] = "Tag Overflow",
|
3915 | 91736d37 | blueswir1 | [TT_CLRWIN] = "Clean Windows",
|
3916 | 91736d37 | blueswir1 | [TT_DIV_ZERO] = "Division By Zero",
|
3917 | 91736d37 | blueswir1 | [TT_DFAULT] = "Data Access Fault",
|
3918 | 91736d37 | blueswir1 | [TT_DMISS] = "Data Access MMU Miss",
|
3919 | 91736d37 | blueswir1 | [TT_DATA_ACCESS] = "Data Access Error",
|
3920 | 91736d37 | blueswir1 | [TT_DPROT] = "Data Protection Error",
|
3921 | 91736d37 | blueswir1 | [TT_UNALIGNED] = "Unaligned Memory Access",
|
3922 | 91736d37 | blueswir1 | [TT_PRIV_ACT] = "Privileged Action",
|
3923 | 91736d37 | blueswir1 | [TT_EXTINT | 0x1] = "External Interrupt 1", |
3924 | 91736d37 | blueswir1 | [TT_EXTINT | 0x2] = "External Interrupt 2", |
3925 | 91736d37 | blueswir1 | [TT_EXTINT | 0x3] = "External Interrupt 3", |
3926 | 91736d37 | blueswir1 | [TT_EXTINT | 0x4] = "External Interrupt 4", |
3927 | 91736d37 | blueswir1 | [TT_EXTINT | 0x5] = "External Interrupt 5", |
3928 | 91736d37 | blueswir1 | [TT_EXTINT | 0x6] = "External Interrupt 6", |
3929 | 91736d37 | blueswir1 | [TT_EXTINT | 0x7] = "External Interrupt 7", |
3930 | 91736d37 | blueswir1 | [TT_EXTINT | 0x8] = "External Interrupt 8", |
3931 | 91736d37 | blueswir1 | [TT_EXTINT | 0x9] = "External Interrupt 9", |
3932 | 91736d37 | blueswir1 | [TT_EXTINT | 0xa] = "External Interrupt 10", |
3933 | 91736d37 | blueswir1 | [TT_EXTINT | 0xb] = "External Interrupt 11", |
3934 | 91736d37 | blueswir1 | [TT_EXTINT | 0xc] = "External Interrupt 12", |
3935 | 91736d37 | blueswir1 | [TT_EXTINT | 0xd] = "External Interrupt 13", |
3936 | 91736d37 | blueswir1 | [TT_EXTINT | 0xe] = "External Interrupt 14", |
3937 | 91736d37 | blueswir1 | [TT_EXTINT | 0xf] = "External Interrupt 15", |
3938 | 91736d37 | blueswir1 | }; |
3939 | 91736d37 | blueswir1 | #endif
|
3940 | 91736d37 | blueswir1 | |
3941 | 8194f35a | Igor Kovalenko | trap_state* cpu_tsptr(CPUState* env) |
3942 | 8194f35a | Igor Kovalenko | { |
3943 | 8194f35a | Igor Kovalenko | return &env->ts[env->tl & MAXTL_MASK];
|
3944 | 8194f35a | Igor Kovalenko | } |
3945 | 8194f35a | Igor Kovalenko | |
3946 | 91736d37 | blueswir1 | void do_interrupt(CPUState *env)
|
3947 | 91736d37 | blueswir1 | { |
3948 | 91736d37 | blueswir1 | int intno = env->exception_index;
|
3949 | 8194f35a | Igor Kovalenko | trap_state* tsptr; |
3950 | 91736d37 | blueswir1 | |
3951 | 91736d37 | blueswir1 | #ifdef DEBUG_PCALL
|
3952 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
3953 | 91736d37 | blueswir1 | static int count; |
3954 | 91736d37 | blueswir1 | const char *name; |
3955 | 91736d37 | blueswir1 | |
3956 | 91736d37 | blueswir1 | if (intno < 0 || intno >= 0x180) |
3957 | 91736d37 | blueswir1 | name = "Unknown";
|
3958 | 91736d37 | blueswir1 | else if (intno >= 0x100) |
3959 | 91736d37 | blueswir1 | name = "Trap Instruction";
|
3960 | 91736d37 | blueswir1 | else if (intno >= 0xc0) |
3961 | 91736d37 | blueswir1 | name = "Window Fill";
|
3962 | 91736d37 | blueswir1 | else if (intno >= 0x80) |
3963 | 91736d37 | blueswir1 | name = "Window Spill";
|
3964 | 91736d37 | blueswir1 | else {
|
3965 | 91736d37 | blueswir1 | name = excp_names[intno]; |
3966 | 91736d37 | blueswir1 | if (!name)
|
3967 | 91736d37 | blueswir1 | name = "Unknown";
|
3968 | 91736d37 | blueswir1 | } |
3969 | 91736d37 | blueswir1 | |
3970 | 93fcfe39 | aliguori | qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 |
3971 | 91736d37 | blueswir1 | " SP=%016" PRIx64 "\n", |
3972 | 91736d37 | blueswir1 | count, name, intno, |
3973 | 91736d37 | blueswir1 | env->pc, |
3974 | 91736d37 | blueswir1 | env->npc, env->regwptr[6]);
|
3975 | 93fcfe39 | aliguori | log_cpu_state(env, 0);
|
3976 | 91736d37 | blueswir1 | #if 0
|
3977 | 91736d37 | blueswir1 | {
|
3978 | 91736d37 | blueswir1 | int i;
|
3979 | 91736d37 | blueswir1 | uint8_t *ptr;
|
3980 | 91736d37 | blueswir1 | |
3981 | 93fcfe39 | aliguori | qemu_log(" code=");
|
3982 | 91736d37 | blueswir1 | ptr = (uint8_t *)env->pc;
|
3983 | 91736d37 | blueswir1 | for(i = 0; i < 16; i++) {
|
3984 | 93fcfe39 | aliguori | qemu_log(" %02x", ldub(ptr + i));
|
3985 | 91736d37 | blueswir1 | }
|
3986 | 93fcfe39 | aliguori | qemu_log("\n");
|
3987 | 91736d37 | blueswir1 | }
|
3988 | 91736d37 | blueswir1 | #endif
|
3989 | 91736d37 | blueswir1 | count++; |
3990 | 91736d37 | blueswir1 | } |
3991 | 91736d37 | blueswir1 | #endif
|
3992 | 91736d37 | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
3993 | 91736d37 | blueswir1 | if (env->tl >= env->maxtl) {
|
3994 | 91736d37 | blueswir1 | cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
|
3995 | 91736d37 | blueswir1 | " Error state", env->exception_index, env->tl, env->maxtl);
|
3996 | 91736d37 | blueswir1 | return;
|
3997 | 91736d37 | blueswir1 | } |
3998 | 91736d37 | blueswir1 | #endif
|
3999 | 91736d37 | blueswir1 | if (env->tl < env->maxtl - 1) { |
4000 | 91736d37 | blueswir1 | env->tl++; |
4001 | 91736d37 | blueswir1 | } else {
|
4002 | 91736d37 | blueswir1 | env->pstate |= PS_RED; |
4003 | 91736d37 | blueswir1 | if (env->tl < env->maxtl)
|
4004 | 91736d37 | blueswir1 | env->tl++; |
4005 | 91736d37 | blueswir1 | } |
4006 | 8194f35a | Igor Kovalenko | tsptr = cpu_tsptr(env); |
4007 | 8194f35a | Igor Kovalenko | |
4008 | 5a834bb4 | Blue Swirl | tsptr->tstate = (get_ccr() << 32) |
|
4009 | 91736d37 | blueswir1 | ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
4010 | 5a834bb4 | Blue Swirl | get_cwp64(); |
4011 | 8194f35a | Igor Kovalenko | tsptr->tpc = env->pc; |
4012 | 8194f35a | Igor Kovalenko | tsptr->tnpc = env->npc; |
4013 | 8194f35a | Igor Kovalenko | tsptr->tt = intno; |
4014 | 5210977a | Igor Kovalenko | |
4015 | 5210977a | Igor Kovalenko | switch (intno) {
|
4016 | 5210977a | Igor Kovalenko | case TT_IVEC:
|
4017 | 5210977a | Igor Kovalenko | change_pstate(PS_PEF | PS_PRIV | PS_IG); |
4018 | 5210977a | Igor Kovalenko | break;
|
4019 | 5210977a | Igor Kovalenko | case TT_TFAULT:
|
4020 | 5210977a | Igor Kovalenko | case TT_DFAULT:
|
4021 | 87f6d3f6 | Igor V. Kovalenko | case TT_TMISS ... TT_TMISS + 3: |
4022 | 87f6d3f6 | Igor V. Kovalenko | case TT_DMISS ... TT_DMISS + 3: |
4023 | 87f6d3f6 | Igor V. Kovalenko | case TT_DPROT ... TT_DPROT + 3: |
4024 | 5210977a | Igor Kovalenko | change_pstate(PS_PEF | PS_PRIV | PS_MG); |
4025 | 5210977a | Igor Kovalenko | break;
|
4026 | 5210977a | Igor Kovalenko | default:
|
4027 | 5210977a | Igor Kovalenko | change_pstate(PS_PEF | PS_PRIV | PS_AG); |
4028 | 5210977a | Igor Kovalenko | break;
|
4029 | 91736d37 | blueswir1 | } |
4030 | 5210977a | Igor Kovalenko | |
4031 | 5a834bb4 | Blue Swirl | if (intno == TT_CLRWIN) {
|
4032 | 5a834bb4 | Blue Swirl | set_cwp(cwp_dec(env->cwp - 1));
|
4033 | 5a834bb4 | Blue Swirl | } else if ((intno & 0x1c0) == TT_SPILL) { |
4034 | 5a834bb4 | Blue Swirl | set_cwp(cwp_dec(env->cwp - env->cansave - 2));
|
4035 | 5a834bb4 | Blue Swirl | } else if ((intno & 0x1c0) == TT_FILL) { |
4036 | 5a834bb4 | Blue Swirl | set_cwp(cwp_inc(env->cwp + 1));
|
4037 | 5a834bb4 | Blue Swirl | } |
4038 | 91736d37 | blueswir1 | env->tbr &= ~0x7fffULL;
|
4039 | 91736d37 | blueswir1 | env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
4040 | 91736d37 | blueswir1 | env->pc = env->tbr; |
4041 | 91736d37 | blueswir1 | env->npc = env->pc + 4;
|
4042 | 821b19fe | Igor V. Kovalenko | env->exception_index = -1;
|
4043 | ee5bbe38 | bellard | } |
4044 | 91736d37 | blueswir1 | #else
|
4045 | 91736d37 | blueswir1 | #ifdef DEBUG_PCALL
|
4046 | 91736d37 | blueswir1 | static const char * const excp_names[0x80] = { |
4047 | 91736d37 | blueswir1 | [TT_TFAULT] = "Instruction Access Fault",
|
4048 | 91736d37 | blueswir1 | [TT_ILL_INSN] = "Illegal Instruction",
|
4049 | 91736d37 | blueswir1 | [TT_PRIV_INSN] = "Privileged Instruction",
|
4050 | 91736d37 | blueswir1 | [TT_NFPU_INSN] = "FPU Disabled",
|
4051 | 91736d37 | blueswir1 | [TT_WIN_OVF] = "Window Overflow",
|
4052 | 91736d37 | blueswir1 | [TT_WIN_UNF] = "Window Underflow",
|
4053 | 91736d37 | blueswir1 | [TT_UNALIGNED] = "Unaligned Memory Access",
|
4054 | 91736d37 | blueswir1 | [TT_FP_EXCP] = "FPU Exception",
|
4055 | 91736d37 | blueswir1 | [TT_DFAULT] = "Data Access Fault",
|
4056 | 91736d37 | blueswir1 | [TT_TOVF] = "Tag Overflow",
|
4057 | 91736d37 | blueswir1 | [TT_EXTINT | 0x1] = "External Interrupt 1", |
4058 | 91736d37 | blueswir1 | [TT_EXTINT | 0x2] = "External Interrupt 2", |
4059 | 91736d37 | blueswir1 | [TT_EXTINT | 0x3] = "External Interrupt 3", |
4060 | 91736d37 | blueswir1 | [TT_EXTINT | 0x4] = "External Interrupt 4", |
4061 | 91736d37 | blueswir1 | [TT_EXTINT | 0x5] = "External Interrupt 5", |
4062 | 91736d37 | blueswir1 | [TT_EXTINT | 0x6] = "External Interrupt 6", |
4063 | 91736d37 | blueswir1 | [TT_EXTINT | 0x7] = "External Interrupt 7", |
4064 | 91736d37 | blueswir1 | [TT_EXTINT | 0x8] = "External Interrupt 8", |
4065 | 91736d37 | blueswir1 | [TT_EXTINT | 0x9] = "External Interrupt 9", |
4066 | 91736d37 | blueswir1 | [TT_EXTINT | 0xa] = "External Interrupt 10", |
4067 | 91736d37 | blueswir1 | [TT_EXTINT | 0xb] = "External Interrupt 11", |
4068 | 91736d37 | blueswir1 | [TT_EXTINT | 0xc] = "External Interrupt 12", |
4069 | 91736d37 | blueswir1 | [TT_EXTINT | 0xd] = "External Interrupt 13", |
4070 | 91736d37 | blueswir1 | [TT_EXTINT | 0xe] = "External Interrupt 14", |
4071 | 91736d37 | blueswir1 | [TT_EXTINT | 0xf] = "External Interrupt 15", |
4072 | 91736d37 | blueswir1 | [TT_TOVF] = "Tag Overflow",
|
4073 | 91736d37 | blueswir1 | [TT_CODE_ACCESS] = "Instruction Access Error",
|
4074 | 91736d37 | blueswir1 | [TT_DATA_ACCESS] = "Data Access Error",
|
4075 | 91736d37 | blueswir1 | [TT_DIV_ZERO] = "Division By Zero",
|
4076 | 91736d37 | blueswir1 | [TT_NCP_INSN] = "Coprocessor Disabled",
|
4077 | 91736d37 | blueswir1 | }; |
4078 | 91736d37 | blueswir1 | #endif
|
4079 | ee5bbe38 | bellard | |
4080 | 91736d37 | blueswir1 | void do_interrupt(CPUState *env)
|
4081 | ee5bbe38 | bellard | { |
4082 | 91736d37 | blueswir1 | int cwp, intno = env->exception_index;
|
4083 | 91736d37 | blueswir1 | |
4084 | 91736d37 | blueswir1 | #ifdef DEBUG_PCALL
|
4085 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
4086 | 91736d37 | blueswir1 | static int count; |
4087 | 91736d37 | blueswir1 | const char *name; |
4088 | 91736d37 | blueswir1 | |
4089 | 91736d37 | blueswir1 | if (intno < 0 || intno >= 0x100) |
4090 | 91736d37 | blueswir1 | name = "Unknown";
|
4091 | 91736d37 | blueswir1 | else if (intno >= 0x80) |
4092 | 91736d37 | blueswir1 | name = "Trap Instruction";
|
4093 | 91736d37 | blueswir1 | else {
|
4094 | 91736d37 | blueswir1 | name = excp_names[intno]; |
4095 | 91736d37 | blueswir1 | if (!name)
|
4096 | 91736d37 | blueswir1 | name = "Unknown";
|
4097 | 91736d37 | blueswir1 | } |
4098 | 91736d37 | blueswir1 | |
4099 | 93fcfe39 | aliguori | qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
|
4100 | 91736d37 | blueswir1 | count, name, intno, |
4101 | 91736d37 | blueswir1 | env->pc, |
4102 | 91736d37 | blueswir1 | env->npc, env->regwptr[6]);
|
4103 | 93fcfe39 | aliguori | log_cpu_state(env, 0);
|
4104 | 91736d37 | blueswir1 | #if 0
|
4105 | 91736d37 | blueswir1 | {
|
4106 | 91736d37 | blueswir1 | int i;
|
4107 | 91736d37 | blueswir1 | uint8_t *ptr;
|
4108 | 91736d37 | blueswir1 | |
4109 | 93fcfe39 | aliguori | qemu_log(" code=");
|
4110 | 91736d37 | blueswir1 | ptr = (uint8_t *)env->pc;
|
4111 | 91736d37 | blueswir1 | for(i = 0; i < 16; i++) {
|
4112 | 93fcfe39 | aliguori | qemu_log(" %02x", ldub(ptr + i));
|
4113 | 91736d37 | blueswir1 | }
|
4114 | 93fcfe39 | aliguori | qemu_log("\n");
|
4115 | 91736d37 | blueswir1 | }
|
4116 | 91736d37 | blueswir1 | #endif
|
4117 | 91736d37 | blueswir1 | count++; |
4118 | 91736d37 | blueswir1 | } |
4119 | 91736d37 | blueswir1 | #endif
|
4120 | 91736d37 | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
4121 | 91736d37 | blueswir1 | if (env->psret == 0) { |
4122 | 91736d37 | blueswir1 | cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
|
4123 | 91736d37 | blueswir1 | env->exception_index); |
4124 | 91736d37 | blueswir1 | return;
|
4125 | 91736d37 | blueswir1 | } |
4126 | 91736d37 | blueswir1 | #endif
|
4127 | 91736d37 | blueswir1 | env->psret = 0;
|
4128 | 5a834bb4 | Blue Swirl | cwp = cwp_dec(env->cwp - 1);
|
4129 | 5a834bb4 | Blue Swirl | set_cwp(cwp); |
4130 | 91736d37 | blueswir1 | env->regwptr[9] = env->pc;
|
4131 | 91736d37 | blueswir1 | env->regwptr[10] = env->npc;
|
4132 | 91736d37 | blueswir1 | env->psrps = env->psrs; |
4133 | 91736d37 | blueswir1 | env->psrs = 1;
|
4134 | 91736d37 | blueswir1 | env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
4135 | 91736d37 | blueswir1 | env->pc = env->tbr; |
4136 | 91736d37 | blueswir1 | env->npc = env->pc + 4;
|
4137 | 95372a39 | Blue Swirl | env->exception_index = -1;
|
4138 | ee5bbe38 | bellard | } |
4139 | 91736d37 | blueswir1 | #endif
|
4140 | ee5bbe38 | bellard | |
4141 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
4142 | ee5bbe38 | bellard | |
4143 | d2889a3e | blueswir1 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
4144 | d2889a3e | blueswir1 | void *retaddr);
|
4145 | d2889a3e | blueswir1 | |
4146 | ee5bbe38 | bellard | #define MMUSUFFIX _mmu
|
4147 | d2889a3e | blueswir1 | #define ALIGNED_ONLY
|
4148 | ee5bbe38 | bellard | |
4149 | ee5bbe38 | bellard | #define SHIFT 0 |
4150 | ee5bbe38 | bellard | #include "softmmu_template.h" |
4151 | ee5bbe38 | bellard | |
4152 | ee5bbe38 | bellard | #define SHIFT 1 |
4153 | ee5bbe38 | bellard | #include "softmmu_template.h" |
4154 | ee5bbe38 | bellard | |
4155 | ee5bbe38 | bellard | #define SHIFT 2 |
4156 | ee5bbe38 | bellard | #include "softmmu_template.h" |
4157 | ee5bbe38 | bellard | |
4158 | ee5bbe38 | bellard | #define SHIFT 3 |
4159 | ee5bbe38 | bellard | #include "softmmu_template.h" |
4160 | ee5bbe38 | bellard | |
4161 | c2bc0e38 | blueswir1 | /* XXX: make it generic ? */
|
4162 | c2bc0e38 | blueswir1 | static void cpu_restore_state2(void *retaddr) |
4163 | c2bc0e38 | blueswir1 | { |
4164 | c2bc0e38 | blueswir1 | TranslationBlock *tb; |
4165 | c2bc0e38 | blueswir1 | unsigned long pc; |
4166 | c2bc0e38 | blueswir1 | |
4167 | c2bc0e38 | blueswir1 | if (retaddr) {
|
4168 | c2bc0e38 | blueswir1 | /* now we have a real cpu fault */
|
4169 | c2bc0e38 | blueswir1 | pc = (unsigned long)retaddr; |
4170 | c2bc0e38 | blueswir1 | tb = tb_find_pc(pc); |
4171 | c2bc0e38 | blueswir1 | if (tb) {
|
4172 | c2bc0e38 | blueswir1 | /* the PC is inside the translated code. It means that we have
|
4173 | c2bc0e38 | blueswir1 | a virtual CPU fault */
|
4174 | c2bc0e38 | blueswir1 | cpu_restore_state(tb, env, pc, (void *)(long)env->cond); |
4175 | c2bc0e38 | blueswir1 | } |
4176 | c2bc0e38 | blueswir1 | } |
4177 | c2bc0e38 | blueswir1 | } |
4178 | c2bc0e38 | blueswir1 | |
4179 | d2889a3e | blueswir1 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
4180 | d2889a3e | blueswir1 | void *retaddr)
|
4181 | d2889a3e | blueswir1 | { |
4182 | 94554550 | blueswir1 | #ifdef DEBUG_UNALIGNED
|
4183 | c2bc0e38 | blueswir1 | printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx |
4184 | c2bc0e38 | blueswir1 | "\n", addr, env->pc);
|
4185 | 94554550 | blueswir1 | #endif
|
4186 | c2bc0e38 | blueswir1 | cpu_restore_state2(retaddr); |
4187 | 94554550 | blueswir1 | raise_exception(TT_UNALIGNED); |
4188 | d2889a3e | blueswir1 | } |
4189 | ee5bbe38 | bellard | |
4190 | ee5bbe38 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
|
4191 | ee5bbe38 | bellard | NULL, it means that the function was called in C code (i.e. not
|
4192 | ee5bbe38 | bellard | from generated code or from helper.c) */
|
4193 | ee5bbe38 | bellard | /* XXX: fix it to restore all registers */
|
4194 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
4195 | ee5bbe38 | bellard | { |
4196 | ee5bbe38 | bellard | int ret;
|
4197 | ee5bbe38 | bellard | CPUState *saved_env; |
4198 | ee5bbe38 | bellard | |
4199 | ee5bbe38 | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
4200 | ee5bbe38 | bellard | generated code */
|
4201 | ee5bbe38 | bellard | saved_env = env; |
4202 | ee5bbe38 | bellard | env = cpu_single_env; |
4203 | ee5bbe38 | bellard | |
4204 | 6ebbf390 | j_mayer | ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
4205 | ee5bbe38 | bellard | if (ret) {
|
4206 | c2bc0e38 | blueswir1 | cpu_restore_state2(retaddr); |
4207 | ee5bbe38 | bellard | cpu_loop_exit(); |
4208 | ee5bbe38 | bellard | } |
4209 | ee5bbe38 | bellard | env = saved_env; |
4210 | ee5bbe38 | bellard | } |
4211 | ee5bbe38 | bellard | |
4212 | 3c7b48b7 | Paul Brook | #endif /* !CONFIG_USER_ONLY */ |
4213 | 6c36d3fa | blueswir1 | |
4214 | 6c36d3fa | blueswir1 | #ifndef TARGET_SPARC64
|
4215 | 3c7b48b7 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
|
4216 | c227f099 | Anthony Liguori | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
4217 | e18231a3 | blueswir1 | int is_asi, int size) |
4218 | 6c36d3fa | blueswir1 | { |
4219 | 6c36d3fa | blueswir1 | CPUState *saved_env; |
4220 | 576c2cdc | Artyom Tarasenko | int fault_type;
|
4221 | 6c36d3fa | blueswir1 | |
4222 | 6c36d3fa | blueswir1 | /* XXX: hack to restore env in all cases, even if not called from
|
4223 | 6c36d3fa | blueswir1 | generated code */
|
4224 | 6c36d3fa | blueswir1 | saved_env = env; |
4225 | 6c36d3fa | blueswir1 | env = cpu_single_env; |
4226 | 8543e2cf | blueswir1 | #ifdef DEBUG_UNASSIGNED
|
4227 | 8543e2cf | blueswir1 | if (is_asi)
|
4228 | e18231a3 | blueswir1 | printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
|
4229 | 77f193da | blueswir1 | " asi 0x%02x from " TARGET_FMT_lx "\n", |
4230 | e18231a3 | blueswir1 | is_exec ? "exec" : is_write ? "write" : "read", size, |
4231 | e18231a3 | blueswir1 | size == 1 ? "" : "s", addr, is_asi, env->pc); |
4232 | 8543e2cf | blueswir1 | else
|
4233 | e18231a3 | blueswir1 | printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
|
4234 | e18231a3 | blueswir1 | " from " TARGET_FMT_lx "\n", |
4235 | e18231a3 | blueswir1 | is_exec ? "exec" : is_write ? "write" : "read", size, |
4236 | e18231a3 | blueswir1 | size == 1 ? "" : "s", addr, env->pc); |
4237 | 8543e2cf | blueswir1 | #endif
|
4238 | 576c2cdc | Artyom Tarasenko | /* Don't overwrite translation and access faults */
|
4239 | 576c2cdc | Artyom Tarasenko | fault_type = (env->mmuregs[3] & 0x1c) >> 2; |
4240 | 576c2cdc | Artyom Tarasenko | if ((fault_type > 4) || (fault_type == 0)) { |
4241 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] = 0; /* Fault status register */ |
4242 | 576c2cdc | Artyom Tarasenko | if (is_asi)
|
4243 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= 1 << 16; |
4244 | 576c2cdc | Artyom Tarasenko | if (env->psrs)
|
4245 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= 1 << 5; |
4246 | 576c2cdc | Artyom Tarasenko | if (is_exec)
|
4247 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= 1 << 6; |
4248 | 576c2cdc | Artyom Tarasenko | if (is_write)
|
4249 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= 1 << 7; |
4250 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= (5 << 2) | 2; |
4251 | 576c2cdc | Artyom Tarasenko | /* SuperSPARC will never place instruction fault addresses in the FAR */
|
4252 | 576c2cdc | Artyom Tarasenko | if (!is_exec) {
|
4253 | 576c2cdc | Artyom Tarasenko | env->mmuregs[4] = addr; /* Fault address register */ |
4254 | 576c2cdc | Artyom Tarasenko | } |
4255 | 576c2cdc | Artyom Tarasenko | } |
4256 | 576c2cdc | Artyom Tarasenko | /* overflow (same type fault was not read before another fault) */
|
4257 | 576c2cdc | Artyom Tarasenko | if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { |
4258 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= 1; |
4259 | 576c2cdc | Artyom Tarasenko | } |
4260 | 576c2cdc | Artyom Tarasenko | |
4261 | 6c36d3fa | blueswir1 | if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
4262 | 1b2e93c1 | blueswir1 | if (is_exec)
|
4263 | 1b2e93c1 | blueswir1 | raise_exception(TT_CODE_ACCESS); |
4264 | 1b2e93c1 | blueswir1 | else
|
4265 | 1b2e93c1 | blueswir1 | raise_exception(TT_DATA_ACCESS); |
4266 | 6c36d3fa | blueswir1 | } |
4267 | 576c2cdc | Artyom Tarasenko | |
4268 | 576c2cdc | Artyom Tarasenko | /* flush neverland mappings created during no-fault mode,
|
4269 | 576c2cdc | Artyom Tarasenko | so the sequential MMU faults report proper fault types */
|
4270 | 576c2cdc | Artyom Tarasenko | if (env->mmuregs[0] & MMU_NF) { |
4271 | 576c2cdc | Artyom Tarasenko | tlb_flush(env, 1);
|
4272 | 576c2cdc | Artyom Tarasenko | } |
4273 | 15e7c451 | Artyom Tarasenko | |
4274 | 15e7c451 | Artyom Tarasenko | env = saved_env; |
4275 | 6c36d3fa | blueswir1 | } |
4276 | 3c7b48b7 | Paul Brook | #endif
|
4277 | 3c7b48b7 | Paul Brook | #else
|
4278 | 3c7b48b7 | Paul Brook | #if defined(CONFIG_USER_ONLY)
|
4279 | 3c7b48b7 | Paul Brook | static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, |
4280 | 3c7b48b7 | Paul Brook | int is_asi, int size) |
4281 | 6c36d3fa | blueswir1 | #else
|
4282 | c227f099 | Anthony Liguori | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
4283 | e18231a3 | blueswir1 | int is_asi, int size) |
4284 | 3c7b48b7 | Paul Brook | #endif
|
4285 | 6c36d3fa | blueswir1 | { |
4286 | 6c36d3fa | blueswir1 | CPUState *saved_env; |
4287 | 6c36d3fa | blueswir1 | |
4288 | 6c36d3fa | blueswir1 | /* XXX: hack to restore env in all cases, even if not called from
|
4289 | 6c36d3fa | blueswir1 | generated code */
|
4290 | 6c36d3fa | blueswir1 | saved_env = env; |
4291 | 6c36d3fa | blueswir1 | env = cpu_single_env; |
4292 | dffbe217 | Igor V. Kovalenko | |
4293 | dffbe217 | Igor V. Kovalenko | #ifdef DEBUG_UNASSIGNED
|
4294 | 77f193da | blueswir1 | printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx |
4295 | 77f193da | blueswir1 | "\n", addr, env->pc);
|
4296 | 6c36d3fa | blueswir1 | #endif
|
4297 | dffbe217 | Igor V. Kovalenko | |
4298 | 1b2e93c1 | blueswir1 | if (is_exec)
|
4299 | 1b2e93c1 | blueswir1 | raise_exception(TT_CODE_ACCESS); |
4300 | 1b2e93c1 | blueswir1 | else
|
4301 | 1b2e93c1 | blueswir1 | raise_exception(TT_DATA_ACCESS); |
4302 | dffbe217 | Igor V. Kovalenko | |
4303 | dffbe217 | Igor V. Kovalenko | env = saved_env; |
4304 | 6c36d3fa | blueswir1 | } |
4305 | 6c36d3fa | blueswir1 | #endif
|
4306 | 20c9f095 | blueswir1 | |
4307 | 3c7b48b7 | Paul Brook | |
4308 | f4b1a842 | blueswir1 | #ifdef TARGET_SPARC64
|
4309 | f4b1a842 | blueswir1 | void helper_tick_set_count(void *opaque, uint64_t count) |
4310 | f4b1a842 | blueswir1 | { |
4311 | f4b1a842 | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
4312 | f4b1a842 | blueswir1 | cpu_tick_set_count(opaque, count); |
4313 | f4b1a842 | blueswir1 | #endif
|
4314 | f4b1a842 | blueswir1 | } |
4315 | f4b1a842 | blueswir1 | |
4316 | f4b1a842 | blueswir1 | uint64_t helper_tick_get_count(void *opaque)
|
4317 | f4b1a842 | blueswir1 | { |
4318 | f4b1a842 | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
4319 | f4b1a842 | blueswir1 | return cpu_tick_get_count(opaque);
|
4320 | f4b1a842 | blueswir1 | #else
|
4321 | f4b1a842 | blueswir1 | return 0; |
4322 | f4b1a842 | blueswir1 | #endif
|
4323 | f4b1a842 | blueswir1 | } |
4324 | f4b1a842 | blueswir1 | |
4325 | f4b1a842 | blueswir1 | void helper_tick_set_limit(void *opaque, uint64_t limit) |
4326 | f4b1a842 | blueswir1 | { |
4327 | f4b1a842 | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
4328 | f4b1a842 | blueswir1 | cpu_tick_set_limit(opaque, limit); |
4329 | f4b1a842 | blueswir1 | #endif
|
4330 | f4b1a842 | blueswir1 | } |
4331 | f4b1a842 | blueswir1 | #endif |