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# Date Author Comment
fe987e23 06/02/2010 11:05 pm Igor V. Kovalenko

sparc64: fix ldxfsr insn

- rearrange code to break from switch when appropriate
- allow deprecated ldfsr insn

Signed-off-by: Igor V. Kovalenko <>
Signed-off-by: Blue Swirl <>

1295001c 06/02/2010 11:03 pm Igor V. Kovalenko

sparc64: fix missing address masking v1

- address masking for ldqf and stqf insns
- address masking for lddf and stdf insns
- address masking for translating ASI (Ultrasparc IIi)
v0->v1:
- move arch-specific code to helpers and drop more ifdefs at call sites...

9fd1ae3a 05/22/2010 03:51 pm Igor V. Kovalenko

sparc64: fix mmu context at trap levels above zero

- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero
- cpu_get_tb_cpu_state: store trap level and primary context in flags
this allows to restart code translation when address translation is changed...

2aae2b8e 05/22/2010 03:48 pm Igor V. Kovalenko

sparc64: fix pstate privilege bits

- refactor code to handle hpstate only if available for current cpu
- conditionally set hypervisor bit in hpstate register
- reorder softmmu indices so user accessable ones go first, translation context
macros supervisor() and hypervisor() adjusted as well...

70c48285 05/20/2010 10:58 pm Richard Henderson

target-sparc: Inline some generation of carry for ADDX/SUBX.

Computing carry is trivial for some inputs. By avoiding an
external function call, we generate near-optimal code for
the common cases of add+addx (double-word arithmetic) and
cmp+addx (a setcc pattern)....

275ea265 05/09/2010 06:40 pm Blue Swirl

sparc: lazy C flag calculation

Calculate only the carry flag for ADDX/SUBX instead of full
set of flags.

Thanks to Igor Kovalenko for spotting a bug with an earlier
version.

Signed-off-by: Blue Swirl <>

060718c1 04/26/2010 08:23 pm Richard Henderson

target-sparc: Fix -singlestep.

Single-stepping was not properly updating npc, resulting in some
instructions being executed twice. In addition, we were emitting
dead code at the end of the TB.

Fix both by teaching gen_goto_tb to avoid goto_tb for single-step...

6ad6135d 04/18/2010 05:22 pm Blue Swirl

Fix harmless if statements with empty body, spotted by clang

These clang errors are harmless but worth fixing:
CC ppc-softmmu/usb-ohci.o
/src/qemu/hw/usb-ohci.c:1104:59: error: if statement has empty body [-Wempty-body]
ohci->ctrl_head, ohci->ctrl_cur);...

42a8aa83 04/17/2010 07:25 pm Richard Henderson

target-sparc: Free instruction temporaries.

Rather than creating new temporaries for constants, use the
ones created in disas_sparc_insn. Remember the temps created
there so that they can be freed at the end of the function.

Profile data collected by TCG while booting sparc-test kernel:...

cca1d527 04/17/2010 07:25 pm Blue Swirl

Sparc: fix PC/NPC during FPU traps

All FPU instructions can trap, so save PC/NPC state before
executing them.

Signed-off-by: Blue Swirl <>

d7da2a10 04/11/2010 10:47 pm Blue Swirl

Sparc: fix exceptions in delay slot

Fix a case where an exception happens with the
instruction in the delay slot.

Recovery of branch condition in the exception handling
code was not converted to TCG. Because the condition
was bogus, wrong NPC could be selected from the two...

1a7ff922 04/08/2010 10:34 pm Paolo Bonzini

remove TARGET_* defines from translate-all.c

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Aurelien Jarno <>

bc57c114 02/25/2010 08:26 pm Stefan Weil

target-sparc: fix --enable-debug build for 64 bit host

b551ec04ca45d1925417dd2ec7c1b7f115c84f1d fixed
the compilation for 32 bit hosts, but introduced
a new error for 64 bit hosts:

tcg_temp_new_ptr needs a matching tcg_temp_free_ptr.

Signed-off-by: Stefan Weil <>...

b551ec04 02/20/2010 01:09 pm Jay Foad

target-sparc: fix --enable-debug build

Use 32-bit arithmetic for the address offset calculation to fix a
build failure on 32-bit hosts.

Signed-off-by: Jay Foad <>
Signed-off-by: Blue Swirl <>

1fae7b70 01/08/2010 07:14 pm Igor V. Kovalenko

sparc64: use helper_wrpil to check pending irq on write

Signed-off-by: Igor V. Kovalenko <>
Signed-off-by: Blue Swirl <>

01b5d4e5 09/23/2009 11:00 pm Igor V. Kovalenko

sparc64-8bit-asi

Sparc64 alternate space load/store helpers expect 8 bit ASI value,
while wrasi implementation sign-extends ASI operand causing
for example 0x80 to appear as 0xFFFFFF80. Resulting value falls
out of switch in helpers and causes obscure load/store faults....

72cf2d4f 09/12/2009 10:36 am Blue Swirl

Fix sys-queue.h conflict for good

Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...

c27e2752 08/22/2009 02:46 pm Blue Swirl

Sparc32/64: fix jmpl followed by branch

Fix a case where 'jmpl' instruction followed by a branch instruction was
handled incorrectly.

Signed-off-by: Blue Swirl <>

cfa90513 08/15/2009 07:52 pm Blue Swirl

Fix desynchronization of condition code state when a memory access traps

Signed-off-by: Blue Swirl <>

8194f35a 08/04/2009 11:22 pm Igor Kovalenko

Sparc64: replace tsptr with helper routine

tl and tsptr of members sparc64 cpu state must be changed
simultaneously to keep trap state window in sync with current
trap level. Currently translation of store to tl does not change
tsptr, which leads to corrupt trap state on corresponding...

14ed7adc 07/31/2009 09:48 am Igor Kovalenko

sparc64 flush pending conditional evaluations before exposing cpu state

If translation block is interrupted by e.g. mmu exception
we need to compute conditional flags for inclusion into
saved cpu state. Otherwise after return from trap
conditional instructions would use stale psr/xcc data....

8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>

25517f99 06/06/2009 04:54 am Paul Brook

Use correct type for SPARC cpu_cc_op

Signed-off-by: Paul Brook <>

d084469c 05/10/2009 10:43 am Blue Swirl

Convert mulscc

Signed-off-by: Blue Swirl <>

6c78ea32 05/10/2009 10:42 am Blue Swirl

Convert udiv/sdiv

Signed-off-by: Blue Swirl <>

3b2d1e92 05/10/2009 10:38 am Blue Swirl

Convert tagged ops

Signed-off-by: Blue Swirl <>

38482a77 05/10/2009 10:38 am Blue Swirl

Convert logical operations and umul/smul

Signed-off-by: Blue Swirl <>

d4b0d468 05/10/2009 10:38 am Blue Swirl

Convert sub

Signed-off-by: Blue Swirl <>

2ca1d92b 05/10/2009 10:38 am Blue Swirl

Convert subx

Signed-off-by: Blue Swirl <>

789c91ef 05/10/2009 10:19 am Blue Swirl

Convert addx

Signed-off-by: Blue Swirl <>

bdf9f35d 05/10/2009 10:19 am Blue Swirl

Convert add

Signed-off-by: Blue Swirl <>

8393617c 05/10/2009 10:19 am Blue Swirl

Use dynamical computation for condition codes

Signed-off-by: Blue Swirl <>

719f66a7 05/03/2009 09:51 pm Blue Swirl

Optimize cmp x, 0 case

Signed-off-by: Blue Swirl <>

dc1a6971 05/03/2009 09:51 pm Blue Swirl

Reindent

Signed-off-by: Blue Swirl <>

b89e94af 05/02/2009 11:19 pm Blue Swirl

Improve instruction name comments for easier searching

Signed-off-by: Blue Swirl <>

41d72852 05/02/2009 10:14 pm Blue Swirl

Optimize operations with immediate parameters

67526b20 05/02/2009 09:58 pm Blue Swirl

Fix Sparc64 sign extension problems

Signed-off-by: Blue Swirl <>

1b530a6d 04/05/2009 11:08 pm aurel32

Add new command line option -singlestep for tcg single stepping.

This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode....

d78f3995 03/16/2009 06:33 pm blueswir1

Delete some unused macros detected with -Wp,-Wunused-macros use

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6856 c046a42c-6fe2-441c-8c8c-71466251a162

8fec2b8c 01/16/2009 12:36 am aliguori

global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)

These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...

93fcfe39 01/16/2009 12:34 am aliguori

Convert references to logfile/loglevel to use qemu_log*() macros

This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...

fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...

c0ce998e 11/26/2008 12:13 am aliguori

Use sys-queue.h for break/watchpoint managment (Jan Kiszka)

This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the
code and also fixing a use after release issue in
cpu_break/watchpoint_remove_all.

Signed-off-by: Jan Kiszka <>...

a1d1bb31 11/18/2008 10:07 pm aliguori

Refactor and enhance break/watchpoint API (Jan Kiszka)

This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the
succeeding enhancements this series comes with.

First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching
to dynamically allocated data structures that are kept in linked lists....

a7812ae4 11/17/2008 04:43 pm pbrook

TCG variable type checking.

Signed-off-by: Paul Brook <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162

2576d836 11/09/2008 09:52 pm blueswir1

Use TCG not op

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5663 c046a42c-6fe2-441c-8c8c-71466251a162

81b5b816 11/09/2008 09:50 pm blueswir1

Use andc, orc, nor and nand
Also fix which argument gets negated in fandnot12 and fornot12

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5662 c046a42c-6fe2-441c-8c8c-71466251a162

527067d8 11/01/2008 03:44 pm blueswir1

Fix TCGv size mismatches

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5593 c046a42c-6fe2-441c-8c8c-71466251a162

b158a785 09/26/2008 09:05 pm blueswir1

Implement UA2005 hypervisor traps

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162

9d926598 09/22/2008 10:50 pm blueswir1

Add software and timer interrupt support

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162

ab508019 09/21/2008 09:43 pm blueswir1

Use the new concat_tl_i64 op for std and stda

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5283 c046a42c-6fe2-441c-8c8c-71466251a162

a7ec4229 09/21/2008 05:49 pm blueswir1

Use the new concat_i32_i64 op for std and stda

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5281 c046a42c-6fe2-441c-8c8c-71466251a162

72ccba79 09/13/2008 08:20 pm blueswir1

Fix mulscc with high bits set in either src1 or src2

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5201 c046a42c-6fe2-441c-8c8c-71466251a162

5068cbd9 09/11/2008 07:01 pm blueswir1

Write zeros to high bits of y, based on patch by Vince Weaver

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5196 c046a42c-6fe2-441c-8c8c-71466251a162

d84763bc 09/10/2008 11:09 pm blueswir1

Convert rest of ops using float32 to TCG, remove FT0 and FT1

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162

c5d04e99 09/10/2008 11:00 pm blueswir1

Partially convert float128 conversion ops to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162

e2ea21b3 09/10/2008 10:57 pm blueswir1

Convert basic 64 bit VIS ops to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162

1d01299d 09/10/2008 10:57 pm blueswir1

Convert basic 32 bit VIS ops to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162

714547bb 09/10/2008 10:54 pm blueswir1

Convert basic float32 ops to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162

3a3b925d 09/09/2008 10:02 pm blueswir1

Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162

510aba20 09/06/2008 08:54 pm blueswir1

Fix a typo in fpsub32

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5177 c046a42c-6fe2-441c-8c8c-71466251a162

255e1fcb 09/06/2008 08:51 pm blueswir1

Convert most env fields to TCG registers

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5176 c046a42c-6fe2-441c-8c8c-71466251a162

47ad35f1 09/06/2008 08:50 pm blueswir1

Silence gcc warning about constant overflow

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5175 c046a42c-6fe2-441c-8c8c-71466251a162

b991c385 09/02/2008 07:33 pm blueswir1

Fix sign extension problems with smul and umul (Vince Weaver)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5138 c046a42c-6fe2-441c-8c8c-71466251a162

105a1f04 09/01/2008 10:35 pm blueswir1

Fix y register loads and stores

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5123 c046a42c-6fe2-441c-8c8c-71466251a162

ba6a9d8c 08/30/2008 12:03 am blueswir1

Fix FCC handling for Sparc64 target, initial patch by Vince Weaver

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5110 c046a42c-6fe2-441c-8c8c-71466251a162

c93e7817 08/21/2008 08:34 pm blueswir1

Fix wrwim masking (Luis Pureza)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5043 c046a42c-6fe2-441c-8c8c-71466251a162

5578ceab 08/21/2008 08:33 pm blueswir1

Use initial CPU definition structure for some CPU fields instead of copying
them around, based on patch by Luis Pureza.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5042 c046a42c-6fe2-441c-8c8c-71466251a162

2ae72bce 08/17/2008 11:33 am blueswir1

Correct 32bit carry flag for add instruction (Igor Kovalenko)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5017 c046a42c-6fe2-441c-8c8c-71466251a162

01b1fa6d 08/06/2008 09:13 pm blueswir1

Fix Sparc64 shifts

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4990 c046a42c-6fe2-441c-8c8c-71466251a162

95f9397c 08/06/2008 06:28 pm blueswir1

Fix offset handling for ASI loads and stores (Vince Weaver)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4988 c046a42c-6fe2-441c-8c8c-71466251a162

dd5e6304 07/29/2008 09:11 pm blueswir1

Fix cmp/subcc/addcc op bugs reported by Vince Weaver

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4970 c046a42c-6fe2-441c-8c8c-71466251a162

fb79ceb9 07/20/2008 09:22 pm blueswir1

Make UA200x features selectable, add MMU types

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4911 c046a42c-6fe2-441c-8c8c-71466251a162

db166940 07/19/2008 04:25 pm blueswir1

Implement nucleus quad ldda

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4902 c046a42c-6fe2-441c-8c8c-71466251a162

2cfc5f17 07/18/2008 09:01 pm ths

Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162

8d7d8c4b 07/18/2008 01:26 pm blueswir1

wrhpr hstick_cmpr is a store, not a load

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4887 c046a42c-6fe2-441c-8c8c-71466251a162

2cade6a3 07/17/2008 03:53 pm blueswir1

Support for address masking

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4882 c046a42c-6fe2-441c-8c8c-71466251a162

c5f2f668 07/16/2008 02:51 pm blueswir1

Flushw can generate exceptions, so save PC & NPC

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4876 c046a42c-6fe2-441c-8c8c-71466251a162

71817e48 07/15/2008 05:52 pm blueswir1

Really fix cas

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4869 c046a42c-6fe2-441c-8c8c-71466251a162

2e70f6ef 06/29/2008 04:03 am pbrook

Add instruction counter.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162

d987963a 06/22/2008 01:58 pm blueswir1

Eliminate cpu_T0

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4776 c046a42c-6fe2-441c-8c8c-71466251a162

3f0436fe 06/22/2008 11:52 am blueswir1

Eliminate cpu_T1

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4775 c046a42c-6fe2-441c-8c8c-71466251a162

ece43b8d 06/21/2008 10:50 pm blueswir1

Convert some cpu_dst uses (with loads/stores) to cpu_tmp0

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4772 c046a42c-6fe2-441c-8c8c-71466251a162

5c6a0628 06/21/2008 10:46 pm blueswir1

Avoid brcond problems, use temps for cpu_src1 & cpu_src2

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4771 c046a42c-6fe2-441c-8c8c-71466251a162

07bf2857 06/15/2008 09:06 pm blueswir1

Avoid temporary variable use across basic blocks for udivx

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4744 c046a42c-6fe2-441c-8c8c-71466251a162

1a14026e 06/07/2008 11:07 am blueswir1

Allow NWINDOWS selection (CPU feature with model specific defaults)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4690 c046a42c-6fe2-441c-8c8c-71466251a162

e30b4678 05/29/2008 09:20 pm blueswir1

MicroSparc I didn't have fsmuld op

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4618 c046a42c-6fe2-441c-8c8c-71466251a162

2ea815ca 05/27/2008 10:39 pm blueswir1

Free temps

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4591 c046a42c-6fe2-441c-8c8c-71466251a162

8d96d209 05/26/2008 10:42 pm blueswir1

More TCG type fixes

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4589 c046a42c-6fe2-441c-8c8c-71466251a162

ef28fd86 05/26/2008 08:53 pm blueswir1

Fix cas on i386

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4587 c046a42c-6fe2-441c-8c8c-71466251a162

4f7de373 05/25/2008 09:01 pm bellard

remove absolete function

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4579 c046a42c-6fe2-441c-8c8c-71466251a162

a8c768c0 05/25/2008 02:17 pm blueswir1

Nicer debug output

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4573 c046a42c-6fe2-441c-8c8c-71466251a162

bcb0126f 05/24/2008 05:24 am pbrook

More TCGv type fixes.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4553 c046a42c-6fe2-441c-8c8c-71466251a162

cb63669a 05/24/2008 05:22 am pbrook

Fix ARM conditional branch bug.
Add tcg_gen_brcondi.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4552 c046a42c-6fe2-441c-8c8c-71466251a162

455f9004 05/24/2008 05:12 am pbrook

Fix helper operand type mismatch.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4551 c046a42c-6fe2-441c-8c8c-71466251a162

c9e03d8f 05/22/2008 09:16 pm blueswir1

Register op helpers

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4534 c046a42c-6fe2-441c-8c8c-71466251a162

e35298cd 05/17/2008 12:43 pm blueswir1

Generate better code for Sparc32 shifts

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4467 c046a42c-6fe2-441c-8c8c-71466251a162

77f193da 05/12/2008 07:13 pm blueswir1

Wrap long lines

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4440 c046a42c-6fe2-441c-8c8c-71466251a162

c2bc0e38 05/11/2008 10:24 pm blueswir1

Remove someexplicit alignment checks (initial patch by Fabrice Bellard)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4431 c046a42c-6fe2-441c-8c8c-71466251a162

0dcda9be 05/10/2008 03:09 pm blueswir1

Add a TODO file

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4410 c046a42c-6fe2-441c-8c8c-71466251a162