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/*
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 * ACPI implementation
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 * 
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 * Copyright (c) 2006 Fabrice Bellard
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 * 
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License version 2 as published by the Free Software Foundation.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "vl.h"
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//#define DEBUG
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/* i82731AB (PIIX4) compatible power management function */
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#define PM_FREQ 3579545
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/* XXX: make them variable */
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#define PM_IO_BASE        0xb000
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#define SMI_CMD_IO_ADDR   0xb040
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#define ACPI_DBG_IO_ADDR  0xb044
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typedef struct PIIX4PMState {
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    PCIDevice dev;
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    uint16_t pmsts;
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    uint16_t pmen;
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    uint16_t pmcntrl;
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    QEMUTimer *tmr_timer;
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    int64_t tmr_overflow_time;
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} PIIX4PMState;
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define SCI_EN (1 << 0)
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#define SUS_EN (1 << 13)
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/* Note: only used for ACPI bios init. Could be deleted when ACPI init
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   is integrated in Bochs BIOS */
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static PIIX4PMState *piix4_pm_state;
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{
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    uint32_t d;
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    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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    return d & 0xffffff;
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}
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static int get_pmsts(PIIX4PMState *s)
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{
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    int64_t d;
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    int pmsts;
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    pmsts = s->pmsts;
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    d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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    if (d >= s->tmr_overflow_time)
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        s->pmsts |= TMROF_EN;
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    return pmsts;
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}
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static void pm_update_sci(PIIX4PMState *s)
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{
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    int sci_level, pmsts;
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    int64_t expire_time;
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    pmsts = get_pmsts(s);
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    sci_level = (((pmsts & s->pmen) & 
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                  (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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    pci_set_irq(&s->dev, 0, sci_level);
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    /* schedule a timer interruption if needed */
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    if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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        expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
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        qemu_mod_timer(s->tmr_timer, expire_time);
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    } else {
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        qemu_del_timer(s->tmr_timer);
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    }
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}
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static void pm_tmr_timer(void *opaque)
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{
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    PIIX4PMState *s = opaque;
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    pm_update_sci(s);
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}
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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    PIIX4PMState *s = opaque;
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    addr &= 0x3f;
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    switch(addr) {
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    case 0x00:
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        {
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            int64_t d;
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            int pmsts;
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            pmsts = get_pmsts(s);
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            if (pmsts & val & TMROF_EN) {
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                /* if TMRSTS is reset, then compute the new overflow time */
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                d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
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                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
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            }
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            s->pmsts &= ~val;
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            pm_update_sci(s);
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        }
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        break;
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    case 0x02:
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        s->pmen = val;
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        pm_update_sci(s);
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        break;
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    case 0x04:
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        {
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            int sus_typ;
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            s->pmcntrl = val & ~(SUS_EN);
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            if (val & SUS_EN) {
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                /* change suspend type */
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                sus_typ = (val >> 10) & 3;
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                switch(sus_typ) {
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                case 0: /* soft power off */
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                    qemu_system_shutdown_request();
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                    break;
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                default:
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                    break;
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                }
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            }
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        }
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        break;
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    default:
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        break;
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    }
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#ifdef DEBUG
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    printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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#endif
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}
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
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{
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    PIIX4PMState *s = opaque;
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    uint32_t val;
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    addr &= 0x3f;
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    switch(addr) {
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    case 0x00:
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        val = get_pmsts(s);
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        break;
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    case 0x02:
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        val = s->pmen;
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        break;
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    case 0x04:
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        val = s->pmcntrl;
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        break;
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    default:
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        val = 0;
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        break;
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    }
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#ifdef DEBUG
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    printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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#endif
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    return val;
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}
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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    //    PIIX4PMState *s = opaque;
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    addr &= 0x3f;
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#ifdef DEBUG
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    printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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#endif
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}
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
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{
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    PIIX4PMState *s = opaque;
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    uint32_t val;
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    addr &= 0x3f;
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    switch(addr) {
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    case 0x08:
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        val = get_pmtmr(s);
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        break;
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    default:
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        val = 0;
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        break;
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    }
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#ifdef DEBUG
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    printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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#endif
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    return val;
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}
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static void smi_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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    PIIX4PMState *s = opaque;
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#ifdef DEBUG
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    printf("SMI cmd val=0x%02x\n", val);
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#endif
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    switch(val) {
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    case 0xf0: /* ACPI disable */
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        s->pmcntrl &= ~SCI_EN;
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        break;
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    case 0xf1: /* ACPI enable */
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        s->pmcntrl |= SCI_EN;
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        break;
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    }
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}
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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#if defined(DEBUG)
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    printf("ACPI: DBG: 0x%08x\n", val);
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#endif
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}
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/* XXX: we still add it to the PIIX3 and we count on the fact that
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   OSes are smart enough to accept this strange configuration */
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void piix4_pm_init(PCIBus *bus, int devfn)
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{
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    PIIX4PMState *s;
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    uint8_t *pci_conf;
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    uint32_t pm_io_base;
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    s = (PIIX4PMState *)pci_register_device(bus,
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                                         "PM", sizeof(PIIX4PMState),
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                                         devfn, NULL, NULL);
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    pci_conf = s->dev.config;
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    pci_conf[0x00] = 0x86;
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    pci_conf[0x01] = 0x80;
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    pci_conf[0x02] = 0x13;
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    pci_conf[0x03] = 0x71;
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    pci_conf[0x08] = 0x00; // revision number
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    pci_conf[0x09] = 0x00;
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    pci_conf[0x0a] = 0x80; // other bridge device
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    pci_conf[0x0b] = 0x06; // bridge device
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    pci_conf[0x0e] = 0x00; // header_type
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    pci_conf[0x3d] = 0x01; // interrupt pin 1
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    pci_conf[0x60] = 0x10; // release number
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    pm_io_base = PM_IO_BASE;
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    pci_conf[0x40] = pm_io_base | 1;
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    pci_conf[0x41] = pm_io_base >> 8;
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    register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
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    register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
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    register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
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    register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
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    register_ioport_write(SMI_CMD_IO_ADDR, 1, 1, smi_cmd_writeb, s);
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    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
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    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
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    piix4_pm_state = s;
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}
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/* ACPI tables */
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/* XXX: move them in the Bochs BIOS ? */
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/*************************************************/
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/* Table structure from Linux kernel (the ACPI tables are under the
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   BSD license) */
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#define ACPI_TABLE_HEADER_DEF   /* ACPI common table header */ \
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        uint8_t                            signature [4];          /* ACPI signature (4 ASCII characters) */\
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        uint32_t                             length;                 /* Length of table, in bytes, including header */\
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        uint8_t                              revision;               /* ACPI Specification minor version # */\
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        uint8_t                              checksum;               /* To make sum of entire table == 0 */\
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        uint8_t                            oem_id [6];             /* OEM identification */\
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        uint8_t                            oem_table_id [8];       /* OEM table identification */\
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        uint32_t                             oem_revision;           /* OEM revision number */\
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        uint8_t                            asl_compiler_id [4];    /* ASL compiler vendor ID */\
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        uint32_t                             asl_compiler_revision;  /* ASL compiler revision number */
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struct acpi_table_header         /* ACPI common table header */
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{
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        ACPI_TABLE_HEADER_DEF
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};
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struct rsdp_descriptor         /* Root System Descriptor Pointer */
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{
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        uint8_t                            signature [8];          /* ACPI signature, contains "RSD PTR " */
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        uint8_t                              checksum;               /* To make sum of struct == 0 */
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        uint8_t                            oem_id [6];             /* OEM identification */
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        uint8_t                              revision;               /* Must be 0 for 1.0, 2 for 2.0 */
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        uint32_t                             rsdt_physical_address;  /* 32-bit physical address of RSDT */
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        uint32_t                             length;                 /* XSDT Length in bytes including hdr */
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        uint64_t                             xsdt_physical_address;  /* 64-bit physical address of XSDT */
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        uint8_t                              extended_checksum;      /* Checksum of entire table */
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        uint8_t                            reserved [3];           /* Reserved field must be 0 */
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};
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/*
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 * ACPI 1.0 Root System Description Table (RSDT)
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 */
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struct rsdt_descriptor_rev1
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{
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        ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
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        uint32_t                             table_offset_entry [2]; /* Array of pointers to other */
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                         /* ACPI tables */
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};
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/*
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 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
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 */
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struct facs_descriptor_rev1
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{
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        uint8_t                            signature[4];           /* ACPI Signature */
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        uint32_t                             length;                 /* Length of structure, in bytes */
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        uint32_t                             hardware_signature;     /* Hardware configuration signature */
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        uint32_t                             firmware_waking_vector; /* ACPI OS waking vector */
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        uint32_t                             global_lock;            /* Global Lock */
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        uint32_t                             S4bios_f        : 1;    /* Indicates if S4BIOS support is present */
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        uint32_t                             reserved1       : 31;   /* Must be 0 */
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        uint8_t                              resverved3 [40];        /* Reserved - must be zero */
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};
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/*
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 * ACPI 1.0 Fixed ACPI Description Table (FADT)
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 */
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struct fadt_descriptor_rev1
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{
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        ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
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        uint32_t                             firmware_ctrl;          /* Physical address of FACS */
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        uint32_t                             dsdt;                   /* Physical address of DSDT */
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        uint8_t                              model;                  /* System Interrupt Model */
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        uint8_t                              reserved1;              /* Reserved */
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        uint16_t                             sci_int;                /* System vector of SCI interrupt */
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        uint32_t                             smi_cmd;                /* Port address of SMI command port */
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        uint8_t                              acpi_enable;            /* Value to write to smi_cmd to enable ACPI */
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        uint8_t                              acpi_disable;           /* Value to write to smi_cmd to disable ACPI */
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        uint8_t                              S4bios_req;             /* Value to write to SMI CMD to enter S4BIOS state */
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        uint8_t                              reserved2;              /* Reserved - must be zero */
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        uint32_t                             pm1a_evt_blk;           /* Port address of Power Mgt 1a acpi_event Reg Blk */
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        uint32_t                             pm1b_evt_blk;           /* Port address of Power Mgt 1b acpi_event Reg Blk */
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        uint32_t                             pm1a_cnt_blk;           /* Port address of Power Mgt 1a Control Reg Blk */
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        uint32_t                             pm1b_cnt_blk;           /* Port address of Power Mgt 1b Control Reg Blk */
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        uint32_t                             pm2_cnt_blk;            /* Port address of Power Mgt 2 Control Reg Blk */
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        uint32_t                             pm_tmr_blk;             /* Port address of Power Mgt Timer Ctrl Reg Blk */
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        uint32_t                             gpe0_blk;               /* Port addr of General Purpose acpi_event 0 Reg Blk */
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        uint32_t                             gpe1_blk;               /* Port addr of General Purpose acpi_event 1 Reg Blk */
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        uint8_t                              pm1_evt_len;            /* Byte length of ports at pm1_x_evt_blk */
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        uint8_t                              pm1_cnt_len;            /* Byte length of ports at pm1_x_cnt_blk */
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        uint8_t                              pm2_cnt_len;            /* Byte Length of ports at pm2_cnt_blk */
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        uint8_t                              pm_tmr_len;              /* Byte Length of ports at pm_tm_blk */
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        uint8_t                              gpe0_blk_len;           /* Byte Length of ports at gpe0_blk */
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        uint8_t                              gpe1_blk_len;           /* Byte Length of ports at gpe1_blk */
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        uint8_t                              gpe1_base;              /* Offset in gpe model where gpe1 events start */
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        uint8_t                              reserved3;              /* Reserved */
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        uint16_t                             plvl2_lat;              /* Worst case HW latency to enter/exit C2 state */
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        uint16_t                             plvl3_lat;              /* Worst case HW latency to enter/exit C3 state */
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        uint16_t                             flush_size;             /* Size of area read to flush caches */
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        uint16_t                             flush_stride;           /* Stride used in flushing caches */
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        uint8_t                              duty_offset;            /* Bit location of duty cycle field in p_cnt reg */
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        uint8_t                              duty_width;             /* Bit width of duty cycle field in p_cnt reg */
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        uint8_t                              day_alrm;               /* Index to day-of-month alarm in RTC CMOS RAM */
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        uint8_t                              mon_alrm;               /* Index to month-of-year alarm in RTC CMOS RAM */
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        uint8_t                              century;                /* Index to century in RTC CMOS RAM */
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        uint8_t                              reserved4;              /* Reserved */
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        uint8_t                              reserved4a;             /* Reserved */
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        uint8_t                              reserved4b;             /* Reserved */
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#if 0
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        uint32_t                             wb_invd         : 1;    /* The wbinvd instruction works properly */
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        uint32_t                             wb_invd_flush   : 1;    /* The wbinvd flushes but does not invalidate */
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        uint32_t                             proc_c1         : 1;    /* All processors support C1 state */
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        uint32_t                             plvl2_up        : 1;    /* C2 state works on MP system */
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        uint32_t                             pwr_button      : 1;    /* Power button is handled as a generic feature */
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        uint32_t                             sleep_button    : 1;    /* Sleep button is handled as a generic feature, or not present */
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        uint32_t                             fixed_rTC       : 1;    /* RTC wakeup stat not in fixed register space */
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        uint32_t                             rtcs4           : 1;    /* RTC wakeup stat not possible from S4 */
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        uint32_t                             tmr_val_ext     : 1;    /* The tmr_val width is 32 bits (0 = 24 bits) */
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        uint32_t                             reserved5       : 23;   /* Reserved - must be zero */
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#else
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        uint32_t flags;
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#endif
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};
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/*
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 * MADT values and structures
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 */
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/* Values for MADT PCATCompat */
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#define DUAL_PIC                0
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#define MULTIPLE_APIC           1
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/* Master MADT */
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struct multiple_apic_table
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{
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        ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
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        uint32_t                             local_apic_address;     /* Physical address of local APIC */
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#if 0
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        uint32_t                             PCATcompat      : 1;    /* A one indicates system also has dual 8259s */
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        uint32_t                             reserved1       : 31;
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#else
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        uint32_t                             flags;
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#endif
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};
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/* Values for Type in APIC_HEADER_DEF */
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#define APIC_PROCESSOR          0
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#define APIC_IO                 1
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#define APIC_XRUPT_OVERRIDE     2
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#define APIC_NMI                3
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#define APIC_LOCAL_NMI          4
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#define APIC_ADDRESS_OVERRIDE   5
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#define APIC_IO_SAPIC           6
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#define APIC_LOCAL_SAPIC        7
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#define APIC_XRUPT_SOURCE       8
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#define APIC_RESERVED           9           /* 9 and greater are reserved */
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/*
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 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
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 */
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#define APIC_HEADER_DEF                     /* Common APIC sub-structure header */\
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        uint8_t                              type; \
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        uint8_t                              length;
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/* Sub-structures for MADT */
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struct madt_processor_apic
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{
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        APIC_HEADER_DEF
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        uint8_t                              processor_id;           /* ACPI processor id */
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        uint8_t                              local_apic_id;          /* Processor's local APIC id */
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#if 0
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        uint32_t                             processor_enabled: 1;   /* Processor is usable if set */
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        uint32_t                             reserved2       : 31;   /* Reserved, must be zero */
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#else
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        uint32_t flags;
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#endif
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};
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struct madt_io_apic
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{
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        APIC_HEADER_DEF
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        uint8_t                              io_apic_id;             /* I/O APIC ID */
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        uint8_t                              reserved;               /* Reserved - must be zero */
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        uint32_t                             address;                /* APIC physical address */
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        uint32_t                             interrupt;              /* Global system interrupt where INTI
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                          * lines start */
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};
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#include "acpi-dsdt.hex"
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static int acpi_checksum(const uint8_t *data, int len)
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{
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    int sum, i;
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    sum = 0;
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    for(i = 0; i < len; i++)
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        sum += data[i];
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    return (-sum) & 0xff;
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}
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static void acpi_build_table_header(struct acpi_table_header *h, 
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                                    char *sig, int len)
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{
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    memcpy(h->signature, sig, 4);
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    h->length = cpu_to_le32(len);
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    h->revision = 0;
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    memcpy(h->oem_id, "QEMU  ", 6);
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    memcpy(h->oem_table_id, "QEMU", 4);
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    memcpy(h->oem_table_id + 4, sig, 4);
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    h->oem_revision = cpu_to_le32(1);
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    memcpy(h->asl_compiler_id, "QEMU", 4);
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    h->asl_compiler_revision = cpu_to_le32(1);
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    h->checksum = acpi_checksum((void *)h, len);
478 6515b203 bellard
}
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#define ACPI_TABLES_BASE 0x000e8000
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/* base_addr must be a multiple of 4KB */
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void acpi_bios_init(void)
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{
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    struct rsdp_descriptor *rsdp;
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    struct rsdt_descriptor_rev1 *rsdt;
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    struct fadt_descriptor_rev1 *fadt;
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    struct facs_descriptor_rev1 *facs;
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    struct multiple_apic_table *madt;
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    uint8_t *dsdt;
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    uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr;
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    uint32_t pm_io_base, acpi_tables_size, madt_addr, madt_size;
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    int i;
494 6515b203 bellard
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    /* compute PCI I/O addresses */
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    pm_io_base = (piix4_pm_state->dev.config[0x40] | 
497 6515b203 bellard
        (piix4_pm_state->dev.config[0x41] << 8)) & ~0x3f;
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    base_addr = ACPI_TABLES_BASE;
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    /* reserve memory space for tables */
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    addr = base_addr;
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    rsdp = (void *)(phys_ram_base + addr);
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    addr += sizeof(*rsdp);
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    rsdt_addr = addr;
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    rsdt = (void *)(phys_ram_base + addr);
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    addr += sizeof(*rsdt);
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    fadt_addr = addr;
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    fadt = (void *)(phys_ram_base + addr);
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    addr += sizeof(*fadt);
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    /* XXX: FACS should be in RAM */
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    addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
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    facs_addr = addr;
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    facs = (void *)(phys_ram_base + addr);
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    addr += sizeof(*facs);
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    dsdt_addr = addr;
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    dsdt = (void *)(phys_ram_base + addr);
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    addr += sizeof(AmlCode);
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    addr = (addr + 7) & ~7;
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    madt_addr = addr;
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    madt_size = sizeof(*madt) + 
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        sizeof(struct madt_processor_apic) * smp_cpus +
528 6515b203 bellard
        sizeof(struct madt_io_apic);
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    madt = (void *)(phys_ram_base + addr);
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    addr += madt_size;
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    acpi_tables_size = addr - base_addr;
533 6515b203 bellard
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    cpu_register_physical_memory(base_addr, acpi_tables_size, 
535 6515b203 bellard
                                 base_addr | IO_MEM_ROM);
536 6515b203 bellard
    
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    /* RSDP */
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    memset(rsdp, 0, sizeof(*rsdp));
539 6515b203 bellard
    memcpy(rsdp->signature, "RSD PTR ", 8);
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    memcpy(rsdp->oem_id, "QEMU  ", 6);
541 6515b203 bellard
    rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
542 6515b203 bellard
    rsdp->checksum = acpi_checksum((void *)rsdp, 20);
543 6515b203 bellard
    
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    /* RSDT */
545 6515b203 bellard
    rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
546 6515b203 bellard
    rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
547 6515b203 bellard
    acpi_build_table_header((struct acpi_table_header *)rsdt, 
548 6515b203 bellard
                            "RSDT", sizeof(*rsdt));
549 6515b203 bellard
    
550 6515b203 bellard
    /* FADT */
551 6515b203 bellard
    memset(fadt, 0, sizeof(*fadt));
552 6515b203 bellard
    fadt->firmware_ctrl = cpu_to_le32(facs_addr);
553 6515b203 bellard
    fadt->dsdt = cpu_to_le32(dsdt_addr);
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    fadt->model = 1;
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    fadt->reserved1 = 0;
556 6515b203 bellard
    fadt->sci_int = cpu_to_le16(piix4_pm_state->dev.config[0x3c]);
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    fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
558 6515b203 bellard
    fadt->acpi_enable = 0xf1;
559 6515b203 bellard
    fadt->acpi_disable = 0xf0;
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    fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
561 6515b203 bellard
    fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
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    fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
563 6515b203 bellard
    fadt->pm1_evt_len = 4;
564 6515b203 bellard
    fadt->pm1_cnt_len = 2;
565 6515b203 bellard
    fadt->pm_tmr_len = 4;
566 6515b203 bellard
    fadt->plvl2_lat = cpu_to_le16(50);
567 6515b203 bellard
    fadt->plvl3_lat = cpu_to_le16(50);
568 6515b203 bellard
    fadt->plvl3_lat = cpu_to_le16(50);
569 6515b203 bellard
    /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
570 6515b203 bellard
    fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
571 6515b203 bellard
    acpi_build_table_header((struct acpi_table_header *)fadt, "FACP", 
572 6515b203 bellard
                            sizeof(*fadt));
573 6515b203 bellard
574 6515b203 bellard
    /* FACS */
575 6515b203 bellard
    memset(facs, 0, sizeof(*facs));
576 6515b203 bellard
    memcpy(facs->signature, "FACS", 4);
577 6515b203 bellard
    facs->length = cpu_to_le32(sizeof(*facs));
578 6515b203 bellard
579 6515b203 bellard
    /* DSDT */
580 6515b203 bellard
    memcpy(dsdt, AmlCode, sizeof(AmlCode));
581 6515b203 bellard
582 6515b203 bellard
    /* MADT */
583 6515b203 bellard
    {
584 6515b203 bellard
        struct madt_processor_apic *apic;
585 6515b203 bellard
        struct madt_io_apic *io_apic;
586 6515b203 bellard
587 6515b203 bellard
        memset(madt, 0, madt_size);
588 6515b203 bellard
        madt->local_apic_address = cpu_to_le32(0xfee00000);
589 6515b203 bellard
        madt->flags = cpu_to_le32(1);
590 6515b203 bellard
        apic = (void *)(madt + 1);
591 6515b203 bellard
        for(i=0;i<smp_cpus;i++) {
592 6515b203 bellard
            apic->type = APIC_PROCESSOR;
593 6515b203 bellard
            apic->length = sizeof(*apic);
594 6515b203 bellard
            apic->processor_id = i;
595 6515b203 bellard
            apic->local_apic_id = i;
596 6515b203 bellard
            apic->flags = cpu_to_le32(1);
597 6515b203 bellard
            apic++;
598 6515b203 bellard
        }
599 6515b203 bellard
        io_apic = (void *)apic;
600 6515b203 bellard
        io_apic->type = APIC_IO;
601 6515b203 bellard
        io_apic->length = sizeof(*io_apic);
602 6515b203 bellard
        io_apic->io_apic_id = smp_cpus;
603 6515b203 bellard
        io_apic->address = cpu_to_le32(0xfec00000);
604 6515b203 bellard
        io_apic->interrupt = cpu_to_le32(0);
605 6515b203 bellard
606 6515b203 bellard
        acpi_build_table_header((struct acpi_table_header *)madt, 
607 6515b203 bellard
                                "APIC", madt_size);
608 6515b203 bellard
    }
609 6515b203 bellard
}