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/*
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* QEMU Lance emulation
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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/* debug LANCE card */
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//#define DEBUG_LANCE
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#ifdef DEBUG_LANCE
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#define DPRINTF(fmt, args...) \
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do { printf("LANCE: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...)
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#endif
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#ifndef LANCE_LOG_TX_BUFFERS
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#define LANCE_LOG_TX_BUFFERS 4 |
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#define LANCE_LOG_RX_BUFFERS 4 |
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#endif
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#define LE_CSR0 0 |
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#define LE_CSR1 1 |
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#define LE_CSR2 2 |
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#define LE_CSR3 3 |
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#define LE_NREGS (LE_CSR3 + 1) |
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#define LE_MAXREG LE_CSR3
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|
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#define LE_RDP 0 |
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#define LE_RAP 1 |
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|
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#define LE_MO_PROM 0x8000 /* Enable promiscuous mode */ |
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#define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */ |
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#define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */ |
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#define LE_C0_CERR 0x2000 /* SQE: Signal quality error */ |
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#define LE_C0_MISS 0x1000 /* MISS: Missed a packet */ |
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#define LE_C0_MERR 0x0800 /* ME: Memory error */ |
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#define LE_C0_RINT 0x0400 /* Received interrupt */ |
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#define LE_C0_TINT 0x0200 /* Transmitter Interrupt */ |
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#define LE_C0_IDON 0x0100 /* IFIN: Init finished. */ |
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#define LE_C0_INTR 0x0080 /* Interrupt or error */ |
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#define LE_C0_INEA 0x0040 /* Interrupt enable */ |
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#define LE_C0_RXON 0x0020 /* Receiver on */ |
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#define LE_C0_TXON 0x0010 /* Transmitter on */ |
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#define LE_C0_TDMD 0x0008 /* Transmitter demand */ |
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#define LE_C0_STOP 0x0004 /* Stop the card */ |
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#define LE_C0_STRT 0x0002 /* Start the card */ |
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#define LE_C0_INIT 0x0001 /* Init the card */ |
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#define LE_C3_BSWP 0x4 /* SWAP */ |
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#define LE_C3_ACON 0x2 /* ALE Control */ |
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#define LE_C3_BCON 0x1 /* Byte control */ |
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/* Receive message descriptor 1 */
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#define LE_R1_OWN 0x80 /* Who owns the entry */ |
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#define LE_R1_ERR 0x40 /* Error: if FRA, OFL, CRC or BUF is set */ |
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#define LE_R1_FRA 0x20 /* FRA: Frame error */ |
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#define LE_R1_OFL 0x10 /* OFL: Frame overflow */ |
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#define LE_R1_CRC 0x08 /* CRC error */ |
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#define LE_R1_BUF 0x04 /* BUF: Buffer error */ |
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#define LE_R1_SOP 0x02 /* Start of packet */ |
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#define LE_R1_EOP 0x01 /* End of packet */ |
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#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */ |
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#define LE_T1_OWN 0x80 /* Lance owns the packet */ |
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#define LE_T1_ERR 0x40 /* Error summary */ |
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#define LE_T1_EMORE 0x10 /* Error: more than one retry needed */ |
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#define LE_T1_EONE 0x08 /* Error: one retry needed */ |
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#define LE_T1_EDEF 0x04 /* Error: deferred */ |
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#define LE_T1_SOP 0x02 /* Start of packet */ |
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#define LE_T1_EOP 0x01 /* End of packet */ |
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#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */ |
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#define LE_T3_BUF 0x8000 /* Buffer error */ |
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#define LE_T3_UFL 0x4000 /* Error underflow */ |
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#define LE_T3_LCOL 0x1000 /* Error late collision */ |
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#define LE_T3_CLOS 0x0800 /* Error carrier loss */ |
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#define LE_T3_RTY 0x0400 /* Error retry */ |
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#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */ |
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#define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS)) |
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#define TX_RING_MOD_MASK (TX_RING_SIZE - 1) |
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#define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29) |
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#define RX_RING_SIZE (1 << (LANCE_LOG_RX_BUFFERS)) |
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#define RX_RING_MOD_MASK (RX_RING_SIZE - 1) |
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#define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29) |
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#define PKT_BUF_SZ 1544 |
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#define RX_BUFF_SIZE PKT_BUF_SZ
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#define TX_BUFF_SIZE PKT_BUF_SZ
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struct lance_rx_desc {
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unsigned short rmd0; /* low address of packet */ |
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unsigned char rmd1_bits; /* descriptor bits */ |
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unsigned char rmd1_hadr; /* high address of packet */ |
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short length; /* This length is 2s complement (negative)! |
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* Buffer length
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*/
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unsigned short mblength; /* This is the actual number of bytes received */ |
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}; |
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struct lance_tx_desc {
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unsigned short tmd0; /* low address of packet */ |
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unsigned char tmd1_bits; /* descriptor bits */ |
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unsigned char tmd1_hadr; /* high address of packet */ |
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short length; /* Length is 2s complement (negative)! */ |
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unsigned short misc; |
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}; |
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/* The LANCE initialization block, described in databook. */
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/* On the Sparc, this block should be on a DMA region */
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struct lance_init_block {
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unsigned short mode; /* Pre-set mode (reg. 15) */ |
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unsigned char phys_addr[6]; /* Physical ethernet address */ |
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unsigned filter[2]; /* Multicast filter. */ |
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/* Receive and transmit ring base, along with extra bits. */
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unsigned short rx_ptr; /* receive descriptor addr */ |
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unsigned short rx_len; /* receive len and high addr */ |
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unsigned short tx_ptr; /* transmit descriptor addr */ |
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unsigned short tx_len; /* transmit len and high addr */ |
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/* The Tx and Rx ring entries must aligned on 8-byte boundaries. */
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struct lance_rx_desc brx_ring[RX_RING_SIZE];
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struct lance_tx_desc btx_ring[TX_RING_SIZE];
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char tx_buf [TX_RING_SIZE][TX_BUFF_SIZE];
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char pad[2]; /* align rx_buf for copy_and_sum(). */ |
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char rx_buf [RX_RING_SIZE][RX_BUFF_SIZE];
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}; |
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#define LEDMA_REGS 4 |
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#define LEDMA_MAXADDR (LEDMA_REGS * 4 - 1) |
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typedef struct LANCEState { |
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VLANClientState *vc; |
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uint8_t macaddr[6]; /* init mac address */ |
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uint32_t leptr; |
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uint16_t addr; |
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uint16_t regs[LE_NREGS]; |
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uint8_t phys[6]; /* mac address */ |
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int irq;
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unsigned int rxptr, txptr; |
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uint32_t ledmaregs[LEDMA_REGS]; |
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} LANCEState; |
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static void lance_send(void *opaque); |
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static void lance_reset(void *opaque) |
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{ |
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LANCEState *s = opaque; |
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memcpy(s->phys, s->macaddr, 6);
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s->rxptr = 0;
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s->txptr = 0;
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memset(s->regs, 0, LE_NREGS * 2); |
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s->regs[LE_CSR0] = LE_C0_STOP; |
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memset(s->ledmaregs, 0, LEDMA_REGS * 4); |
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} |
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static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr) |
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{ |
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LANCEState *s = opaque; |
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uint32_t saddr; |
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saddr = addr & LE_MAXREG; |
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switch (saddr >> 1) { |
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case LE_RDP:
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DPRINTF("read dreg[%d] = %4.4x\n", s->addr, s->regs[s->addr]);
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return s->regs[s->addr];
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case LE_RAP:
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DPRINTF("read areg = %4.4x\n", s->addr);
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return s->addr;
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default:
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DPRINTF("read unknown(%d)\n", saddr>>1); |
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break;
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} |
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return 0; |
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} |
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static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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LANCEState *s = opaque; |
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uint32_t saddr; |
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uint16_t reg; |
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saddr = addr & LE_MAXREG; |
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switch (saddr >> 1) { |
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case LE_RDP:
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DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val);
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switch(s->addr) {
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case LE_CSR0:
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if (val & LE_C0_STOP) {
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s->regs[LE_CSR0] = LE_C0_STOP; |
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break;
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} |
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reg = s->regs[LE_CSR0]; |
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// 1 = clear for some bits
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reg &= ~(val & 0x7f00);
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// generated bits
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reg &= ~(LE_C0_ERR | LE_C0_INTR); |
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if (reg & 0x7100) |
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reg |= LE_C0_ERR; |
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if (reg & 0x7f00) |
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reg |= LE_C0_INTR; |
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// direct bit
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reg &= ~LE_C0_INEA; |
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reg |= val & LE_C0_INEA; |
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// exclusive bits
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if (val & LE_C0_INIT) {
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reg |= LE_C0_IDON | LE_C0_INIT; |
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reg &= ~LE_C0_STOP; |
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} |
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else if (val & LE_C0_STRT) { |
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reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON; |
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reg &= ~LE_C0_STOP; |
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} |
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s->regs[LE_CSR0] = reg; |
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break;
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case LE_CSR1:
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s->leptr = (s->leptr & 0xffff0000) | (val & 0xffff); |
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s->regs[s->addr] = val; |
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break;
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case LE_CSR2:
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s->leptr = (s->leptr & 0xffff) | ((val & 0xffff) << 16); |
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s->regs[s->addr] = val; |
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break;
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case LE_CSR3:
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s->regs[s->addr] = val; |
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break;
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} |
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break;
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case LE_RAP:
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DPRINTF("write areg = %4.4x\n", val);
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if (val < LE_NREGS)
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s->addr = val; |
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break;
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default:
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DPRINTF("write unknown(%d) = %4.4x\n", saddr>>1, val); |
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break;
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} |
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lance_send(s); |
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} |
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static CPUReadMemoryFunc *lance_mem_read[3] = { |
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lance_mem_readw, |
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lance_mem_readw, |
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lance_mem_readw, |
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}; |
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static CPUWriteMemoryFunc *lance_mem_write[3] = { |
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lance_mem_writew, |
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lance_mem_writew, |
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lance_mem_writew, |
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}; |
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|
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#define MIN_BUF_SIZE 60 |
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static int lance_can_receive(void *opaque) |
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{ |
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return 1; |
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} |
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|
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static void lance_receive(void *opaque, const uint8_t *buf, int size) |
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{ |
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LANCEState *s = opaque; |
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uint32_t dmaptr = s->leptr + s->ledmaregs[3];
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struct lance_init_block *ib;
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unsigned int i, old_rxptr; |
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uint16_t temp16; |
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uint8_t temp8; |
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DPRINTF("receive size %d\n", size);
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if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
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return;
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ib = (void *) iommu_translate(dmaptr);
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old_rxptr = s->rxptr; |
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for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); i = (i + 1) & RX_RING_MOD_MASK) { |
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cpu_physical_memory_read((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1); |
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if (temp8 == (LE_R1_OWN)) {
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s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK;
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temp16 = size + 4;
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bswap16s(&temp16); |
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cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].mblength, (void *) &temp16, 2); |
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cpu_physical_memory_write((uint32_t)&ib->rx_buf[i], buf, size); |
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temp8 = LE_R1_POK; |
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cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1); |
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s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR; |
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if (s->regs[LE_CSR0] & LE_C0_INEA)
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pic_set_irq(s->irq, 1);
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DPRINTF("got packet, len %d\n", size);
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return;
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} |
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} |
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} |
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|
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static void lance_send(void *opaque) |
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{ |
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LANCEState *s = opaque; |
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uint32_t dmaptr = s->leptr + s->ledmaregs[3];
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struct lance_init_block *ib;
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unsigned int i, old_txptr; |
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uint16_t temp16; |
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uint8_t temp8; |
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char pkt_buf[PKT_BUF_SZ];
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DPRINTF("sending packet? (csr0 %4.4x)\n", s->regs[LE_CSR0]);
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if ((s->regs[LE_CSR0] & LE_C0_STOP) == LE_C0_STOP)
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return;
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ib = (void *) iommu_translate(dmaptr);
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DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", dmaptr, ib, &ib->btx_ring);
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old_txptr = s->txptr; |
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for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); i = (i + 1) & TX_RING_MOD_MASK) { |
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cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1); |
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if (temp8 == (LE_T1_POK|LE_T1_OWN)) {
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cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].length, (void *) &temp16, 2); |
348 |
bswap16s(&temp16); |
349 |
temp16 = (~temp16) + 1;
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cpu_physical_memory_read((uint32_t)&ib->tx_buf[i], pkt_buf, temp16); |
351 |
DPRINTF("sending packet, len %d\n", temp16);
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qemu_send_packet(s->vc, pkt_buf, temp16); |
353 |
temp8 = LE_T1_POK; |
354 |
cpu_physical_memory_write((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1); |
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s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK;
|
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s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR; |
357 |
} |
358 |
} |
359 |
if ((s->regs[LE_CSR0] & LE_C0_INTR) && (s->regs[LE_CSR0] & LE_C0_INEA))
|
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pic_set_irq(s->irq, 1);
|
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} |
362 |
|
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static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr) |
364 |
{ |
365 |
LANCEState *s = opaque; |
366 |
uint32_t saddr; |
367 |
|
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saddr = (addr & LEDMA_MAXADDR) >> 2;
|
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return s->ledmaregs[saddr];
|
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} |
371 |
|
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static void ledma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
373 |
{ |
374 |
LANCEState *s = opaque; |
375 |
uint32_t saddr; |
376 |
|
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saddr = (addr & LEDMA_MAXADDR) >> 2;
|
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s->ledmaregs[saddr] = val; |
379 |
} |
380 |
|
381 |
static CPUReadMemoryFunc *ledma_mem_read[3] = { |
382 |
ledma_mem_readl, |
383 |
ledma_mem_readl, |
384 |
ledma_mem_readl, |
385 |
}; |
386 |
|
387 |
static CPUWriteMemoryFunc *ledma_mem_write[3] = { |
388 |
ledma_mem_writel, |
389 |
ledma_mem_writel, |
390 |
ledma_mem_writel, |
391 |
}; |
392 |
|
393 |
static void lance_save(QEMUFile *f, void *opaque) |
394 |
{ |
395 |
LANCEState *s = opaque; |
396 |
int i;
|
397 |
|
398 |
qemu_put_be32s(f, &s->leptr); |
399 |
qemu_put_be16s(f, &s->addr); |
400 |
for (i = 0; i < LE_NREGS; i ++) |
401 |
qemu_put_be16s(f, &s->regs[i]); |
402 |
qemu_put_buffer(f, s->phys, 6);
|
403 |
qemu_put_be32s(f, &s->irq); |
404 |
for (i = 0; i < LEDMA_REGS; i ++) |
405 |
qemu_put_be32s(f, &s->ledmaregs[i]); |
406 |
} |
407 |
|
408 |
static int lance_load(QEMUFile *f, void *opaque, int version_id) |
409 |
{ |
410 |
LANCEState *s = opaque; |
411 |
int i;
|
412 |
|
413 |
if (version_id != 1) |
414 |
return -EINVAL;
|
415 |
|
416 |
qemu_get_be32s(f, &s->leptr); |
417 |
qemu_get_be16s(f, &s->addr); |
418 |
for (i = 0; i < LE_NREGS; i ++) |
419 |
qemu_get_be16s(f, &s->regs[i]); |
420 |
qemu_get_buffer(f, s->phys, 6);
|
421 |
qemu_get_be32s(f, &s->irq); |
422 |
for (i = 0; i < LEDMA_REGS; i ++) |
423 |
qemu_get_be32s(f, &s->ledmaregs[i]); |
424 |
return 0; |
425 |
} |
426 |
|
427 |
void lance_init(NICInfo *nd, int irq, uint32_t leaddr, uint32_t ledaddr) |
428 |
{ |
429 |
LANCEState *s; |
430 |
int lance_io_memory, ledma_io_memory;
|
431 |
|
432 |
s = qemu_mallocz(sizeof(LANCEState));
|
433 |
if (!s)
|
434 |
return;
|
435 |
|
436 |
s->irq = irq; |
437 |
|
438 |
lance_io_memory = cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
|
439 |
cpu_register_physical_memory(leaddr, 4, lance_io_memory);
|
440 |
|
441 |
ledma_io_memory = cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
|
442 |
cpu_register_physical_memory(ledaddr, 16, ledma_io_memory);
|
443 |
|
444 |
memcpy(s->macaddr, nd->macaddr, 6);
|
445 |
|
446 |
lance_reset(s); |
447 |
|
448 |
s->vc = qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive, s); |
449 |
|
450 |
snprintf(s->vc->info_str, sizeof(s->vc->info_str),
|
451 |
"lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
|
452 |
s->macaddr[0],
|
453 |
s->macaddr[1],
|
454 |
s->macaddr[2],
|
455 |
s->macaddr[3],
|
456 |
s->macaddr[4],
|
457 |
s->macaddr[5]);
|
458 |
|
459 |
register_savevm("lance", leaddr, 1, lance_save, lance_load, s); |
460 |
qemu_register_reset(lance_reset, s); |
461 |
} |
462 |
|