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/*
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 * QEMU Sun4u System Emulator
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 * 
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 * Copyright (c) 2005 Fabrice Bellard
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "vl.h"
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#include "m48t59.h"
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#define KERNEL_LOAD_ADDR     0x00404000
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#define CMDLINE_ADDR         0x003ff000
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#define INITRD_LOAD_ADDR     0x00300000
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#define PROM_SIZE_MAX        (256 * 1024)
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#define PROM_ADDR             0x1fff0000000ULL
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#define APB_SPECIAL_BASE     0x1fe00000000ULL
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#define APB_MEM_BASE             0x1ff00000000ULL
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#define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
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#define PROM_FILENAME             "openbios-sparc64"
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#define NVRAM_SIZE           0x2000
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/* TSC handling */
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uint64_t cpu_get_tsc()
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{
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    return qemu_get_clock(vm_clock);
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}
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int DMA_get_channel_mode (int nchan)
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{
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    return 0;
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}
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int DMA_read_memory (int nchan, void *buf, int pos, int size)
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{
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    return 0;
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}
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int DMA_write_memory (int nchan, void *buf, int pos, int size)
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{
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    return 0;
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}
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void DMA_hold_DREQ (int nchan) {}
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void DMA_release_DREQ (int nchan) {}
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void DMA_schedule(int nchan) {}
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void DMA_run (void) {}
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void DMA_init (int high_page_enable) {}
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void DMA_register_channel (int nchan,
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                           DMA_transfer_handler transfer_handler,
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                           void *opaque)
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{
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}
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/* NVRAM helpers */
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void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
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{
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    m48t59_write(nvram, addr, value);
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}
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uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
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{
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    return m48t59_read(nvram, addr);
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}
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void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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{
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    m48t59_write(nvram, addr, value >> 8);
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    m48t59_write(nvram, addr + 1, value & 0xFF);
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}
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uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
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{
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    uint16_t tmp;
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    tmp = m48t59_read(nvram, addr) << 8;
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    tmp |= m48t59_read(nvram, addr + 1);
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    return tmp;
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}
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void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
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{
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    m48t59_write(nvram, addr, value >> 24);
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    m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
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    m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
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    m48t59_write(nvram, addr + 3, value & 0xFF);
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}
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uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
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{
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    uint32_t tmp;
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    tmp = m48t59_read(nvram, addr) << 24;
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    tmp |= m48t59_read(nvram, addr + 1) << 16;
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    tmp |= m48t59_read(nvram, addr + 2) << 8;
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    tmp |= m48t59_read(nvram, addr + 3);
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    return tmp;
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}
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void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
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                       const unsigned char *str, uint32_t max)
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{
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    int i;
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    for (i = 0; i < max && str[i] != '\0'; i++) {
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        m48t59_write(nvram, addr + i, str[i]);
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    }
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    m48t59_write(nvram, addr + max - 1, '\0');
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}
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int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
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{
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    int i;
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    memset(dst, 0, max);
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    for (i = 0; i < max; i++) {
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        dst[i] = NVRAM_get_byte(nvram, addr + i);
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        if (dst[i] == '\0')
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            break;
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    }
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    return i;
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}
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static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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{
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    uint16_t tmp;
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    uint16_t pd, pd1, pd2;
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    tmp = prev >> 8;
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    pd = prev ^ value;
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    pd1 = pd & 0x000F;
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    pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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    tmp ^= (pd1 << 3) | (pd1 << 8);
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    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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    return tmp;
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}
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uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
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{
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    uint32_t i;
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    uint16_t crc = 0xFFFF;
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    int odd;
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    odd = count & 1;
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    count &= ~1;
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    for (i = 0; i != count; i++) {
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        crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
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    }
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    if (odd) {
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        crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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    }
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    return crc;
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}
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extern int nographic;
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int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
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                          const unsigned char *arch,
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                          uint32_t RAM_size, int boot_device,
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                          uint32_t kernel_image, uint32_t kernel_size,
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                          const char *cmdline,
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                          uint32_t initrd_image, uint32_t initrd_size,
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                          uint32_t NVRAM_image,
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                          int width, int height, int depth)
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{
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    uint16_t crc;
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    /* Set parameters for Open Hack'Ware BIOS */
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    NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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    NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
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    NVRAM_set_word(nvram,   0x14, NVRAM_size);
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    NVRAM_set_string(nvram, 0x20, arch, 16);
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    NVRAM_set_byte(nvram,   0x2f, nographic & 0xff);
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    NVRAM_set_lword(nvram,  0x30, RAM_size);
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    NVRAM_set_byte(nvram,   0x34, boot_device);
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    NVRAM_set_lword(nvram,  0x38, kernel_image);
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    NVRAM_set_lword(nvram,  0x3C, kernel_size);
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    if (cmdline) {
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        /* XXX: put the cmdline in NVRAM too ? */
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        strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
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        NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
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        NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
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    } else {
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        NVRAM_set_lword(nvram,  0x40, 0);
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        NVRAM_set_lword(nvram,  0x44, 0);
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    }
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    NVRAM_set_lword(nvram,  0x48, initrd_image);
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    NVRAM_set_lword(nvram,  0x4C, initrd_size);
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    NVRAM_set_lword(nvram,  0x50, NVRAM_image);
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    NVRAM_set_word(nvram,   0x54, width);
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    NVRAM_set_word(nvram,   0x56, height);
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    NVRAM_set_word(nvram,   0x58, depth);
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    crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
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    NVRAM_set_word(nvram,  0xFC, crc);
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    return 0;
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}
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void pic_info()
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{
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}
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void irq_info()
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{
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}
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void pic_set_irq(int irq, int level)
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{
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}
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void pic_set_irq_new(void *opaque, int irq, int level)
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{
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}
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void qemu_system_powerdown(void)
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{
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}
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static void main_cpu_reset(void *opaque)
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{
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    CPUState *env = opaque;
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    cpu_reset(env);
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}
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 14, 15 };
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static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
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static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
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static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
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static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
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static fdctrl_t *floppy_controller;
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/* Sun4u hardware initialisation */
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static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
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             DisplayState *ds, const char **fd_filename, int snapshot,
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             const char *kernel_filename, const char *kernel_cmdline,
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             const char *initrd_filename)
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{
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    CPUState *env;
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    char buf[1024];
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    m48t59_t *nvram;
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    int ret, linux_boot;
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    unsigned int i;
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    long prom_offset, initrd_size, kernel_size;
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    PCIBus *pci_bus;
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    linux_boot = (kernel_filename != NULL);
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    env = cpu_init();
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    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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    qemu_register_reset(main_cpu_reset, env);
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    /* allocate RAM */
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    cpu_register_physical_memory(0, ram_size, 0);
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    prom_offset = ram_size + vga_ram_size;
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    cpu_register_physical_memory(PROM_ADDR, 
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                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, 
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                                 prom_offset | IO_MEM_ROM);
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    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
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    ret = load_elf(buf, 0, NULL);
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    if (ret < 0) {
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        fprintf(stderr, "qemu: could not load prom '%s'\n", 
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                buf);
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        exit(1);
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    }
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    kernel_size = 0;
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    initrd_size = 0;
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    if (linux_boot) {
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        /* XXX: put correct offset */
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        kernel_size = load_elf(kernel_filename, 0, NULL);
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        if (kernel_size < 0)
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            kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
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        if (kernel_size < 0)
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            kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
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        if (kernel_size < 0) {
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            fprintf(stderr, "qemu: could not load kernel '%s'\n", 
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                    kernel_filename);
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            exit(1);
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        }
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        /* load initrd */
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        if (initrd_filename) {
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            initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
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            if (initrd_size < 0) {
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                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 
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                        initrd_filename);
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                exit(1);
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            }
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        }
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        if (initrd_size > 0) {
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            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
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                if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
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                    == 0x48647253) { // HdrS
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                    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
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                    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
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                    break;
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                }
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            }
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        }
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    }
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    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
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    isa_mem_base = VGA_BASE;
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    vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, 
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                   vga_ram_size, 0, 0);
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    cpu_register_physical_memory(VGA_BASE, vga_ram_size, ram_size);
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    //pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
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    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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        if (serial_hds[i]) {
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            serial_init(&pic_set_irq_new, NULL,
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                        serial_io[i], serial_irq[i], serial_hds[i]);
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        }
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    }
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    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
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        if (parallel_hds[i]) {
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            parallel_init(parallel_io[i], parallel_irq[i], parallel_hds[i]);
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        }
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    }
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    for(i = 0; i < nb_nics; i++) {
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        if (!nd_table[i].model)
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            nd_table[i].model = "ne2k_pci";
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        pci_nic_init(pci_bus, &nd_table[i]);
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    }
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    pci_cmd646_ide_init(pci_bus, bs_table, 1);
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    kbd_init();
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    floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
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    nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
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    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
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                         KERNEL_LOAD_ADDR, kernel_size,
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                         kernel_cmdline,
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                         INITRD_LOAD_ADDR, initrd_size,
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                         /* XXX: need an option to load a NVRAM image */
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                         0,
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                         graphic_width, graphic_height, graphic_depth);
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}
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QEMUMachine sun4u_machine = {
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    "sun4u",
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    "Sun4u platform",
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    sun4u_init,
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};