root / tcg / x86_64 / tcg-target.c @ 09aac126
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1 | c896fe29 | bellard | /*
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2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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3 | c896fe29 | bellard | *
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4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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5 | c896fe29 | bellard | *
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6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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12 | c896fe29 | bellard | *
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13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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15 | c896fe29 | bellard | *
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16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | c896fe29 | bellard | * THE SOFTWARE.
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23 | c896fe29 | bellard | */
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24 | d4a9eb1f | blueswir1 | |
25 | d4a9eb1f | blueswir1 | #ifndef NDEBUG
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26 | d4a9eb1f | blueswir1 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
27 | c896fe29 | bellard | "%rax",
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28 | c896fe29 | bellard | "%rcx",
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29 | c896fe29 | bellard | "%rdx",
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30 | c896fe29 | bellard | "%rbx",
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31 | c896fe29 | bellard | "%rsp",
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32 | c896fe29 | bellard | "%rbp",
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33 | c896fe29 | bellard | "%rsi",
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34 | c896fe29 | bellard | "%rdi",
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35 | c896fe29 | bellard | "%r8",
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36 | c896fe29 | bellard | "%r9",
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37 | c896fe29 | bellard | "%r10",
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38 | c896fe29 | bellard | "%r11",
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39 | c896fe29 | bellard | "%r12",
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40 | c896fe29 | bellard | "%r13",
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41 | c896fe29 | bellard | "%r14",
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42 | c896fe29 | bellard | "%r15",
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43 | c896fe29 | bellard | }; |
44 | d4a9eb1f | blueswir1 | #endif
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45 | c896fe29 | bellard | |
46 | d4a9eb1f | blueswir1 | static const int tcg_target_reg_alloc_order[] = { |
47 | c896fe29 | bellard | TCG_REG_RBP, |
48 | c896fe29 | bellard | TCG_REG_RBX, |
49 | c896fe29 | bellard | TCG_REG_R12, |
50 | c896fe29 | bellard | TCG_REG_R13, |
51 | c896fe29 | bellard | TCG_REG_R14, |
52 | c896fe29 | bellard | TCG_REG_R15, |
53 | 79d342dc | aurel32 | TCG_REG_R10, |
54 | 79d342dc | aurel32 | TCG_REG_R11, |
55 | 79d342dc | aurel32 | TCG_REG_R9, |
56 | 79d342dc | aurel32 | TCG_REG_R8, |
57 | 79d342dc | aurel32 | TCG_REG_RCX, |
58 | 79d342dc | aurel32 | TCG_REG_RDX, |
59 | 79d342dc | aurel32 | TCG_REG_RSI, |
60 | 79d342dc | aurel32 | TCG_REG_RDI, |
61 | 79d342dc | aurel32 | TCG_REG_RAX, |
62 | c896fe29 | bellard | }; |
63 | c896fe29 | bellard | |
64 | d4a9eb1f | blueswir1 | static const int tcg_target_call_iarg_regs[6] = { |
65 | c896fe29 | bellard | TCG_REG_RDI, |
66 | c896fe29 | bellard | TCG_REG_RSI, |
67 | c896fe29 | bellard | TCG_REG_RDX, |
68 | c896fe29 | bellard | TCG_REG_RCX, |
69 | c896fe29 | bellard | TCG_REG_R8, |
70 | c896fe29 | bellard | TCG_REG_R9, |
71 | c896fe29 | bellard | }; |
72 | c896fe29 | bellard | |
73 | d4a9eb1f | blueswir1 | static const int tcg_target_call_oarg_regs[2] = { |
74 | c896fe29 | bellard | TCG_REG_RAX, |
75 | c896fe29 | bellard | TCG_REG_RDX |
76 | c896fe29 | bellard | }; |
77 | c896fe29 | bellard | |
78 | b03cce8e | bellard | static uint8_t *tb_ret_addr;
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79 | b03cce8e | bellard | |
80 | c896fe29 | bellard | static void patch_reloc(uint8_t *code_ptr, int type, |
81 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
82 | c896fe29 | bellard | { |
83 | f54b3f92 | aurel32 | value += addend; |
84 | c896fe29 | bellard | switch(type) {
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85 | c896fe29 | bellard | case R_X86_64_32:
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86 | c896fe29 | bellard | if (value != (uint32_t)value)
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87 | c896fe29 | bellard | tcg_abort(); |
88 | c896fe29 | bellard | *(uint32_t *)code_ptr = value; |
89 | c896fe29 | bellard | break;
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90 | c896fe29 | bellard | case R_X86_64_32S:
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91 | c896fe29 | bellard | if (value != (int32_t)value)
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92 | c896fe29 | bellard | tcg_abort(); |
93 | c896fe29 | bellard | *(uint32_t *)code_ptr = value; |
94 | c896fe29 | bellard | break;
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95 | c896fe29 | bellard | case R_386_PC32:
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96 | c896fe29 | bellard | value -= (long)code_ptr;
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97 | c896fe29 | bellard | if (value != (int32_t)value)
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98 | c896fe29 | bellard | tcg_abort(); |
99 | c896fe29 | bellard | *(uint32_t *)code_ptr = value; |
100 | c896fe29 | bellard | break;
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101 | c896fe29 | bellard | default:
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102 | c896fe29 | bellard | tcg_abort(); |
103 | c896fe29 | bellard | } |
104 | c896fe29 | bellard | } |
105 | c896fe29 | bellard | |
106 | c896fe29 | bellard | /* maximum number of register used for input function arguments */
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107 | c896fe29 | bellard | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
108 | c896fe29 | bellard | { |
109 | c896fe29 | bellard | return 6; |
110 | c896fe29 | bellard | } |
111 | c896fe29 | bellard | |
112 | c896fe29 | bellard | /* parse target specific constraints */
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113 | 8fcd3692 | blueswir1 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
114 | c896fe29 | bellard | { |
115 | c896fe29 | bellard | const char *ct_str; |
116 | c896fe29 | bellard | |
117 | c896fe29 | bellard | ct_str = *pct_str; |
118 | c896fe29 | bellard | switch(ct_str[0]) { |
119 | c896fe29 | bellard | case 'a': |
120 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
121 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX); |
122 | c896fe29 | bellard | break;
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123 | c896fe29 | bellard | case 'b': |
124 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
125 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX); |
126 | c896fe29 | bellard | break;
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127 | c896fe29 | bellard | case 'c': |
128 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
129 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX); |
130 | c896fe29 | bellard | break;
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131 | c896fe29 | bellard | case 'd': |
132 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
133 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX); |
134 | c896fe29 | bellard | break;
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135 | c896fe29 | bellard | case 'S': |
136 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
137 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI); |
138 | c896fe29 | bellard | break;
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139 | c896fe29 | bellard | case 'D': |
140 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
141 | c896fe29 | bellard | tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI); |
142 | c896fe29 | bellard | break;
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143 | c896fe29 | bellard | case 'q': |
144 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
145 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xf); |
146 | c896fe29 | bellard | break;
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147 | c896fe29 | bellard | case 'r': |
148 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
149 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xffff); |
150 | c896fe29 | bellard | break;
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151 | c896fe29 | bellard | case 'L': /* qemu_ld/st constraint */ |
152 | c896fe29 | bellard | ct->ct |= TCG_CT_REG; |
153 | c896fe29 | bellard | tcg_regset_set32(ct->u.regs, 0, 0xffff); |
154 | c896fe29 | bellard | tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI); |
155 | c896fe29 | bellard | tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI); |
156 | c896fe29 | bellard | break;
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157 | c896fe29 | bellard | case 'e': |
158 | c896fe29 | bellard | ct->ct |= TCG_CT_CONST_S32; |
159 | c896fe29 | bellard | break;
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160 | c896fe29 | bellard | case 'Z': |
161 | c896fe29 | bellard | ct->ct |= TCG_CT_CONST_U32; |
162 | c896fe29 | bellard | break;
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163 | c896fe29 | bellard | default:
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164 | c896fe29 | bellard | return -1; |
165 | c896fe29 | bellard | } |
166 | c896fe29 | bellard | ct_str++; |
167 | c896fe29 | bellard | *pct_str = ct_str; |
168 | c896fe29 | bellard | return 0; |
169 | c896fe29 | bellard | } |
170 | c896fe29 | bellard | |
171 | c896fe29 | bellard | /* test if a constant matches the constraint */
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172 | c896fe29 | bellard | static inline int tcg_target_const_match(tcg_target_long val, |
173 | c896fe29 | bellard | const TCGArgConstraint *arg_ct)
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174 | c896fe29 | bellard | { |
175 | c896fe29 | bellard | int ct;
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176 | c896fe29 | bellard | ct = arg_ct->ct; |
177 | c896fe29 | bellard | if (ct & TCG_CT_CONST)
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178 | c896fe29 | bellard | return 1; |
179 | c896fe29 | bellard | else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) |
180 | c896fe29 | bellard | return 1; |
181 | c896fe29 | bellard | else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) |
182 | c896fe29 | bellard | return 1; |
183 | c896fe29 | bellard | else
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184 | c896fe29 | bellard | return 0; |
185 | c896fe29 | bellard | } |
186 | c896fe29 | bellard | |
187 | c896fe29 | bellard | #define ARITH_ADD 0 |
188 | c896fe29 | bellard | #define ARITH_OR 1 |
189 | c896fe29 | bellard | #define ARITH_ADC 2 |
190 | c896fe29 | bellard | #define ARITH_SBB 3 |
191 | c896fe29 | bellard | #define ARITH_AND 4 |
192 | c896fe29 | bellard | #define ARITH_SUB 5 |
193 | c896fe29 | bellard | #define ARITH_XOR 6 |
194 | c896fe29 | bellard | #define ARITH_CMP 7 |
195 | c896fe29 | bellard | |
196 | d42f183c | aurel32 | #define SHIFT_ROL 0 |
197 | d42f183c | aurel32 | #define SHIFT_ROR 1 |
198 | c896fe29 | bellard | #define SHIFT_SHL 4 |
199 | c896fe29 | bellard | #define SHIFT_SHR 5 |
200 | c896fe29 | bellard | #define SHIFT_SAR 7 |
201 | c896fe29 | bellard | |
202 | c896fe29 | bellard | #define JCC_JMP (-1) |
203 | c896fe29 | bellard | #define JCC_JO 0x0 |
204 | c896fe29 | bellard | #define JCC_JNO 0x1 |
205 | c896fe29 | bellard | #define JCC_JB 0x2 |
206 | c896fe29 | bellard | #define JCC_JAE 0x3 |
207 | c896fe29 | bellard | #define JCC_JE 0x4 |
208 | c896fe29 | bellard | #define JCC_JNE 0x5 |
209 | c896fe29 | bellard | #define JCC_JBE 0x6 |
210 | c896fe29 | bellard | #define JCC_JA 0x7 |
211 | c896fe29 | bellard | #define JCC_JS 0x8 |
212 | c896fe29 | bellard | #define JCC_JNS 0x9 |
213 | c896fe29 | bellard | #define JCC_JP 0xa |
214 | c896fe29 | bellard | #define JCC_JNP 0xb |
215 | c896fe29 | bellard | #define JCC_JL 0xc |
216 | c896fe29 | bellard | #define JCC_JGE 0xd |
217 | c896fe29 | bellard | #define JCC_JLE 0xe |
218 | c896fe29 | bellard | #define JCC_JG 0xf |
219 | c896fe29 | bellard | |
220 | 09aac126 | Richard Henderson | #define P_EXT 0x100 /* 0x0f opcode prefix */ |
221 | 09aac126 | Richard Henderson | #define P_REXW 0x200 /* set rex.w = 1 */ |
222 | 09aac126 | Richard Henderson | #define P_REXB_R 0x400 /* REG field as byte register */ |
223 | 09aac126 | Richard Henderson | #define P_REXB_RM 0x800 /* R/M field as byte register */ |
224 | c896fe29 | bellard | |
225 | c896fe29 | bellard | static const uint8_t tcg_cond_to_jcc[10] = { |
226 | c896fe29 | bellard | [TCG_COND_EQ] = JCC_JE, |
227 | c896fe29 | bellard | [TCG_COND_NE] = JCC_JNE, |
228 | c896fe29 | bellard | [TCG_COND_LT] = JCC_JL, |
229 | c896fe29 | bellard | [TCG_COND_GE] = JCC_JGE, |
230 | c896fe29 | bellard | [TCG_COND_LE] = JCC_JLE, |
231 | c896fe29 | bellard | [TCG_COND_GT] = JCC_JG, |
232 | c896fe29 | bellard | [TCG_COND_LTU] = JCC_JB, |
233 | c896fe29 | bellard | [TCG_COND_GEU] = JCC_JAE, |
234 | c896fe29 | bellard | [TCG_COND_LEU] = JCC_JBE, |
235 | c896fe29 | bellard | [TCG_COND_GTU] = JCC_JA, |
236 | c896fe29 | bellard | }; |
237 | c896fe29 | bellard | |
238 | 09aac126 | Richard Henderson | static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) |
239 | c896fe29 | bellard | { |
240 | 09aac126 | Richard Henderson | int rex = 0; |
241 | 09aac126 | Richard Henderson | |
242 | 09aac126 | Richard Henderson | rex |= (opc & P_REXW) >> 6; /* REX.W */ |
243 | 09aac126 | Richard Henderson | rex |= (r & 8) >> 1; /* REX.R */ |
244 | 09aac126 | Richard Henderson | rex |= (x & 8) >> 2; /* REX.X */ |
245 | 09aac126 | Richard Henderson | rex |= (rm & 8) >> 3; /* REX.B */ |
246 | 09aac126 | Richard Henderson | |
247 | 09aac126 | Richard Henderson | /* P_REXB_{R,RM} indicates that the given register is the low byte.
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248 | 09aac126 | Richard Henderson | For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
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249 | 09aac126 | Richard Henderson | as otherwise the encoding indicates %[abcd]h. Note that the values
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250 | 09aac126 | Richard Henderson | that are ORed in merely indicate that the REX byte must be present;
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251 | 09aac126 | Richard Henderson | those bits get discarded in output. */
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252 | 09aac126 | Richard Henderson | rex |= opc & (r >= 4 ? P_REXB_R : 0); |
253 | 09aac126 | Richard Henderson | rex |= opc & (rm >= 4 ? P_REXB_RM : 0); |
254 | 09aac126 | Richard Henderson | |
255 | 09aac126 | Richard Henderson | if (rex) {
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256 | 09aac126 | Richard Henderson | tcg_out8(s, (uint8_t)(rex | 0x40));
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257 | c896fe29 | bellard | } |
258 | 09aac126 | Richard Henderson | if (opc & P_EXT) {
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259 | c896fe29 | bellard | tcg_out8(s, 0x0f);
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260 | 09aac126 | Richard Henderson | } |
261 | 9e622b15 | blueswir1 | tcg_out8(s, opc & 0xff);
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262 | c896fe29 | bellard | } |
263 | c896fe29 | bellard | |
264 | c896fe29 | bellard | static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) |
265 | c896fe29 | bellard | { |
266 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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267 | c896fe29 | bellard | tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7)); |
268 | c896fe29 | bellard | } |
269 | c896fe29 | bellard | |
270 | c896fe29 | bellard | /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
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271 | c896fe29 | bellard | static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, |
272 | c896fe29 | bellard | tcg_target_long offset) |
273 | c896fe29 | bellard | { |
274 | c896fe29 | bellard | if (rm < 0) { |
275 | c896fe29 | bellard | tcg_target_long val; |
276 | c896fe29 | bellard | tcg_out_opc(s, opc, r, 0, 0); |
277 | c896fe29 | bellard | val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1)); |
278 | c896fe29 | bellard | if (val == (int32_t)val) {
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279 | c896fe29 | bellard | /* eip relative */
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280 | c896fe29 | bellard | tcg_out8(s, 0x05 | ((r & 7) << 3)); |
281 | c896fe29 | bellard | tcg_out32(s, val); |
282 | c896fe29 | bellard | } else if (offset == (int32_t)offset) { |
283 | c896fe29 | bellard | tcg_out8(s, 0x04 | ((r & 7) << 3)); |
284 | c896fe29 | bellard | tcg_out8(s, 0x25); /* sib */ |
285 | c896fe29 | bellard | tcg_out32(s, offset); |
286 | c896fe29 | bellard | } else {
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287 | c896fe29 | bellard | tcg_abort(); |
288 | c896fe29 | bellard | } |
289 | c896fe29 | bellard | } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
290 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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291 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
292 | c896fe29 | bellard | tcg_out8(s, 0x04 | ((r & 7) << 3)); |
293 | c896fe29 | bellard | tcg_out8(s, 0x24);
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294 | c896fe29 | bellard | } else {
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295 | c896fe29 | bellard | tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7)); |
296 | c896fe29 | bellard | } |
297 | c896fe29 | bellard | } else if ((int8_t)offset == offset) { |
298 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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299 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
300 | c896fe29 | bellard | tcg_out8(s, 0x44 | ((r & 7) << 3)); |
301 | c896fe29 | bellard | tcg_out8(s, 0x24);
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302 | c896fe29 | bellard | } else {
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303 | c896fe29 | bellard | tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7)); |
304 | c896fe29 | bellard | } |
305 | c896fe29 | bellard | tcg_out8(s, offset); |
306 | c896fe29 | bellard | } else {
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307 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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308 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
309 | c896fe29 | bellard | tcg_out8(s, 0x84 | ((r & 7) << 3)); |
310 | c896fe29 | bellard | tcg_out8(s, 0x24);
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311 | c896fe29 | bellard | } else {
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312 | c896fe29 | bellard | tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7)); |
313 | c896fe29 | bellard | } |
314 | c896fe29 | bellard | tcg_out32(s, offset); |
315 | c896fe29 | bellard | } |
316 | c896fe29 | bellard | } |
317 | c896fe29 | bellard | |
318 | bffd92fe | blueswir1 | #if defined(CONFIG_SOFTMMU)
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319 | c896fe29 | bellard | /* XXX: incomplete. index must be different from ESP */
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320 | c896fe29 | bellard | static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm, |
321 | c896fe29 | bellard | int index, int shift, |
322 | c896fe29 | bellard | tcg_target_long offset) |
323 | c896fe29 | bellard | { |
324 | c896fe29 | bellard | int mod;
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325 | c896fe29 | bellard | if (rm == -1) |
326 | c896fe29 | bellard | tcg_abort(); |
327 | c896fe29 | bellard | if (offset == 0 && (rm & 7) != TCG_REG_RBP) { |
328 | c896fe29 | bellard | mod = 0;
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329 | c896fe29 | bellard | } else if (offset == (int8_t)offset) { |
330 | c896fe29 | bellard | mod = 0x40;
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331 | c896fe29 | bellard | } else if (offset == (int32_t)offset) { |
332 | c896fe29 | bellard | mod = 0x80;
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333 | c896fe29 | bellard | } else {
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334 | c896fe29 | bellard | tcg_abort(); |
335 | c896fe29 | bellard | } |
336 | c896fe29 | bellard | if (index == -1) { |
337 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, 0);
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338 | c896fe29 | bellard | if ((rm & 7) == TCG_REG_RSP) { |
339 | c896fe29 | bellard | tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
340 | c896fe29 | bellard | tcg_out8(s, 0x04 | (rm & 7)); |
341 | c896fe29 | bellard | } else {
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342 | c896fe29 | bellard | tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7)); |
343 | c896fe29 | bellard | } |
344 | c896fe29 | bellard | } else {
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345 | c896fe29 | bellard | tcg_out_opc(s, opc, r, rm, index); |
346 | c896fe29 | bellard | tcg_out8(s, mod | ((r & 7) << 3) | 0x04); |
347 | c896fe29 | bellard | tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7)); |
348 | c896fe29 | bellard | } |
349 | c896fe29 | bellard | if (mod == 0x40) { |
350 | c896fe29 | bellard | tcg_out8(s, offset); |
351 | c896fe29 | bellard | } else if (mod == 0x80) { |
352 | c896fe29 | bellard | tcg_out32(s, offset); |
353 | c896fe29 | bellard | } |
354 | c896fe29 | bellard | } |
355 | bffd92fe | blueswir1 | #endif
|
356 | c896fe29 | bellard | |
357 | c896fe29 | bellard | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
358 | c896fe29 | bellard | { |
359 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
|
360 | c896fe29 | bellard | } |
361 | c896fe29 | bellard | |
362 | c896fe29 | bellard | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
363 | c896fe29 | bellard | int ret, tcg_target_long arg)
|
364 | c896fe29 | bellard | { |
365 | c896fe29 | bellard | if (arg == 0) { |
366 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */ |
367 | c896fe29 | bellard | } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) { |
368 | c896fe29 | bellard | tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0); |
369 | c896fe29 | bellard | tcg_out32(s, arg); |
370 | c896fe29 | bellard | } else if (arg == (int32_t)arg) { |
371 | c896fe29 | bellard | tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret); |
372 | c896fe29 | bellard | tcg_out32(s, arg); |
373 | c896fe29 | bellard | } else {
|
374 | c896fe29 | bellard | tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0); |
375 | c896fe29 | bellard | tcg_out32(s, arg); |
376 | c896fe29 | bellard | tcg_out32(s, arg >> 32);
|
377 | c896fe29 | bellard | } |
378 | c896fe29 | bellard | } |
379 | c896fe29 | bellard | |
380 | abb6ae2c | malc | static void tcg_out_goto(TCGContext *s, int call, uint8_t *target) |
381 | abb6ae2c | malc | { |
382 | abb6ae2c | malc | int32_t disp; |
383 | abb6ae2c | malc | |
384 | abb6ae2c | malc | disp = target - s->code_ptr - 5;
|
385 | abb6ae2c | malc | if (disp == (target - s->code_ptr - 5)) { |
386 | abb6ae2c | malc | tcg_out8(s, call ? 0xe8 : 0xe9); |
387 | abb6ae2c | malc | tcg_out32(s, disp); |
388 | abb6ae2c | malc | } else {
|
389 | abb6ae2c | malc | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, (tcg_target_long) target); |
390 | abb6ae2c | malc | tcg_out_modrm(s, 0xff, call ? 2 : 4, TCG_REG_R10); |
391 | abb6ae2c | malc | } |
392 | abb6ae2c | malc | } |
393 | abb6ae2c | malc | |
394 | e4d5434c | blueswir1 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
395 | c896fe29 | bellard | int arg1, tcg_target_long arg2)
|
396 | c896fe29 | bellard | { |
397 | e4d5434c | blueswir1 | if (type == TCG_TYPE_I32)
|
398 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */ |
399 | e4d5434c | blueswir1 | else
|
400 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */ |
401 | c896fe29 | bellard | } |
402 | c896fe29 | bellard | |
403 | e4d5434c | blueswir1 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
404 | c896fe29 | bellard | int arg1, tcg_target_long arg2)
|
405 | c896fe29 | bellard | { |
406 | e4d5434c | blueswir1 | if (type == TCG_TYPE_I32)
|
407 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */ |
408 | e4d5434c | blueswir1 | else
|
409 | e4d5434c | blueswir1 | tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */ |
410 | c896fe29 | bellard | } |
411 | c896fe29 | bellard | |
412 | c896fe29 | bellard | static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val) |
413 | c896fe29 | bellard | { |
414 | a4b18c6d | Aurelien Jarno | if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) { |
415 | a4b18c6d | Aurelien Jarno | /* inc */
|
416 | a4b18c6d | Aurelien Jarno | tcg_out_modrm(s, 0xff, 0, r0); |
417 | a4b18c6d | Aurelien Jarno | } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) { |
418 | a4b18c6d | Aurelien Jarno | /* dec */
|
419 | a4b18c6d | Aurelien Jarno | tcg_out_modrm(s, 0xff, 1, r0); |
420 | a4b18c6d | Aurelien Jarno | } else if (val == (int8_t)val) { |
421 | c896fe29 | bellard | tcg_out_modrm(s, 0x83, c, r0);
|
422 | c896fe29 | bellard | tcg_out8(s, val); |
423 | 733fef0e | pbrook | } else if (c == ARITH_AND && val == 0xffu) { |
424 | 733fef0e | pbrook | /* movzbl */
|
425 | 09aac126 | Richard Henderson | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, r0, r0);
|
426 | 733fef0e | pbrook | } else if (c == ARITH_AND && val == 0xffffu) { |
427 | 733fef0e | pbrook | /* movzwl */
|
428 | 733fef0e | pbrook | tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
|
429 | c896fe29 | bellard | } else {
|
430 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, c, r0);
|
431 | c896fe29 | bellard | tcg_out32(s, val); |
432 | c896fe29 | bellard | } |
433 | c896fe29 | bellard | } |
434 | c896fe29 | bellard | |
435 | c896fe29 | bellard | static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val) |
436 | c896fe29 | bellard | { |
437 | a4b18c6d | Aurelien Jarno | if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) { |
438 | a4b18c6d | Aurelien Jarno | /* inc */
|
439 | a4b18c6d | Aurelien Jarno | tcg_out_modrm(s, 0xff | P_REXW, 0, r0); |
440 | a4b18c6d | Aurelien Jarno | } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) { |
441 | a4b18c6d | Aurelien Jarno | /* dec */
|
442 | a4b18c6d | Aurelien Jarno | tcg_out_modrm(s, 0xff | P_REXW, 1, r0); |
443 | 733fef0e | pbrook | } else if (c == ARITH_AND && val == 0xffffffffu) { |
444 | 733fef0e | pbrook | /* 32-bit mov zero extends */
|
445 | 733fef0e | pbrook | tcg_out_modrm(s, 0x8b, r0, r0);
|
446 | 57169903 | Richard Henderson | } else if (c == ARITH_AND && val == (uint32_t)val) { |
447 | 57169903 | Richard Henderson | /* AND with no high bits set can use a 32-bit operation. */
|
448 | 57169903 | Richard Henderson | tgen_arithi32(s, c, r0, (uint32_t)val); |
449 | 57169903 | Richard Henderson | } else if (val == (int8_t)val) { |
450 | 57169903 | Richard Henderson | tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
|
451 | 57169903 | Richard Henderson | tcg_out8(s, val); |
452 | c896fe29 | bellard | } else if (val == (int32_t)val) { |
453 | c896fe29 | bellard | tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
|
454 | c896fe29 | bellard | tcg_out32(s, val); |
455 | c896fe29 | bellard | } else {
|
456 | c896fe29 | bellard | tcg_abort(); |
457 | c896fe29 | bellard | } |
458 | c896fe29 | bellard | } |
459 | c896fe29 | bellard | |
460 | 8fcd3692 | blueswir1 | static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
461 | c896fe29 | bellard | { |
462 | c896fe29 | bellard | if (val != 0) |
463 | c896fe29 | bellard | tgen_arithi64(s, ARITH_ADD, reg, val); |
464 | c896fe29 | bellard | } |
465 | c896fe29 | bellard | |
466 | c896fe29 | bellard | static void tcg_out_jxx(TCGContext *s, int opc, int label_index) |
467 | c896fe29 | bellard | { |
468 | c896fe29 | bellard | int32_t val, val1; |
469 | c896fe29 | bellard | TCGLabel *l = &s->labels[label_index]; |
470 | c896fe29 | bellard | |
471 | c896fe29 | bellard | if (l->has_value) {
|
472 | c896fe29 | bellard | val = l->u.value - (tcg_target_long)s->code_ptr; |
473 | c896fe29 | bellard | val1 = val - 2;
|
474 | c896fe29 | bellard | if ((int8_t)val1 == val1) {
|
475 | c896fe29 | bellard | if (opc == -1) |
476 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
477 | c896fe29 | bellard | else
|
478 | c896fe29 | bellard | tcg_out8(s, 0x70 + opc);
|
479 | c896fe29 | bellard | tcg_out8(s, val1); |
480 | c896fe29 | bellard | } else {
|
481 | c896fe29 | bellard | if (opc == -1) { |
482 | c896fe29 | bellard | tcg_out8(s, 0xe9);
|
483 | c896fe29 | bellard | tcg_out32(s, val - 5);
|
484 | c896fe29 | bellard | } else {
|
485 | c896fe29 | bellard | tcg_out8(s, 0x0f);
|
486 | c896fe29 | bellard | tcg_out8(s, 0x80 + opc);
|
487 | c896fe29 | bellard | tcg_out32(s, val - 6);
|
488 | c896fe29 | bellard | } |
489 | c896fe29 | bellard | } |
490 | c896fe29 | bellard | } else {
|
491 | c896fe29 | bellard | if (opc == -1) { |
492 | c896fe29 | bellard | tcg_out8(s, 0xe9);
|
493 | c896fe29 | bellard | } else {
|
494 | c896fe29 | bellard | tcg_out8(s, 0x0f);
|
495 | c896fe29 | bellard | tcg_out8(s, 0x80 + opc);
|
496 | c896fe29 | bellard | } |
497 | c896fe29 | bellard | tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
|
498 | 623e265c | pbrook | s->code_ptr += 4;
|
499 | c896fe29 | bellard | } |
500 | c896fe29 | bellard | } |
501 | c896fe29 | bellard | |
502 | c896fe29 | bellard | static void tcg_out_brcond(TCGContext *s, int cond, |
503 | c896fe29 | bellard | TCGArg arg1, TCGArg arg2, int const_arg2,
|
504 | c896fe29 | bellard | int label_index, int rexw) |
505 | c896fe29 | bellard | { |
506 | c896fe29 | bellard | if (const_arg2) {
|
507 | c896fe29 | bellard | if (arg2 == 0) { |
508 | c896fe29 | bellard | /* test r, r */
|
509 | c896fe29 | bellard | tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
|
510 | c896fe29 | bellard | } else {
|
511 | c896fe29 | bellard | if (rexw)
|
512 | c896fe29 | bellard | tgen_arithi64(s, ARITH_CMP, arg1, arg2); |
513 | c896fe29 | bellard | else
|
514 | c896fe29 | bellard | tgen_arithi32(s, ARITH_CMP, arg1, arg2); |
515 | c896fe29 | bellard | } |
516 | c896fe29 | bellard | } else {
|
517 | bb210e78 | bellard | tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1); |
518 | c896fe29 | bellard | } |
519 | 560f92cc | bellard | tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index); |
520 | c896fe29 | bellard | } |
521 | c896fe29 | bellard | |
522 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
523 | c896fe29 | bellard | |
524 | 79383c9c | blueswir1 | #include "../../softmmu_defs.h" |
525 | c896fe29 | bellard | |
526 | c896fe29 | bellard | static void *qemu_ld_helpers[4] = { |
527 | c896fe29 | bellard | __ldb_mmu, |
528 | c896fe29 | bellard | __ldw_mmu, |
529 | c896fe29 | bellard | __ldl_mmu, |
530 | c896fe29 | bellard | __ldq_mmu, |
531 | c896fe29 | bellard | }; |
532 | c896fe29 | bellard | |
533 | c896fe29 | bellard | static void *qemu_st_helpers[4] = { |
534 | c896fe29 | bellard | __stb_mmu, |
535 | c896fe29 | bellard | __stw_mmu, |
536 | c896fe29 | bellard | __stl_mmu, |
537 | c896fe29 | bellard | __stq_mmu, |
538 | c896fe29 | bellard | }; |
539 | c896fe29 | bellard | #endif
|
540 | c896fe29 | bellard | |
541 | c896fe29 | bellard | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
542 | c896fe29 | bellard | int opc)
|
543 | c896fe29 | bellard | { |
544 | c896fe29 | bellard | int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
545 | 379f6698 | Paul Brook | int32_t offset; |
546 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
547 | c896fe29 | bellard | uint8_t *label1_ptr, *label2_ptr; |
548 | c896fe29 | bellard | #endif
|
549 | c896fe29 | bellard | |
550 | c896fe29 | bellard | data_reg = *args++; |
551 | c896fe29 | bellard | addr_reg = *args++; |
552 | c896fe29 | bellard | mem_index = *args; |
553 | c896fe29 | bellard | s_bits = opc & 3;
|
554 | c896fe29 | bellard | |
555 | c896fe29 | bellard | r0 = TCG_REG_RDI; |
556 | c896fe29 | bellard | r1 = TCG_REG_RSI; |
557 | c896fe29 | bellard | |
558 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
559 | c896fe29 | bellard | rexw = 0;
|
560 | c896fe29 | bellard | #else
|
561 | c896fe29 | bellard | rexw = P_REXW; |
562 | c896fe29 | bellard | #endif
|
563 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
564 | c896fe29 | bellard | /* mov */
|
565 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
|
566 | c896fe29 | bellard | |
567 | c896fe29 | bellard | /* mov */
|
568 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
569 | c896fe29 | bellard | |
570 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
571 | c896fe29 | bellard | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
572 | c896fe29 | bellard | |
573 | c896fe29 | bellard | tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
574 | c896fe29 | bellard | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
575 | c896fe29 | bellard | |
576 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
577 | c896fe29 | bellard | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
578 | c896fe29 | bellard | |
579 | c896fe29 | bellard | /* lea offset(r1, env), r1 */
|
580 | c896fe29 | bellard | tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
581 | c896fe29 | bellard | offsetof(CPUState, tlb_table[mem_index][0].addr_read));
|
582 | c896fe29 | bellard | |
583 | c896fe29 | bellard | /* cmp 0(r1), r0 */
|
584 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
585 | c896fe29 | bellard | |
586 | c896fe29 | bellard | /* mov */
|
587 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
588 | c896fe29 | bellard | |
589 | c896fe29 | bellard | /* je label1 */
|
590 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JE);
|
591 | c896fe29 | bellard | label1_ptr = s->code_ptr; |
592 | c896fe29 | bellard | s->code_ptr++; |
593 | c896fe29 | bellard | |
594 | c896fe29 | bellard | /* XXX: move that code at the end of the TB */
|
595 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index); |
596 | abb6ae2c | malc | tcg_out_goto(s, 1, qemu_ld_helpers[s_bits]);
|
597 | c896fe29 | bellard | |
598 | c896fe29 | bellard | switch(opc) {
|
599 | c896fe29 | bellard | case 0 | 4: |
600 | c896fe29 | bellard | /* movsbq */
|
601 | c896fe29 | bellard | tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
602 | c896fe29 | bellard | break;
|
603 | c896fe29 | bellard | case 1 | 4: |
604 | c896fe29 | bellard | /* movswq */
|
605 | c896fe29 | bellard | tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
606 | c896fe29 | bellard | break;
|
607 | c896fe29 | bellard | case 2 | 4: |
608 | c896fe29 | bellard | /* movslq */
|
609 | c896fe29 | bellard | tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
|
610 | c896fe29 | bellard | break;
|
611 | c896fe29 | bellard | case 0: |
612 | 9db3ba4d | aurel32 | /* movzbq */
|
613 | 9db3ba4d | aurel32 | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
614 | 9db3ba4d | aurel32 | break;
|
615 | c896fe29 | bellard | case 1: |
616 | 9db3ba4d | aurel32 | /* movzwq */
|
617 | 9db3ba4d | aurel32 | tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
|
618 | 9db3ba4d | aurel32 | break;
|
619 | c896fe29 | bellard | case 2: |
620 | c896fe29 | bellard | default:
|
621 | c896fe29 | bellard | /* movl */
|
622 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
|
623 | c896fe29 | bellard | break;
|
624 | c896fe29 | bellard | case 3: |
625 | c896fe29 | bellard | tcg_out_mov(s, data_reg, TCG_REG_RAX); |
626 | c896fe29 | bellard | break;
|
627 | c896fe29 | bellard | } |
628 | c896fe29 | bellard | |
629 | c896fe29 | bellard | /* jmp label2 */
|
630 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
631 | c896fe29 | bellard | label2_ptr = s->code_ptr; |
632 | c896fe29 | bellard | s->code_ptr++; |
633 | c896fe29 | bellard | |
634 | c896fe29 | bellard | /* label1: */
|
635 | c896fe29 | bellard | *label1_ptr = s->code_ptr - label1_ptr - 1;
|
636 | c896fe29 | bellard | |
637 | c896fe29 | bellard | /* add x(r1), r0 */
|
638 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
639 | c896fe29 | bellard | offsetof(CPUTLBEntry, addr_read)); |
640 | 379f6698 | Paul Brook | offset = 0;
|
641 | c896fe29 | bellard | #else
|
642 | 379f6698 | Paul Brook | if (GUEST_BASE == (int32_t)GUEST_BASE) {
|
643 | 379f6698 | Paul Brook | r0 = addr_reg; |
644 | 379f6698 | Paul Brook | offset = GUEST_BASE; |
645 | 379f6698 | Paul Brook | } else {
|
646 | 379f6698 | Paul Brook | offset = 0;
|
647 | 379f6698 | Paul Brook | /* movq $GUEST_BASE, r0 */
|
648 | 379f6698 | Paul Brook | tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0); |
649 | 379f6698 | Paul Brook | tcg_out32(s, GUEST_BASE); |
650 | 379f6698 | Paul Brook | tcg_out32(s, GUEST_BASE >> 32);
|
651 | 379f6698 | Paul Brook | /* addq addr_reg, r0 */
|
652 | 379f6698 | Paul Brook | tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
|
653 | 379f6698 | Paul Brook | } |
654 | c896fe29 | bellard | #endif
|
655 | c896fe29 | bellard | |
656 | c896fe29 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
657 | c896fe29 | bellard | bswap = 1;
|
658 | c896fe29 | bellard | #else
|
659 | c896fe29 | bellard | bswap = 0;
|
660 | c896fe29 | bellard | #endif
|
661 | c896fe29 | bellard | switch(opc) {
|
662 | c896fe29 | bellard | case 0: |
663 | c896fe29 | bellard | /* movzbl */
|
664 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, offset);
|
665 | c896fe29 | bellard | break;
|
666 | c896fe29 | bellard | case 0 | 4: |
667 | c896fe29 | bellard | /* movsbX */
|
668 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, offset);
|
669 | c896fe29 | bellard | break;
|
670 | c896fe29 | bellard | case 1: |
671 | c896fe29 | bellard | /* movzwl */
|
672 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
|
673 | c896fe29 | bellard | if (bswap) {
|
674 | c896fe29 | bellard | /* rolw $8, data_reg */
|
675 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
676 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, data_reg); |
677 | c896fe29 | bellard | tcg_out8(s, 8);
|
678 | c896fe29 | bellard | } |
679 | c896fe29 | bellard | break;
|
680 | c896fe29 | bellard | case 1 | 4: |
681 | c896fe29 | bellard | if (bswap) {
|
682 | c896fe29 | bellard | /* movzwl */
|
683 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
|
684 | c896fe29 | bellard | /* rolw $8, data_reg */
|
685 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
686 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, data_reg); |
687 | c896fe29 | bellard | tcg_out8(s, 8);
|
688 | c896fe29 | bellard | |
689 | c896fe29 | bellard | /* movswX data_reg, data_reg */
|
690 | c896fe29 | bellard | tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
|
691 | c896fe29 | bellard | } else {
|
692 | c896fe29 | bellard | /* movswX */
|
693 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, offset);
|
694 | c896fe29 | bellard | } |
695 | c896fe29 | bellard | break;
|
696 | c896fe29 | bellard | case 2: |
697 | c896fe29 | bellard | /* movl (r0), data_reg */
|
698 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
|
699 | c896fe29 | bellard | if (bswap) {
|
700 | c896fe29 | bellard | /* bswap */
|
701 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
702 | c896fe29 | bellard | } |
703 | c896fe29 | bellard | break;
|
704 | c896fe29 | bellard | case 2 | 4: |
705 | c896fe29 | bellard | if (bswap) {
|
706 | c896fe29 | bellard | /* movl (r0), data_reg */
|
707 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
|
708 | c896fe29 | bellard | /* bswap */
|
709 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0); |
710 | c896fe29 | bellard | /* movslq */
|
711 | c896fe29 | bellard | tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
|
712 | c896fe29 | bellard | } else {
|
713 | c896fe29 | bellard | /* movslq */
|
714 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, offset);
|
715 | c896fe29 | bellard | } |
716 | c896fe29 | bellard | break;
|
717 | c896fe29 | bellard | case 3: |
718 | c896fe29 | bellard | /* movq (r0), data_reg */
|
719 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, offset);
|
720 | c896fe29 | bellard | if (bswap) {
|
721 | c896fe29 | bellard | /* bswap */
|
722 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0); |
723 | c896fe29 | bellard | } |
724 | c896fe29 | bellard | break;
|
725 | c896fe29 | bellard | default:
|
726 | c896fe29 | bellard | tcg_abort(); |
727 | c896fe29 | bellard | } |
728 | c896fe29 | bellard | |
729 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
730 | c896fe29 | bellard | /* label2: */
|
731 | c896fe29 | bellard | *label2_ptr = s->code_ptr - label2_ptr - 1;
|
732 | c896fe29 | bellard | #endif
|
733 | c896fe29 | bellard | } |
734 | c896fe29 | bellard | |
735 | c896fe29 | bellard | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
736 | c896fe29 | bellard | int opc)
|
737 | c896fe29 | bellard | { |
738 | c896fe29 | bellard | int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
|
739 | 379f6698 | Paul Brook | int32_t offset; |
740 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
741 | c896fe29 | bellard | uint8_t *label1_ptr, *label2_ptr; |
742 | c896fe29 | bellard | #endif
|
743 | c896fe29 | bellard | |
744 | c896fe29 | bellard | data_reg = *args++; |
745 | c896fe29 | bellard | addr_reg = *args++; |
746 | c896fe29 | bellard | mem_index = *args; |
747 | c896fe29 | bellard | |
748 | c896fe29 | bellard | s_bits = opc; |
749 | c896fe29 | bellard | |
750 | c896fe29 | bellard | r0 = TCG_REG_RDI; |
751 | c896fe29 | bellard | r1 = TCG_REG_RSI; |
752 | c896fe29 | bellard | |
753 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
754 | c896fe29 | bellard | rexw = 0;
|
755 | c896fe29 | bellard | #else
|
756 | c896fe29 | bellard | rexw = P_REXW; |
757 | c896fe29 | bellard | #endif
|
758 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
759 | c896fe29 | bellard | /* mov */
|
760 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
|
761 | c896fe29 | bellard | |
762 | c896fe29 | bellard | /* mov */
|
763 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
764 | c896fe29 | bellard | |
765 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */ |
766 | c896fe29 | bellard | tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
767 | c896fe29 | bellard | |
768 | c896fe29 | bellard | tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */ |
769 | c896fe29 | bellard | tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
770 | c896fe29 | bellard | |
771 | c896fe29 | bellard | tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
772 | c896fe29 | bellard | tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
773 | c896fe29 | bellard | |
774 | c896fe29 | bellard | /* lea offset(r1, env), r1 */
|
775 | c896fe29 | bellard | tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0, |
776 | c896fe29 | bellard | offsetof(CPUState, tlb_table[mem_index][0].addr_write));
|
777 | c896fe29 | bellard | |
778 | c896fe29 | bellard | /* cmp 0(r1), r0 */
|
779 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0); |
780 | c896fe29 | bellard | |
781 | c896fe29 | bellard | /* mov */
|
782 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
|
783 | c896fe29 | bellard | |
784 | c896fe29 | bellard | /* je label1 */
|
785 | c896fe29 | bellard | tcg_out8(s, 0x70 + JCC_JE);
|
786 | c896fe29 | bellard | label1_ptr = s->code_ptr; |
787 | c896fe29 | bellard | s->code_ptr++; |
788 | c896fe29 | bellard | |
789 | c896fe29 | bellard | /* XXX: move that code at the end of the TB */
|
790 | c896fe29 | bellard | switch(opc) {
|
791 | c896fe29 | bellard | case 0: |
792 | c896fe29 | bellard | /* movzbl */
|
793 | 09aac126 | Richard Henderson | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, TCG_REG_RSI, data_reg);
|
794 | c896fe29 | bellard | break;
|
795 | c896fe29 | bellard | case 1: |
796 | c896fe29 | bellard | /* movzwl */
|
797 | c896fe29 | bellard | tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
|
798 | c896fe29 | bellard | break;
|
799 | c896fe29 | bellard | case 2: |
800 | c896fe29 | bellard | /* movl */
|
801 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
|
802 | c896fe29 | bellard | break;
|
803 | c896fe29 | bellard | default:
|
804 | c896fe29 | bellard | case 3: |
805 | c896fe29 | bellard | tcg_out_mov(s, TCG_REG_RSI, data_reg); |
806 | c896fe29 | bellard | break;
|
807 | c896fe29 | bellard | } |
808 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index); |
809 | abb6ae2c | malc | tcg_out_goto(s, 1, qemu_st_helpers[s_bits]);
|
810 | c896fe29 | bellard | |
811 | c896fe29 | bellard | /* jmp label2 */
|
812 | c896fe29 | bellard | tcg_out8(s, 0xeb);
|
813 | c896fe29 | bellard | label2_ptr = s->code_ptr; |
814 | c896fe29 | bellard | s->code_ptr++; |
815 | c896fe29 | bellard | |
816 | c896fe29 | bellard | /* label1: */
|
817 | c896fe29 | bellard | *label1_ptr = s->code_ptr - label1_ptr - 1;
|
818 | c896fe29 | bellard | |
819 | c896fe29 | bellard | /* add x(r1), r0 */
|
820 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
|
821 | c896fe29 | bellard | offsetof(CPUTLBEntry, addr_write)); |
822 | 379f6698 | Paul Brook | offset = 0;
|
823 | c896fe29 | bellard | #else
|
824 | 379f6698 | Paul Brook | if (GUEST_BASE == (int32_t)GUEST_BASE) {
|
825 | 379f6698 | Paul Brook | r0 = addr_reg; |
826 | 379f6698 | Paul Brook | offset = GUEST_BASE; |
827 | 379f6698 | Paul Brook | } else {
|
828 | 379f6698 | Paul Brook | offset = 0;
|
829 | 379f6698 | Paul Brook | /* movq $GUEST_BASE, r0 */
|
830 | 379f6698 | Paul Brook | tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0); |
831 | 379f6698 | Paul Brook | tcg_out32(s, GUEST_BASE); |
832 | 379f6698 | Paul Brook | tcg_out32(s, GUEST_BASE >> 32);
|
833 | 379f6698 | Paul Brook | /* addq addr_reg, r0 */
|
834 | 379f6698 | Paul Brook | tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
|
835 | 379f6698 | Paul Brook | } |
836 | c896fe29 | bellard | #endif
|
837 | c896fe29 | bellard | |
838 | c896fe29 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
839 | c896fe29 | bellard | bswap = 1;
|
840 | c896fe29 | bellard | #else
|
841 | c896fe29 | bellard | bswap = 0;
|
842 | c896fe29 | bellard | #endif
|
843 | c896fe29 | bellard | switch(opc) {
|
844 | c896fe29 | bellard | case 0: |
845 | c896fe29 | bellard | /* movb */
|
846 | 09aac126 | Richard Henderson | tcg_out_modrm_offset(s, 0x88 | P_REXB_R, data_reg, r0, offset);
|
847 | c896fe29 | bellard | break;
|
848 | c896fe29 | bellard | case 1: |
849 | c896fe29 | bellard | if (bswap) {
|
850 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */ |
851 | c896fe29 | bellard | tcg_out8(s, 0x66); /* rolw $8, %ecx */ |
852 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, 0, r1); |
853 | c896fe29 | bellard | tcg_out8(s, 8);
|
854 | c896fe29 | bellard | data_reg = r1; |
855 | c896fe29 | bellard | } |
856 | c896fe29 | bellard | /* movw */
|
857 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
858 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
|
859 | c896fe29 | bellard | break;
|
860 | c896fe29 | bellard | case 2: |
861 | c896fe29 | bellard | if (bswap) {
|
862 | c896fe29 | bellard | tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */ |
863 | c896fe29 | bellard | /* bswap data_reg */
|
864 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0); |
865 | c896fe29 | bellard | data_reg = r1; |
866 | c896fe29 | bellard | } |
867 | c896fe29 | bellard | /* movl */
|
868 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
|
869 | c896fe29 | bellard | break;
|
870 | c896fe29 | bellard | case 3: |
871 | c896fe29 | bellard | if (bswap) {
|
872 | c896fe29 | bellard | tcg_out_mov(s, r1, data_reg); |
873 | c896fe29 | bellard | /* bswap data_reg */
|
874 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0); |
875 | c896fe29 | bellard | data_reg = r1; |
876 | c896fe29 | bellard | } |
877 | c896fe29 | bellard | /* movq */
|
878 | 379f6698 | Paul Brook | tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, offset);
|
879 | c896fe29 | bellard | break;
|
880 | c896fe29 | bellard | default:
|
881 | c896fe29 | bellard | tcg_abort(); |
882 | c896fe29 | bellard | } |
883 | c896fe29 | bellard | |
884 | c896fe29 | bellard | #if defined(CONFIG_SOFTMMU)
|
885 | c896fe29 | bellard | /* label2: */
|
886 | c896fe29 | bellard | *label2_ptr = s->code_ptr - label2_ptr - 1;
|
887 | c896fe29 | bellard | #endif
|
888 | c896fe29 | bellard | } |
889 | c896fe29 | bellard | |
890 | c896fe29 | bellard | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
891 | c896fe29 | bellard | const int *const_args) |
892 | c896fe29 | bellard | { |
893 | c896fe29 | bellard | int c;
|
894 | c896fe29 | bellard | |
895 | c896fe29 | bellard | switch(opc) {
|
896 | c896fe29 | bellard | case INDEX_op_exit_tb:
|
897 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
|
898 | abb6ae2c | malc | tcg_out_goto(s, 0, tb_ret_addr);
|
899 | c896fe29 | bellard | break;
|
900 | c896fe29 | bellard | case INDEX_op_goto_tb:
|
901 | c896fe29 | bellard | if (s->tb_jmp_offset) {
|
902 | c896fe29 | bellard | /* direct jump method */
|
903 | c896fe29 | bellard | tcg_out8(s, 0xe9); /* jmp im */ |
904 | c896fe29 | bellard | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
905 | c896fe29 | bellard | tcg_out32(s, 0);
|
906 | c896fe29 | bellard | } else {
|
907 | c896fe29 | bellard | /* indirect jump method */
|
908 | c896fe29 | bellard | /* jmp Ev */
|
909 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xff, 4, -1, |
910 | c896fe29 | bellard | (tcg_target_long)(s->tb_next + |
911 | c896fe29 | bellard | args[0]));
|
912 | c896fe29 | bellard | } |
913 | c896fe29 | bellard | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
914 | c896fe29 | bellard | break;
|
915 | c896fe29 | bellard | case INDEX_op_call:
|
916 | c896fe29 | bellard | if (const_args[0]) { |
917 | abb6ae2c | malc | tcg_out_goto(s, 1, (void *) args[0]); |
918 | c896fe29 | bellard | } else {
|
919 | c896fe29 | bellard | tcg_out_modrm(s, 0xff, 2, args[0]); |
920 | c896fe29 | bellard | } |
921 | c896fe29 | bellard | break;
|
922 | c896fe29 | bellard | case INDEX_op_jmp:
|
923 | c896fe29 | bellard | if (const_args[0]) { |
924 | abb6ae2c | malc | tcg_out_goto(s, 0, (void *) args[0]); |
925 | c896fe29 | bellard | } else {
|
926 | c896fe29 | bellard | tcg_out_modrm(s, 0xff, 4, args[0]); |
927 | c896fe29 | bellard | } |
928 | c896fe29 | bellard | break;
|
929 | c896fe29 | bellard | case INDEX_op_br:
|
930 | c896fe29 | bellard | tcg_out_jxx(s, JCC_JMP, args[0]);
|
931 | c896fe29 | bellard | break;
|
932 | c896fe29 | bellard | case INDEX_op_movi_i32:
|
933 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
934 | c896fe29 | bellard | break;
|
935 | c896fe29 | bellard | case INDEX_op_movi_i64:
|
936 | c896fe29 | bellard | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
937 | c896fe29 | bellard | break;
|
938 | c896fe29 | bellard | case INDEX_op_ld8u_i32:
|
939 | c896fe29 | bellard | case INDEX_op_ld8u_i64:
|
940 | c896fe29 | bellard | /* movzbl */
|
941 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]); |
942 | c896fe29 | bellard | break;
|
943 | c896fe29 | bellard | case INDEX_op_ld8s_i32:
|
944 | c896fe29 | bellard | /* movsbl */
|
945 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]); |
946 | c896fe29 | bellard | break;
|
947 | c896fe29 | bellard | case INDEX_op_ld8s_i64:
|
948 | c896fe29 | bellard | /* movsbq */
|
949 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]); |
950 | c896fe29 | bellard | break;
|
951 | c896fe29 | bellard | case INDEX_op_ld16u_i32:
|
952 | c896fe29 | bellard | case INDEX_op_ld16u_i64:
|
953 | c896fe29 | bellard | /* movzwl */
|
954 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]); |
955 | c896fe29 | bellard | break;
|
956 | c896fe29 | bellard | case INDEX_op_ld16s_i32:
|
957 | c896fe29 | bellard | /* movswl */
|
958 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]); |
959 | c896fe29 | bellard | break;
|
960 | c896fe29 | bellard | case INDEX_op_ld16s_i64:
|
961 | c896fe29 | bellard | /* movswq */
|
962 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]); |
963 | c896fe29 | bellard | break;
|
964 | c896fe29 | bellard | case INDEX_op_ld_i32:
|
965 | c896fe29 | bellard | case INDEX_op_ld32u_i64:
|
966 | c896fe29 | bellard | /* movl */
|
967 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]); |
968 | c896fe29 | bellard | break;
|
969 | c896fe29 | bellard | case INDEX_op_ld32s_i64:
|
970 | c896fe29 | bellard | /* movslq */
|
971 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]); |
972 | c896fe29 | bellard | break;
|
973 | c896fe29 | bellard | case INDEX_op_ld_i64:
|
974 | c896fe29 | bellard | /* movq */
|
975 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]); |
976 | c896fe29 | bellard | break;
|
977 | c896fe29 | bellard | |
978 | c896fe29 | bellard | case INDEX_op_st8_i32:
|
979 | c896fe29 | bellard | case INDEX_op_st8_i64:
|
980 | c896fe29 | bellard | /* movb */
|
981 | 09aac126 | Richard Henderson | tcg_out_modrm_offset(s, 0x88 | P_REXB_R, args[0], args[1], args[2]); |
982 | c896fe29 | bellard | break;
|
983 | c896fe29 | bellard | case INDEX_op_st16_i32:
|
984 | c896fe29 | bellard | case INDEX_op_st16_i64:
|
985 | c896fe29 | bellard | /* movw */
|
986 | c896fe29 | bellard | tcg_out8(s, 0x66);
|
987 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
988 | c896fe29 | bellard | break;
|
989 | c896fe29 | bellard | case INDEX_op_st_i32:
|
990 | c896fe29 | bellard | case INDEX_op_st32_i64:
|
991 | c896fe29 | bellard | /* movl */
|
992 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
993 | c896fe29 | bellard | break;
|
994 | c896fe29 | bellard | case INDEX_op_st_i64:
|
995 | c896fe29 | bellard | /* movq */
|
996 | c896fe29 | bellard | tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]); |
997 | c896fe29 | bellard | break;
|
998 | c896fe29 | bellard | |
999 | c896fe29 | bellard | case INDEX_op_sub_i32:
|
1000 | c896fe29 | bellard | c = ARITH_SUB; |
1001 | c896fe29 | bellard | goto gen_arith32;
|
1002 | c896fe29 | bellard | case INDEX_op_and_i32:
|
1003 | c896fe29 | bellard | c = ARITH_AND; |
1004 | c896fe29 | bellard | goto gen_arith32;
|
1005 | c896fe29 | bellard | case INDEX_op_or_i32:
|
1006 | c896fe29 | bellard | c = ARITH_OR; |
1007 | c896fe29 | bellard | goto gen_arith32;
|
1008 | c896fe29 | bellard | case INDEX_op_xor_i32:
|
1009 | c896fe29 | bellard | c = ARITH_XOR; |
1010 | c896fe29 | bellard | goto gen_arith32;
|
1011 | c896fe29 | bellard | case INDEX_op_add_i32:
|
1012 | c896fe29 | bellard | c = ARITH_ADD; |
1013 | c896fe29 | bellard | gen_arith32:
|
1014 | c896fe29 | bellard | if (const_args[2]) { |
1015 | c896fe29 | bellard | tgen_arithi32(s, c, args[0], args[2]); |
1016 | c896fe29 | bellard | } else {
|
1017 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]); |
1018 | c896fe29 | bellard | } |
1019 | c896fe29 | bellard | break;
|
1020 | c896fe29 | bellard | |
1021 | c896fe29 | bellard | case INDEX_op_sub_i64:
|
1022 | c896fe29 | bellard | c = ARITH_SUB; |
1023 | c896fe29 | bellard | goto gen_arith64;
|
1024 | c896fe29 | bellard | case INDEX_op_and_i64:
|
1025 | c896fe29 | bellard | c = ARITH_AND; |
1026 | c896fe29 | bellard | goto gen_arith64;
|
1027 | c896fe29 | bellard | case INDEX_op_or_i64:
|
1028 | c896fe29 | bellard | c = ARITH_OR; |
1029 | c896fe29 | bellard | goto gen_arith64;
|
1030 | c896fe29 | bellard | case INDEX_op_xor_i64:
|
1031 | c896fe29 | bellard | c = ARITH_XOR; |
1032 | c896fe29 | bellard | goto gen_arith64;
|
1033 | c896fe29 | bellard | case INDEX_op_add_i64:
|
1034 | c896fe29 | bellard | c = ARITH_ADD; |
1035 | c896fe29 | bellard | gen_arith64:
|
1036 | c896fe29 | bellard | if (const_args[2]) { |
1037 | c896fe29 | bellard | tgen_arithi64(s, c, args[0], args[2]); |
1038 | c896fe29 | bellard | } else {
|
1039 | c896fe29 | bellard | tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]); |
1040 | c896fe29 | bellard | } |
1041 | c896fe29 | bellard | break;
|
1042 | c896fe29 | bellard | |
1043 | c896fe29 | bellard | case INDEX_op_mul_i32:
|
1044 | c896fe29 | bellard | if (const_args[2]) { |
1045 | c896fe29 | bellard | int32_t val; |
1046 | c896fe29 | bellard | val = args[2];
|
1047 | c896fe29 | bellard | if (val == (int8_t)val) {
|
1048 | c896fe29 | bellard | tcg_out_modrm(s, 0x6b, args[0], args[0]); |
1049 | c896fe29 | bellard | tcg_out8(s, val); |
1050 | c896fe29 | bellard | } else {
|
1051 | c896fe29 | bellard | tcg_out_modrm(s, 0x69, args[0], args[0]); |
1052 | c896fe29 | bellard | tcg_out32(s, val); |
1053 | c896fe29 | bellard | } |
1054 | c896fe29 | bellard | } else {
|
1055 | c896fe29 | bellard | tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]); |
1056 | c896fe29 | bellard | } |
1057 | c896fe29 | bellard | break;
|
1058 | c896fe29 | bellard | case INDEX_op_mul_i64:
|
1059 | c896fe29 | bellard | if (const_args[2]) { |
1060 | c896fe29 | bellard | int32_t val; |
1061 | c896fe29 | bellard | val = args[2];
|
1062 | c896fe29 | bellard | if (val == (int8_t)val) {
|
1063 | c896fe29 | bellard | tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]); |
1064 | c896fe29 | bellard | tcg_out8(s, val); |
1065 | c896fe29 | bellard | } else {
|
1066 | c896fe29 | bellard | tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]); |
1067 | c896fe29 | bellard | tcg_out32(s, val); |
1068 | c896fe29 | bellard | } |
1069 | c896fe29 | bellard | } else {
|
1070 | c896fe29 | bellard | tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]); |
1071 | c896fe29 | bellard | } |
1072 | c896fe29 | bellard | break;
|
1073 | c896fe29 | bellard | case INDEX_op_div2_i32:
|
1074 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7, 7, args[4]); |
1075 | c896fe29 | bellard | break;
|
1076 | c896fe29 | bellard | case INDEX_op_divu2_i32:
|
1077 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7, 6, args[4]); |
1078 | c896fe29 | bellard | break;
|
1079 | c896fe29 | bellard | case INDEX_op_div2_i64:
|
1080 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]); |
1081 | c896fe29 | bellard | break;
|
1082 | c896fe29 | bellard | case INDEX_op_divu2_i64:
|
1083 | c896fe29 | bellard | tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]); |
1084 | c896fe29 | bellard | break;
|
1085 | c896fe29 | bellard | |
1086 | c896fe29 | bellard | case INDEX_op_shl_i32:
|
1087 | c896fe29 | bellard | c = SHIFT_SHL; |
1088 | c896fe29 | bellard | gen_shift32:
|
1089 | c896fe29 | bellard | if (const_args[2]) { |
1090 | c896fe29 | bellard | if (args[2] == 1) { |
1091 | c896fe29 | bellard | tcg_out_modrm(s, 0xd1, c, args[0]); |
1092 | c896fe29 | bellard | } else {
|
1093 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1, c, args[0]); |
1094 | c896fe29 | bellard | tcg_out8(s, args[2]);
|
1095 | c896fe29 | bellard | } |
1096 | c896fe29 | bellard | } else {
|
1097 | c896fe29 | bellard | tcg_out_modrm(s, 0xd3, c, args[0]); |
1098 | c896fe29 | bellard | } |
1099 | c896fe29 | bellard | break;
|
1100 | c896fe29 | bellard | case INDEX_op_shr_i32:
|
1101 | c896fe29 | bellard | c = SHIFT_SHR; |
1102 | c896fe29 | bellard | goto gen_shift32;
|
1103 | c896fe29 | bellard | case INDEX_op_sar_i32:
|
1104 | c896fe29 | bellard | c = SHIFT_SAR; |
1105 | c896fe29 | bellard | goto gen_shift32;
|
1106 | d42f183c | aurel32 | case INDEX_op_rotl_i32:
|
1107 | d42f183c | aurel32 | c = SHIFT_ROL; |
1108 | d42f183c | aurel32 | goto gen_shift32;
|
1109 | d42f183c | aurel32 | case INDEX_op_rotr_i32:
|
1110 | d42f183c | aurel32 | c = SHIFT_ROR; |
1111 | d42f183c | aurel32 | goto gen_shift32;
|
1112 | d42f183c | aurel32 | |
1113 | c896fe29 | bellard | case INDEX_op_shl_i64:
|
1114 | c896fe29 | bellard | c = SHIFT_SHL; |
1115 | c896fe29 | bellard | gen_shift64:
|
1116 | c896fe29 | bellard | if (const_args[2]) { |
1117 | c896fe29 | bellard | if (args[2] == 1) { |
1118 | c896fe29 | bellard | tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]); |
1119 | c896fe29 | bellard | } else {
|
1120 | c896fe29 | bellard | tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]); |
1121 | c896fe29 | bellard | tcg_out8(s, args[2]);
|
1122 | c896fe29 | bellard | } |
1123 | c896fe29 | bellard | } else {
|
1124 | c896fe29 | bellard | tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]); |
1125 | c896fe29 | bellard | } |
1126 | c896fe29 | bellard | break;
|
1127 | c896fe29 | bellard | case INDEX_op_shr_i64:
|
1128 | c896fe29 | bellard | c = SHIFT_SHR; |
1129 | c896fe29 | bellard | goto gen_shift64;
|
1130 | c896fe29 | bellard | case INDEX_op_sar_i64:
|
1131 | c896fe29 | bellard | c = SHIFT_SAR; |
1132 | c896fe29 | bellard | goto gen_shift64;
|
1133 | d42f183c | aurel32 | case INDEX_op_rotl_i64:
|
1134 | d42f183c | aurel32 | c = SHIFT_ROL; |
1135 | d42f183c | aurel32 | goto gen_shift64;
|
1136 | d42f183c | aurel32 | case INDEX_op_rotr_i64:
|
1137 | d42f183c | aurel32 | c = SHIFT_ROR; |
1138 | d42f183c | aurel32 | goto gen_shift64;
|
1139 | d42f183c | aurel32 | |
1140 | c896fe29 | bellard | case INDEX_op_brcond_i32:
|
1141 | c896fe29 | bellard | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1142 | c896fe29 | bellard | args[3], 0); |
1143 | c896fe29 | bellard | break;
|
1144 | c896fe29 | bellard | case INDEX_op_brcond_i64:
|
1145 | c896fe29 | bellard | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1146 | c896fe29 | bellard | args[3], P_REXW);
|
1147 | c896fe29 | bellard | break;
|
1148 | c896fe29 | bellard | |
1149 | 86dbdd40 | aurel32 | case INDEX_op_bswap16_i32:
|
1150 | 86dbdd40 | aurel32 | case INDEX_op_bswap16_i64:
|
1151 | 86dbdd40 | aurel32 | tcg_out8(s, 0x66);
|
1152 | 86dbdd40 | aurel32 | tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]); |
1153 | 86dbdd40 | aurel32 | tcg_out8(s, 8);
|
1154 | 86dbdd40 | aurel32 | break;
|
1155 | 66896cb8 | aurel32 | case INDEX_op_bswap32_i32:
|
1156 | 86dbdd40 | aurel32 | case INDEX_op_bswap32_i64:
|
1157 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0); |
1158 | c896fe29 | bellard | break;
|
1159 | 66896cb8 | aurel32 | case INDEX_op_bswap64_i64:
|
1160 | c896fe29 | bellard | tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0); |
1161 | c896fe29 | bellard | break;
|
1162 | c896fe29 | bellard | |
1163 | 390efc54 | pbrook | case INDEX_op_neg_i32:
|
1164 | 390efc54 | pbrook | tcg_out_modrm(s, 0xf7, 3, args[0]); |
1165 | 390efc54 | pbrook | break;
|
1166 | 390efc54 | pbrook | case INDEX_op_neg_i64:
|
1167 | 390efc54 | pbrook | tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]); |
1168 | 390efc54 | pbrook | break;
|
1169 | 390efc54 | pbrook | |
1170 | d2604285 | aurel32 | case INDEX_op_not_i32:
|
1171 | d2604285 | aurel32 | tcg_out_modrm(s, 0xf7, 2, args[0]); |
1172 | d2604285 | aurel32 | break;
|
1173 | d2604285 | aurel32 | case INDEX_op_not_i64:
|
1174 | d2604285 | aurel32 | tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]); |
1175 | d2604285 | aurel32 | break;
|
1176 | d2604285 | aurel32 | |
1177 | b6d17150 | pbrook | case INDEX_op_ext8s_i32:
|
1178 | 09aac126 | Richard Henderson | tcg_out_modrm(s, 0xbe | P_EXT | P_REXB_RM, args[0], args[1]); |
1179 | b6d17150 | pbrook | break;
|
1180 | b6d17150 | pbrook | case INDEX_op_ext16s_i32:
|
1181 | b6d17150 | pbrook | tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]); |
1182 | b6d17150 | pbrook | break;
|
1183 | b6d17150 | pbrook | case INDEX_op_ext8s_i64:
|
1184 | b6d17150 | pbrook | tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]); |
1185 | b6d17150 | pbrook | break;
|
1186 | b6d17150 | pbrook | case INDEX_op_ext16s_i64:
|
1187 | b6d17150 | pbrook | tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]); |
1188 | b6d17150 | pbrook | break;
|
1189 | b6d17150 | pbrook | case INDEX_op_ext32s_i64:
|
1190 | b6d17150 | pbrook | tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]); |
1191 | b6d17150 | pbrook | break;
|
1192 | 64584218 | Aurelien Jarno | case INDEX_op_ext8u_i32:
|
1193 | 57169903 | Richard Henderson | case INDEX_op_ext8u_i64:
|
1194 | 09aac126 | Richard Henderson | tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, args[0], args[1]); |
1195 | 64584218 | Aurelien Jarno | break;
|
1196 | 64584218 | Aurelien Jarno | case INDEX_op_ext16u_i32:
|
1197 | 64584218 | Aurelien Jarno | case INDEX_op_ext16u_i64:
|
1198 | 57169903 | Richard Henderson | tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]); |
1199 | 64584218 | Aurelien Jarno | break;
|
1200 | 64584218 | Aurelien Jarno | case INDEX_op_ext32u_i64:
|
1201 | 64584218 | Aurelien Jarno | tcg_out_modrm(s, 0x8b, args[0], args[1]); |
1202 | 64584218 | Aurelien Jarno | break;
|
1203 | b6d17150 | pbrook | |
1204 | c896fe29 | bellard | case INDEX_op_qemu_ld8u:
|
1205 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 0);
|
1206 | c896fe29 | bellard | break;
|
1207 | c896fe29 | bellard | case INDEX_op_qemu_ld8s:
|
1208 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 0 | 4); |
1209 | c896fe29 | bellard | break;
|
1210 | c896fe29 | bellard | case INDEX_op_qemu_ld16u:
|
1211 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 1);
|
1212 | c896fe29 | bellard | break;
|
1213 | c896fe29 | bellard | case INDEX_op_qemu_ld16s:
|
1214 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 1 | 4); |
1215 | c896fe29 | bellard | break;
|
1216 | c896fe29 | bellard | case INDEX_op_qemu_ld32u:
|
1217 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 2);
|
1218 | c896fe29 | bellard | break;
|
1219 | c896fe29 | bellard | case INDEX_op_qemu_ld32s:
|
1220 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 2 | 4); |
1221 | c896fe29 | bellard | break;
|
1222 | c896fe29 | bellard | case INDEX_op_qemu_ld64:
|
1223 | c896fe29 | bellard | tcg_out_qemu_ld(s, args, 3);
|
1224 | c896fe29 | bellard | break;
|
1225 | c896fe29 | bellard | |
1226 | c896fe29 | bellard | case INDEX_op_qemu_st8:
|
1227 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 0);
|
1228 | c896fe29 | bellard | break;
|
1229 | c896fe29 | bellard | case INDEX_op_qemu_st16:
|
1230 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 1);
|
1231 | c896fe29 | bellard | break;
|
1232 | c896fe29 | bellard | case INDEX_op_qemu_st32:
|
1233 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 2);
|
1234 | c896fe29 | bellard | break;
|
1235 | c896fe29 | bellard | case INDEX_op_qemu_st64:
|
1236 | c896fe29 | bellard | tcg_out_qemu_st(s, args, 3);
|
1237 | c896fe29 | bellard | break;
|
1238 | c896fe29 | bellard | |
1239 | c896fe29 | bellard | default:
|
1240 | c896fe29 | bellard | tcg_abort(); |
1241 | c896fe29 | bellard | } |
1242 | c896fe29 | bellard | } |
1243 | c896fe29 | bellard | |
1244 | b03cce8e | bellard | static int tcg_target_callee_save_regs[] = { |
1245 | b03cce8e | bellard | TCG_REG_RBP, |
1246 | b03cce8e | bellard | TCG_REG_RBX, |
1247 | b03cce8e | bellard | TCG_REG_R12, |
1248 | b03cce8e | bellard | TCG_REG_R13, |
1249 | b03cce8e | bellard | /* TCG_REG_R14, */ /* currently used for the global env, so no |
1250 | b03cce8e | bellard | need to save */
|
1251 | b03cce8e | bellard | TCG_REG_R15, |
1252 | b03cce8e | bellard | }; |
1253 | b03cce8e | bellard | |
1254 | b03cce8e | bellard | static inline void tcg_out_push(TCGContext *s, int reg) |
1255 | b03cce8e | bellard | { |
1256 | b03cce8e | bellard | tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0); |
1257 | b03cce8e | bellard | } |
1258 | b03cce8e | bellard | |
1259 | b03cce8e | bellard | static inline void tcg_out_pop(TCGContext *s, int reg) |
1260 | b03cce8e | bellard | { |
1261 | b03cce8e | bellard | tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0); |
1262 | b03cce8e | bellard | } |
1263 | b03cce8e | bellard | |
1264 | b03cce8e | bellard | /* Generate global QEMU prologue and epilogue code */
|
1265 | b03cce8e | bellard | void tcg_target_qemu_prologue(TCGContext *s)
|
1266 | b03cce8e | bellard | { |
1267 | b03cce8e | bellard | int i, frame_size, push_size, stack_addend;
|
1268 | b03cce8e | bellard | |
1269 | b03cce8e | bellard | /* TB prologue */
|
1270 | b03cce8e | bellard | /* save all callee saved registers */
|
1271 | b03cce8e | bellard | for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { |
1272 | b03cce8e | bellard | tcg_out_push(s, tcg_target_callee_save_regs[i]); |
1273 | b03cce8e | bellard | |
1274 | b03cce8e | bellard | } |
1275 | b03cce8e | bellard | /* reserve some stack space */
|
1276 | b03cce8e | bellard | push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8; |
1277 | b03cce8e | bellard | frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE; |
1278 | b03cce8e | bellard | frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
|
1279 | b03cce8e | bellard | ~(TCG_TARGET_STACK_ALIGN - 1);
|
1280 | b03cce8e | bellard | stack_addend = frame_size - push_size; |
1281 | b03cce8e | bellard | tcg_out_addi(s, TCG_REG_RSP, -stack_addend); |
1282 | b03cce8e | bellard | |
1283 | b03cce8e | bellard | tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */ |
1284 | b03cce8e | bellard | |
1285 | b03cce8e | bellard | /* TB epilogue */
|
1286 | b03cce8e | bellard | tb_ret_addr = s->code_ptr; |
1287 | b03cce8e | bellard | tcg_out_addi(s, TCG_REG_RSP, stack_addend); |
1288 | b03cce8e | bellard | for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { |
1289 | b03cce8e | bellard | tcg_out_pop(s, tcg_target_callee_save_regs[i]); |
1290 | b03cce8e | bellard | } |
1291 | b03cce8e | bellard | tcg_out8(s, 0xc3); /* ret */ |
1292 | b03cce8e | bellard | } |
1293 | b03cce8e | bellard | |
1294 | c896fe29 | bellard | static const TCGTargetOpDef x86_64_op_defs[] = { |
1295 | c896fe29 | bellard | { INDEX_op_exit_tb, { } }, |
1296 | c896fe29 | bellard | { INDEX_op_goto_tb, { } }, |
1297 | c896fe29 | bellard | { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */ |
1298 | c896fe29 | bellard | { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */ |
1299 | c896fe29 | bellard | { INDEX_op_br, { } }, |
1300 | c896fe29 | bellard | |
1301 | c896fe29 | bellard | { INDEX_op_mov_i32, { "r", "r" } }, |
1302 | c896fe29 | bellard | { INDEX_op_movi_i32, { "r" } },
|
1303 | c896fe29 | bellard | { INDEX_op_ld8u_i32, { "r", "r" } }, |
1304 | c896fe29 | bellard | { INDEX_op_ld8s_i32, { "r", "r" } }, |
1305 | c896fe29 | bellard | { INDEX_op_ld16u_i32, { "r", "r" } }, |
1306 | c896fe29 | bellard | { INDEX_op_ld16s_i32, { "r", "r" } }, |
1307 | c896fe29 | bellard | { INDEX_op_ld_i32, { "r", "r" } }, |
1308 | c896fe29 | bellard | { INDEX_op_st8_i32, { "r", "r" } }, |
1309 | c896fe29 | bellard | { INDEX_op_st16_i32, { "r", "r" } }, |
1310 | c896fe29 | bellard | { INDEX_op_st_i32, { "r", "r" } }, |
1311 | c896fe29 | bellard | |
1312 | c896fe29 | bellard | { INDEX_op_add_i32, { "r", "0", "ri" } }, |
1313 | c896fe29 | bellard | { INDEX_op_mul_i32, { "r", "0", "ri" } }, |
1314 | c896fe29 | bellard | { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } }, |
1315 | c896fe29 | bellard | { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } }, |
1316 | c896fe29 | bellard | { INDEX_op_sub_i32, { "r", "0", "ri" } }, |
1317 | c896fe29 | bellard | { INDEX_op_and_i32, { "r", "0", "ri" } }, |
1318 | c896fe29 | bellard | { INDEX_op_or_i32, { "r", "0", "ri" } }, |
1319 | c896fe29 | bellard | { INDEX_op_xor_i32, { "r", "0", "ri" } }, |
1320 | c896fe29 | bellard | |
1321 | c896fe29 | bellard | { INDEX_op_shl_i32, { "r", "0", "ci" } }, |
1322 | c896fe29 | bellard | { INDEX_op_shr_i32, { "r", "0", "ci" } }, |
1323 | c896fe29 | bellard | { INDEX_op_sar_i32, { "r", "0", "ci" } }, |
1324 | d42f183c | aurel32 | { INDEX_op_rotl_i32, { "r", "0", "ci" } }, |
1325 | d42f183c | aurel32 | { INDEX_op_rotr_i32, { "r", "0", "ci" } }, |
1326 | c896fe29 | bellard | |
1327 | c896fe29 | bellard | { INDEX_op_brcond_i32, { "r", "ri" } }, |
1328 | c896fe29 | bellard | |
1329 | c896fe29 | bellard | { INDEX_op_mov_i64, { "r", "r" } }, |
1330 | c896fe29 | bellard | { INDEX_op_movi_i64, { "r" } },
|
1331 | c896fe29 | bellard | { INDEX_op_ld8u_i64, { "r", "r" } }, |
1332 | c896fe29 | bellard | { INDEX_op_ld8s_i64, { "r", "r" } }, |
1333 | c896fe29 | bellard | { INDEX_op_ld16u_i64, { "r", "r" } }, |
1334 | c896fe29 | bellard | { INDEX_op_ld16s_i64, { "r", "r" } }, |
1335 | c896fe29 | bellard | { INDEX_op_ld32u_i64, { "r", "r" } }, |
1336 | c896fe29 | bellard | { INDEX_op_ld32s_i64, { "r", "r" } }, |
1337 | c896fe29 | bellard | { INDEX_op_ld_i64, { "r", "r" } }, |
1338 | c896fe29 | bellard | { INDEX_op_st8_i64, { "r", "r" } }, |
1339 | c896fe29 | bellard | { INDEX_op_st16_i64, { "r", "r" } }, |
1340 | c896fe29 | bellard | { INDEX_op_st32_i64, { "r", "r" } }, |
1341 | c896fe29 | bellard | { INDEX_op_st_i64, { "r", "r" } }, |
1342 | c896fe29 | bellard | |
1343 | c896fe29 | bellard | { INDEX_op_add_i64, { "r", "0", "re" } }, |
1344 | c896fe29 | bellard | { INDEX_op_mul_i64, { "r", "0", "re" } }, |
1345 | c896fe29 | bellard | { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } }, |
1346 | c896fe29 | bellard | { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } }, |
1347 | c896fe29 | bellard | { INDEX_op_sub_i64, { "r", "0", "re" } }, |
1348 | c896fe29 | bellard | { INDEX_op_and_i64, { "r", "0", "reZ" } }, |
1349 | c896fe29 | bellard | { INDEX_op_or_i64, { "r", "0", "re" } }, |
1350 | c896fe29 | bellard | { INDEX_op_xor_i64, { "r", "0", "re" } }, |
1351 | c896fe29 | bellard | |
1352 | c896fe29 | bellard | { INDEX_op_shl_i64, { "r", "0", "ci" } }, |
1353 | c896fe29 | bellard | { INDEX_op_shr_i64, { "r", "0", "ci" } }, |
1354 | c896fe29 | bellard | { INDEX_op_sar_i64, { "r", "0", "ci" } }, |
1355 | d42f183c | aurel32 | { INDEX_op_rotl_i64, { "r", "0", "ci" } }, |
1356 | d42f183c | aurel32 | { INDEX_op_rotr_i64, { "r", "0", "ci" } }, |
1357 | c896fe29 | bellard | |
1358 | c896fe29 | bellard | { INDEX_op_brcond_i64, { "r", "re" } }, |
1359 | c896fe29 | bellard | |
1360 | 86dbdd40 | aurel32 | { INDEX_op_bswap16_i32, { "r", "0" } }, |
1361 | 86dbdd40 | aurel32 | { INDEX_op_bswap16_i64, { "r", "0" } }, |
1362 | 66896cb8 | aurel32 | { INDEX_op_bswap32_i32, { "r", "0" } }, |
1363 | 86dbdd40 | aurel32 | { INDEX_op_bswap32_i64, { "r", "0" } }, |
1364 | 66896cb8 | aurel32 | { INDEX_op_bswap64_i64, { "r", "0" } }, |
1365 | c896fe29 | bellard | |
1366 | 390efc54 | pbrook | { INDEX_op_neg_i32, { "r", "0" } }, |
1367 | 390efc54 | pbrook | { INDEX_op_neg_i64, { "r", "0" } }, |
1368 | 390efc54 | pbrook | |
1369 | d2604285 | aurel32 | { INDEX_op_not_i32, { "r", "0" } }, |
1370 | d2604285 | aurel32 | { INDEX_op_not_i64, { "r", "0" } }, |
1371 | d2604285 | aurel32 | |
1372 | b6d17150 | pbrook | { INDEX_op_ext8s_i32, { "r", "r"} }, |
1373 | b6d17150 | pbrook | { INDEX_op_ext16s_i32, { "r", "r"} }, |
1374 | b6d17150 | pbrook | { INDEX_op_ext8s_i64, { "r", "r"} }, |
1375 | b6d17150 | pbrook | { INDEX_op_ext16s_i64, { "r", "r"} }, |
1376 | b6d17150 | pbrook | { INDEX_op_ext32s_i64, { "r", "r"} }, |
1377 | 64584218 | Aurelien Jarno | { INDEX_op_ext8u_i32, { "r", "r"} }, |
1378 | 64584218 | Aurelien Jarno | { INDEX_op_ext16u_i32, { "r", "r"} }, |
1379 | 64584218 | Aurelien Jarno | { INDEX_op_ext8u_i64, { "r", "r"} }, |
1380 | 64584218 | Aurelien Jarno | { INDEX_op_ext16u_i64, { "r", "r"} }, |
1381 | 64584218 | Aurelien Jarno | { INDEX_op_ext32u_i64, { "r", "r"} }, |
1382 | b6d17150 | pbrook | |
1383 | c896fe29 | bellard | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
1384 | c896fe29 | bellard | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
1385 | c896fe29 | bellard | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
1386 | c896fe29 | bellard | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
1387 | c896fe29 | bellard | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
1388 | c896fe29 | bellard | { INDEX_op_qemu_ld32s, { "r", "L" } }, |
1389 | c896fe29 | bellard | { INDEX_op_qemu_ld64, { "r", "L" } }, |
1390 | c896fe29 | bellard | |
1391 | c896fe29 | bellard | { INDEX_op_qemu_st8, { "L", "L" } }, |
1392 | c896fe29 | bellard | { INDEX_op_qemu_st16, { "L", "L" } }, |
1393 | c896fe29 | bellard | { INDEX_op_qemu_st32, { "L", "L" } }, |
1394 | 016b2b28 | Aurelien Jarno | { INDEX_op_qemu_st64, { "L", "L" } }, |
1395 | c896fe29 | bellard | |
1396 | c896fe29 | bellard | { -1 },
|
1397 | c896fe29 | bellard | }; |
1398 | c896fe29 | bellard | |
1399 | c896fe29 | bellard | void tcg_target_init(TCGContext *s)
|
1400 | c896fe29 | bellard | { |
1401 | b03cce8e | bellard | /* fail safe */
|
1402 | b03cce8e | bellard | if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) |
1403 | b03cce8e | bellard | tcg_abort(); |
1404 | b03cce8e | bellard | |
1405 | c896fe29 | bellard | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); |
1406 | c896fe29 | bellard | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); |
1407 | c896fe29 | bellard | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1408 | c896fe29 | bellard | (1 << TCG_REG_RDI) |
|
1409 | c896fe29 | bellard | (1 << TCG_REG_RSI) |
|
1410 | c896fe29 | bellard | (1 << TCG_REG_RDX) |
|
1411 | c896fe29 | bellard | (1 << TCG_REG_RCX) |
|
1412 | c896fe29 | bellard | (1 << TCG_REG_R8) |
|
1413 | c896fe29 | bellard | (1 << TCG_REG_R9) |
|
1414 | c896fe29 | bellard | (1 << TCG_REG_RAX) |
|
1415 | c896fe29 | bellard | (1 << TCG_REG_R10) |
|
1416 | c896fe29 | bellard | (1 << TCG_REG_R11));
|
1417 | c896fe29 | bellard | |
1418 | c896fe29 | bellard | tcg_regset_clear(s->reserved_regs); |
1419 | c896fe29 | bellard | tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP); |
1420 | 3c3a1d20 | bellard | |
1421 | c896fe29 | bellard | tcg_add_target_add_op_defs(x86_64_op_defs); |
1422 | c896fe29 | bellard | } |