root / hw / mips_r4k.c @ 09b26c5e
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1 | 6af0bf9c | bellard | #include "vl.h" |
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2 | 6af0bf9c | bellard | |
3 | 6af0bf9c | bellard | #define BIOS_FILENAME "mips_bios.bin" |
4 | 6af0bf9c | bellard | //#define BIOS_FILENAME "system.bin"
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5 | 6af0bf9c | bellard | #define KERNEL_LOAD_ADDR 0x80010000 |
6 | 6af0bf9c | bellard | #define INITRD_LOAD_ADDR 0x80800000 |
7 | 6af0bf9c | bellard | |
8 | 6af0bf9c | bellard | extern FILE *logfile;
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9 | 6af0bf9c | bellard | |
10 | 697584ab | bellard | static PITState *pit;
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11 | 697584ab | bellard | |
12 | 73133662 | bellard | static void pic_irq_request(void *opaque, int level) |
13 | 6af0bf9c | bellard | { |
14 | c68ea704 | bellard | CPUState *env = first_cpu; |
15 | 73133662 | bellard | if (level) {
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16 | c68ea704 | bellard | env->CP0_Cause |= 0x00000400;
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17 | c68ea704 | bellard | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
18 | 6af0bf9c | bellard | } else {
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19 | c68ea704 | bellard | env->CP0_Cause &= ~0x00000400;
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20 | c68ea704 | bellard | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
21 | 6af0bf9c | bellard | } |
22 | 6af0bf9c | bellard | } |
23 | 6af0bf9c | bellard | |
24 | 6af0bf9c | bellard | void cpu_mips_irqctrl_init (void) |
25 | 6af0bf9c | bellard | { |
26 | 6af0bf9c | bellard | } |
27 | 6af0bf9c | bellard | |
28 | 6af0bf9c | bellard | uint32_t cpu_mips_get_random (CPUState *env) |
29 | 6af0bf9c | bellard | { |
30 | 899abcf5 | bellard | uint32_t now = qemu_get_clock(vm_clock); |
31 | 6af0bf9c | bellard | |
32 | 899abcf5 | bellard | return now % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
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33 | 6af0bf9c | bellard | } |
34 | 6af0bf9c | bellard | |
35 | 899abcf5 | bellard | /* MIPS R4K timer */
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36 | 6af0bf9c | bellard | uint32_t cpu_mips_get_count (CPUState *env) |
37 | 6af0bf9c | bellard | { |
38 | 6af0bf9c | bellard | return env->CP0_Count +
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39 | 6af0bf9c | bellard | (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
40 | 6af0bf9c | bellard | 100 * 1000 * 1000, ticks_per_sec); |
41 | 6af0bf9c | bellard | } |
42 | 6af0bf9c | bellard | |
43 | 6af0bf9c | bellard | static void cpu_mips_update_count (CPUState *env, uint32_t count, |
44 | 6af0bf9c | bellard | uint32_t compare) |
45 | 6af0bf9c | bellard | { |
46 | 6af0bf9c | bellard | uint64_t now, next; |
47 | 6af0bf9c | bellard | uint32_t tmp; |
48 | 6af0bf9c | bellard | |
49 | 6af0bf9c | bellard | tmp = count; |
50 | 6af0bf9c | bellard | if (count == compare)
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51 | 6af0bf9c | bellard | tmp++; |
52 | 6af0bf9c | bellard | now = qemu_get_clock(vm_clock); |
53 | 6af0bf9c | bellard | next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); |
54 | 6af0bf9c | bellard | if (next == now)
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55 | 6af0bf9c | bellard | next++; |
56 | 2d7272a5 | bellard | #if 0
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57 | 6af0bf9c | bellard | if (logfile) {
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58 | 6af0bf9c | bellard | fprintf(logfile, "%s: 0x%08llx %08x %08x => 0x%08llx\n",
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59 | 6af0bf9c | bellard | __func__, now, count, compare, next - now);
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60 | 6af0bf9c | bellard | }
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61 | 6af0bf9c | bellard | #endif
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62 | 6af0bf9c | bellard | /* Store new count and compare registers */
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63 | 6af0bf9c | bellard | env->CP0_Compare = compare; |
64 | 6af0bf9c | bellard | env->CP0_Count = |
65 | 6af0bf9c | bellard | count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); |
66 | 6af0bf9c | bellard | /* Adjust timer */
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67 | 6af0bf9c | bellard | qemu_mod_timer(env->timer, next); |
68 | 6af0bf9c | bellard | } |
69 | 6af0bf9c | bellard | |
70 | 6af0bf9c | bellard | void cpu_mips_store_count (CPUState *env, uint32_t value)
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71 | 6af0bf9c | bellard | { |
72 | 6af0bf9c | bellard | cpu_mips_update_count(env, value, env->CP0_Compare); |
73 | 6af0bf9c | bellard | } |
74 | 6af0bf9c | bellard | |
75 | 6af0bf9c | bellard | void cpu_mips_store_compare (CPUState *env, uint32_t value)
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76 | 6af0bf9c | bellard | { |
77 | 6af0bf9c | bellard | cpu_mips_update_count(env, cpu_mips_get_count(env), value); |
78 | c68ea704 | bellard | env->CP0_Cause &= ~0x00008000;
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79 | c68ea704 | bellard | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
80 | 6af0bf9c | bellard | } |
81 | 6af0bf9c | bellard | |
82 | 6af0bf9c | bellard | static void mips_timer_cb (void *opaque) |
83 | 6af0bf9c | bellard | { |
84 | 6af0bf9c | bellard | CPUState *env; |
85 | 6af0bf9c | bellard | |
86 | 6af0bf9c | bellard | env = opaque; |
87 | 2d7272a5 | bellard | #if 0
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88 | 6af0bf9c | bellard | if (logfile) {
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89 | 6af0bf9c | bellard | fprintf(logfile, "%s\n", __func__);
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90 | 6af0bf9c | bellard | }
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91 | 6af0bf9c | bellard | #endif
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92 | 6af0bf9c | bellard | cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); |
93 | c68ea704 | bellard | env->CP0_Cause |= 0x00008000;
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94 | c68ea704 | bellard | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
95 | 6af0bf9c | bellard | } |
96 | 6af0bf9c | bellard | |
97 | 6af0bf9c | bellard | void cpu_mips_clock_init (CPUState *env)
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98 | 6af0bf9c | bellard | { |
99 | 6af0bf9c | bellard | env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
100 | 6af0bf9c | bellard | env->CP0_Compare = 0;
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101 | 6af0bf9c | bellard | cpu_mips_update_count(env, 1, 0); |
102 | 6af0bf9c | bellard | } |
103 | 6af0bf9c | bellard | |
104 | 6af0bf9c | bellard | static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
105 | 6af0bf9c | bellard | { |
106 | 2d7272a5 | bellard | #if 0
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107 | 6af0bf9c | bellard | if (logfile)
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108 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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109 | 2d7272a5 | bellard | #endif
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110 | 6af0bf9c | bellard | cpu_outb(NULL, addr & 0xffff, value); |
111 | 6af0bf9c | bellard | } |
112 | 6af0bf9c | bellard | |
113 | 6af0bf9c | bellard | static uint32_t io_readb (void *opaque, target_phys_addr_t addr) |
114 | 6af0bf9c | bellard | { |
115 | 6af0bf9c | bellard | uint32_t ret = cpu_inb(NULL, addr & 0xffff); |
116 | 2d7272a5 | bellard | #if 0
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117 | 6af0bf9c | bellard | if (logfile)
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118 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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119 | 2d7272a5 | bellard | #endif
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120 | 6af0bf9c | bellard | return ret;
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121 | 6af0bf9c | bellard | } |
122 | 6af0bf9c | bellard | |
123 | 6af0bf9c | bellard | static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
124 | 6af0bf9c | bellard | { |
125 | 2d7272a5 | bellard | #if 0
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126 | 6af0bf9c | bellard | if (logfile)
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127 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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128 | 2d7272a5 | bellard | #endif
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129 | 6af0bf9c | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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130 | 6af0bf9c | bellard | value = bswap16(value); |
131 | 6af0bf9c | bellard | #endif
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132 | 6af0bf9c | bellard | cpu_outw(NULL, addr & 0xffff, value); |
133 | 6af0bf9c | bellard | } |
134 | 6af0bf9c | bellard | |
135 | 6af0bf9c | bellard | static uint32_t io_readw (void *opaque, target_phys_addr_t addr) |
136 | 6af0bf9c | bellard | { |
137 | 6af0bf9c | bellard | uint32_t ret = cpu_inw(NULL, addr & 0xffff); |
138 | 6af0bf9c | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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139 | 6af0bf9c | bellard | ret = bswap16(ret); |
140 | 6af0bf9c | bellard | #endif
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141 | 2d7272a5 | bellard | #if 0
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142 | 6af0bf9c | bellard | if (logfile)
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143 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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144 | 2d7272a5 | bellard | #endif
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145 | 6af0bf9c | bellard | return ret;
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146 | 6af0bf9c | bellard | } |
147 | 6af0bf9c | bellard | |
148 | 6af0bf9c | bellard | static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
149 | 6af0bf9c | bellard | { |
150 | 2d7272a5 | bellard | #if 0
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151 | 6af0bf9c | bellard | if (logfile)
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152 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value);
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153 | 2d7272a5 | bellard | #endif
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154 | 6af0bf9c | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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155 | 6af0bf9c | bellard | value = bswap32(value); |
156 | 6af0bf9c | bellard | #endif
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157 | 6af0bf9c | bellard | cpu_outl(NULL, addr & 0xffff, value); |
158 | 6af0bf9c | bellard | } |
159 | 6af0bf9c | bellard | |
160 | 6af0bf9c | bellard | static uint32_t io_readl (void *opaque, target_phys_addr_t addr) |
161 | 6af0bf9c | bellard | { |
162 | 6af0bf9c | bellard | uint32_t ret = cpu_inl(NULL, addr & 0xffff); |
163 | 6af0bf9c | bellard | |
164 | 6af0bf9c | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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165 | 6af0bf9c | bellard | ret = bswap32(ret); |
166 | 6af0bf9c | bellard | #endif
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167 | 2d7272a5 | bellard | #if 0
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168 | 6af0bf9c | bellard | if (logfile)
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169 | 6af0bf9c | bellard | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret);
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170 | 2d7272a5 | bellard | #endif
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171 | 6af0bf9c | bellard | return ret;
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172 | 6af0bf9c | bellard | } |
173 | 6af0bf9c | bellard | |
174 | 6af0bf9c | bellard | CPUWriteMemoryFunc *io_write[] = { |
175 | 6af0bf9c | bellard | &io_writeb, |
176 | 6af0bf9c | bellard | &io_writew, |
177 | 6af0bf9c | bellard | &io_writel, |
178 | 6af0bf9c | bellard | }; |
179 | 6af0bf9c | bellard | |
180 | 6af0bf9c | bellard | CPUReadMemoryFunc *io_read[] = { |
181 | 6af0bf9c | bellard | &io_readb, |
182 | 6af0bf9c | bellard | &io_readw, |
183 | 6af0bf9c | bellard | &io_readl, |
184 | 6af0bf9c | bellard | }; |
185 | 6af0bf9c | bellard | |
186 | 6af0bf9c | bellard | void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
187 | 6af0bf9c | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
188 | 6af0bf9c | bellard | const char *kernel_filename, const char *kernel_cmdline, |
189 | 6af0bf9c | bellard | const char *initrd_filename) |
190 | 6af0bf9c | bellard | { |
191 | 6af0bf9c | bellard | char buf[1024]; |
192 | 6af0bf9c | bellard | target_ulong kernel_base, kernel_size, initrd_base, initrd_size; |
193 | 6af0bf9c | bellard | unsigned long bios_offset; |
194 | 6af0bf9c | bellard | int io_memory;
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195 | 6af0bf9c | bellard | int linux_boot;
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196 | 6af0bf9c | bellard | int ret;
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197 | c68ea704 | bellard | CPUState *env; |
198 | 6af0bf9c | bellard | |
199 | 6af0bf9c | bellard | printf("%s: start\n", __func__);
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200 | 6af0bf9c | bellard | linux_boot = (kernel_filename != NULL);
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201 | c68ea704 | bellard | |
202 | c68ea704 | bellard | env = cpu_init(); |
203 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
204 | c68ea704 | bellard | |
205 | 6af0bf9c | bellard | /* allocate RAM */
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206 | 6af0bf9c | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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207 | 6af0bf9c | bellard | bios_offset = ram_size + vga_ram_size; |
208 | 6af0bf9c | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
209 | 6af0bf9c | bellard | printf("%s: load BIOS '%s' size %d\n", __func__, buf, BIOS_SIZE);
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210 | 6af0bf9c | bellard | ret = load_image(buf, phys_ram_base + bios_offset); |
211 | 6af0bf9c | bellard | if (ret != BIOS_SIZE) {
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212 | 6af0bf9c | bellard | fprintf(stderr, "qemu: could not load MIPS bios '%s'\n", buf);
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213 | 6af0bf9c | bellard | exit(1);
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214 | 6af0bf9c | bellard | } |
215 | 6af0bf9c | bellard | cpu_register_physical_memory((uint32_t)(0x1fc00000),
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216 | 6af0bf9c | bellard | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
217 | 6af0bf9c | bellard | #if 0
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218 | 6af0bf9c | bellard | memcpy(phys_ram_base + 0x10000, phys_ram_base + bios_offset, BIOS_SIZE);
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219 | c68ea704 | bellard | env->PC = 0x80010004;
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220 | 6af0bf9c | bellard | #else
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221 | c68ea704 | bellard | env->PC = 0xBFC00004;
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222 | 6af0bf9c | bellard | #endif
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223 | 6af0bf9c | bellard | if (linux_boot) {
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224 | 6af0bf9c | bellard | kernel_base = KERNEL_LOAD_ADDR; |
225 | 6af0bf9c | bellard | /* now we can load the kernel */
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226 | de12d636 | bellard | kernel_size = load_image(kernel_filename, |
227 | de12d636 | bellard | phys_ram_base + (kernel_base - 0x80000000));
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228 | de12d636 | bellard | if (kernel_size == (target_ulong) -1) { |
229 | 6af0bf9c | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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230 | 6af0bf9c | bellard | kernel_filename); |
231 | 6af0bf9c | bellard | exit(1);
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232 | 6af0bf9c | bellard | } |
233 | 6af0bf9c | bellard | /* load initrd */
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234 | 6af0bf9c | bellard | if (initrd_filename) {
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235 | 6af0bf9c | bellard | initrd_base = INITRD_LOAD_ADDR; |
236 | 6af0bf9c | bellard | initrd_size = load_image(initrd_filename, |
237 | 6af0bf9c | bellard | phys_ram_base + initrd_base); |
238 | de12d636 | bellard | if (initrd_size == (target_ulong) -1) { |
239 | 6af0bf9c | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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240 | 6af0bf9c | bellard | initrd_filename); |
241 | 6af0bf9c | bellard | exit(1);
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242 | 6af0bf9c | bellard | } |
243 | 6af0bf9c | bellard | } else {
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244 | 6af0bf9c | bellard | initrd_base = 0;
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245 | 6af0bf9c | bellard | initrd_size = 0;
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246 | 6af0bf9c | bellard | } |
247 | c68ea704 | bellard | env->PC = KERNEL_LOAD_ADDR; |
248 | 2d7272a5 | bellard | /* Store command line. */
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249 | 2d7272a5 | bellard | strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); |
250 | 2d7272a5 | bellard | /* FIXME: little endian support */
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251 | 2d7272a5 | bellard | *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
252 | 2d7272a5 | bellard | *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); |
253 | 6af0bf9c | bellard | } else {
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254 | 6af0bf9c | bellard | kernel_base = 0;
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255 | 6af0bf9c | bellard | kernel_size = 0;
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256 | 6af0bf9c | bellard | initrd_base = 0;
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257 | 6af0bf9c | bellard | initrd_size = 0;
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258 | 6af0bf9c | bellard | } |
259 | 6af0bf9c | bellard | |
260 | 6af0bf9c | bellard | /* Init internal devices */
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261 | c68ea704 | bellard | cpu_mips_clock_init(env); |
262 | 6af0bf9c | bellard | cpu_mips_irqctrl_init(); |
263 | 6af0bf9c | bellard | |
264 | 0699b548 | bellard | /* Register 64 KB of ISA IO space at 0x14000000 */
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265 | 6af0bf9c | bellard | io_memory = cpu_register_io_memory(0, io_read, io_write, NULL); |
266 | 0699b548 | bellard | cpu_register_physical_memory(0x14000000, 0x00010000, io_memory); |
267 | 0699b548 | bellard | isa_mem_base = 0x10000000;
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268 | 0699b548 | bellard | |
269 | c68ea704 | bellard | isa_pic = pic_init(pic_irq_request, env); |
270 | 697584ab | bellard | pit = pit_init(0x40, 0); |
271 | e5d13e2f | bellard | serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
272 | 0699b548 | bellard | vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size,
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273 | d5295253 | bellard | vga_ram_size, 0, 0); |
274 | 9827e95c | bellard | |
275 | a41b2ff2 | pbrook | if (nd_table[0].vlan) { |
276 | a41b2ff2 | pbrook | if (nd_table[0].model == NULL |
277 | a41b2ff2 | pbrook | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
278 | a41b2ff2 | pbrook | isa_ne2000_init(0x300, 9, &nd_table[0]); |
279 | a41b2ff2 | pbrook | } else {
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280 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
281 | a41b2ff2 | pbrook | exit (1);
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282 | a41b2ff2 | pbrook | } |
283 | a41b2ff2 | pbrook | } |
284 | 6af0bf9c | bellard | } |
285 | 6af0bf9c | bellard | |
286 | 6af0bf9c | bellard | QEMUMachine mips_machine = { |
287 | 6af0bf9c | bellard | "mips",
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288 | 6af0bf9c | bellard | "mips r4k platform",
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289 | 6af0bf9c | bellard | mips_r4k_init, |
290 | 6af0bf9c | bellard | }; |