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1 | 69b91039 | bellard | /*
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2 | 69b91039 | bellard | * QEMU PCI bus manager
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3 | 69b91039 | bellard | *
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4 | 69b91039 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | 69b91039 | bellard | *
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6 | 69b91039 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 69b91039 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 69b91039 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 69b91039 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 69b91039 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 69b91039 | bellard | * furnished to do so, subject to the following conditions:
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12 | 69b91039 | bellard | *
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13 | 69b91039 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 69b91039 | bellard | * all copies or substantial portions of the Software.
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15 | 69b91039 | bellard | *
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16 | 69b91039 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 69b91039 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 69b91039 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 69b91039 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 69b91039 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 69b91039 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 69b91039 | bellard | * THE SOFTWARE.
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23 | 69b91039 | bellard | */
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24 | 69b91039 | bellard | #include "vl.h" |
25 | 69b91039 | bellard | |
26 | 69b91039 | bellard | //#define DEBUG_PCI
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27 | 69b91039 | bellard | |
28 | 0ac32c83 | bellard | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
29 | 0ac32c83 | bellard | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
30 | 0ac32c83 | bellard | #define PCI_COMMAND 0x04 /* 16 bits */ |
31 | 0ac32c83 | bellard | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
32 | 0ac32c83 | bellard | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
33 | 0ac32c83 | bellard | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
34 | 0ac32c83 | bellard | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
35 | 0ac32c83 | bellard | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
36 | 0ac32c83 | bellard | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
37 | 0ac32c83 | bellard | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
38 | 0ac32c83 | bellard | |
39 | 0ac32c83 | bellard | /* just used for simpler irq handling. */
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40 | 0ac32c83 | bellard | #define PCI_DEVICES_MAX 64 |
41 | 0ac32c83 | bellard | #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
42 | 0ac32c83 | bellard | |
43 | 30468f78 | bellard | struct PCIBus {
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44 | 30468f78 | bellard | int bus_num;
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45 | 30468f78 | bellard | int devfn_min;
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46 | 30468f78 | bellard | void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level); |
47 | 30468f78 | bellard | uint32_t config_reg; /* XXX: suppress */
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48 | 384d8876 | bellard | /* low level pic */
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49 | 384d8876 | bellard | SetIRQFunc *low_set_irq; |
50 | 384d8876 | bellard | void *irq_opaque;
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51 | 30468f78 | bellard | PCIDevice *devices[256];
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52 | 30468f78 | bellard | }; |
53 | 69b91039 | bellard | |
54 | 69b91039 | bellard | target_phys_addr_t pci_mem_base; |
55 | 0ac32c83 | bellard | static int pci_irq_index; |
56 | 0ac32c83 | bellard | static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS]; |
57 | 30468f78 | bellard | static PCIBus *first_bus;
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58 | 30468f78 | bellard | |
59 | 30468f78 | bellard | static PCIBus *pci_register_bus(void) |
60 | 30468f78 | bellard | { |
61 | 30468f78 | bellard | PCIBus *bus; |
62 | 30468f78 | bellard | bus = qemu_mallocz(sizeof(PCIBus));
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63 | 30468f78 | bellard | first_bus = bus; |
64 | 30468f78 | bellard | return bus;
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65 | 30468f78 | bellard | } |
66 | 69b91039 | bellard | |
67 | 30ca2aab | bellard | void generic_pci_save(QEMUFile* f, void *opaque) |
68 | 30ca2aab | bellard | { |
69 | 30ca2aab | bellard | PCIDevice* s=(PCIDevice*)opaque; |
70 | 30ca2aab | bellard | |
71 | 30ca2aab | bellard | qemu_put_buffer(f, s->config, 256);
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72 | 30ca2aab | bellard | } |
73 | 30ca2aab | bellard | |
74 | 30ca2aab | bellard | int generic_pci_load(QEMUFile* f, void *opaque, int version_id) |
75 | 30ca2aab | bellard | { |
76 | 30ca2aab | bellard | PCIDevice* s=(PCIDevice*)opaque; |
77 | 30ca2aab | bellard | |
78 | 30ca2aab | bellard | if (version_id != 1) |
79 | 30ca2aab | bellard | return -EINVAL;
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80 | 30ca2aab | bellard | |
81 | 30ca2aab | bellard | qemu_get_buffer(f, s->config, 256);
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82 | 30ca2aab | bellard | return 0; |
83 | 30ca2aab | bellard | } |
84 | 30ca2aab | bellard | |
85 | 69b91039 | bellard | /* -1 for devfn means auto assign */
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86 | 30468f78 | bellard | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
87 | 30468f78 | bellard | int instance_size, int devfn, |
88 | 69b91039 | bellard | PCIConfigReadFunc *config_read, |
89 | 69b91039 | bellard | PCIConfigWriteFunc *config_write) |
90 | 69b91039 | bellard | { |
91 | 30468f78 | bellard | PCIDevice *pci_dev; |
92 | 69b91039 | bellard | |
93 | 0ac32c83 | bellard | if (pci_irq_index >= PCI_DEVICES_MAX)
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94 | 0ac32c83 | bellard | return NULL; |
95 | 0ac32c83 | bellard | |
96 | 69b91039 | bellard | if (devfn < 0) { |
97 | 30468f78 | bellard | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
98 | 30468f78 | bellard | if (!bus->devices[devfn])
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99 | 69b91039 | bellard | goto found;
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100 | 69b91039 | bellard | } |
101 | 69b91039 | bellard | return NULL; |
102 | 69b91039 | bellard | found: ;
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103 | 69b91039 | bellard | } |
104 | 69b91039 | bellard | pci_dev = qemu_mallocz(instance_size); |
105 | 69b91039 | bellard | if (!pci_dev)
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106 | 69b91039 | bellard | return NULL; |
107 | 30468f78 | bellard | pci_dev->bus = bus; |
108 | 69b91039 | bellard | pci_dev->devfn = devfn; |
109 | 69b91039 | bellard | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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110 | 0ac32c83 | bellard | |
111 | 0ac32c83 | bellard | if (!config_read)
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112 | 0ac32c83 | bellard | config_read = pci_default_read_config; |
113 | 0ac32c83 | bellard | if (!config_write)
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114 | 0ac32c83 | bellard | config_write = pci_default_write_config; |
115 | 69b91039 | bellard | pci_dev->config_read = config_read; |
116 | 69b91039 | bellard | pci_dev->config_write = config_write; |
117 | 0ac32c83 | bellard | pci_dev->irq_index = pci_irq_index++; |
118 | 30468f78 | bellard | bus->devices[devfn] = pci_dev; |
119 | 69b91039 | bellard | return pci_dev;
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120 | 69b91039 | bellard | } |
121 | 69b91039 | bellard | |
122 | 69b91039 | bellard | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
123 | 69b91039 | bellard | uint32_t size, int type,
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124 | 69b91039 | bellard | PCIMapIORegionFunc *map_func) |
125 | 69b91039 | bellard | { |
126 | 69b91039 | bellard | PCIIORegion *r; |
127 | 69b91039 | bellard | |
128 | 8a8696a3 | bellard | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
129 | 69b91039 | bellard | return;
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130 | 69b91039 | bellard | r = &pci_dev->io_regions[region_num]; |
131 | 69b91039 | bellard | r->addr = -1;
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132 | 69b91039 | bellard | r->size = size; |
133 | 69b91039 | bellard | r->type = type; |
134 | 69b91039 | bellard | r->map_func = map_func; |
135 | 69b91039 | bellard | } |
136 | 69b91039 | bellard | |
137 | 0ac32c83 | bellard | static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
138 | 69b91039 | bellard | { |
139 | 30468f78 | bellard | PCIBus *s = opaque; |
140 | 69b91039 | bellard | s->config_reg = val; |
141 | 69b91039 | bellard | } |
142 | 69b91039 | bellard | |
143 | 0ac32c83 | bellard | static uint32_t pci_addr_readl(void* opaque, uint32_t addr) |
144 | 69b91039 | bellard | { |
145 | 30468f78 | bellard | PCIBus *s = opaque; |
146 | 69b91039 | bellard | return s->config_reg;
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147 | 69b91039 | bellard | } |
148 | 69b91039 | bellard | |
149 | 0ac32c83 | bellard | static void pci_update_mappings(PCIDevice *d) |
150 | 0ac32c83 | bellard | { |
151 | 0ac32c83 | bellard | PCIIORegion *r; |
152 | 0ac32c83 | bellard | int cmd, i;
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153 | 8a8696a3 | bellard | uint32_t last_addr, new_addr, config_ofs; |
154 | 0ac32c83 | bellard | |
155 | 0ac32c83 | bellard | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
156 | 8a8696a3 | bellard | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
157 | 0ac32c83 | bellard | r = &d->io_regions[i]; |
158 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT) {
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159 | 8a8696a3 | bellard | config_ofs = 0x30;
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160 | 8a8696a3 | bellard | } else {
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161 | 8a8696a3 | bellard | config_ofs = 0x10 + i * 4; |
162 | 8a8696a3 | bellard | } |
163 | 0ac32c83 | bellard | if (r->size != 0) { |
164 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
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165 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_IO) {
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166 | 0ac32c83 | bellard | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
167 | 8a8696a3 | bellard | config_ofs)); |
168 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
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169 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
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170 | 0ac32c83 | bellard | /* NOTE: we have only 64K ioports on PC */
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171 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
172 | 0ac32c83 | bellard | last_addr >= 0x10000) {
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173 | 0ac32c83 | bellard | new_addr = -1;
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174 | 0ac32c83 | bellard | } |
175 | 0ac32c83 | bellard | } else {
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176 | 0ac32c83 | bellard | new_addr = -1;
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177 | 0ac32c83 | bellard | } |
178 | 0ac32c83 | bellard | } else {
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179 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_MEMORY) {
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180 | 0ac32c83 | bellard | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
181 | 8a8696a3 | bellard | config_ofs)); |
182 | 8a8696a3 | bellard | /* the ROM slot has a specific enable bit */
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183 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
184 | 8a8696a3 | bellard | goto no_mem_map;
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185 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
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186 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
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187 | 0ac32c83 | bellard | /* NOTE: we do not support wrapping */
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188 | 0ac32c83 | bellard | /* XXX: as we cannot support really dynamic
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189 | 0ac32c83 | bellard | mappings, we handle specific values as invalid
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190 | 0ac32c83 | bellard | mappings. */
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191 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
192 | 0ac32c83 | bellard | last_addr == -1) {
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193 | 0ac32c83 | bellard | new_addr = -1;
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194 | 0ac32c83 | bellard | } |
195 | 0ac32c83 | bellard | } else {
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196 | 8a8696a3 | bellard | no_mem_map:
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197 | 0ac32c83 | bellard | new_addr = -1;
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198 | 0ac32c83 | bellard | } |
199 | 0ac32c83 | bellard | } |
200 | 0ac32c83 | bellard | /* now do the real mapping */
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201 | 0ac32c83 | bellard | if (new_addr != r->addr) {
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202 | 0ac32c83 | bellard | if (r->addr != -1) { |
203 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
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204 | 0ac32c83 | bellard | int class;
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205 | 0ac32c83 | bellard | /* NOTE: specific hack for IDE in PC case:
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206 | 0ac32c83 | bellard | only one byte must be mapped. */
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207 | 0ac32c83 | bellard | class = d->config[0x0a] | (d->config[0x0b] << 8); |
208 | 0ac32c83 | bellard | if (class == 0x0101 && r->size == 4) { |
209 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr + 2, 1); |
210 | 0ac32c83 | bellard | } else {
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211 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr, r->size); |
212 | 0ac32c83 | bellard | } |
213 | 0ac32c83 | bellard | } else {
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214 | 0ac32c83 | bellard | cpu_register_physical_memory(r->addr + pci_mem_base, |
215 | 0ac32c83 | bellard | r->size, |
216 | 0ac32c83 | bellard | IO_MEM_UNASSIGNED); |
217 | 0ac32c83 | bellard | } |
218 | 0ac32c83 | bellard | } |
219 | 0ac32c83 | bellard | r->addr = new_addr; |
220 | 0ac32c83 | bellard | if (r->addr != -1) { |
221 | 0ac32c83 | bellard | r->map_func(d, i, r->addr, r->size, r->type); |
222 | 0ac32c83 | bellard | } |
223 | 0ac32c83 | bellard | } |
224 | 0ac32c83 | bellard | } |
225 | 0ac32c83 | bellard | } |
226 | 0ac32c83 | bellard | } |
227 | 0ac32c83 | bellard | |
228 | 0ac32c83 | bellard | uint32_t pci_default_read_config(PCIDevice *d, |
229 | 0ac32c83 | bellard | uint32_t address, int len)
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230 | 69b91039 | bellard | { |
231 | 0ac32c83 | bellard | uint32_t val; |
232 | 0ac32c83 | bellard | switch(len) {
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233 | 0ac32c83 | bellard | case 1: |
234 | 0ac32c83 | bellard | val = d->config[address]; |
235 | 0ac32c83 | bellard | break;
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236 | 0ac32c83 | bellard | case 2: |
237 | 0ac32c83 | bellard | val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
238 | 0ac32c83 | bellard | break;
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239 | 0ac32c83 | bellard | default:
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240 | 0ac32c83 | bellard | case 4: |
241 | 0ac32c83 | bellard | val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
242 | 0ac32c83 | bellard | break;
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243 | 0ac32c83 | bellard | } |
244 | 0ac32c83 | bellard | return val;
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245 | 0ac32c83 | bellard | } |
246 | 0ac32c83 | bellard | |
247 | 0ac32c83 | bellard | void pci_default_write_config(PCIDevice *d,
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248 | 0ac32c83 | bellard | uint32_t address, uint32_t val, int len)
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249 | 0ac32c83 | bellard | { |
250 | 0ac32c83 | bellard | int can_write, i;
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251 | 7bf5be70 | bellard | uint32_t end, addr; |
252 | 0ac32c83 | bellard | |
253 | 8a8696a3 | bellard | if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
254 | 8a8696a3 | bellard | (address >= 0x30 && address < 0x34))) { |
255 | 0ac32c83 | bellard | PCIIORegion *r; |
256 | 0ac32c83 | bellard | int reg;
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257 | 0ac32c83 | bellard | |
258 | 8a8696a3 | bellard | if ( address >= 0x30 ) { |
259 | 8a8696a3 | bellard | reg = PCI_ROM_SLOT; |
260 | 8a8696a3 | bellard | }else{
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261 | 8a8696a3 | bellard | reg = (address - 0x10) >> 2; |
262 | 8a8696a3 | bellard | } |
263 | 0ac32c83 | bellard | r = &d->io_regions[reg]; |
264 | 0ac32c83 | bellard | if (r->size == 0) |
265 | 0ac32c83 | bellard | goto default_config;
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266 | 0ac32c83 | bellard | /* compute the stored value */
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267 | 8a8696a3 | bellard | if (reg == PCI_ROM_SLOT) {
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268 | 8a8696a3 | bellard | /* keep ROM enable bit */
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269 | 8a8696a3 | bellard | val &= (~(r->size - 1)) | 1; |
270 | 8a8696a3 | bellard | } else {
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271 | 8a8696a3 | bellard | val &= ~(r->size - 1);
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272 | 8a8696a3 | bellard | val |= r->type; |
273 | 8a8696a3 | bellard | } |
274 | 8a8696a3 | bellard | *(uint32_t *)(d->config + address) = cpu_to_le32(val); |
275 | 0ac32c83 | bellard | pci_update_mappings(d); |
276 | 69b91039 | bellard | return;
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277 | 0ac32c83 | bellard | } |
278 | 0ac32c83 | bellard | default_config:
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279 | 0ac32c83 | bellard | /* not efficient, but simple */
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280 | 7bf5be70 | bellard | addr = address; |
281 | 0ac32c83 | bellard | for(i = 0; i < len; i++) { |
282 | 0ac32c83 | bellard | /* default read/write accesses */
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283 | 1f62d938 | bellard | switch(d->config[0x0e]) { |
284 | 0ac32c83 | bellard | case 0x00: |
285 | 1f62d938 | bellard | case 0x80: |
286 | 1f62d938 | bellard | switch(addr) {
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287 | 1f62d938 | bellard | case 0x00: |
288 | 1f62d938 | bellard | case 0x01: |
289 | 1f62d938 | bellard | case 0x02: |
290 | 1f62d938 | bellard | case 0x03: |
291 | 1f62d938 | bellard | case 0x08: |
292 | 1f62d938 | bellard | case 0x09: |
293 | 1f62d938 | bellard | case 0x0a: |
294 | 1f62d938 | bellard | case 0x0b: |
295 | 1f62d938 | bellard | case 0x0e: |
296 | 1f62d938 | bellard | case 0x10 ... 0x27: /* base */ |
297 | 1f62d938 | bellard | case 0x30 ... 0x33: /* rom */ |
298 | 1f62d938 | bellard | case 0x3d: |
299 | 1f62d938 | bellard | can_write = 0;
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300 | 1f62d938 | bellard | break;
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301 | 1f62d938 | bellard | default:
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302 | 1f62d938 | bellard | can_write = 1;
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303 | 1f62d938 | bellard | break;
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304 | 1f62d938 | bellard | } |
305 | 0ac32c83 | bellard | break;
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306 | 0ac32c83 | bellard | default:
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307 | 1f62d938 | bellard | case 0x01: |
308 | 1f62d938 | bellard | switch(addr) {
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309 | 1f62d938 | bellard | case 0x00: |
310 | 1f62d938 | bellard | case 0x01: |
311 | 1f62d938 | bellard | case 0x02: |
312 | 1f62d938 | bellard | case 0x03: |
313 | 1f62d938 | bellard | case 0x08: |
314 | 1f62d938 | bellard | case 0x09: |
315 | 1f62d938 | bellard | case 0x0a: |
316 | 1f62d938 | bellard | case 0x0b: |
317 | 1f62d938 | bellard | case 0x0e: |
318 | 1f62d938 | bellard | case 0x38 ... 0x3b: /* rom */ |
319 | 1f62d938 | bellard | case 0x3d: |
320 | 1f62d938 | bellard | can_write = 0;
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321 | 1f62d938 | bellard | break;
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322 | 1f62d938 | bellard | default:
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323 | 1f62d938 | bellard | can_write = 1;
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324 | 1f62d938 | bellard | break;
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325 | 1f62d938 | bellard | } |
326 | 0ac32c83 | bellard | break;
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327 | 0ac32c83 | bellard | } |
328 | 0ac32c83 | bellard | if (can_write) {
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329 | 7bf5be70 | bellard | d->config[addr] = val; |
330 | 0ac32c83 | bellard | } |
331 | 7bf5be70 | bellard | addr++; |
332 | 0ac32c83 | bellard | val >>= 8;
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333 | 0ac32c83 | bellard | } |
334 | 0ac32c83 | bellard | |
335 | 0ac32c83 | bellard | end = address + len; |
336 | 0ac32c83 | bellard | if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
337 | 0ac32c83 | bellard | /* if the command register is modified, we must modify the mappings */
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338 | 0ac32c83 | bellard | pci_update_mappings(d); |
339 | 69b91039 | bellard | } |
340 | 69b91039 | bellard | } |
341 | 69b91039 | bellard | |
342 | 69b91039 | bellard | static void pci_data_write(void *opaque, uint32_t addr, |
343 | 69b91039 | bellard | uint32_t val, int len)
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344 | 69b91039 | bellard | { |
345 | 30468f78 | bellard | PCIBus *s = opaque; |
346 | 30468f78 | bellard | PCIDevice *pci_dev; |
347 | 30468f78 | bellard | int config_addr, bus_num;
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348 | 69b91039 | bellard | |
349 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
350 | 69b91039 | bellard | printf("pci_data_write: addr=%08x val=%08x len=%d\n",
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351 | 69b91039 | bellard | s->config_reg, val, len); |
352 | 69b91039 | bellard | #endif
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353 | 69b91039 | bellard | if (!(s->config_reg & (1 << 31))) { |
354 | 69b91039 | bellard | return;
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355 | 69b91039 | bellard | } |
356 | 30468f78 | bellard | bus_num = (s->config_reg >> 16) & 0xff; |
357 | 30468f78 | bellard | if (bus_num != 0) |
358 | 69b91039 | bellard | return;
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359 | 30468f78 | bellard | pci_dev = s->devices[(s->config_reg >> 8) & 0xff]; |
360 | 69b91039 | bellard | if (!pci_dev)
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361 | 69b91039 | bellard | return;
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362 | 69b91039 | bellard | config_addr = (s->config_reg & 0xfc) | (addr & 3); |
363 | 69b91039 | bellard | #if defined(DEBUG_PCI)
|
364 | 69b91039 | bellard | printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
365 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
366 | 69b91039 | bellard | #endif
|
367 | 0ac32c83 | bellard | pci_dev->config_write(pci_dev, config_addr, val, len); |
368 | 69b91039 | bellard | } |
369 | 69b91039 | bellard | |
370 | 69b91039 | bellard | static uint32_t pci_data_read(void *opaque, uint32_t addr, |
371 | 69b91039 | bellard | int len)
|
372 | 69b91039 | bellard | { |
373 | 30468f78 | bellard | PCIBus *s = opaque; |
374 | 30468f78 | bellard | PCIDevice *pci_dev; |
375 | 30468f78 | bellard | int config_addr, bus_num;
|
376 | 69b91039 | bellard | uint32_t val; |
377 | 69b91039 | bellard | |
378 | 69b91039 | bellard | if (!(s->config_reg & (1 << 31))) |
379 | 69b91039 | bellard | goto fail;
|
380 | 30468f78 | bellard | bus_num = (s->config_reg >> 16) & 0xff; |
381 | 30468f78 | bellard | if (bus_num != 0) |
382 | 69b91039 | bellard | goto fail;
|
383 | 30468f78 | bellard | pci_dev = s->devices[(s->config_reg >> 8) & 0xff]; |
384 | 69b91039 | bellard | if (!pci_dev) {
|
385 | 69b91039 | bellard | fail:
|
386 | 63ce9e0a | bellard | switch(len) {
|
387 | 63ce9e0a | bellard | case 1: |
388 | 63ce9e0a | bellard | val = 0xff;
|
389 | 63ce9e0a | bellard | break;
|
390 | 63ce9e0a | bellard | case 2: |
391 | 63ce9e0a | bellard | val = 0xffff;
|
392 | 63ce9e0a | bellard | break;
|
393 | 63ce9e0a | bellard | default:
|
394 | 63ce9e0a | bellard | case 4: |
395 | 63ce9e0a | bellard | val = 0xffffffff;
|
396 | 63ce9e0a | bellard | break;
|
397 | 63ce9e0a | bellard | } |
398 | 69b91039 | bellard | goto the_end;
|
399 | 69b91039 | bellard | } |
400 | 69b91039 | bellard | config_addr = (s->config_reg & 0xfc) | (addr & 3); |
401 | 69b91039 | bellard | val = pci_dev->config_read(pci_dev, config_addr, len); |
402 | 69b91039 | bellard | #if defined(DEBUG_PCI)
|
403 | 69b91039 | bellard | printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
404 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
405 | 69b91039 | bellard | #endif
|
406 | 69b91039 | bellard | the_end:
|
407 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
408 | 69b91039 | bellard | printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
409 | 69b91039 | bellard | s->config_reg, val, len); |
410 | 69b91039 | bellard | #endif
|
411 | 69b91039 | bellard | return val;
|
412 | 69b91039 | bellard | } |
413 | 69b91039 | bellard | |
414 | 69b91039 | bellard | static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val) |
415 | 69b91039 | bellard | { |
416 | 69b91039 | bellard | pci_data_write(opaque, addr, val, 1);
|
417 | 69b91039 | bellard | } |
418 | 69b91039 | bellard | |
419 | 69b91039 | bellard | static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val) |
420 | 69b91039 | bellard | { |
421 | 69b91039 | bellard | pci_data_write(opaque, addr, val, 2);
|
422 | 69b91039 | bellard | } |
423 | 69b91039 | bellard | |
424 | 69b91039 | bellard | static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val) |
425 | 69b91039 | bellard | { |
426 | 69b91039 | bellard | pci_data_write(opaque, addr, val, 4);
|
427 | 69b91039 | bellard | } |
428 | 69b91039 | bellard | |
429 | 69b91039 | bellard | static uint32_t pci_data_readb(void* opaque, uint32_t addr) |
430 | 69b91039 | bellard | { |
431 | 69b91039 | bellard | return pci_data_read(opaque, addr, 1); |
432 | 69b91039 | bellard | } |
433 | 69b91039 | bellard | |
434 | 69b91039 | bellard | static uint32_t pci_data_readw(void* opaque, uint32_t addr) |
435 | 69b91039 | bellard | { |
436 | 69b91039 | bellard | return pci_data_read(opaque, addr, 2); |
437 | 69b91039 | bellard | } |
438 | 69b91039 | bellard | |
439 | 69b91039 | bellard | static uint32_t pci_data_readl(void* opaque, uint32_t addr) |
440 | 69b91039 | bellard | { |
441 | 69b91039 | bellard | return pci_data_read(opaque, addr, 4); |
442 | 69b91039 | bellard | } |
443 | 69b91039 | bellard | |
444 | 69b91039 | bellard | /* i440FX PCI bridge */
|
445 | 69b91039 | bellard | |
446 | 30468f78 | bellard | static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level); |
447 | 30468f78 | bellard | |
448 | 30468f78 | bellard | PCIBus *i440fx_init(void)
|
449 | 69b91039 | bellard | { |
450 | 30468f78 | bellard | PCIBus *s; |
451 | 69b91039 | bellard | PCIDevice *d; |
452 | 69b91039 | bellard | |
453 | 30468f78 | bellard | s = pci_register_bus(); |
454 | 30468f78 | bellard | s->set_irq = piix3_set_irq; |
455 | 30468f78 | bellard | |
456 | 0ac32c83 | bellard | register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
457 | 0ac32c83 | bellard | register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
458 | 69b91039 | bellard | |
459 | 69b91039 | bellard | register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
460 | 69b91039 | bellard | register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
461 | 69b91039 | bellard | register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
462 | 69b91039 | bellard | register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
463 | 69b91039 | bellard | register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
464 | 69b91039 | bellard | register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
465 | 69b91039 | bellard | |
466 | 30468f78 | bellard | d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0, |
467 | 0ac32c83 | bellard | NULL, NULL); |
468 | 69b91039 | bellard | |
469 | 69b91039 | bellard | d->config[0x00] = 0x86; // vendor_id |
470 | 69b91039 | bellard | d->config[0x01] = 0x80; |
471 | 69b91039 | bellard | d->config[0x02] = 0x37; // device_id |
472 | 69b91039 | bellard | d->config[0x03] = 0x12; |
473 | 69b91039 | bellard | d->config[0x08] = 0x02; // revision |
474 | 358c6407 | bellard | d->config[0x0a] = 0x00; // class_sub = host2pci |
475 | 69b91039 | bellard | d->config[0x0b] = 0x06; // class_base = PCI_bridge |
476 | 358c6407 | bellard | d->config[0x0e] = 0x00; // header_type |
477 | 30468f78 | bellard | return s;
|
478 | 69b91039 | bellard | } |
479 | 69b91039 | bellard | |
480 | 0ac32c83 | bellard | /* PIIX3 PCI to ISA bridge */
|
481 | 0ac32c83 | bellard | |
482 | 0ac32c83 | bellard | typedef struct PIIX3State { |
483 | 0ac32c83 | bellard | PCIDevice dev; |
484 | 0ac32c83 | bellard | } PIIX3State; |
485 | 0ac32c83 | bellard | |
486 | 0ac32c83 | bellard | PIIX3State *piix3_state; |
487 | 0ac32c83 | bellard | |
488 | 30468f78 | bellard | /* return the global irq number corresponding to a given device irq
|
489 | 30468f78 | bellard | pin. We could also use the bus number to have a more precise
|
490 | 30468f78 | bellard | mapping. */
|
491 | 30468f78 | bellard | static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
492 | 30468f78 | bellard | { |
493 | 30468f78 | bellard | int slot_addend;
|
494 | 39d22439 | bellard | slot_addend = (pci_dev->devfn >> 3) - 1; |
495 | 30468f78 | bellard | return (irq_num + slot_addend) & 3; |
496 | 30468f78 | bellard | } |
497 | 30468f78 | bellard | |
498 | 72cc6cfe | bellard | static inline int get_pci_irq_level(int irq_num) |
499 | 72cc6cfe | bellard | { |
500 | 72cc6cfe | bellard | int pic_level;
|
501 | 72cc6cfe | bellard | #if (PCI_IRQ_WORDS == 2) |
502 | 72cc6cfe | bellard | pic_level = ((pci_irq_levels[irq_num][0] |
|
503 | 72cc6cfe | bellard | pci_irq_levels[irq_num][1]) != 0); |
504 | 72cc6cfe | bellard | #else
|
505 | 72cc6cfe | bellard | { |
506 | 72cc6cfe | bellard | int i;
|
507 | 72cc6cfe | bellard | pic_level = 0;
|
508 | 72cc6cfe | bellard | for(i = 0; i < PCI_IRQ_WORDS; i++) { |
509 | 72cc6cfe | bellard | if (pci_irq_levels[irq_num][i]) {
|
510 | 72cc6cfe | bellard | pic_level = 1;
|
511 | 72cc6cfe | bellard | break;
|
512 | 72cc6cfe | bellard | } |
513 | 72cc6cfe | bellard | } |
514 | 72cc6cfe | bellard | } |
515 | 72cc6cfe | bellard | #endif
|
516 | 72cc6cfe | bellard | return pic_level;
|
517 | 72cc6cfe | bellard | } |
518 | 72cc6cfe | bellard | |
519 | 30468f78 | bellard | static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
520 | 30468f78 | bellard | { |
521 | 30468f78 | bellard | int irq_index, shift, pic_irq, pic_level;
|
522 | 30468f78 | bellard | uint32_t *p; |
523 | 30468f78 | bellard | |
524 | 30468f78 | bellard | irq_num = pci_slot_get_pirq(pci_dev, irq_num); |
525 | 30468f78 | bellard | irq_index = pci_dev->irq_index; |
526 | 30468f78 | bellard | p = &pci_irq_levels[irq_num][irq_index >> 5];
|
527 | 30468f78 | bellard | shift = (irq_index & 0x1f);
|
528 | 30468f78 | bellard | *p = (*p & ~(1 << shift)) | (level << shift);
|
529 | 30468f78 | bellard | |
530 | 30468f78 | bellard | /* now we change the pic irq level according to the piix irq mappings */
|
531 | 72cc6cfe | bellard | /* XXX: optimize */
|
532 | 30468f78 | bellard | pic_irq = piix3_state->dev.config[0x60 + irq_num];
|
533 | 30468f78 | bellard | if (pic_irq < 16) { |
534 | 30468f78 | bellard | /* the pic level is the logical OR of all the PCI irqs mapped
|
535 | 30468f78 | bellard | to it */
|
536 | 30468f78 | bellard | pic_level = 0;
|
537 | 72cc6cfe | bellard | if (pic_irq == piix3_state->dev.config[0x60]) |
538 | 72cc6cfe | bellard | pic_level |= get_pci_irq_level(0);
|
539 | 72cc6cfe | bellard | if (pic_irq == piix3_state->dev.config[0x61]) |
540 | 72cc6cfe | bellard | pic_level |= get_pci_irq_level(1);
|
541 | 72cc6cfe | bellard | if (pic_irq == piix3_state->dev.config[0x62]) |
542 | 72cc6cfe | bellard | pic_level |= get_pci_irq_level(2);
|
543 | 72cc6cfe | bellard | if (pic_irq == piix3_state->dev.config[0x63]) |
544 | 72cc6cfe | bellard | pic_level |= get_pci_irq_level(3);
|
545 | 30468f78 | bellard | pic_set_irq(pic_irq, pic_level); |
546 | 30468f78 | bellard | } |
547 | 30468f78 | bellard | } |
548 | 30468f78 | bellard | |
549 | 0ac32c83 | bellard | static void piix3_reset(PIIX3State *d) |
550 | 0ac32c83 | bellard | { |
551 | 0ac32c83 | bellard | uint8_t *pci_conf = d->dev.config; |
552 | 0ac32c83 | bellard | |
553 | 0ac32c83 | bellard | pci_conf[0x04] = 0x07; // master, memory and I/O |
554 | 0ac32c83 | bellard | pci_conf[0x05] = 0x00; |
555 | 0ac32c83 | bellard | pci_conf[0x06] = 0x00; |
556 | 0ac32c83 | bellard | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
557 | 0ac32c83 | bellard | pci_conf[0x4c] = 0x4d; |
558 | 0ac32c83 | bellard | pci_conf[0x4e] = 0x03; |
559 | 0ac32c83 | bellard | pci_conf[0x4f] = 0x00; |
560 | 0ac32c83 | bellard | pci_conf[0x60] = 0x80; |
561 | 0ac32c83 | bellard | pci_conf[0x69] = 0x02; |
562 | 0ac32c83 | bellard | pci_conf[0x70] = 0x80; |
563 | 0ac32c83 | bellard | pci_conf[0x76] = 0x0c; |
564 | 0ac32c83 | bellard | pci_conf[0x77] = 0x0c; |
565 | 0ac32c83 | bellard | pci_conf[0x78] = 0x02; |
566 | 0ac32c83 | bellard | pci_conf[0x79] = 0x00; |
567 | 0ac32c83 | bellard | pci_conf[0x80] = 0x00; |
568 | 0ac32c83 | bellard | pci_conf[0x82] = 0x00; |
569 | 0ac32c83 | bellard | pci_conf[0xa0] = 0x08; |
570 | 0ac32c83 | bellard | pci_conf[0xa0] = 0x08; |
571 | 0ac32c83 | bellard | pci_conf[0xa2] = 0x00; |
572 | 0ac32c83 | bellard | pci_conf[0xa3] = 0x00; |
573 | 0ac32c83 | bellard | pci_conf[0xa4] = 0x00; |
574 | 0ac32c83 | bellard | pci_conf[0xa5] = 0x00; |
575 | 0ac32c83 | bellard | pci_conf[0xa6] = 0x00; |
576 | 0ac32c83 | bellard | pci_conf[0xa7] = 0x00; |
577 | 0ac32c83 | bellard | pci_conf[0xa8] = 0x0f; |
578 | 0ac32c83 | bellard | pci_conf[0xaa] = 0x00; |
579 | 0ac32c83 | bellard | pci_conf[0xab] = 0x00; |
580 | 0ac32c83 | bellard | pci_conf[0xac] = 0x00; |
581 | 0ac32c83 | bellard | pci_conf[0xae] = 0x00; |
582 | 0ac32c83 | bellard | } |
583 | 0ac32c83 | bellard | |
584 | 30468f78 | bellard | void piix3_init(PCIBus *bus)
|
585 | 0ac32c83 | bellard | { |
586 | 0ac32c83 | bellard | PIIX3State *d; |
587 | 0ac32c83 | bellard | uint8_t *pci_conf; |
588 | 0ac32c83 | bellard | |
589 | 30468f78 | bellard | d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State), |
590 | 30468f78 | bellard | -1, NULL, NULL); |
591 | 30ca2aab | bellard | register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d); |
592 | 30ca2aab | bellard | |
593 | 0ac32c83 | bellard | piix3_state = d; |
594 | 0ac32c83 | bellard | pci_conf = d->dev.config; |
595 | 0ac32c83 | bellard | |
596 | 0ac32c83 | bellard | pci_conf[0x00] = 0x86; // Intel |
597 | 0ac32c83 | bellard | pci_conf[0x01] = 0x80; |
598 | 0ac32c83 | bellard | pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
599 | 0ac32c83 | bellard | pci_conf[0x03] = 0x70; |
600 | 0ac32c83 | bellard | pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
601 | 0ac32c83 | bellard | pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
602 | 0ac32c83 | bellard | pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
603 | 0ac32c83 | bellard | |
604 | 0ac32c83 | bellard | piix3_reset(d); |
605 | 0ac32c83 | bellard | } |
606 | 0ac32c83 | bellard | |
607 | 77d4bc34 | bellard | /* PREP pci init */
|
608 | 77d4bc34 | bellard | |
609 | 30468f78 | bellard | static inline void set_config(PCIBus *s, target_phys_addr_t addr) |
610 | 77d4bc34 | bellard | { |
611 | 77d4bc34 | bellard | int devfn, i;
|
612 | 77d4bc34 | bellard | |
613 | 77d4bc34 | bellard | for(i = 0; i < 11; i++) { |
614 | 77d4bc34 | bellard | if ((addr & (1 << (11 + i))) != 0) |
615 | 77d4bc34 | bellard | break;
|
616 | 77d4bc34 | bellard | } |
617 | 77d4bc34 | bellard | devfn = ((addr >> 8) & 7) | (i << 3); |
618 | 77d4bc34 | bellard | s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8); |
619 | 77d4bc34 | bellard | } |
620 | 77d4bc34 | bellard | |
621 | 8a8696a3 | bellard | static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
622 | 77d4bc34 | bellard | { |
623 | 30468f78 | bellard | PCIBus *s = opaque; |
624 | 77d4bc34 | bellard | set_config(s, addr); |
625 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 1);
|
626 | 77d4bc34 | bellard | } |
627 | 77d4bc34 | bellard | |
628 | 8a8696a3 | bellard | static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
629 | 77d4bc34 | bellard | { |
630 | 30468f78 | bellard | PCIBus *s = opaque; |
631 | 77d4bc34 | bellard | set_config(s, addr); |
632 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
633 | 77d4bc34 | bellard | val = bswap16(val); |
634 | 77d4bc34 | bellard | #endif
|
635 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 2);
|
636 | 77d4bc34 | bellard | } |
637 | 77d4bc34 | bellard | |
638 | 8a8696a3 | bellard | static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
639 | 77d4bc34 | bellard | { |
640 | 30468f78 | bellard | PCIBus *s = opaque; |
641 | 77d4bc34 | bellard | set_config(s, addr); |
642 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
643 | 77d4bc34 | bellard | val = bswap32(val); |
644 | 77d4bc34 | bellard | #endif
|
645 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 4);
|
646 | 77d4bc34 | bellard | } |
647 | 77d4bc34 | bellard | |
648 | 8a8696a3 | bellard | static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) |
649 | 77d4bc34 | bellard | { |
650 | 30468f78 | bellard | PCIBus *s = opaque; |
651 | 77d4bc34 | bellard | uint32_t val; |
652 | 77d4bc34 | bellard | set_config(s, addr); |
653 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 1);
|
654 | 77d4bc34 | bellard | return val;
|
655 | 77d4bc34 | bellard | } |
656 | 77d4bc34 | bellard | |
657 | 8a8696a3 | bellard | static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) |
658 | 77d4bc34 | bellard | { |
659 | 30468f78 | bellard | PCIBus *s = opaque; |
660 | 77d4bc34 | bellard | uint32_t val; |
661 | 77d4bc34 | bellard | set_config(s, addr); |
662 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 2);
|
663 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
664 | 77d4bc34 | bellard | val = bswap16(val); |
665 | 77d4bc34 | bellard | #endif
|
666 | 77d4bc34 | bellard | return val;
|
667 | 77d4bc34 | bellard | } |
668 | 77d4bc34 | bellard | |
669 | 8a8696a3 | bellard | static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) |
670 | 77d4bc34 | bellard | { |
671 | 30468f78 | bellard | PCIBus *s = opaque; |
672 | 77d4bc34 | bellard | uint32_t val; |
673 | 77d4bc34 | bellard | set_config(s, addr); |
674 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 4);
|
675 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
676 | 77d4bc34 | bellard | val = bswap32(val); |
677 | 77d4bc34 | bellard | #endif
|
678 | 77d4bc34 | bellard | return val;
|
679 | 77d4bc34 | bellard | } |
680 | 77d4bc34 | bellard | |
681 | 77d4bc34 | bellard | static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
|
682 | 77d4bc34 | bellard | &PPC_PCIIO_writeb, |
683 | 77d4bc34 | bellard | &PPC_PCIIO_writew, |
684 | 77d4bc34 | bellard | &PPC_PCIIO_writel, |
685 | 77d4bc34 | bellard | }; |
686 | 77d4bc34 | bellard | |
687 | 77d4bc34 | bellard | static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
|
688 | 77d4bc34 | bellard | &PPC_PCIIO_readb, |
689 | 77d4bc34 | bellard | &PPC_PCIIO_readw, |
690 | 77d4bc34 | bellard | &PPC_PCIIO_readl, |
691 | 77d4bc34 | bellard | }; |
692 | 77d4bc34 | bellard | |
693 | 30468f78 | bellard | static void prep_set_irq(PCIDevice *d, int irq_num, int level) |
694 | 30468f78 | bellard | { |
695 | 30468f78 | bellard | /* XXX: we do not simulate the hardware - we rely on the BIOS to
|
696 | 30468f78 | bellard | set correctly for irq line field */
|
697 | 30468f78 | bellard | pic_set_irq(d->config[PCI_INTERRUPT_LINE], level); |
698 | 30468f78 | bellard | } |
699 | 30468f78 | bellard | |
700 | 30468f78 | bellard | PCIBus *pci_prep_init(void)
|
701 | 77d4bc34 | bellard | { |
702 | 30468f78 | bellard | PCIBus *s; |
703 | 77d4bc34 | bellard | PCIDevice *d; |
704 | 77d4bc34 | bellard | int PPC_io_memory;
|
705 | 77d4bc34 | bellard | |
706 | 30468f78 | bellard | s = pci_register_bus(); |
707 | 30468f78 | bellard | s->set_irq = prep_set_irq; |
708 | 30468f78 | bellard | |
709 | da9b266b | bellard | register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
710 | da9b266b | bellard | register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
711 | da9b266b | bellard | |
712 | da9b266b | bellard | register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
713 | da9b266b | bellard | register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
714 | da9b266b | bellard | register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
715 | da9b266b | bellard | register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
716 | da9b266b | bellard | register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
717 | da9b266b | bellard | register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
718 | da9b266b | bellard | |
719 | 8a8696a3 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
|
720 | 8a8696a3 | bellard | PPC_PCIIO_write, s); |
721 | 77d4bc34 | bellard | cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); |
722 | 77d4bc34 | bellard | |
723 | 384d8876 | bellard | /* PCI host bridge */
|
724 | 384d8876 | bellard | d = pci_register_device(s, "PREP Host Bridge - Motorola Raven",
|
725 | 384d8876 | bellard | sizeof(PCIDevice), 0, NULL, NULL); |
726 | 384d8876 | bellard | d->config[0x00] = 0x57; // vendor_id : Motorola |
727 | 77d4bc34 | bellard | d->config[0x01] = 0x10; |
728 | 384d8876 | bellard | d->config[0x02] = 0x01; // device_id : Raven |
729 | 384d8876 | bellard | d->config[0x03] = 0x48; |
730 | 384d8876 | bellard | d->config[0x08] = 0x00; // revision |
731 | 384d8876 | bellard | d->config[0x0A] = 0x00; // class_sub = pci host |
732 | 384d8876 | bellard | d->config[0x0B] = 0x06; // class_base = PCI_bridge |
733 | 384d8876 | bellard | d->config[0x0C] = 0x08; // cache_line_size |
734 | 384d8876 | bellard | d->config[0x0D] = 0x10; // latency_timer |
735 | 384d8876 | bellard | d->config[0x0E] = 0x00; // header_type |
736 | 384d8876 | bellard | d->config[0x34] = 0x00; // capabilities_pointer |
737 | 384d8876 | bellard | |
738 | 30468f78 | bellard | return s;
|
739 | 77d4bc34 | bellard | } |
740 | 77d4bc34 | bellard | |
741 | 77d4bc34 | bellard | |
742 | f2aa58c6 | bellard | /* Grackle PCI host */
|
743 | f2aa58c6 | bellard | static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, |
744 | f2aa58c6 | bellard | uint32_t val) |
745 | 77d4bc34 | bellard | { |
746 | 30468f78 | bellard | PCIBus *s = opaque; |
747 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
748 | 77d4bc34 | bellard | val = bswap32(val); |
749 | 77d4bc34 | bellard | #endif
|
750 | 77d4bc34 | bellard | s->config_reg = val; |
751 | 77d4bc34 | bellard | } |
752 | 77d4bc34 | bellard | |
753 | f2aa58c6 | bellard | static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) |
754 | 77d4bc34 | bellard | { |
755 | 30468f78 | bellard | PCIBus *s = opaque; |
756 | 77d4bc34 | bellard | uint32_t val; |
757 | 77d4bc34 | bellard | |
758 | 77d4bc34 | bellard | val = s->config_reg; |
759 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
760 | 77d4bc34 | bellard | val = bswap32(val); |
761 | 77d4bc34 | bellard | #endif
|
762 | 77d4bc34 | bellard | return val;
|
763 | 77d4bc34 | bellard | } |
764 | 77d4bc34 | bellard | |
765 | f2aa58c6 | bellard | static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
|
766 | f2aa58c6 | bellard | &pci_grackle_config_writel, |
767 | f2aa58c6 | bellard | &pci_grackle_config_writel, |
768 | f2aa58c6 | bellard | &pci_grackle_config_writel, |
769 | 77d4bc34 | bellard | }; |
770 | 77d4bc34 | bellard | |
771 | f2aa58c6 | bellard | static CPUReadMemoryFunc *pci_grackle_config_read[] = {
|
772 | f2aa58c6 | bellard | &pci_grackle_config_readl, |
773 | f2aa58c6 | bellard | &pci_grackle_config_readl, |
774 | f2aa58c6 | bellard | &pci_grackle_config_readl, |
775 | 77d4bc34 | bellard | }; |
776 | 77d4bc34 | bellard | |
777 | f2aa58c6 | bellard | static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr, |
778 | f2aa58c6 | bellard | uint32_t val) |
779 | 77d4bc34 | bellard | { |
780 | 30468f78 | bellard | PCIBus *s = opaque; |
781 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 1);
|
782 | 77d4bc34 | bellard | } |
783 | 77d4bc34 | bellard | |
784 | f2aa58c6 | bellard | static void pci_grackle_writew (void *opaque, target_phys_addr_t addr, |
785 | f2aa58c6 | bellard | uint32_t val) |
786 | 77d4bc34 | bellard | { |
787 | 30468f78 | bellard | PCIBus *s = opaque; |
788 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
789 | 77d4bc34 | bellard | val = bswap16(val); |
790 | 77d4bc34 | bellard | #endif
|
791 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 2);
|
792 | 77d4bc34 | bellard | } |
793 | 77d4bc34 | bellard | |
794 | f2aa58c6 | bellard | static void pci_grackle_writel (void *opaque, target_phys_addr_t addr, |
795 | f2aa58c6 | bellard | uint32_t val) |
796 | 77d4bc34 | bellard | { |
797 | 30468f78 | bellard | PCIBus *s = opaque; |
798 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
799 | 77d4bc34 | bellard | val = bswap32(val); |
800 | 77d4bc34 | bellard | #endif
|
801 | 77d4bc34 | bellard | pci_data_write(s, addr, val, 4);
|
802 | 77d4bc34 | bellard | } |
803 | 77d4bc34 | bellard | |
804 | f2aa58c6 | bellard | static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr) |
805 | 77d4bc34 | bellard | { |
806 | 30468f78 | bellard | PCIBus *s = opaque; |
807 | 77d4bc34 | bellard | uint32_t val; |
808 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 1);
|
809 | 77d4bc34 | bellard | return val;
|
810 | 77d4bc34 | bellard | } |
811 | 77d4bc34 | bellard | |
812 | f2aa58c6 | bellard | static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr) |
813 | 77d4bc34 | bellard | { |
814 | 30468f78 | bellard | PCIBus *s = opaque; |
815 | 77d4bc34 | bellard | uint32_t val; |
816 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 2);
|
817 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
818 | 77d4bc34 | bellard | val = bswap16(val); |
819 | 77d4bc34 | bellard | #endif
|
820 | 77d4bc34 | bellard | return val;
|
821 | 77d4bc34 | bellard | } |
822 | 77d4bc34 | bellard | |
823 | f2aa58c6 | bellard | static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr) |
824 | f2aa58c6 | bellard | { |
825 | 30468f78 | bellard | PCIBus *s = opaque; |
826 | f2aa58c6 | bellard | uint32_t val; |
827 | f2aa58c6 | bellard | |
828 | f2aa58c6 | bellard | val = pci_data_read(s, addr, 4);
|
829 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
830 | f2aa58c6 | bellard | val = bswap32(val); |
831 | f2aa58c6 | bellard | #endif
|
832 | f2aa58c6 | bellard | return val;
|
833 | f2aa58c6 | bellard | } |
834 | f2aa58c6 | bellard | |
835 | f2aa58c6 | bellard | static CPUWriteMemoryFunc *pci_grackle_write[] = {
|
836 | f2aa58c6 | bellard | &pci_grackle_writeb, |
837 | f2aa58c6 | bellard | &pci_grackle_writew, |
838 | f2aa58c6 | bellard | &pci_grackle_writel, |
839 | f2aa58c6 | bellard | }; |
840 | f2aa58c6 | bellard | |
841 | f2aa58c6 | bellard | static CPUReadMemoryFunc *pci_grackle_read[] = {
|
842 | f2aa58c6 | bellard | &pci_grackle_readb, |
843 | f2aa58c6 | bellard | &pci_grackle_readw, |
844 | f2aa58c6 | bellard | &pci_grackle_readl, |
845 | f2aa58c6 | bellard | }; |
846 | 384d8876 | bellard | |
847 | 384d8876 | bellard | void pci_set_pic(PCIBus *bus, SetIRQFunc *set_irq, void *irq_opaque) |
848 | 384d8876 | bellard | { |
849 | 384d8876 | bellard | bus->low_set_irq = set_irq; |
850 | 384d8876 | bellard | bus->irq_opaque = irq_opaque; |
851 | 384d8876 | bellard | } |
852 | 384d8876 | bellard | |
853 | 384d8876 | bellard | /* XXX: we do not simulate the hardware - we rely on the BIOS to
|
854 | 384d8876 | bellard | set correctly for irq line field */
|
855 | 384d8876 | bellard | static void pci_set_irq_simple(PCIDevice *d, int irq_num, int level) |
856 | 384d8876 | bellard | { |
857 | 384d8876 | bellard | PCIBus *s = d->bus; |
858 | 384d8876 | bellard | s->low_set_irq(s->irq_opaque, d->config[PCI_INTERRUPT_LINE], level); |
859 | 384d8876 | bellard | } |
860 | 384d8876 | bellard | |
861 | 384d8876 | bellard | PCIBus *pci_grackle_init(uint32_t base) |
862 | 384d8876 | bellard | { |
863 | 384d8876 | bellard | PCIBus *s; |
864 | 384d8876 | bellard | PCIDevice *d; |
865 | 384d8876 | bellard | int pci_mem_config, pci_mem_data;
|
866 | 384d8876 | bellard | |
867 | 384d8876 | bellard | s = pci_register_bus(); |
868 | 384d8876 | bellard | s->set_irq = pci_set_irq_simple; |
869 | 384d8876 | bellard | |
870 | 384d8876 | bellard | pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
|
871 | 384d8876 | bellard | pci_grackle_config_write, s); |
872 | 384d8876 | bellard | pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
|
873 | 384d8876 | bellard | pci_grackle_write, s); |
874 | 384d8876 | bellard | cpu_register_physical_memory(base, 0x1000, pci_mem_config);
|
875 | 384d8876 | bellard | cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data); |
876 | 384d8876 | bellard | d = pci_register_device(s, "Grackle host bridge", sizeof(PCIDevice), |
877 | 384d8876 | bellard | 0, NULL, NULL); |
878 | 384d8876 | bellard | d->config[0x00] = 0x57; // vendor_id |
879 | 384d8876 | bellard | d->config[0x01] = 0x10; |
880 | 384d8876 | bellard | d->config[0x02] = 0x02; // device_id |
881 | 384d8876 | bellard | d->config[0x03] = 0x00; |
882 | 384d8876 | bellard | d->config[0x08] = 0x00; // revision |
883 | 384d8876 | bellard | d->config[0x09] = 0x01; |
884 | 384d8876 | bellard | d->config[0x0a] = 0x00; // class_sub = host |
885 | 384d8876 | bellard | d->config[0x0b] = 0x06; // class_base = PCI_bridge |
886 | 384d8876 | bellard | d->config[0x0e] = 0x00; // header_type |
887 | 384d8876 | bellard | |
888 | 384d8876 | bellard | d->config[0x18] = 0x00; // primary_bus |
889 | 384d8876 | bellard | d->config[0x19] = 0x01; // secondary_bus |
890 | 384d8876 | bellard | d->config[0x1a] = 0x00; // subordinate_bus |
891 | 384d8876 | bellard | d->config[0x1c] = 0x00; |
892 | 384d8876 | bellard | d->config[0x1d] = 0x00; |
893 | 384d8876 | bellard | |
894 | 384d8876 | bellard | d->config[0x20] = 0x00; // memory_base |
895 | 384d8876 | bellard | d->config[0x21] = 0x00; |
896 | 384d8876 | bellard | d->config[0x22] = 0x01; // memory_limit |
897 | 384d8876 | bellard | d->config[0x23] = 0x00; |
898 | 384d8876 | bellard | |
899 | 384d8876 | bellard | d->config[0x24] = 0x00; // prefetchable_memory_base |
900 | 384d8876 | bellard | d->config[0x25] = 0x00; |
901 | 384d8876 | bellard | d->config[0x26] = 0x00; // prefetchable_memory_limit |
902 | 384d8876 | bellard | d->config[0x27] = 0x00; |
903 | 384d8876 | bellard | |
904 | 384d8876 | bellard | #if 0
|
905 | 384d8876 | bellard | /* PCI2PCI bridge same values as PearPC - check this */
|
906 | 384d8876 | bellard | d->config[0x00] = 0x11; // vendor_id
|
907 | 384d8876 | bellard | d->config[0x01] = 0x10;
|
908 | 384d8876 | bellard | d->config[0x02] = 0x26; // device_id
|
909 | 384d8876 | bellard | d->config[0x03] = 0x00;
|
910 | 384d8876 | bellard | d->config[0x08] = 0x02; // revision
|
911 | 384d8876 | bellard | d->config[0x0a] = 0x04; // class_sub = pci2pci
|
912 | 384d8876 | bellard | d->config[0x0b] = 0x06; // class_base = PCI_bridge
|
913 | 384d8876 | bellard | d->config[0x0e] = 0x01; // header_type
|
914 | 384d8876 | bellard | |
915 | 384d8876 | bellard | d->config[0x18] = 0x0; // primary_bus
|
916 | 384d8876 | bellard | d->config[0x19] = 0x1; // secondary_bus
|
917 | 384d8876 | bellard | d->config[0x1a] = 0x1; // subordinate_bus
|
918 | 384d8876 | bellard | d->config[0x1c] = 0x10; // io_base
|
919 | 384d8876 | bellard | d->config[0x1d] = 0x20; // io_limit
|
920 | 384d8876 | bellard |
|
921 | 384d8876 | bellard | d->config[0x20] = 0x80; // memory_base
|
922 | 384d8876 | bellard | d->config[0x21] = 0x80;
|
923 | 384d8876 | bellard | d->config[0x22] = 0x90; // memory_limit
|
924 | 384d8876 | bellard | d->config[0x23] = 0x80;
|
925 | 384d8876 | bellard |
|
926 | 384d8876 | bellard | d->config[0x24] = 0x00; // prefetchable_memory_base
|
927 | 384d8876 | bellard | d->config[0x25] = 0x84;
|
928 | 384d8876 | bellard | d->config[0x26] = 0x00; // prefetchable_memory_limit
|
929 | 384d8876 | bellard | d->config[0x27] = 0x85;
|
930 | 30468f78 | bellard | #endif
|
931 | 384d8876 | bellard | return s;
|
932 | 384d8876 | bellard | } |
933 | f2aa58c6 | bellard | |
934 | f2aa58c6 | bellard | /* Uninorth PCI host (for all Mac99 and newer machines */
|
935 | f2aa58c6 | bellard | static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
936 | f2aa58c6 | bellard | uint32_t val) |
937 | f2aa58c6 | bellard | { |
938 | 30468f78 | bellard | PCIBus *s = opaque; |
939 | f2aa58c6 | bellard | int i;
|
940 | f2aa58c6 | bellard | |
941 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
942 | f2aa58c6 | bellard | val = bswap32(val); |
943 | f2aa58c6 | bellard | #endif
|
944 | f2aa58c6 | bellard | |
945 | f2aa58c6 | bellard | for (i = 11; i < 32; i++) { |
946 | f2aa58c6 | bellard | if ((val & (1 << i)) != 0) |
947 | f2aa58c6 | bellard | break;
|
948 | f2aa58c6 | bellard | } |
949 | f2aa58c6 | bellard | #if 0
|
950 | f2aa58c6 | bellard | s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
|
951 | f2aa58c6 | bellard | #else
|
952 | f2aa58c6 | bellard | s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11); |
953 | f2aa58c6 | bellard | #endif
|
954 | f2aa58c6 | bellard | } |
955 | f2aa58c6 | bellard | |
956 | f2aa58c6 | bellard | static uint32_t pci_unin_main_config_readl (void *opaque, |
957 | f2aa58c6 | bellard | target_phys_addr_t addr) |
958 | f2aa58c6 | bellard | { |
959 | 30468f78 | bellard | PCIBus *s = opaque; |
960 | f2aa58c6 | bellard | uint32_t val; |
961 | f2aa58c6 | bellard | int devfn;
|
962 | f2aa58c6 | bellard | |
963 | f2aa58c6 | bellard | devfn = (s->config_reg >> 8) & 0xFF; |
964 | f2aa58c6 | bellard | val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); |
965 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
966 | f2aa58c6 | bellard | val = bswap32(val); |
967 | f2aa58c6 | bellard | #endif
|
968 | f2aa58c6 | bellard | |
969 | f2aa58c6 | bellard | return val;
|
970 | f2aa58c6 | bellard | } |
971 | f2aa58c6 | bellard | |
972 | f2aa58c6 | bellard | static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
|
973 | f2aa58c6 | bellard | &pci_unin_main_config_writel, |
974 | f2aa58c6 | bellard | &pci_unin_main_config_writel, |
975 | f2aa58c6 | bellard | &pci_unin_main_config_writel, |
976 | f2aa58c6 | bellard | }; |
977 | f2aa58c6 | bellard | |
978 | f2aa58c6 | bellard | static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
|
979 | f2aa58c6 | bellard | &pci_unin_main_config_readl, |
980 | f2aa58c6 | bellard | &pci_unin_main_config_readl, |
981 | f2aa58c6 | bellard | &pci_unin_main_config_readl, |
982 | f2aa58c6 | bellard | }; |
983 | f2aa58c6 | bellard | |
984 | f2aa58c6 | bellard | static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr, |
985 | f2aa58c6 | bellard | uint32_t val) |
986 | f2aa58c6 | bellard | { |
987 | 30468f78 | bellard | PCIBus *s = opaque; |
988 | f2aa58c6 | bellard | pci_data_write(s, addr & 7, val, 1); |
989 | f2aa58c6 | bellard | } |
990 | f2aa58c6 | bellard | |
991 | f2aa58c6 | bellard | static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr, |
992 | f2aa58c6 | bellard | uint32_t val) |
993 | f2aa58c6 | bellard | { |
994 | 30468f78 | bellard | PCIBus *s = opaque; |
995 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
996 | f2aa58c6 | bellard | val = bswap16(val); |
997 | f2aa58c6 | bellard | #endif
|
998 | f2aa58c6 | bellard | pci_data_write(s, addr & 7, val, 2); |
999 | f2aa58c6 | bellard | } |
1000 | f2aa58c6 | bellard | |
1001 | f2aa58c6 | bellard | static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr, |
1002 | f2aa58c6 | bellard | uint32_t val) |
1003 | f2aa58c6 | bellard | { |
1004 | 30468f78 | bellard | PCIBus *s = opaque; |
1005 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1006 | f2aa58c6 | bellard | val = bswap32(val); |
1007 | f2aa58c6 | bellard | #endif
|
1008 | f2aa58c6 | bellard | pci_data_write(s, addr & 7, val, 4); |
1009 | f2aa58c6 | bellard | } |
1010 | f2aa58c6 | bellard | |
1011 | f2aa58c6 | bellard | static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr) |
1012 | f2aa58c6 | bellard | { |
1013 | 30468f78 | bellard | PCIBus *s = opaque; |
1014 | f2aa58c6 | bellard | uint32_t val; |
1015 | f2aa58c6 | bellard | |
1016 | f2aa58c6 | bellard | val = pci_data_read(s, addr & 7, 1); |
1017 | f2aa58c6 | bellard | |
1018 | f2aa58c6 | bellard | return val;
|
1019 | f2aa58c6 | bellard | } |
1020 | f2aa58c6 | bellard | |
1021 | f2aa58c6 | bellard | static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr) |
1022 | f2aa58c6 | bellard | { |
1023 | 30468f78 | bellard | PCIBus *s = opaque; |
1024 | f2aa58c6 | bellard | uint32_t val; |
1025 | f2aa58c6 | bellard | |
1026 | f2aa58c6 | bellard | val = pci_data_read(s, addr & 7, 2); |
1027 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1028 | f2aa58c6 | bellard | val = bswap16(val); |
1029 | f2aa58c6 | bellard | #endif
|
1030 | f2aa58c6 | bellard | |
1031 | f2aa58c6 | bellard | return val;
|
1032 | f2aa58c6 | bellard | } |
1033 | f2aa58c6 | bellard | |
1034 | f2aa58c6 | bellard | static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr) |
1035 | 77d4bc34 | bellard | { |
1036 | 30468f78 | bellard | PCIBus *s = opaque; |
1037 | 77d4bc34 | bellard | uint32_t val; |
1038 | 77d4bc34 | bellard | |
1039 | 77d4bc34 | bellard | val = pci_data_read(s, addr, 4);
|
1040 | 77d4bc34 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1041 | 77d4bc34 | bellard | val = bswap32(val); |
1042 | 77d4bc34 | bellard | #endif
|
1043 | f2aa58c6 | bellard | |
1044 | f2aa58c6 | bellard | return val;
|
1045 | f2aa58c6 | bellard | } |
1046 | f2aa58c6 | bellard | |
1047 | f2aa58c6 | bellard | static CPUWriteMemoryFunc *pci_unin_main_write[] = {
|
1048 | f2aa58c6 | bellard | &pci_unin_main_writeb, |
1049 | f2aa58c6 | bellard | &pci_unin_main_writew, |
1050 | f2aa58c6 | bellard | &pci_unin_main_writel, |
1051 | f2aa58c6 | bellard | }; |
1052 | f2aa58c6 | bellard | |
1053 | f2aa58c6 | bellard | static CPUReadMemoryFunc *pci_unin_main_read[] = {
|
1054 | f2aa58c6 | bellard | &pci_unin_main_readb, |
1055 | f2aa58c6 | bellard | &pci_unin_main_readw, |
1056 | f2aa58c6 | bellard | &pci_unin_main_readl, |
1057 | f2aa58c6 | bellard | }; |
1058 | f2aa58c6 | bellard | |
1059 | 30468f78 | bellard | #if 0
|
1060 | 30468f78 | bellard | |
1061 | f2aa58c6 | bellard | static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
|
1062 | f2aa58c6 | bellard | uint32_t val)
|
1063 | f2aa58c6 | bellard | {
|
1064 | 30468f78 | bellard | PCIBus *s = opaque;
|
1065 | f2aa58c6 | bellard | |
1066 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1067 | f2aa58c6 | bellard | val = bswap32(val);
|
1068 | f2aa58c6 | bellard | #endif
|
1069 | f2aa58c6 | bellard | s->config_reg = 0x80000000 | (val & ~0x00000001); |
1070 | f2aa58c6 | bellard | } |
1071 | f2aa58c6 | bellard | |
1072 | f2aa58c6 | bellard | static uint32_t pci_unin_config_readl (void *opaque, |
1073 | f2aa58c6 | bellard | target_phys_addr_t addr) |
1074 | f2aa58c6 | bellard | { |
1075 | 30468f78 | bellard | PCIBus *s = opaque; |
1076 | f2aa58c6 | bellard | uint32_t val; |
1077 | f2aa58c6 | bellard | |
1078 | f2aa58c6 | bellard | val = (s->config_reg | 0x00000001) & ~0x80000000; |
1079 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1080 | f2aa58c6 | bellard | val = bswap32(val); |
1081 | f2aa58c6 | bellard | #endif
|
1082 | f2aa58c6 | bellard | |
1083 | f2aa58c6 | bellard | return val;
|
1084 | f2aa58c6 | bellard | } |
1085 | f2aa58c6 | bellard | |
1086 | f2aa58c6 | bellard | static CPUWriteMemoryFunc *pci_unin_config_write[] = {
|
1087 | f2aa58c6 | bellard | &pci_unin_config_writel, |
1088 | f2aa58c6 | bellard | &pci_unin_config_writel, |
1089 | f2aa58c6 | bellard | &pci_unin_config_writel, |
1090 | f2aa58c6 | bellard | }; |
1091 | f2aa58c6 | bellard | |
1092 | f2aa58c6 | bellard | static CPUReadMemoryFunc *pci_unin_config_read[] = {
|
1093 | f2aa58c6 | bellard | &pci_unin_config_readl, |
1094 | f2aa58c6 | bellard | &pci_unin_config_readl, |
1095 | f2aa58c6 | bellard | &pci_unin_config_readl, |
1096 | f2aa58c6 | bellard | }; |
1097 | f2aa58c6 | bellard | |
1098 | f2aa58c6 | bellard | static void pci_unin_writeb (void *opaque, target_phys_addr_t addr, |
1099 | f2aa58c6 | bellard | uint32_t val) |
1100 | f2aa58c6 | bellard | { |
1101 | 30468f78 | bellard | PCIBus *s = opaque; |
1102 | f2aa58c6 | bellard | pci_data_write(s, addr & 3, val, 1); |
1103 | f2aa58c6 | bellard | } |
1104 | f2aa58c6 | bellard | |
1105 | f2aa58c6 | bellard | static void pci_unin_writew (void *opaque, target_phys_addr_t addr, |
1106 | f2aa58c6 | bellard | uint32_t val) |
1107 | f2aa58c6 | bellard | { |
1108 | 30468f78 | bellard | PCIBus *s = opaque; |
1109 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1110 | f2aa58c6 | bellard | val = bswap16(val); |
1111 | f2aa58c6 | bellard | #endif
|
1112 | f2aa58c6 | bellard | pci_data_write(s, addr & 3, val, 2); |
1113 | f2aa58c6 | bellard | } |
1114 | f2aa58c6 | bellard | |
1115 | f2aa58c6 | bellard | static void pci_unin_writel (void *opaque, target_phys_addr_t addr, |
1116 | f2aa58c6 | bellard | uint32_t val) |
1117 | f2aa58c6 | bellard | { |
1118 | 30468f78 | bellard | PCIBus *s = opaque; |
1119 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1120 | f2aa58c6 | bellard | val = bswap32(val); |
1121 | f2aa58c6 | bellard | #endif
|
1122 | f2aa58c6 | bellard | pci_data_write(s, addr & 3, val, 4); |
1123 | f2aa58c6 | bellard | } |
1124 | f2aa58c6 | bellard | |
1125 | f2aa58c6 | bellard | static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr) |
1126 | f2aa58c6 | bellard | { |
1127 | 30468f78 | bellard | PCIBus *s = opaque; |
1128 | f2aa58c6 | bellard | uint32_t val; |
1129 | f2aa58c6 | bellard | |
1130 | f2aa58c6 | bellard | val = pci_data_read(s, addr & 3, 1); |
1131 | f2aa58c6 | bellard | |
1132 | f2aa58c6 | bellard | return val;
|
1133 | f2aa58c6 | bellard | } |
1134 | f2aa58c6 | bellard | |
1135 | f2aa58c6 | bellard | static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr) |
1136 | f2aa58c6 | bellard | { |
1137 | 30468f78 | bellard | PCIBus *s = opaque; |
1138 | f2aa58c6 | bellard | uint32_t val; |
1139 | f2aa58c6 | bellard | |
1140 | f2aa58c6 | bellard | val = pci_data_read(s, addr & 3, 2); |
1141 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1142 | f2aa58c6 | bellard | val = bswap16(val); |
1143 | f2aa58c6 | bellard | #endif
|
1144 | f2aa58c6 | bellard | |
1145 | f2aa58c6 | bellard | return val;
|
1146 | f2aa58c6 | bellard | } |
1147 | f2aa58c6 | bellard | |
1148 | f2aa58c6 | bellard | static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr) |
1149 | f2aa58c6 | bellard | { |
1150 | 30468f78 | bellard | PCIBus *s = opaque; |
1151 | f2aa58c6 | bellard | uint32_t val; |
1152 | f2aa58c6 | bellard | |
1153 | f2aa58c6 | bellard | val = pci_data_read(s, addr & 3, 4); |
1154 | f2aa58c6 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
1155 | f2aa58c6 | bellard | val = bswap32(val); |
1156 | f2aa58c6 | bellard | #endif
|
1157 | f2aa58c6 | bellard | |
1158 | 77d4bc34 | bellard | return val;
|
1159 | 77d4bc34 | bellard | } |
1160 | 77d4bc34 | bellard | |
1161 | f2aa58c6 | bellard | static CPUWriteMemoryFunc *pci_unin_write[] = {
|
1162 | f2aa58c6 | bellard | &pci_unin_writeb, |
1163 | f2aa58c6 | bellard | &pci_unin_writew, |
1164 | f2aa58c6 | bellard | &pci_unin_writel, |
1165 | 77d4bc34 | bellard | }; |
1166 | 77d4bc34 | bellard | |
1167 | f2aa58c6 | bellard | static CPUReadMemoryFunc *pci_unin_read[] = {
|
1168 | f2aa58c6 | bellard | &pci_unin_readb, |
1169 | f2aa58c6 | bellard | &pci_unin_readw, |
1170 | f2aa58c6 | bellard | &pci_unin_readl, |
1171 | 77d4bc34 | bellard | }; |
1172 | 30468f78 | bellard | #endif
|
1173 | 30468f78 | bellard | |
1174 | 30468f78 | bellard | PCIBus *pci_pmac_init(void)
|
1175 | 77d4bc34 | bellard | { |
1176 | 30468f78 | bellard | PCIBus *s; |
1177 | 77d4bc34 | bellard | PCIDevice *d; |
1178 | 77d4bc34 | bellard | int pci_mem_config, pci_mem_data;
|
1179 | 77d4bc34 | bellard | |
1180 | f2aa58c6 | bellard | /* Use values found on a real PowerMac */
|
1181 | f2aa58c6 | bellard | /* Uninorth main bus */
|
1182 | 30468f78 | bellard | s = pci_register_bus(); |
1183 | 384d8876 | bellard | s->set_irq = pci_set_irq_simple; |
1184 | 30468f78 | bellard | |
1185 | f2aa58c6 | bellard | pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
|
1186 | f2aa58c6 | bellard | pci_unin_main_config_write, s); |
1187 | f2aa58c6 | bellard | pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
|
1188 | f2aa58c6 | bellard | pci_unin_main_write, s); |
1189 | f2aa58c6 | bellard | cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config); |
1190 | f2aa58c6 | bellard | cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data); |
1191 | 30468f78 | bellard | s->devfn_min = 11 << 3; |
1192 | 30468f78 | bellard | d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice), |
1193 | 30468f78 | bellard | 11 << 3, NULL, NULL); |
1194 | f2aa58c6 | bellard | d->config[0x00] = 0x6b; // vendor_id : Apple |
1195 | f2aa58c6 | bellard | d->config[0x01] = 0x10; |
1196 | f2aa58c6 | bellard | d->config[0x02] = 0x1F; // device_id |
1197 | f2aa58c6 | bellard | d->config[0x03] = 0x00; |
1198 | f2aa58c6 | bellard | d->config[0x08] = 0x00; // revision |
1199 | f2aa58c6 | bellard | d->config[0x0A] = 0x00; // class_sub = pci host |
1200 | f2aa58c6 | bellard | d->config[0x0B] = 0x06; // class_base = PCI_bridge |
1201 | f2aa58c6 | bellard | d->config[0x0C] = 0x08; // cache_line_size |
1202 | f2aa58c6 | bellard | d->config[0x0D] = 0x10; // latency_timer |
1203 | f2aa58c6 | bellard | d->config[0x0E] = 0x00; // header_type |
1204 | f2aa58c6 | bellard | d->config[0x34] = 0x00; // capabilities_pointer |
1205 | f2aa58c6 | bellard | |
1206 | f2aa58c6 | bellard | #if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
|
1207 | f2aa58c6 | bellard | /* pci-to-pci bridge */
|
1208 | f2aa58c6 | bellard | d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
|
1209 | f2aa58c6 | bellard | NULL, NULL);
|
1210 | f2aa58c6 | bellard | d->config[0x00] = 0x11; // vendor_id : TI
|
1211 | f2aa58c6 | bellard | d->config[0x01] = 0x10;
|
1212 | f2aa58c6 | bellard | d->config[0x02] = 0x26; // device_id
|
1213 | f2aa58c6 | bellard | d->config[0x03] = 0x00;
|
1214 | f2aa58c6 | bellard | d->config[0x08] = 0x05; // revision
|
1215 | f2aa58c6 | bellard | d->config[0x0A] = 0x04; // class_sub = pci2pci
|
1216 | f2aa58c6 | bellard | d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1217 | f2aa58c6 | bellard | d->config[0x0C] = 0x08; // cache_line_size
|
1218 | f2aa58c6 | bellard | d->config[0x0D] = 0x20; // latency_timer
|
1219 | f2aa58c6 | bellard | d->config[0x0E] = 0x01; // header_type
|
1220 | f2aa58c6 | bellard | |
1221 | f2aa58c6 | bellard | d->config[0x18] = 0x01; // primary_bus
|
1222 | f2aa58c6 | bellard | d->config[0x19] = 0x02; // secondary_bus
|
1223 | f2aa58c6 | bellard | d->config[0x1A] = 0x02; // subordinate_bus
|
1224 | f2aa58c6 | bellard | d->config[0x1B] = 0x20; // secondary_latency_timer
|
1225 | f2aa58c6 | bellard | d->config[0x1C] = 0x11; // io_base
|
1226 | f2aa58c6 | bellard | d->config[0x1D] = 0x01; // io_limit
|
1227 | f2aa58c6 | bellard | d->config[0x20] = 0x00; // memory_base
|
1228 | f2aa58c6 | bellard | d->config[0x21] = 0x80;
|
1229 | f2aa58c6 | bellard | d->config[0x22] = 0x00; // memory_limit
|
1230 | f2aa58c6 | bellard | d->config[0x23] = 0x80;
|
1231 | f2aa58c6 | bellard | d->config[0x24] = 0x01; // prefetchable_memory_base
|
1232 | f2aa58c6 | bellard | d->config[0x25] = 0x80;
|
1233 | f2aa58c6 | bellard | d->config[0x26] = 0xF1; // prefectchable_memory_limit
|
1234 | f2aa58c6 | bellard | d->config[0x27] = 0x7F;
|
1235 | f2aa58c6 | bellard | // d->config[0x34] = 0xdc // capabilities_pointer
|
1236 | f2aa58c6 | bellard | #endif
|
1237 | f2aa58c6 | bellard | #if 0 // XXX: not needed for now
|
1238 | f2aa58c6 | bellard | /* Uninorth AGP bus */
|
1239 | f2aa58c6 | bellard | s = &pci_bridge[1];
|
1240 | f2aa58c6 | bellard | pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
|
1241 | f2aa58c6 | bellard | pci_unin_config_write, s);
|
1242 | f2aa58c6 | bellard | pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
|
1243 | f2aa58c6 | bellard | pci_unin_write, s);
|
1244 | f2aa58c6 | bellard | cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
|
1245 | f2aa58c6 | bellard | cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
|
1246 | f2aa58c6 | bellard | |
1247 | f2aa58c6 | bellard | d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
|
1248 | f2aa58c6 | bellard | NULL, NULL);
|
1249 | f2aa58c6 | bellard | d->config[0x00] = 0x6b; // vendor_id : Apple
|
1250 | f2aa58c6 | bellard | d->config[0x01] = 0x10;
|
1251 | f2aa58c6 | bellard | d->config[0x02] = 0x20; // device_id
|
1252 | f2aa58c6 | bellard | d->config[0x03] = 0x00;
|
1253 | f2aa58c6 | bellard | d->config[0x08] = 0x00; // revision
|
1254 | f2aa58c6 | bellard | d->config[0x0A] = 0x00; // class_sub = pci host
|
1255 | f2aa58c6 | bellard | d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1256 | f2aa58c6 | bellard | d->config[0x0C] = 0x08; // cache_line_size
|
1257 | f2aa58c6 | bellard | d->config[0x0D] = 0x10; // latency_timer
|
1258 | f2aa58c6 | bellard | d->config[0x0E] = 0x00; // header_type
|
1259 | f2aa58c6 | bellard | // d->config[0x34] = 0x80; // capabilities_pointer
|
1260 | f2aa58c6 | bellard | #endif
|
1261 | 77d4bc34 | bellard | |
1262 | f2aa58c6 | bellard | #if 0 // XXX: not needed for now
|
1263 | f2aa58c6 | bellard | /* Uninorth internal bus */
|
1264 | f2aa58c6 | bellard | s = &pci_bridge[2];
|
1265 | f2aa58c6 | bellard | pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
|
1266 | f2aa58c6 | bellard | pci_unin_config_write, s);
|
1267 | f2aa58c6 | bellard | pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
|
1268 | f2aa58c6 | bellard | pci_unin_write, s);
|
1269 | f2aa58c6 | bellard | cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
|
1270 | f2aa58c6 | bellard | cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
|
1271 | f2aa58c6 | bellard | |
1272 | f2aa58c6 | bellard | d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
|
1273 | f2aa58c6 | bellard | 3, 11 << 3, NULL, NULL);
|
1274 | f2aa58c6 | bellard | d->config[0x00] = 0x6b; // vendor_id : Apple
|
1275 | f2aa58c6 | bellard | d->config[0x01] = 0x10;
|
1276 | f2aa58c6 | bellard | d->config[0x02] = 0x1E; // device_id
|
1277 | f2aa58c6 | bellard | d->config[0x03] = 0x00;
|
1278 | f2aa58c6 | bellard | d->config[0x08] = 0x00; // revision
|
1279 | f2aa58c6 | bellard | d->config[0x0A] = 0x00; // class_sub = pci host
|
1280 | f2aa58c6 | bellard | d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1281 | f2aa58c6 | bellard | d->config[0x0C] = 0x08; // cache_line_size
|
1282 | f2aa58c6 | bellard | d->config[0x0D] = 0x10; // latency_timer
|
1283 | f2aa58c6 | bellard | d->config[0x0E] = 0x00; // header_type
|
1284 | f2aa58c6 | bellard | d->config[0x34] = 0x00; // capabilities_pointer
|
1285 | f2aa58c6 | bellard | #endif
|
1286 | 30468f78 | bellard | return s;
|
1287 | 77d4bc34 | bellard | } |
1288 | 77d4bc34 | bellard | |
1289 | 83469015 | bellard | /* Ultrasparc APB PCI host */
|
1290 | 83469015 | bellard | static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr, |
1291 | 83469015 | bellard | uint32_t val) |
1292 | 83469015 | bellard | { |
1293 | 83469015 | bellard | PCIBus *s = opaque; |
1294 | 83469015 | bellard | int i;
|
1295 | 83469015 | bellard | |
1296 | 83469015 | bellard | for (i = 11; i < 32; i++) { |
1297 | 83469015 | bellard | if ((val & (1 << i)) != 0) |
1298 | 83469015 | bellard | break;
|
1299 | 83469015 | bellard | } |
1300 | 83469015 | bellard | s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11); |
1301 | 83469015 | bellard | } |
1302 | 83469015 | bellard | |
1303 | 83469015 | bellard | static uint32_t pci_apb_config_readl (void *opaque, |
1304 | 83469015 | bellard | target_phys_addr_t addr) |
1305 | 83469015 | bellard | { |
1306 | 83469015 | bellard | PCIBus *s = opaque; |
1307 | 83469015 | bellard | uint32_t val; |
1308 | 83469015 | bellard | int devfn;
|
1309 | 83469015 | bellard | |
1310 | 83469015 | bellard | devfn = (s->config_reg >> 8) & 0xFF; |
1311 | 83469015 | bellard | val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); |
1312 | 83469015 | bellard | return val;
|
1313 | 83469015 | bellard | } |
1314 | 83469015 | bellard | |
1315 | 83469015 | bellard | static CPUWriteMemoryFunc *pci_apb_config_write[] = {
|
1316 | 83469015 | bellard | &pci_apb_config_writel, |
1317 | 83469015 | bellard | &pci_apb_config_writel, |
1318 | 83469015 | bellard | &pci_apb_config_writel, |
1319 | 83469015 | bellard | }; |
1320 | 83469015 | bellard | |
1321 | 83469015 | bellard | static CPUReadMemoryFunc *pci_apb_config_read[] = {
|
1322 | 83469015 | bellard | &pci_apb_config_readl, |
1323 | 83469015 | bellard | &pci_apb_config_readl, |
1324 | 83469015 | bellard | &pci_apb_config_readl, |
1325 | 83469015 | bellard | }; |
1326 | 83469015 | bellard | |
1327 | 83469015 | bellard | static void apb_config_writel (void *opaque, target_phys_addr_t addr, |
1328 | 83469015 | bellard | uint32_t val) |
1329 | 83469015 | bellard | { |
1330 | 83469015 | bellard | //PCIBus *s = opaque;
|
1331 | 83469015 | bellard | |
1332 | 83469015 | bellard | switch (addr & 0x3f) { |
1333 | 83469015 | bellard | case 0x00: // Control/Status |
1334 | 83469015 | bellard | case 0x10: // AFSR |
1335 | 83469015 | bellard | case 0x18: // AFAR |
1336 | 83469015 | bellard | case 0x20: // Diagnostic |
1337 | 83469015 | bellard | case 0x28: // Target address space |
1338 | 83469015 | bellard | // XXX
|
1339 | 83469015 | bellard | default:
|
1340 | 83469015 | bellard | break;
|
1341 | 83469015 | bellard | } |
1342 | 83469015 | bellard | } |
1343 | 83469015 | bellard | |
1344 | 83469015 | bellard | static uint32_t apb_config_readl (void *opaque, |
1345 | 83469015 | bellard | target_phys_addr_t addr) |
1346 | 83469015 | bellard | { |
1347 | 83469015 | bellard | //PCIBus *s = opaque;
|
1348 | 83469015 | bellard | uint32_t val; |
1349 | 83469015 | bellard | |
1350 | 83469015 | bellard | switch (addr & 0x3f) { |
1351 | 83469015 | bellard | case 0x00: // Control/Status |
1352 | 83469015 | bellard | case 0x10: // AFSR |
1353 | 83469015 | bellard | case 0x18: // AFAR |
1354 | 83469015 | bellard | case 0x20: // Diagnostic |
1355 | 83469015 | bellard | case 0x28: // Target address space |
1356 | 83469015 | bellard | // XXX
|
1357 | 83469015 | bellard | default:
|
1358 | 83469015 | bellard | val = 0;
|
1359 | 83469015 | bellard | break;
|
1360 | 83469015 | bellard | } |
1361 | 83469015 | bellard | return val;
|
1362 | 83469015 | bellard | } |
1363 | 83469015 | bellard | |
1364 | 83469015 | bellard | static CPUWriteMemoryFunc *apb_config_write[] = {
|
1365 | 83469015 | bellard | &apb_config_writel, |
1366 | 83469015 | bellard | &apb_config_writel, |
1367 | 83469015 | bellard | &apb_config_writel, |
1368 | 83469015 | bellard | }; |
1369 | 83469015 | bellard | |
1370 | 83469015 | bellard | static CPUReadMemoryFunc *apb_config_read[] = {
|
1371 | 83469015 | bellard | &apb_config_readl, |
1372 | 83469015 | bellard | &apb_config_readl, |
1373 | 83469015 | bellard | &apb_config_readl, |
1374 | 83469015 | bellard | }; |
1375 | 83469015 | bellard | |
1376 | 83469015 | bellard | static void pci_apb_writeb (void *opaque, target_phys_addr_t addr, |
1377 | 83469015 | bellard | uint32_t val) |
1378 | 83469015 | bellard | { |
1379 | 83469015 | bellard | PCIBus *s = opaque; |
1380 | 83469015 | bellard | |
1381 | 83469015 | bellard | pci_data_write(s, addr & 7, val, 1); |
1382 | 83469015 | bellard | } |
1383 | 83469015 | bellard | |
1384 | 83469015 | bellard | static void pci_apb_writew (void *opaque, target_phys_addr_t addr, |
1385 | 83469015 | bellard | uint32_t val) |
1386 | 83469015 | bellard | { |
1387 | 83469015 | bellard | PCIBus *s = opaque; |
1388 | 83469015 | bellard | |
1389 | 83469015 | bellard | pci_data_write(s, addr & 7, val, 2); |
1390 | 83469015 | bellard | } |
1391 | 83469015 | bellard | |
1392 | 83469015 | bellard | static void pci_apb_writel (void *opaque, target_phys_addr_t addr, |
1393 | 83469015 | bellard | uint32_t val) |
1394 | 83469015 | bellard | { |
1395 | 83469015 | bellard | PCIBus *s = opaque; |
1396 | 83469015 | bellard | |
1397 | 83469015 | bellard | pci_data_write(s, addr & 7, val, 4); |
1398 | 83469015 | bellard | } |
1399 | 83469015 | bellard | |
1400 | 83469015 | bellard | static uint32_t pci_apb_readb (void *opaque, target_phys_addr_t addr) |
1401 | 83469015 | bellard | { |
1402 | 83469015 | bellard | PCIBus *s = opaque; |
1403 | 83469015 | bellard | uint32_t val; |
1404 | 83469015 | bellard | |
1405 | 83469015 | bellard | val = pci_data_read(s, addr & 7, 1); |
1406 | 83469015 | bellard | return val;
|
1407 | 83469015 | bellard | } |
1408 | 83469015 | bellard | |
1409 | 83469015 | bellard | static uint32_t pci_apb_readw (void *opaque, target_phys_addr_t addr) |
1410 | 83469015 | bellard | { |
1411 | 83469015 | bellard | PCIBus *s = opaque; |
1412 | 83469015 | bellard | uint32_t val; |
1413 | 83469015 | bellard | |
1414 | 83469015 | bellard | val = pci_data_read(s, addr & 7, 2); |
1415 | 83469015 | bellard | return val;
|
1416 | 83469015 | bellard | } |
1417 | 83469015 | bellard | |
1418 | 83469015 | bellard | static uint32_t pci_apb_readl (void *opaque, target_phys_addr_t addr) |
1419 | 83469015 | bellard | { |
1420 | 83469015 | bellard | PCIBus *s = opaque; |
1421 | 83469015 | bellard | uint32_t val; |
1422 | 83469015 | bellard | |
1423 | 83469015 | bellard | val = pci_data_read(s, addr, 4);
|
1424 | 83469015 | bellard | return val;
|
1425 | 83469015 | bellard | } |
1426 | 83469015 | bellard | |
1427 | 83469015 | bellard | static CPUWriteMemoryFunc *pci_apb_write[] = {
|
1428 | 83469015 | bellard | &pci_apb_writeb, |
1429 | 83469015 | bellard | &pci_apb_writew, |
1430 | 83469015 | bellard | &pci_apb_writel, |
1431 | 83469015 | bellard | }; |
1432 | 83469015 | bellard | |
1433 | 83469015 | bellard | static CPUReadMemoryFunc *pci_apb_read[] = {
|
1434 | 83469015 | bellard | &pci_apb_readb, |
1435 | 83469015 | bellard | &pci_apb_readw, |
1436 | 83469015 | bellard | &pci_apb_readl, |
1437 | 83469015 | bellard | }; |
1438 | 83469015 | bellard | |
1439 | 83469015 | bellard | static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr, |
1440 | 83469015 | bellard | uint32_t val) |
1441 | 83469015 | bellard | { |
1442 | 83469015 | bellard | cpu_outb(NULL, addr & 0xffff, val); |
1443 | 83469015 | bellard | } |
1444 | 83469015 | bellard | |
1445 | 83469015 | bellard | static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr, |
1446 | 83469015 | bellard | uint32_t val) |
1447 | 83469015 | bellard | { |
1448 | 83469015 | bellard | cpu_outw(NULL, addr & 0xffff, val); |
1449 | 83469015 | bellard | } |
1450 | 83469015 | bellard | |
1451 | 83469015 | bellard | static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr, |
1452 | 83469015 | bellard | uint32_t val) |
1453 | 83469015 | bellard | { |
1454 | 83469015 | bellard | cpu_outl(NULL, addr & 0xffff, val); |
1455 | 83469015 | bellard | } |
1456 | 83469015 | bellard | |
1457 | 83469015 | bellard | static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr) |
1458 | 83469015 | bellard | { |
1459 | 83469015 | bellard | uint32_t val; |
1460 | 83469015 | bellard | |
1461 | 83469015 | bellard | val = cpu_inb(NULL, addr & 0xffff); |
1462 | 83469015 | bellard | return val;
|
1463 | 83469015 | bellard | } |
1464 | 83469015 | bellard | |
1465 | 83469015 | bellard | static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr) |
1466 | 83469015 | bellard | { |
1467 | 83469015 | bellard | uint32_t val; |
1468 | 83469015 | bellard | |
1469 | 83469015 | bellard | val = cpu_inw(NULL, addr & 0xffff); |
1470 | 83469015 | bellard | return val;
|
1471 | 83469015 | bellard | } |
1472 | 83469015 | bellard | |
1473 | 83469015 | bellard | static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr) |
1474 | 83469015 | bellard | { |
1475 | 83469015 | bellard | uint32_t val; |
1476 | 83469015 | bellard | |
1477 | 83469015 | bellard | val = cpu_inl(NULL, addr & 0xffff); |
1478 | 83469015 | bellard | return val;
|
1479 | 83469015 | bellard | } |
1480 | 83469015 | bellard | |
1481 | 83469015 | bellard | static CPUWriteMemoryFunc *pci_apb_iowrite[] = {
|
1482 | 83469015 | bellard | &pci_apb_iowriteb, |
1483 | 83469015 | bellard | &pci_apb_iowritew, |
1484 | 83469015 | bellard | &pci_apb_iowritel, |
1485 | 83469015 | bellard | }; |
1486 | 83469015 | bellard | |
1487 | 83469015 | bellard | static CPUReadMemoryFunc *pci_apb_ioread[] = {
|
1488 | 83469015 | bellard | &pci_apb_ioreadb, |
1489 | 83469015 | bellard | &pci_apb_ioreadw, |
1490 | 83469015 | bellard | &pci_apb_ioreadl, |
1491 | 83469015 | bellard | }; |
1492 | 83469015 | bellard | |
1493 | 83469015 | bellard | PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base) |
1494 | 83469015 | bellard | { |
1495 | 83469015 | bellard | PCIBus *s; |
1496 | 83469015 | bellard | PCIDevice *d; |
1497 | 83469015 | bellard | int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
|
1498 | 83469015 | bellard | |
1499 | 83469015 | bellard | /* Ultrasparc APB main bus */
|
1500 | 83469015 | bellard | s = pci_register_bus(); |
1501 | 83469015 | bellard | s->set_irq = pci_set_irq_simple; |
1502 | 83469015 | bellard | |
1503 | 83469015 | bellard | pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
|
1504 | 83469015 | bellard | pci_apb_config_write, s); |
1505 | 83469015 | bellard | apb_config = cpu_register_io_memory(0, apb_config_read,
|
1506 | 83469015 | bellard | apb_config_write, s); |
1507 | 83469015 | bellard | pci_mem_data = cpu_register_io_memory(0, pci_apb_read,
|
1508 | 83469015 | bellard | pci_apb_write, s); |
1509 | 83469015 | bellard | pci_ioport = cpu_register_io_memory(0, pci_apb_ioread,
|
1510 | 83469015 | bellard | pci_apb_iowrite, s); |
1511 | 83469015 | bellard | |
1512 | 83469015 | bellard | cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config); |
1513 | 83469015 | bellard | cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, pci_mem_config); |
1514 | 83469015 | bellard | cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport); |
1515 | 83469015 | bellard | cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom |
1516 | 83469015 | bellard | |
1517 | 83469015 | bellard | d = pci_register_device(s, "Advanced PCI Bus", sizeof(PCIDevice), |
1518 | 83469015 | bellard | -1, NULL, NULL); |
1519 | 83469015 | bellard | d->config[0x00] = 0x8e; // vendor_id : Sun |
1520 | 83469015 | bellard | d->config[0x01] = 0x10; |
1521 | 83469015 | bellard | d->config[0x02] = 0x00; // device_id |
1522 | 83469015 | bellard | d->config[0x03] = 0xa0; |
1523 | 83469015 | bellard | d->config[0x04] = 0x06; // command = bus master, pci mem |
1524 | 83469015 | bellard | d->config[0x05] = 0x00; |
1525 | 83469015 | bellard | d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
1526 | 83469015 | bellard | d->config[0x07] = 0x03; // status = medium devsel |
1527 | 83469015 | bellard | d->config[0x08] = 0x00; // revision |
1528 | 83469015 | bellard | d->config[0x09] = 0x00; // programming i/f |
1529 | 83469015 | bellard | d->config[0x0A] = 0x00; // class_sub = pci host |
1530 | 83469015 | bellard | d->config[0x0B] = 0x06; // class_base = PCI_bridge |
1531 | 83469015 | bellard | d->config[0x0D] = 0x10; // latency_timer |
1532 | 83469015 | bellard | d->config[0x0E] = 0x00; // header_type |
1533 | 83469015 | bellard | return s;
|
1534 | 83469015 | bellard | } |
1535 | 83469015 | bellard | |
1536 | 0ac32c83 | bellard | /***********************************************************/
|
1537 | 0ac32c83 | bellard | /* generic PCI irq support */
|
1538 | 0ac32c83 | bellard | |
1539 | 0ac32c83 | bellard | /* 0 <= irq_num <= 3. level must be 0 or 1 */
|
1540 | 77d4bc34 | bellard | void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
1541 | 77d4bc34 | bellard | { |
1542 | 30468f78 | bellard | PCIBus *bus = pci_dev->bus; |
1543 | 30468f78 | bellard | bus->set_irq(pci_dev, irq_num, level); |
1544 | 77d4bc34 | bellard | } |
1545 | 0ac32c83 | bellard | |
1546 | 0ac32c83 | bellard | /***********************************************************/
|
1547 | 0ac32c83 | bellard | /* monitor info on PCI */
|
1548 | 0ac32c83 | bellard | |
1549 | 0ac32c83 | bellard | static void pci_info_device(PCIDevice *d) |
1550 | 0ac32c83 | bellard | { |
1551 | 0ac32c83 | bellard | int i, class;
|
1552 | 0ac32c83 | bellard | PCIIORegion *r; |
1553 | 0ac32c83 | bellard | |
1554 | 8e3a9fd2 | bellard | term_printf(" Bus %2d, device %3d, function %d:\n",
|
1555 | 30468f78 | bellard | d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
1556 | 0ac32c83 | bellard | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
1557 | 8e3a9fd2 | bellard | term_printf(" ");
|
1558 | 0ac32c83 | bellard | switch(class) {
|
1559 | 0ac32c83 | bellard | case 0x0101: |
1560 | 8e3a9fd2 | bellard | term_printf("IDE controller");
|
1561 | 0ac32c83 | bellard | break;
|
1562 | 0ac32c83 | bellard | case 0x0200: |
1563 | 8e3a9fd2 | bellard | term_printf("Ethernet controller");
|
1564 | 0ac32c83 | bellard | break;
|
1565 | 0ac32c83 | bellard | case 0x0300: |
1566 | 8e3a9fd2 | bellard | term_printf("VGA controller");
|
1567 | 0ac32c83 | bellard | break;
|
1568 | 0ac32c83 | bellard | default:
|
1569 | 8e3a9fd2 | bellard | term_printf("Class %04x", class);
|
1570 | 0ac32c83 | bellard | break;
|
1571 | 0ac32c83 | bellard | } |
1572 | 8e3a9fd2 | bellard | term_printf(": PCI device %04x:%04x\n",
|
1573 | 0ac32c83 | bellard | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
1574 | 0ac32c83 | bellard | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
1575 | 0ac32c83 | bellard | |
1576 | 0ac32c83 | bellard | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
1577 | 8e3a9fd2 | bellard | term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
1578 | 0ac32c83 | bellard | } |
1579 | 8a8696a3 | bellard | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
1580 | 0ac32c83 | bellard | r = &d->io_regions[i]; |
1581 | 0ac32c83 | bellard | if (r->size != 0) { |
1582 | 8e3a9fd2 | bellard | term_printf(" BAR%d: ", i);
|
1583 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
1584 | 8e3a9fd2 | bellard | term_printf("I/O at 0x%04x [0x%04x].\n",
|
1585 | 0ac32c83 | bellard | r->addr, r->addr + r->size - 1);
|
1586 | 0ac32c83 | bellard | } else {
|
1587 | 8e3a9fd2 | bellard | term_printf("32 bit memory at 0x%08x [0x%08x].\n",
|
1588 | 0ac32c83 | bellard | r->addr, r->addr + r->size - 1);
|
1589 | 0ac32c83 | bellard | } |
1590 | 0ac32c83 | bellard | } |
1591 | 0ac32c83 | bellard | } |
1592 | 0ac32c83 | bellard | } |
1593 | 0ac32c83 | bellard | |
1594 | 0ac32c83 | bellard | void pci_info(void) |
1595 | 0ac32c83 | bellard | { |
1596 | 30468f78 | bellard | PCIBus *bus = first_bus; |
1597 | 30468f78 | bellard | PCIDevice *d; |
1598 | 30468f78 | bellard | int devfn;
|
1599 | 0ac32c83 | bellard | |
1600 | 30468f78 | bellard | if (bus) {
|
1601 | 30468f78 | bellard | for(devfn = 0; devfn < 256; devfn++) { |
1602 | 30468f78 | bellard | d = bus->devices[devfn]; |
1603 | 30468f78 | bellard | if (d)
|
1604 | 30468f78 | bellard | pci_info_device(d); |
1605 | 0ac32c83 | bellard | } |
1606 | 0ac32c83 | bellard | } |
1607 | 0ac32c83 | bellard | } |
1608 | 0ac32c83 | bellard | |
1609 | 0ac32c83 | bellard | /***********************************************************/
|
1610 | 0ac32c83 | bellard | /* XXX: the following should be moved to the PC BIOS */
|
1611 | 0ac32c83 | bellard | |
1612 | 30468f78 | bellard | static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
|
1613 | 0ac32c83 | bellard | { |
1614 | c68ea704 | bellard | return cpu_inb(NULL, addr); |
1615 | 0ac32c83 | bellard | } |
1616 | 0ac32c83 | bellard | |
1617 | 0ac32c83 | bellard | static void isa_outb(uint32_t val, uint32_t addr) |
1618 | 0ac32c83 | bellard | { |
1619 | c68ea704 | bellard | cpu_outb(NULL, addr, val);
|
1620 | 0ac32c83 | bellard | } |
1621 | 0ac32c83 | bellard | |
1622 | 30468f78 | bellard | static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
|
1623 | 0ac32c83 | bellard | { |
1624 | c68ea704 | bellard | return cpu_inw(NULL, addr); |
1625 | 0ac32c83 | bellard | } |
1626 | 0ac32c83 | bellard | |
1627 | 30468f78 | bellard | static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr) |
1628 | 0ac32c83 | bellard | { |
1629 | c68ea704 | bellard | cpu_outw(NULL, addr, val);
|
1630 | 0ac32c83 | bellard | } |
1631 | 0ac32c83 | bellard | |
1632 | 30468f78 | bellard | static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
|
1633 | 0ac32c83 | bellard | { |
1634 | c68ea704 | bellard | return cpu_inl(NULL, addr); |
1635 | 0ac32c83 | bellard | } |
1636 | 0ac32c83 | bellard | |
1637 | 30468f78 | bellard | static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr) |
1638 | 0ac32c83 | bellard | { |
1639 | c68ea704 | bellard | cpu_outl(NULL, addr, val);
|
1640 | 0ac32c83 | bellard | } |
1641 | 0ac32c83 | bellard | |
1642 | 0ac32c83 | bellard | static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
1643 | 0ac32c83 | bellard | { |
1644 | 30468f78 | bellard | PCIBus *s = d->bus; |
1645 | 30468f78 | bellard | s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1646 | 0ac32c83 | bellard | (d->devfn << 8) | addr;
|
1647 | 0ac32c83 | bellard | pci_data_write(s, 0, val, 4); |
1648 | 0ac32c83 | bellard | } |
1649 | 0ac32c83 | bellard | |
1650 | 0ac32c83 | bellard | static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) |
1651 | 0ac32c83 | bellard | { |
1652 | 30468f78 | bellard | PCIBus *s = d->bus; |
1653 | 30468f78 | bellard | s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1654 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
1655 | 0ac32c83 | bellard | pci_data_write(s, addr & 3, val, 2); |
1656 | 0ac32c83 | bellard | } |
1657 | 0ac32c83 | bellard | |
1658 | 0ac32c83 | bellard | static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) |
1659 | 0ac32c83 | bellard | { |
1660 | 30468f78 | bellard | PCIBus *s = d->bus; |
1661 | 30468f78 | bellard | s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1662 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
1663 | 0ac32c83 | bellard | pci_data_write(s, addr & 3, val, 1); |
1664 | 0ac32c83 | bellard | } |
1665 | 0ac32c83 | bellard | |
1666 | 30468f78 | bellard | static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
|
1667 | 0ac32c83 | bellard | { |
1668 | 30468f78 | bellard | PCIBus *s = d->bus; |
1669 | 30468f78 | bellard | s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1670 | 0ac32c83 | bellard | (d->devfn << 8) | addr;
|
1671 | 0ac32c83 | bellard | return pci_data_read(s, 0, 4); |
1672 | 0ac32c83 | bellard | } |
1673 | 0ac32c83 | bellard | |
1674 | 0ac32c83 | bellard | static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
|
1675 | 0ac32c83 | bellard | { |
1676 | 30468f78 | bellard | PCIBus *s = d->bus; |
1677 | 30468f78 | bellard | s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1678 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
1679 | 0ac32c83 | bellard | return pci_data_read(s, addr & 3, 2); |
1680 | 0ac32c83 | bellard | } |
1681 | 0ac32c83 | bellard | |
1682 | 0ac32c83 | bellard | static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
|
1683 | 0ac32c83 | bellard | { |
1684 | 30468f78 | bellard | PCIBus *s = d->bus; |
1685 | 30468f78 | bellard | s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1686 | 0ac32c83 | bellard | (d->devfn << 8) | (addr & ~3); |
1687 | 0ac32c83 | bellard | return pci_data_read(s, addr & 3, 1); |
1688 | 0ac32c83 | bellard | } |
1689 | 69b91039 | bellard | |
1690 | 69b91039 | bellard | static uint32_t pci_bios_io_addr;
|
1691 | 69b91039 | bellard | static uint32_t pci_bios_mem_addr;
|
1692 | 0ac32c83 | bellard | /* host irqs corresponding to PCI irqs A-D */
|
1693 | 0ac32c83 | bellard | static uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; |
1694 | 69b91039 | bellard | |
1695 | 69b91039 | bellard | static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) |
1696 | 69b91039 | bellard | { |
1697 | 69b91039 | bellard | PCIIORegion *r; |
1698 | 0ac32c83 | bellard | uint16_t cmd; |
1699 | 8a8696a3 | bellard | uint32_t ofs; |
1700 | 8a8696a3 | bellard | |
1701 | 8a8696a3 | bellard | if ( region_num == PCI_ROM_SLOT ) {
|
1702 | 8a8696a3 | bellard | ofs = 0x30;
|
1703 | 8a8696a3 | bellard | }else{
|
1704 | 8a8696a3 | bellard | ofs = 0x10 + region_num * 4; |
1705 | 8a8696a3 | bellard | } |
1706 | 69b91039 | bellard | |
1707 | 8a8696a3 | bellard | pci_config_writel(d, ofs, addr); |
1708 | 69b91039 | bellard | r = &d->io_regions[region_num]; |
1709 | 69b91039 | bellard | |
1710 | 69b91039 | bellard | /* enable memory mappings */
|
1711 | 0ac32c83 | bellard | cmd = pci_config_readw(d, PCI_COMMAND); |
1712 | 8a8696a3 | bellard | if ( region_num == PCI_ROM_SLOT )
|
1713 | 8a8696a3 | bellard | cmd |= 2;
|
1714 | 8a8696a3 | bellard | else if (r->type & PCI_ADDRESS_SPACE_IO) |
1715 | 0ac32c83 | bellard | cmd |= 1;
|
1716 | 69b91039 | bellard | else
|
1717 | 0ac32c83 | bellard | cmd |= 2;
|
1718 | 0ac32c83 | bellard | pci_config_writew(d, PCI_COMMAND, cmd); |
1719 | 69b91039 | bellard | } |
1720 | 69b91039 | bellard | |
1721 | 69b91039 | bellard | static void pci_bios_init_device(PCIDevice *d) |
1722 | 69b91039 | bellard | { |
1723 | 69b91039 | bellard | int class;
|
1724 | 69b91039 | bellard | PCIIORegion *r; |
1725 | 69b91039 | bellard | uint32_t *paddr; |
1726 | 63ce9e0a | bellard | int i, pin, pic_irq, vendor_id, device_id;
|
1727 | 69b91039 | bellard | |
1728 | 63ce9e0a | bellard | class = pci_config_readw(d, PCI_CLASS_DEVICE); |
1729 | 1f62d938 | bellard | vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
1730 | 1f62d938 | bellard | device_id = pci_config_readw(d, PCI_DEVICE_ID); |
1731 | 69b91039 | bellard | switch(class) {
|
1732 | 69b91039 | bellard | case 0x0101: |
1733 | 63ce9e0a | bellard | if (vendor_id == 0x8086 && device_id == 0x7010) { |
1734 | 63ce9e0a | bellard | /* PIIX3 IDE */
|
1735 | 63ce9e0a | bellard | pci_config_writew(d, 0x40, 0x8000); // enable IDE0 |
1736 | 7f647cf6 | bellard | pci_config_writew(d, 0x42, 0x8000); // enable IDE1 |
1737 | d187d4b2 | bellard | goto default_map;
|
1738 | 63ce9e0a | bellard | } else {
|
1739 | 63ce9e0a | bellard | /* IDE: we map it as in ISA mode */
|
1740 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 0, 0x1f0); |
1741 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 1, 0x3f4); |
1742 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 2, 0x170); |
1743 | 63ce9e0a | bellard | pci_set_io_region_addr(d, 3, 0x374); |
1744 | 63ce9e0a | bellard | } |
1745 | 69b91039 | bellard | break;
|
1746 | 0ac32c83 | bellard | case 0x0300: |
1747 | 4c7634bc | bellard | if (vendor_id != 0x1234) |
1748 | 4c7634bc | bellard | goto default_map;
|
1749 | 0ac32c83 | bellard | /* VGA: map frame buffer to default Bochs VBE address */
|
1750 | 0ac32c83 | bellard | pci_set_io_region_addr(d, 0, 0xE0000000); |
1751 | 0ac32c83 | bellard | break;
|
1752 | f2aa58c6 | bellard | case 0x0800: |
1753 | f2aa58c6 | bellard | /* PIC */
|
1754 | f2aa58c6 | bellard | vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
1755 | f2aa58c6 | bellard | device_id = pci_config_readw(d, PCI_DEVICE_ID); |
1756 | f2aa58c6 | bellard | if (vendor_id == 0x1014) { |
1757 | f2aa58c6 | bellard | /* IBM */
|
1758 | f2aa58c6 | bellard | if (device_id == 0x0046 || device_id == 0xFFFF) { |
1759 | f2aa58c6 | bellard | /* MPIC & MPIC2 */
|
1760 | f2aa58c6 | bellard | pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000); |
1761 | f2aa58c6 | bellard | } |
1762 | f2aa58c6 | bellard | } |
1763 | f2aa58c6 | bellard | break;
|
1764 | 1f62d938 | bellard | case 0xff00: |
1765 | f2aa58c6 | bellard | if (vendor_id == 0x0106b && |
1766 | f2aa58c6 | bellard | (device_id == 0x0017 || device_id == 0x0022)) { |
1767 | 1f62d938 | bellard | /* macio bridge */
|
1768 | 1f62d938 | bellard | pci_set_io_region_addr(d, 0, 0x80800000); |
1769 | 1f62d938 | bellard | } |
1770 | 1f62d938 | bellard | break;
|
1771 | 69b91039 | bellard | default:
|
1772 | 4c7634bc | bellard | default_map:
|
1773 | 69b91039 | bellard | /* default memory mappings */
|
1774 | 8a8696a3 | bellard | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
1775 | 69b91039 | bellard | r = &d->io_regions[i]; |
1776 | 69b91039 | bellard | if (r->size) {
|
1777 | 69b91039 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO)
|
1778 | 69b91039 | bellard | paddr = &pci_bios_io_addr; |
1779 | 69b91039 | bellard | else
|
1780 | 69b91039 | bellard | paddr = &pci_bios_mem_addr; |
1781 | 69b91039 | bellard | *paddr = (*paddr + r->size - 1) & ~(r->size - 1); |
1782 | 69b91039 | bellard | pci_set_io_region_addr(d, i, *paddr); |
1783 | 69b91039 | bellard | *paddr += r->size; |
1784 | 69b91039 | bellard | } |
1785 | 69b91039 | bellard | } |
1786 | 69b91039 | bellard | break;
|
1787 | 69b91039 | bellard | } |
1788 | 0ac32c83 | bellard | |
1789 | 0ac32c83 | bellard | /* map the interrupt */
|
1790 | 0ac32c83 | bellard | pin = pci_config_readb(d, PCI_INTERRUPT_PIN); |
1791 | 0ac32c83 | bellard | if (pin != 0) { |
1792 | 0ac32c83 | bellard | pin = pci_slot_get_pirq(d, pin - 1);
|
1793 | 0ac32c83 | bellard | pic_irq = pci_irqs[pin]; |
1794 | 0ac32c83 | bellard | pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); |
1795 | 0ac32c83 | bellard | } |
1796 | 69b91039 | bellard | } |
1797 | 69b91039 | bellard | |
1798 | 69b91039 | bellard | /*
|
1799 | 69b91039 | bellard | * This function initializes the PCI devices as a normal PCI BIOS
|
1800 | 69b91039 | bellard | * would do. It is provided just in case the BIOS has no support for
|
1801 | 69b91039 | bellard | * PCI.
|
1802 | 69b91039 | bellard | */
|
1803 | 69b91039 | bellard | void pci_bios_init(void) |
1804 | 69b91039 | bellard | { |
1805 | 30468f78 | bellard | PCIBus *bus; |
1806 | 30468f78 | bellard | PCIDevice *d; |
1807 | 30468f78 | bellard | int devfn, i, irq;
|
1808 | 0ac32c83 | bellard | uint8_t elcr[2];
|
1809 | 69b91039 | bellard | |
1810 | 69b91039 | bellard | pci_bios_io_addr = 0xc000;
|
1811 | 69b91039 | bellard | pci_bios_mem_addr = 0xf0000000;
|
1812 | 69b91039 | bellard | |
1813 | 0ac32c83 | bellard | /* activate IRQ mappings */
|
1814 | 0ac32c83 | bellard | elcr[0] = 0x00; |
1815 | 0ac32c83 | bellard | elcr[1] = 0x00; |
1816 | 0ac32c83 | bellard | for(i = 0; i < 4; i++) { |
1817 | 0ac32c83 | bellard | irq = pci_irqs[i]; |
1818 | 0ac32c83 | bellard | /* set to trigger level */
|
1819 | 0ac32c83 | bellard | elcr[irq >> 3] |= (1 << (irq & 7)); |
1820 | 0ac32c83 | bellard | /* activate irq remapping in PIIX */
|
1821 | 0ac32c83 | bellard | pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
1822 | 0ac32c83 | bellard | } |
1823 | 0ac32c83 | bellard | isa_outb(elcr[0], 0x4d0); |
1824 | 0ac32c83 | bellard | isa_outb(elcr[1], 0x4d1); |
1825 | 0ac32c83 | bellard | |
1826 | 30468f78 | bellard | bus = first_bus; |
1827 | 30468f78 | bellard | if (bus) {
|
1828 | 30468f78 | bellard | for(devfn = 0; devfn < 256; devfn++) { |
1829 | 30468f78 | bellard | d = bus->devices[devfn]; |
1830 | 30468f78 | bellard | if (d)
|
1831 | 30468f78 | bellard | pci_bios_init_device(d); |
1832 | 77d4bc34 | bellard | } |
1833 | 77d4bc34 | bellard | } |
1834 | 77d4bc34 | bellard | } |
1835 | a41b2ff2 | pbrook | |
1836 | a41b2ff2 | pbrook | /* Initialize a PCI NIC. */
|
1837 | a41b2ff2 | pbrook | void pci_nic_init(PCIBus *bus, NICInfo *nd)
|
1838 | a41b2ff2 | pbrook | { |
1839 | a41b2ff2 | pbrook | if (strcmp(nd->model, "ne2k_pci") == 0) { |
1840 | a41b2ff2 | pbrook | pci_ne2000_init(bus, nd); |
1841 | a41b2ff2 | pbrook | } else if (strcmp(nd->model, "rtl8139") == 0) { |
1842 | a41b2ff2 | pbrook | pci_rtl8139_init(bus, nd); |
1843 | a41b2ff2 | pbrook | } else {
|
1844 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
|
1845 | a41b2ff2 | pbrook | exit (1);
|
1846 | a41b2ff2 | pbrook | } |
1847 | a41b2ff2 | pbrook | } |