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1 | 64201201 | bellard | /*
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2 | 64201201 | bellard | * QEMU PPC CHRP/PMAC hardware System Emulator
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3 | 64201201 | bellard | *
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4 | 64201201 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | 64201201 | bellard | *
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6 | 64201201 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 64201201 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 64201201 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 64201201 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 64201201 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 64201201 | bellard | * furnished to do so, subject to the following conditions:
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12 | 64201201 | bellard | *
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13 | 64201201 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 64201201 | bellard | * all copies or substantial portions of the Software.
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15 | 64201201 | bellard | *
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16 | 64201201 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 64201201 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 64201201 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 64201201 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 64201201 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 64201201 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 64201201 | bellard | * THE SOFTWARE.
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23 | 64201201 | bellard | */
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24 | 64201201 | bellard | #include "vl.h" |
25 | 64201201 | bellard | |
26 | 64201201 | bellard | #define BIOS_FILENAME "ppc_rom.bin" |
27 | d5295253 | bellard | #define VGABIOS_FILENAME "video.x" |
28 | 64201201 | bellard | #define NVRAM_SIZE 0x2000 |
29 | 64201201 | bellard | |
30 | b6b8bd18 | bellard | #define KERNEL_LOAD_ADDR 0x01000000 |
31 | b6b8bd18 | bellard | #define INITRD_LOAD_ADDR 0x01800000 |
32 | b6b8bd18 | bellard | |
33 | 267002cd | bellard | /* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
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34 | e5733356 | bellard | NVRAM */
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35 | 267002cd | bellard | |
36 | 267002cd | bellard | static int dbdma_mem_index; |
37 | 267002cd | bellard | static int cuda_mem_index; |
38 | 0aa6a4a2 | bellard | static int ide0_mem_index = -1; |
39 | 0aa6a4a2 | bellard | static int ide1_mem_index = -1; |
40 | 0aa6a4a2 | bellard | static int openpic_mem_index = -1; |
41 | 0aa6a4a2 | bellard | static int heathrow_pic_mem_index = -1; |
42 | e5733356 | bellard | static int macio_nvram_mem_index = -1; |
43 | 267002cd | bellard | |
44 | 267002cd | bellard | /* DBDMA: currently no op - should suffice right now */
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45 | 267002cd | bellard | |
46 | 267002cd | bellard | static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
47 | 267002cd | bellard | { |
48 | b6b8bd18 | bellard | printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
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49 | 267002cd | bellard | } |
50 | 267002cd | bellard | |
51 | 267002cd | bellard | static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
52 | 267002cd | bellard | { |
53 | 267002cd | bellard | } |
54 | 267002cd | bellard | |
55 | 267002cd | bellard | static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
56 | 267002cd | bellard | { |
57 | 267002cd | bellard | } |
58 | 267002cd | bellard | |
59 | 267002cd | bellard | static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr) |
60 | 267002cd | bellard | { |
61 | b6b8bd18 | bellard | printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
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62 | 267002cd | bellard | return 0; |
63 | 267002cd | bellard | } |
64 | 267002cd | bellard | |
65 | 267002cd | bellard | static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr) |
66 | 267002cd | bellard | { |
67 | 267002cd | bellard | return 0; |
68 | 267002cd | bellard | } |
69 | 267002cd | bellard | |
70 | 267002cd | bellard | static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) |
71 | 267002cd | bellard | { |
72 | 267002cd | bellard | return 0; |
73 | 267002cd | bellard | } |
74 | 267002cd | bellard | |
75 | 267002cd | bellard | static CPUWriteMemoryFunc *dbdma_write[] = {
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76 | 267002cd | bellard | &dbdma_writeb, |
77 | 267002cd | bellard | &dbdma_writew, |
78 | 267002cd | bellard | &dbdma_writel, |
79 | 267002cd | bellard | }; |
80 | 267002cd | bellard | |
81 | 267002cd | bellard | static CPUReadMemoryFunc *dbdma_read[] = {
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82 | 267002cd | bellard | &dbdma_readb, |
83 | 267002cd | bellard | &dbdma_readw, |
84 | 267002cd | bellard | &dbdma_readl, |
85 | 267002cd | bellard | }; |
86 | 267002cd | bellard | |
87 | e5733356 | bellard | /* macio style NVRAM device */
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88 | e5733356 | bellard | typedef struct MacIONVRAMState { |
89 | e5733356 | bellard | uint8_t data[0x2000];
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90 | e5733356 | bellard | } MacIONVRAMState; |
91 | e5733356 | bellard | |
92 | e5733356 | bellard | static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
93 | e5733356 | bellard | { |
94 | e5733356 | bellard | MacIONVRAMState *s = opaque; |
95 | e5733356 | bellard | addr = (addr >> 4) & 0x1fff; |
96 | e5733356 | bellard | s->data[addr] = value; |
97 | e5733356 | bellard | // printf("macio_nvram_writeb %04x = %02x\n", addr, value);
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98 | e5733356 | bellard | } |
99 | e5733356 | bellard | |
100 | e5733356 | bellard | static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr) |
101 | e5733356 | bellard | { |
102 | e5733356 | bellard | MacIONVRAMState *s = opaque; |
103 | e5733356 | bellard | uint32_t value; |
104 | e5733356 | bellard | |
105 | e5733356 | bellard | addr = (addr >> 4) & 0x1fff; |
106 | e5733356 | bellard | value = s->data[addr]; |
107 | e5733356 | bellard | // printf("macio_nvram_readb %04x = %02x\n", addr, value);
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108 | e5733356 | bellard | return value;
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109 | e5733356 | bellard | } |
110 | e5733356 | bellard | |
111 | e5733356 | bellard | static CPUWriteMemoryFunc *macio_nvram_write[] = {
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112 | e5733356 | bellard | &macio_nvram_writeb, |
113 | e5733356 | bellard | &macio_nvram_writeb, |
114 | e5733356 | bellard | &macio_nvram_writeb, |
115 | e5733356 | bellard | }; |
116 | e5733356 | bellard | |
117 | e5733356 | bellard | static CPUReadMemoryFunc *macio_nvram_read[] = {
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118 | e5733356 | bellard | &macio_nvram_readb, |
119 | e5733356 | bellard | &macio_nvram_readb, |
120 | e5733356 | bellard | &macio_nvram_readb, |
121 | e5733356 | bellard | }; |
122 | e5733356 | bellard | |
123 | e5733356 | bellard | static MacIONVRAMState *macio_nvram_init(void) |
124 | e5733356 | bellard | { |
125 | e5733356 | bellard | MacIONVRAMState *s; |
126 | e5733356 | bellard | s = qemu_mallocz(sizeof(MacIONVRAMState));
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127 | e5733356 | bellard | if (!s)
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128 | e5733356 | bellard | return NULL; |
129 | e5733356 | bellard | macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
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130 | e5733356 | bellard | macio_nvram_write, s); |
131 | e5733356 | bellard | return s;
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132 | e5733356 | bellard | } |
133 | e5733356 | bellard | |
134 | 267002cd | bellard | static void macio_map(PCIDevice *pci_dev, int region_num, |
135 | 267002cd | bellard | uint32_t addr, uint32_t size, int type)
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136 | 267002cd | bellard | { |
137 | 0aa6a4a2 | bellard | if (heathrow_pic_mem_index >= 0) { |
138 | 0aa6a4a2 | bellard | cpu_register_physical_memory(addr + 0x00000, 0x1000, |
139 | 0aa6a4a2 | bellard | heathrow_pic_mem_index); |
140 | 0aa6a4a2 | bellard | } |
141 | 267002cd | bellard | cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index); |
142 | 267002cd | bellard | cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index); |
143 | 0aa6a4a2 | bellard | if (ide0_mem_index >= 0) |
144 | 0aa6a4a2 | bellard | cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index); |
145 | 0aa6a4a2 | bellard | if (ide1_mem_index >= 0) |
146 | 0aa6a4a2 | bellard | cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index); |
147 | 0aa6a4a2 | bellard | if (openpic_mem_index >= 0) { |
148 | 0aa6a4a2 | bellard | cpu_register_physical_memory(addr + 0x40000, 0x40000, |
149 | 0aa6a4a2 | bellard | openpic_mem_index); |
150 | 0aa6a4a2 | bellard | } |
151 | e5733356 | bellard | if (macio_nvram_mem_index >= 0) |
152 | e5733356 | bellard | cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index); |
153 | 267002cd | bellard | } |
154 | 267002cd | bellard | |
155 | e5733356 | bellard | static void macio_init(PCIBus *bus, int device_id) |
156 | 267002cd | bellard | { |
157 | 267002cd | bellard | PCIDevice *d; |
158 | 267002cd | bellard | |
159 | 46e50e9d | bellard | d = pci_register_device(bus, "macio", sizeof(PCIDevice), |
160 | 46e50e9d | bellard | -1, NULL, NULL); |
161 | 267002cd | bellard | /* Note: this code is strongly inspirated from the corresponding code
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162 | 267002cd | bellard | in PearPC */
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163 | 267002cd | bellard | d->config[0x00] = 0x6b; // vendor_id |
164 | 267002cd | bellard | d->config[0x01] = 0x10; |
165 | e5733356 | bellard | d->config[0x02] = device_id;
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166 | e5733356 | bellard | d->config[0x03] = device_id >> 8; |
167 | 267002cd | bellard | |
168 | 267002cd | bellard | d->config[0x0a] = 0x00; // class_sub = pci2pci |
169 | 267002cd | bellard | d->config[0x0b] = 0xff; // class_base = bridge |
170 | 267002cd | bellard | d->config[0x0e] = 0x00; // header_type |
171 | 267002cd | bellard | |
172 | 267002cd | bellard | d->config[0x3d] = 0x01; // interrupt on pin 1 |
173 | 267002cd | bellard | |
174 | 267002cd | bellard | dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL); |
175 | 267002cd | bellard | |
176 | 267002cd | bellard | pci_register_io_region(d, 0, 0x80000, |
177 | 267002cd | bellard | PCI_ADDRESS_SPACE_MEM, macio_map); |
178 | 267002cd | bellard | } |
179 | 267002cd | bellard | |
180 | 0aa6a4a2 | bellard | /* UniN device */
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181 | 0aa6a4a2 | bellard | static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
182 | 0aa6a4a2 | bellard | { |
183 | 0aa6a4a2 | bellard | } |
184 | 0aa6a4a2 | bellard | |
185 | 0aa6a4a2 | bellard | static uint32_t unin_readl (void *opaque, target_phys_addr_t addr) |
186 | 0aa6a4a2 | bellard | { |
187 | 0aa6a4a2 | bellard | return 0; |
188 | 0aa6a4a2 | bellard | } |
189 | 0aa6a4a2 | bellard | |
190 | 0aa6a4a2 | bellard | static CPUWriteMemoryFunc *unin_write[] = {
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191 | 0aa6a4a2 | bellard | &unin_writel, |
192 | 0aa6a4a2 | bellard | &unin_writel, |
193 | 0aa6a4a2 | bellard | &unin_writel, |
194 | 0aa6a4a2 | bellard | }; |
195 | 0aa6a4a2 | bellard | |
196 | 0aa6a4a2 | bellard | static CPUReadMemoryFunc *unin_read[] = {
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197 | 0aa6a4a2 | bellard | &unin_readl, |
198 | 0aa6a4a2 | bellard | &unin_readl, |
199 | 0aa6a4a2 | bellard | &unin_readl, |
200 | 0aa6a4a2 | bellard | }; |
201 | 0aa6a4a2 | bellard | |
202 | 0aa6a4a2 | bellard | /* temporary frame buffer OSI calls for the video.x driver. The right
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203 | 0aa6a4a2 | bellard | solution is to modify the driver to use VGA PCI I/Os */
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204 | 0aa6a4a2 | bellard | static int vga_osi_call(CPUState *env) |
205 | 0aa6a4a2 | bellard | { |
206 | 0aa6a4a2 | bellard | static int vga_vbl_enabled; |
207 | 0aa6a4a2 | bellard | int linesize;
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208 | 0aa6a4a2 | bellard | |
209 | 0aa6a4a2 | bellard | // printf("osi_call R5=%d\n", env->gpr[5]);
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210 | 0aa6a4a2 | bellard | |
211 | 0aa6a4a2 | bellard | /* same handler as PearPC, coming from the original MOL video
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212 | 0aa6a4a2 | bellard | driver. */
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213 | 0aa6a4a2 | bellard | switch(env->gpr[5]) { |
214 | 0aa6a4a2 | bellard | case 4: |
215 | 0aa6a4a2 | bellard | break;
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216 | 0aa6a4a2 | bellard | case 28: /* set_vmode */ |
217 | 0aa6a4a2 | bellard | if (env->gpr[6] != 1 || env->gpr[7] != 0) |
218 | 0aa6a4a2 | bellard | env->gpr[3] = 1; |
219 | 0aa6a4a2 | bellard | else
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220 | 0aa6a4a2 | bellard | env->gpr[3] = 0; |
221 | 0aa6a4a2 | bellard | break;
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222 | 0aa6a4a2 | bellard | case 29: /* get_vmode_info */ |
223 | 0aa6a4a2 | bellard | if (env->gpr[6] != 0) { |
224 | 0aa6a4a2 | bellard | if (env->gpr[6] != 1 || env->gpr[7] != 0) { |
225 | 0aa6a4a2 | bellard | env->gpr[3] = 1; |
226 | 0aa6a4a2 | bellard | break;
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227 | 0aa6a4a2 | bellard | } |
228 | 0aa6a4a2 | bellard | } |
229 | 0aa6a4a2 | bellard | env->gpr[3] = 0; |
230 | 0aa6a4a2 | bellard | env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */ |
231 | 0aa6a4a2 | bellard | env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */ |
232 | 0aa6a4a2 | bellard | env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */ |
233 | 0aa6a4a2 | bellard | env->gpr[7] = 85 << 16; /* refresh rate */ |
234 | 0aa6a4a2 | bellard | env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */ |
235 | 0aa6a4a2 | bellard | linesize = ((graphic_depth + 7) >> 3) * graphic_width; |
236 | 0aa6a4a2 | bellard | linesize = (linesize + 3) & ~3; |
237 | 0aa6a4a2 | bellard | env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */ |
238 | 0aa6a4a2 | bellard | break;
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239 | 0aa6a4a2 | bellard | case 31: /* set_video power */ |
240 | 0aa6a4a2 | bellard | env->gpr[3] = 0; |
241 | 0aa6a4a2 | bellard | break;
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242 | 0aa6a4a2 | bellard | case 39: /* video_ctrl */ |
243 | 0aa6a4a2 | bellard | if (env->gpr[6] == 0 || env->gpr[6] == 1) |
244 | 0aa6a4a2 | bellard | vga_vbl_enabled = env->gpr[6];
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245 | 0aa6a4a2 | bellard | env->gpr[3] = 0; |
246 | 0aa6a4a2 | bellard | break;
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247 | 0aa6a4a2 | bellard | case 47: |
248 | 0aa6a4a2 | bellard | break;
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249 | 0aa6a4a2 | bellard | case 59: /* set_color */ |
250 | 0aa6a4a2 | bellard | /* R6 = index, R7 = RGB */
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251 | 0aa6a4a2 | bellard | env->gpr[3] = 0; |
252 | 0aa6a4a2 | bellard | break;
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253 | 0aa6a4a2 | bellard | case 64: /* get color */ |
254 | 0aa6a4a2 | bellard | /* R6 = index */
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255 | 0aa6a4a2 | bellard | env->gpr[3] = 0; |
256 | 0aa6a4a2 | bellard | break;
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257 | 0aa6a4a2 | bellard | case 116: /* set hwcursor */ |
258 | 0aa6a4a2 | bellard | /* R6 = x, R7 = y, R8 = visible, R9 = data */
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259 | 0aa6a4a2 | bellard | break;
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260 | 0aa6a4a2 | bellard | default:
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261 | 0aa6a4a2 | bellard | fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]); |
262 | 0aa6a4a2 | bellard | break;
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263 | 0aa6a4a2 | bellard | } |
264 | 0aa6a4a2 | bellard | return 1; /* osi_call handled */ |
265 | 0aa6a4a2 | bellard | } |
266 | 0aa6a4a2 | bellard | |
267 | 3de388f6 | bellard | /* XXX: suppress that */
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268 | 3de388f6 | bellard | static void pic_irq_request(void *opaque, int level) |
269 | 3de388f6 | bellard | { |
270 | 3de388f6 | bellard | } |
271 | 3de388f6 | bellard | |
272 | e5733356 | bellard | static uint8_t nvram_chksum(const uint8_t *buf, int n) |
273 | e5733356 | bellard | { |
274 | e5733356 | bellard | int sum, i;
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275 | e5733356 | bellard | sum = 0;
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276 | e5733356 | bellard | for(i = 0; i < n; i++) |
277 | e5733356 | bellard | sum += buf[i]; |
278 | e5733356 | bellard | return (sum & 0xff) + (sum >> 8); |
279 | e5733356 | bellard | } |
280 | e5733356 | bellard | |
281 | e5733356 | bellard | /* set a free Mac OS NVRAM partition */
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282 | e5733356 | bellard | void pmac_format_nvram_partition(uint8_t *buf, int len) |
283 | e5733356 | bellard | { |
284 | e5733356 | bellard | char partition_name[12] = "wwwwwwwwwwww"; |
285 | e5733356 | bellard | |
286 | e5733356 | bellard | buf[0] = 0x7f; /* free partition magic */ |
287 | e5733356 | bellard | buf[1] = 0; /* checksum */ |
288 | e5733356 | bellard | buf[2] = len >> 8; |
289 | e5733356 | bellard | buf[3] = len;
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290 | e5733356 | bellard | memcpy(buf + 4, partition_name, 12); |
291 | e5733356 | bellard | buf[1] = nvram_chksum(buf, 16); |
292 | e5733356 | bellard | } |
293 | e5733356 | bellard | |
294 | 0aa6a4a2 | bellard | /* PowerPC CHRP hardware initialisation */
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295 | 0aa6a4a2 | bellard | static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device, |
296 | 0aa6a4a2 | bellard | DisplayState *ds, const char **fd_filename, |
297 | 0aa6a4a2 | bellard | int snapshot,
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298 | 0aa6a4a2 | bellard | const char *kernel_filename, |
299 | 0aa6a4a2 | bellard | const char *kernel_cmdline, |
300 | 0aa6a4a2 | bellard | const char *initrd_filename, |
301 | 0aa6a4a2 | bellard | int is_heathrow)
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302 | 64201201 | bellard | { |
303 | c68ea704 | bellard | CPUState *env; |
304 | 64201201 | bellard | char buf[1024]; |
305 | 0aa6a4a2 | bellard | SetIRQFunc *set_irq; |
306 | 0aa6a4a2 | bellard | void *pic;
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307 | 64201201 | bellard | m48t59_t *nvram; |
308 | 0aa6a4a2 | bellard | int PPC_io_memory, unin_memory;
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309 | d5295253 | bellard | int linux_boot, i;
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310 | d5295253 | bellard | unsigned long bios_offset, vga_bios_offset; |
311 | b6b8bd18 | bellard | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
312 | 3fc6c082 | bellard | ppc_def_t *def; |
313 | 46e50e9d | bellard | PCIBus *pci_bus; |
314 | 0aa6a4a2 | bellard | const char *arch_name; |
315 | d5295253 | bellard | int vga_bios_size, bios_size;
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316 | 46e50e9d | bellard | |
317 | 64201201 | bellard | linux_boot = (kernel_filename != NULL);
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318 | 64201201 | bellard | |
319 | c68ea704 | bellard | /* init CPUs */
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320 | c68ea704 | bellard | env = cpu_init(); |
321 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
322 | c68ea704 | bellard | |
323 | c68ea704 | bellard | /* Register CPU as a 74x/75x */
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324 | c68ea704 | bellard | /* XXX: CPU model (or PVR) should be provided on command line */
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325 | c68ea704 | bellard | // ppc_find_by_name("750gx", &def); // Linux boot OK
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326 | c68ea704 | bellard | // ppc_find_by_name("750fx", &def); // Linux boot OK
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327 | c68ea704 | bellard | /* Linux does not boot on 750cxe (and probably other 750cx based)
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328 | c68ea704 | bellard | * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
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329 | c68ea704 | bellard | */
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330 | c68ea704 | bellard | // ppc_find_by_name("750cxe", &def);
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331 | c68ea704 | bellard | // ppc_find_by_name("750p", &def);
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332 | c68ea704 | bellard | // ppc_find_by_name("740p", &def);
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333 | c68ea704 | bellard | ppc_find_by_name("750", &def);
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334 | c68ea704 | bellard | // ppc_find_by_name("740", &def);
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335 | c68ea704 | bellard | // ppc_find_by_name("G3", &def);
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336 | c68ea704 | bellard | // ppc_find_by_name("604r", &def);
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337 | c68ea704 | bellard | // ppc_find_by_name("604e", &def);
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338 | c68ea704 | bellard | // ppc_find_by_name("604", &def);
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339 | c68ea704 | bellard | if (def == NULL) { |
340 | c68ea704 | bellard | cpu_abort(env, "Unable to find PowerPC CPU definition\n");
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341 | c68ea704 | bellard | } |
342 | c68ea704 | bellard | cpu_ppc_register(env, def); |
343 | c68ea704 | bellard | |
344 | c68ea704 | bellard | /* Set time-base frequency to 100 Mhz */
|
345 | c68ea704 | bellard | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
346 | c68ea704 | bellard | |
347 | c68ea704 | bellard | env->osi_call = vga_osi_call; |
348 | c68ea704 | bellard | |
349 | 64201201 | bellard | /* allocate RAM */
|
350 | 64201201 | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
351 | 64201201 | bellard | |
352 | 64201201 | bellard | /* allocate and load BIOS */
|
353 | 64201201 | bellard | bios_offset = ram_size + vga_ram_size; |
354 | 64201201 | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
355 | d5295253 | bellard | bios_size = load_image(buf, phys_ram_base + bios_offset); |
356 | d5295253 | bellard | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
357 | d5295253 | bellard | fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
|
358 | 64201201 | bellard | exit(1);
|
359 | 64201201 | bellard | } |
360 | d5295253 | bellard | bios_size = (bios_size + 0xfff) & ~0xfff; |
361 | d5295253 | bellard | cpu_register_physical_memory((uint32_t)(-bios_size), |
362 | d5295253 | bellard | bios_size, bios_offset | IO_MEM_ROM); |
363 | d5295253 | bellard | |
364 | d5295253 | bellard | /* allocate and load VGA BIOS */
|
365 | d5295253 | bellard | vga_bios_offset = bios_offset + bios_size; |
366 | d5295253 | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME); |
367 | d5295253 | bellard | vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
|
368 | d5295253 | bellard | if (vga_bios_size < 0) { |
369 | d5295253 | bellard | /* if no bios is present, we can still work */
|
370 | d5295253 | bellard | fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
|
371 | d5295253 | bellard | vga_bios_size = 0;
|
372 | d5295253 | bellard | } else {
|
373 | d5295253 | bellard | /* set a specific header (XXX: find real Apple format for NDRV
|
374 | d5295253 | bellard | drivers) */
|
375 | d5295253 | bellard | phys_ram_base[vga_bios_offset] = 'N';
|
376 | d5295253 | bellard | phys_ram_base[vga_bios_offset + 1] = 'D'; |
377 | d5295253 | bellard | phys_ram_base[vga_bios_offset + 2] = 'R'; |
378 | d5295253 | bellard | phys_ram_base[vga_bios_offset + 3] = 'V'; |
379 | d5295253 | bellard | cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
|
380 | d5295253 | bellard | vga_bios_size); |
381 | d5295253 | bellard | vga_bios_size += 8;
|
382 | d5295253 | bellard | } |
383 | d5295253 | bellard | vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff; |
384 | d5295253 | bellard | |
385 | b6b8bd18 | bellard | if (linux_boot) {
|
386 | b6b8bd18 | bellard | kernel_base = KERNEL_LOAD_ADDR; |
387 | b6b8bd18 | bellard | /* now we can load the kernel */
|
388 | b6b8bd18 | bellard | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
389 | b6b8bd18 | bellard | if (kernel_size < 0) { |
390 | b6b8bd18 | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
391 | b6b8bd18 | bellard | kernel_filename); |
392 | b6b8bd18 | bellard | exit(1);
|
393 | b6b8bd18 | bellard | } |
394 | b6b8bd18 | bellard | /* load initrd */
|
395 | b6b8bd18 | bellard | if (initrd_filename) {
|
396 | b6b8bd18 | bellard | initrd_base = INITRD_LOAD_ADDR; |
397 | b6b8bd18 | bellard | initrd_size = load_image(initrd_filename, |
398 | b6b8bd18 | bellard | phys_ram_base + initrd_base); |
399 | b6b8bd18 | bellard | if (initrd_size < 0) { |
400 | b6b8bd18 | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
401 | b6b8bd18 | bellard | initrd_filename); |
402 | b6b8bd18 | bellard | exit(1);
|
403 | b6b8bd18 | bellard | } |
404 | b6b8bd18 | bellard | } else {
|
405 | b6b8bd18 | bellard | initrd_base = 0;
|
406 | b6b8bd18 | bellard | initrd_size = 0;
|
407 | b6b8bd18 | bellard | } |
408 | b6b8bd18 | bellard | boot_device = 'm';
|
409 | b6b8bd18 | bellard | } else {
|
410 | b6b8bd18 | bellard | kernel_base = 0;
|
411 | b6b8bd18 | bellard | kernel_size = 0;
|
412 | b6b8bd18 | bellard | initrd_base = 0;
|
413 | b6b8bd18 | bellard | initrd_size = 0;
|
414 | b6b8bd18 | bellard | } |
415 | 0aa6a4a2 | bellard | |
416 | 0aa6a4a2 | bellard | if (is_heathrow) {
|
417 | 0aa6a4a2 | bellard | isa_mem_base = 0x80000000;
|
418 | 0aa6a4a2 | bellard | pci_bus = pci_grackle_init(0xfec00000);
|
419 | 0aa6a4a2 | bellard | |
420 | 0aa6a4a2 | bellard | /* Register 2 MB of ISA IO space */
|
421 | 0aa6a4a2 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL); |
422 | 0aa6a4a2 | bellard | cpu_register_physical_memory(0xfe000000, 0x00200000, PPC_io_memory); |
423 | 0aa6a4a2 | bellard | |
424 | 0aa6a4a2 | bellard | /* init basic PC hardware */
|
425 | d5295253 | bellard | vga_initialize(pci_bus, ds, phys_ram_base + ram_size, |
426 | d5295253 | bellard | ram_size, vga_ram_size, |
427 | d5295253 | bellard | vga_bios_offset, vga_bios_size); |
428 | 0aa6a4a2 | bellard | pic = heathrow_pic_init(&heathrow_pic_mem_index); |
429 | 0aa6a4a2 | bellard | set_irq = heathrow_pic_set_irq; |
430 | 0aa6a4a2 | bellard | pci_set_pic(pci_bus, set_irq, pic); |
431 | 0aa6a4a2 | bellard | |
432 | 0aa6a4a2 | bellard | /* XXX: suppress that */
|
433 | fa296b0f | bellard | isa_pic = pic_init(pic_irq_request, NULL);
|
434 | 0aa6a4a2 | bellard | |
435 | 0aa6a4a2 | bellard | /* XXX: use Mac Serial port */
|
436 | e5d13e2f | bellard | serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
437 | 0aa6a4a2 | bellard | |
438 | 0aa6a4a2 | bellard | for(i = 0; i < nb_nics; i++) { |
439 | a41b2ff2 | pbrook | if (!nd_table[i].model)
|
440 | a41b2ff2 | pbrook | nd_table[i].model = "ne2k_pci";
|
441 | a41b2ff2 | pbrook | pci_nic_init(pci_bus, &nd_table[i]); |
442 | 0aa6a4a2 | bellard | } |
443 | 0aa6a4a2 | bellard | |
444 | 0aa6a4a2 | bellard | pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); |
445 | 0aa6a4a2 | bellard | |
446 | 0aa6a4a2 | bellard | /* cuda also initialize ADB */
|
447 | 0aa6a4a2 | bellard | cuda_mem_index = cuda_init(set_irq, pic, 0x12);
|
448 | 0aa6a4a2 | bellard | |
449 | 0aa6a4a2 | bellard | adb_kbd_init(&adb_bus); |
450 | 0aa6a4a2 | bellard | adb_mouse_init(&adb_bus); |
451 | 0aa6a4a2 | bellard | |
452 | e5733356 | bellard | { |
453 | e5733356 | bellard | MacIONVRAMState *nvr; |
454 | e5733356 | bellard | nvr = macio_nvram_init(); |
455 | e5733356 | bellard | pmac_format_nvram_partition(nvr->data, 0x2000);
|
456 | e5733356 | bellard | } |
457 | e5733356 | bellard | |
458 | e5733356 | bellard | macio_init(pci_bus, 0x0017);
|
459 | 0aa6a4a2 | bellard | |
460 | 819385c5 | bellard | nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
461 | 0aa6a4a2 | bellard | |
462 | 0aa6a4a2 | bellard | arch_name = "HEATHROW";
|
463 | 0aa6a4a2 | bellard | } else {
|
464 | 0aa6a4a2 | bellard | isa_mem_base = 0x80000000;
|
465 | 0aa6a4a2 | bellard | pci_bus = pci_pmac_init(); |
466 | 0aa6a4a2 | bellard | |
467 | 0aa6a4a2 | bellard | /* Register 8 MB of ISA IO space */
|
468 | 0aa6a4a2 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL); |
469 | 0aa6a4a2 | bellard | cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory); |
470 | 0aa6a4a2 | bellard | |
471 | 0aa6a4a2 | bellard | /* UniN init */
|
472 | 0aa6a4a2 | bellard | unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL); |
473 | 0aa6a4a2 | bellard | cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory); |
474 | 0aa6a4a2 | bellard | |
475 | 0aa6a4a2 | bellard | /* init basic PC hardware */
|
476 | d5295253 | bellard | vga_initialize(pci_bus, ds, phys_ram_base + ram_size, |
477 | d5295253 | bellard | ram_size, vga_ram_size, |
478 | d5295253 | bellard | vga_bios_offset, vga_bios_size); |
479 | 7668a27f | bellard | pic = openpic_init(NULL, &openpic_mem_index, 1, &env); |
480 | 0aa6a4a2 | bellard | set_irq = openpic_set_irq; |
481 | 0aa6a4a2 | bellard | pci_set_pic(pci_bus, set_irq, pic); |
482 | 0aa6a4a2 | bellard | |
483 | 0aa6a4a2 | bellard | /* XXX: suppress that */
|
484 | fa296b0f | bellard | isa_pic = pic_init(pic_irq_request, NULL);
|
485 | 0aa6a4a2 | bellard | |
486 | 0aa6a4a2 | bellard | /* XXX: use Mac Serial port */
|
487 | e5d13e2f | bellard | serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
488 | 0aa6a4a2 | bellard | |
489 | 0aa6a4a2 | bellard | for(i = 0; i < nb_nics; i++) { |
490 | 0aa6a4a2 | bellard | pci_ne2000_init(pci_bus, &nd_table[i]); |
491 | 0aa6a4a2 | bellard | } |
492 | 0aa6a4a2 | bellard | |
493 | 0aa6a4a2 | bellard | #if 1 |
494 | 0aa6a4a2 | bellard | ide0_mem_index = pmac_ide_init(&bs_table[0], set_irq, pic, 0x13); |
495 | 0aa6a4a2 | bellard | ide1_mem_index = pmac_ide_init(&bs_table[2], set_irq, pic, 0x14); |
496 | 0aa6a4a2 | bellard | #else
|
497 | 0aa6a4a2 | bellard | pci_cmd646_ide_init(pci_bus, &bs_table[0], 0); |
498 | 0aa6a4a2 | bellard | #endif
|
499 | 0aa6a4a2 | bellard | /* cuda also initialize ADB */
|
500 | 0aa6a4a2 | bellard | cuda_mem_index = cuda_init(set_irq, pic, 0x19);
|
501 | 0aa6a4a2 | bellard | |
502 | 0aa6a4a2 | bellard | adb_kbd_init(&adb_bus); |
503 | 0aa6a4a2 | bellard | adb_mouse_init(&adb_bus); |
504 | 0aa6a4a2 | bellard | |
505 | e5733356 | bellard | macio_init(pci_bus, 0x0022);
|
506 | 0aa6a4a2 | bellard | |
507 | 819385c5 | bellard | nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59); |
508 | 0aa6a4a2 | bellard | |
509 | 0aa6a4a2 | bellard | arch_name = "MAC99";
|
510 | 64201201 | bellard | } |
511 | b6b8bd18 | bellard | |
512 | b6b8bd18 | bellard | if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) |
513 | b6b8bd18 | bellard | graphic_depth = 15;
|
514 | 64201201 | bellard | |
515 | 0aa6a4a2 | bellard | PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device, |
516 | b6b8bd18 | bellard | kernel_base, kernel_size, |
517 | b6b8bd18 | bellard | kernel_cmdline, |
518 | b6b8bd18 | bellard | initrd_base, initrd_size, |
519 | 64201201 | bellard | /* XXX: need an option to load a NVRAM image */
|
520 | b6b8bd18 | bellard | 0,
|
521 | b6b8bd18 | bellard | graphic_width, graphic_height, graphic_depth); |
522 | b6b8bd18 | bellard | /* No PCI init: the BIOS will do it */
|
523 | 0aa6a4a2 | bellard | |
524 | 0aa6a4a2 | bellard | /* Special port to get debug messages from Open-Firmware */
|
525 | 0aa6a4a2 | bellard | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
526 | 0aa6a4a2 | bellard | } |
527 | 0aa6a4a2 | bellard | |
528 | 0aa6a4a2 | bellard | static void ppc_core99_init(int ram_size, int vga_ram_size, int boot_device, |
529 | 0aa6a4a2 | bellard | DisplayState *ds, const char **fd_filename, |
530 | 0aa6a4a2 | bellard | int snapshot,
|
531 | 0aa6a4a2 | bellard | const char *kernel_filename, |
532 | 0aa6a4a2 | bellard | const char *kernel_cmdline, |
533 | 0aa6a4a2 | bellard | const char *initrd_filename) |
534 | 0aa6a4a2 | bellard | { |
535 | 0aa6a4a2 | bellard | ppc_chrp_init(ram_size, vga_ram_size, boot_device, |
536 | 0aa6a4a2 | bellard | ds, fd_filename, snapshot, |
537 | 0aa6a4a2 | bellard | kernel_filename, kernel_cmdline, |
538 | 0aa6a4a2 | bellard | initrd_filename, 0);
|
539 | 64201201 | bellard | } |
540 | 0aa6a4a2 | bellard | |
541 | 0aa6a4a2 | bellard | static void ppc_heathrow_init(int ram_size, int vga_ram_size, int boot_device, |
542 | 0aa6a4a2 | bellard | DisplayState *ds, const char **fd_filename, |
543 | 0aa6a4a2 | bellard | int snapshot,
|
544 | 0aa6a4a2 | bellard | const char *kernel_filename, |
545 | 0aa6a4a2 | bellard | const char *kernel_cmdline, |
546 | 0aa6a4a2 | bellard | const char *initrd_filename) |
547 | 0aa6a4a2 | bellard | { |
548 | 0aa6a4a2 | bellard | ppc_chrp_init(ram_size, vga_ram_size, boot_device, |
549 | 0aa6a4a2 | bellard | ds, fd_filename, snapshot, |
550 | 0aa6a4a2 | bellard | kernel_filename, kernel_cmdline, |
551 | 0aa6a4a2 | bellard | initrd_filename, 1);
|
552 | 0aa6a4a2 | bellard | } |
553 | 0aa6a4a2 | bellard | |
554 | 0aa6a4a2 | bellard | QEMUMachine core99_machine = { |
555 | 0289b2c1 | bellard | "mac99",
|
556 | 0289b2c1 | bellard | "Mac99 based PowerMAC",
|
557 | 0aa6a4a2 | bellard | ppc_core99_init, |
558 | 0aa6a4a2 | bellard | }; |
559 | 0aa6a4a2 | bellard | |
560 | 0aa6a4a2 | bellard | QEMUMachine heathrow_machine = { |
561 | 0289b2c1 | bellard | "g3bw",
|
562 | 0aa6a4a2 | bellard | "Heathrow based PowerMAC",
|
563 | 0aa6a4a2 | bellard | ppc_heathrow_init, |
564 | 0aa6a4a2 | bellard | }; |