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1 | 9a64fbe4 | bellard | /*
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2 | a541f297 | bellard | * QEMU PPC PREP hardware System Emulator
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3 | a541f297 | bellard | *
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4 | a541f297 | bellard | * Copyright (c) 2003-2004 Jocelyn Mayer
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5 | a541f297 | bellard | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | 9a64fbe4 | bellard | */
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24 | 9a64fbe4 | bellard | #include "vl.h" |
25 | 9fddaa0c | bellard | |
26 | 9a64fbe4 | bellard | //#define HARD_DEBUG_PPC_IO
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27 | a541f297 | bellard | //#define DEBUG_PPC_IO
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28 | 9a64fbe4 | bellard | |
29 | b6b8bd18 | bellard | #define BIOS_FILENAME "ppc_rom.bin" |
30 | b6b8bd18 | bellard | #define KERNEL_LOAD_ADDR 0x01000000 |
31 | b6b8bd18 | bellard | #define INITRD_LOAD_ADDR 0x01800000 |
32 | 64201201 | bellard | |
33 | 9a64fbe4 | bellard | extern int loglevel; |
34 | 9a64fbe4 | bellard | extern FILE *logfile;
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35 | 9a64fbe4 | bellard | |
36 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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37 | 9a64fbe4 | bellard | #define DEBUG_PPC_IO
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38 | 9a64fbe4 | bellard | #endif
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39 | 9a64fbe4 | bellard | |
40 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO)
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41 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) \
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42 | 9a64fbe4 | bellard | do { \
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43 | b6b8bd18 | bellard | if (loglevel & CPU_LOG_IOPORT) { \
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44 | 9a64fbe4 | bellard | fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
45 | 9a64fbe4 | bellard | } else { \
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46 | 9a64fbe4 | bellard | printf("%s : " fmt, __func__ , ##args); \ |
47 | 9a64fbe4 | bellard | } \ |
48 | 9a64fbe4 | bellard | } while (0) |
49 | 9a64fbe4 | bellard | #elif defined (DEBUG_PPC_IO)
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50 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) \
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51 | 9a64fbe4 | bellard | do { \
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52 | b6b8bd18 | bellard | if (loglevel & CPU_LOG_IOPORT) { \
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53 | 9a64fbe4 | bellard | fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
54 | 9a64fbe4 | bellard | } \ |
55 | 9a64fbe4 | bellard | } while (0) |
56 | 9a64fbe4 | bellard | #else
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57 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) do { } while (0) |
58 | 9a64fbe4 | bellard | #endif
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59 | 9a64fbe4 | bellard | |
60 | 64201201 | bellard | /* Constants for devices init */
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61 | a541f297 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
62 | a541f297 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
63 | a541f297 | bellard | static const int ide_irq[2] = { 13, 13 }; |
64 | a541f297 | bellard | |
65 | a541f297 | bellard | #define NE2000_NB_MAX 6 |
66 | a541f297 | bellard | |
67 | a541f297 | bellard | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
68 | a541f297 | bellard | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
69 | 9a64fbe4 | bellard | |
70 | 64201201 | bellard | //static PITState *pit;
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71 | 64201201 | bellard | |
72 | 64201201 | bellard | /* ISA IO ports bridge */
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73 | 9a64fbe4 | bellard | #define PPC_IO_BASE 0x80000000 |
74 | 9a64fbe4 | bellard | |
75 | 64201201 | bellard | /* Speaker port 0x61 */
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76 | 64201201 | bellard | int speaker_data_on;
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77 | 64201201 | bellard | int dummy_refresh_clock;
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78 | 64201201 | bellard | |
79 | 64201201 | bellard | static void speaker_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
80 | 9a64fbe4 | bellard | { |
81 | a541f297 | bellard | #if 0
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82 | 64201201 | bellard | speaker_data_on = (val >> 1) & 1;
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83 | 64201201 | bellard | pit_set_gate(pit, 2, val & 1);
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84 | a541f297 | bellard | #endif
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85 | 9a64fbe4 | bellard | } |
86 | 9a64fbe4 | bellard | |
87 | 64201201 | bellard | static uint32_t speaker_ioport_read(void *opaque, uint32_t addr) |
88 | 9a64fbe4 | bellard | { |
89 | a541f297 | bellard | #if 0
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90 | 64201201 | bellard | int out;
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91 | 64201201 | bellard | out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
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92 | 64201201 | bellard | dummy_refresh_clock ^= 1;
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93 | 64201201 | bellard | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
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94 | 64201201 | bellard | (dummy_refresh_clock << 4);
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95 | a541f297 | bellard | #endif
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96 | 64201201 | bellard | return 0; |
97 | 9a64fbe4 | bellard | } |
98 | 9a64fbe4 | bellard | |
99 | 3de388f6 | bellard | static void pic_irq_request(void *opaque, int level) |
100 | 3de388f6 | bellard | { |
101 | 3de388f6 | bellard | if (level)
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102 | c68ea704 | bellard | cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
103 | 3de388f6 | bellard | else
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104 | c68ea704 | bellard | cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
105 | 3de388f6 | bellard | } |
106 | 3de388f6 | bellard | |
107 | 64201201 | bellard | /* PCI intack register */
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108 | 64201201 | bellard | /* Read-only register (?) */
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109 | a4193c8a | bellard | static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value) |
110 | 64201201 | bellard | { |
111 | 64201201 | bellard | // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
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112 | 64201201 | bellard | } |
113 | 64201201 | bellard | |
114 | 64201201 | bellard | static inline uint32_t _PPC_intack_read (target_phys_addr_t addr) |
115 | 64201201 | bellard | { |
116 | 64201201 | bellard | uint32_t retval = 0;
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117 | 64201201 | bellard | |
118 | 64201201 | bellard | if (addr == 0xBFFFFFF0) |
119 | 3de388f6 | bellard | retval = pic_intack_read(isa_pic); |
120 | 64201201 | bellard | // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
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121 | 64201201 | bellard | |
122 | 64201201 | bellard | return retval;
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123 | 64201201 | bellard | } |
124 | 64201201 | bellard | |
125 | a4193c8a | bellard | static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
126 | 64201201 | bellard | { |
127 | 64201201 | bellard | return _PPC_intack_read(addr);
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128 | 64201201 | bellard | } |
129 | 64201201 | bellard | |
130 | a4193c8a | bellard | static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
131 | 9a64fbe4 | bellard | { |
132 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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133 | 64201201 | bellard | return bswap16(_PPC_intack_read(addr));
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134 | 64201201 | bellard | #else
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135 | 64201201 | bellard | return _PPC_intack_read(addr);
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136 | f658b4db | bellard | #endif
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137 | 9a64fbe4 | bellard | } |
138 | 9a64fbe4 | bellard | |
139 | a4193c8a | bellard | static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
140 | 9a64fbe4 | bellard | { |
141 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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142 | 64201201 | bellard | return bswap32(_PPC_intack_read(addr));
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143 | 64201201 | bellard | #else
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144 | 64201201 | bellard | return _PPC_intack_read(addr);
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145 | f658b4db | bellard | #endif
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146 | 9a64fbe4 | bellard | } |
147 | 9a64fbe4 | bellard | |
148 | 64201201 | bellard | static CPUWriteMemoryFunc *PPC_intack_write[] = {
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149 | 64201201 | bellard | &_PPC_intack_write, |
150 | 64201201 | bellard | &_PPC_intack_write, |
151 | 64201201 | bellard | &_PPC_intack_write, |
152 | 64201201 | bellard | }; |
153 | 64201201 | bellard | |
154 | 64201201 | bellard | static CPUReadMemoryFunc *PPC_intack_read[] = {
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155 | 64201201 | bellard | &PPC_intack_readb, |
156 | 64201201 | bellard | &PPC_intack_readw, |
157 | 64201201 | bellard | &PPC_intack_readl, |
158 | 64201201 | bellard | }; |
159 | 64201201 | bellard | |
160 | 64201201 | bellard | /* PowerPC control and status registers */
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161 | 64201201 | bellard | #if 0 // Not used
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162 | 64201201 | bellard | static struct {
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163 | 64201201 | bellard | /* IDs */
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164 | 64201201 | bellard | uint32_t veni_devi;
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165 | 64201201 | bellard | uint32_t revi;
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166 | 64201201 | bellard | /* Control and status */
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167 | 64201201 | bellard | uint32_t gcsr;
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168 | 64201201 | bellard | uint32_t xcfr;
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169 | 64201201 | bellard | uint32_t ct32;
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170 | 64201201 | bellard | uint32_t mcsr;
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171 | 64201201 | bellard | /* General purpose registers */
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172 | 64201201 | bellard | uint32_t gprg[6];
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173 | 64201201 | bellard | /* Exceptions */
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174 | 64201201 | bellard | uint32_t feen;
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175 | 64201201 | bellard | uint32_t fest;
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176 | 64201201 | bellard | uint32_t fema;
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177 | 64201201 | bellard | uint32_t fecl;
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178 | 64201201 | bellard | uint32_t eeen;
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179 | 64201201 | bellard | uint32_t eest;
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180 | 64201201 | bellard | uint32_t eecl;
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181 | 64201201 | bellard | uint32_t eeint;
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182 | 64201201 | bellard | uint32_t eemck0;
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183 | 64201201 | bellard | uint32_t eemck1;
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184 | 64201201 | bellard | /* Error diagnostic */
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185 | 64201201 | bellard | } XCSR;
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186 | 64201201 | bellard | |
187 | a4193c8a | bellard | static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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188 | 64201201 | bellard | {
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189 | 64201201 | bellard | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
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190 | 64201201 | bellard | }
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191 | 64201201 | bellard | |
192 | a4193c8a | bellard | static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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193 | 9a64fbe4 | bellard | {
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194 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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195 | 64201201 | bellard | value = bswap16(value);
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196 | f658b4db | bellard | #endif
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197 | 64201201 | bellard | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
198 | 9a64fbe4 | bellard | } |
199 | 9a64fbe4 | bellard | |
200 | a4193c8a | bellard | static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
201 | 9a64fbe4 | bellard | { |
202 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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203 | 64201201 | bellard | value = bswap32(value); |
204 | f658b4db | bellard | #endif
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205 | 64201201 | bellard | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
206 | 9a64fbe4 | bellard | } |
207 | 9a64fbe4 | bellard | |
208 | a4193c8a | bellard | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
209 | 64201201 | bellard | { |
210 | 64201201 | bellard | uint32_t retval = 0;
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211 | 9a64fbe4 | bellard | |
212 | 64201201 | bellard | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
213 | 9a64fbe4 | bellard | |
214 | 64201201 | bellard | return retval;
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215 | 64201201 | bellard | } |
216 | 64201201 | bellard | |
217 | a4193c8a | bellard | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
218 | 9a64fbe4 | bellard | { |
219 | 64201201 | bellard | uint32_t retval = 0;
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220 | 64201201 | bellard | |
221 | 64201201 | bellard | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
222 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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223 | 64201201 | bellard | retval = bswap16(retval); |
224 | 64201201 | bellard | #endif
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225 | 64201201 | bellard | |
226 | 64201201 | bellard | return retval;
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227 | 9a64fbe4 | bellard | } |
228 | 9a64fbe4 | bellard | |
229 | a4193c8a | bellard | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
230 | 9a64fbe4 | bellard | { |
231 | 9a64fbe4 | bellard | uint32_t retval = 0;
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232 | 9a64fbe4 | bellard | |
233 | 64201201 | bellard | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
234 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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235 | 64201201 | bellard | retval = bswap32(retval); |
236 | 64201201 | bellard | #endif
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237 | 9a64fbe4 | bellard | |
238 | 9a64fbe4 | bellard | return retval;
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239 | 9a64fbe4 | bellard | } |
240 | 9a64fbe4 | bellard | |
241 | 64201201 | bellard | static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
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242 | 64201201 | bellard | &PPC_XCSR_writeb, |
243 | 64201201 | bellard | &PPC_XCSR_writew, |
244 | 64201201 | bellard | &PPC_XCSR_writel, |
245 | 9a64fbe4 | bellard | }; |
246 | 9a64fbe4 | bellard | |
247 | 64201201 | bellard | static CPUReadMemoryFunc *PPC_XCSR_read[] = {
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248 | 64201201 | bellard | &PPC_XCSR_readb, |
249 | 64201201 | bellard | &PPC_XCSR_readw, |
250 | 64201201 | bellard | &PPC_XCSR_readl, |
251 | 9a64fbe4 | bellard | }; |
252 | b6b8bd18 | bellard | #endif
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253 | 9a64fbe4 | bellard | |
254 | 64201201 | bellard | /* Fake super-io ports for PREP platform (Intel 82378ZB) */
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255 | 64201201 | bellard | typedef struct sysctrl_t { |
256 | 64201201 | bellard | m48t59_t *nvram; |
257 | 64201201 | bellard | uint8_t state; |
258 | 64201201 | bellard | uint8_t syscontrol; |
259 | 64201201 | bellard | uint8_t fake_io[2];
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260 | da9b266b | bellard | int contiguous_map;
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261 | fb3444b8 | bellard | int endian;
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262 | 64201201 | bellard | } sysctrl_t; |
263 | 9a64fbe4 | bellard | |
264 | 64201201 | bellard | enum {
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265 | 64201201 | bellard | STATE_HARDFILE = 0x01,
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266 | 9a64fbe4 | bellard | }; |
267 | 9a64fbe4 | bellard | |
268 | 64201201 | bellard | static sysctrl_t *sysctrl;
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269 | 9a64fbe4 | bellard | |
270 | a541f297 | bellard | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
271 | 9a64fbe4 | bellard | { |
272 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
273 | 64201201 | bellard | |
274 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); |
275 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398] = val;
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276 | 9a64fbe4 | bellard | } |
277 | 9a64fbe4 | bellard | |
278 | a541f297 | bellard | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
279 | 9a64fbe4 | bellard | { |
280 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
281 | 9a64fbe4 | bellard | |
282 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, |
283 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398]);
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284 | 64201201 | bellard | return sysctrl->fake_io[addr - 0x0398]; |
285 | 64201201 | bellard | } |
286 | 9a64fbe4 | bellard | |
287 | a541f297 | bellard | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
288 | 9a64fbe4 | bellard | { |
289 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
290 | 64201201 | bellard | |
291 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); |
292 | 9a64fbe4 | bellard | switch (addr) {
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293 | 9a64fbe4 | bellard | case 0x0092: |
294 | 9a64fbe4 | bellard | /* Special port 92 */
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295 | 9a64fbe4 | bellard | /* Check soft reset asked */
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296 | 64201201 | bellard | if (val & 0x01) { |
297 | c68ea704 | bellard | // cpu_interrupt(first_cpu, CPU_INTERRUPT_RESET);
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298 | 9a64fbe4 | bellard | } |
299 | 9a64fbe4 | bellard | /* Check LE mode */
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300 | 64201201 | bellard | if (val & 0x02) { |
301 | fb3444b8 | bellard | sysctrl->endian = 1;
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302 | fb3444b8 | bellard | } else {
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303 | fb3444b8 | bellard | sysctrl->endian = 0;
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304 | 9a64fbe4 | bellard | } |
305 | 9a64fbe4 | bellard | break;
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306 | 64201201 | bellard | case 0x0800: |
307 | 64201201 | bellard | /* Motorola CPU configuration register : read-only */
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308 | 64201201 | bellard | break;
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309 | 64201201 | bellard | case 0x0802: |
310 | 64201201 | bellard | /* Motorola base module feature register : read-only */
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311 | 64201201 | bellard | break;
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312 | 64201201 | bellard | case 0x0803: |
313 | 64201201 | bellard | /* Motorola base module status register : read-only */
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314 | 64201201 | bellard | break;
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315 | 9a64fbe4 | bellard | case 0x0808: |
316 | 64201201 | bellard | /* Hardfile light register */
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317 | 64201201 | bellard | if (val & 1) |
318 | 64201201 | bellard | sysctrl->state |= STATE_HARDFILE; |
319 | 64201201 | bellard | else
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320 | 64201201 | bellard | sysctrl->state &= ~STATE_HARDFILE; |
321 | 9a64fbe4 | bellard | break;
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322 | 9a64fbe4 | bellard | case 0x0810: |
323 | 9a64fbe4 | bellard | /* Password protect 1 register */
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324 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
325 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 1);
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326 | 9a64fbe4 | bellard | break;
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327 | 9a64fbe4 | bellard | case 0x0812: |
328 | 9a64fbe4 | bellard | /* Password protect 2 register */
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329 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
330 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 2);
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331 | 9a64fbe4 | bellard | break;
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332 | 9a64fbe4 | bellard | case 0x0814: |
333 | 64201201 | bellard | /* L2 invalidate register */
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334 | c68ea704 | bellard | // tlb_flush(first_cpu, 1);
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335 | 9a64fbe4 | bellard | break;
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336 | 9a64fbe4 | bellard | case 0x081C: |
337 | 9a64fbe4 | bellard | /* system control register */
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338 | 64201201 | bellard | sysctrl->syscontrol = val & 0x0F;
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339 | 9a64fbe4 | bellard | break;
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340 | 9a64fbe4 | bellard | case 0x0850: |
341 | 9a64fbe4 | bellard | /* I/O map type register */
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342 | da9b266b | bellard | sysctrl->contiguous_map = val & 0x01;
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343 | 9a64fbe4 | bellard | break;
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344 | 9a64fbe4 | bellard | default:
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345 | 64201201 | bellard | printf("ERROR: unaffected IO port write: %04lx => %02x\n",
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346 | 64201201 | bellard | (long)addr, val);
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347 | 9a64fbe4 | bellard | break;
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348 | 9a64fbe4 | bellard | } |
349 | 9a64fbe4 | bellard | } |
350 | 9a64fbe4 | bellard | |
351 | a541f297 | bellard | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
352 | 9a64fbe4 | bellard | { |
353 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
354 | 9a64fbe4 | bellard | uint32_t retval = 0xFF;
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355 | 9a64fbe4 | bellard | |
356 | 9a64fbe4 | bellard | switch (addr) {
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357 | 9a64fbe4 | bellard | case 0x0092: |
358 | 9a64fbe4 | bellard | /* Special port 92 */
|
359 | 64201201 | bellard | retval = 0x00;
|
360 | 64201201 | bellard | break;
|
361 | 64201201 | bellard | case 0x0800: |
362 | 64201201 | bellard | /* Motorola CPU configuration register */
|
363 | 64201201 | bellard | retval = 0xEF; /* MPC750 */ |
364 | 64201201 | bellard | break;
|
365 | 64201201 | bellard | case 0x0802: |
366 | 64201201 | bellard | /* Motorola Base module feature register */
|
367 | 64201201 | bellard | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
368 | 64201201 | bellard | break;
|
369 | 64201201 | bellard | case 0x0803: |
370 | 64201201 | bellard | /* Motorola base module status register */
|
371 | 64201201 | bellard | retval = 0xE0; /* Standard MPC750 */ |
372 | 9a64fbe4 | bellard | break;
|
373 | 9a64fbe4 | bellard | case 0x080C: |
374 | 9a64fbe4 | bellard | /* Equipment present register:
|
375 | 9a64fbe4 | bellard | * no L2 cache
|
376 | 9a64fbe4 | bellard | * no upgrade processor
|
377 | 9a64fbe4 | bellard | * no cards in PCI slots
|
378 | 9a64fbe4 | bellard | * SCSI fuse is bad
|
379 | 9a64fbe4 | bellard | */
|
380 | 64201201 | bellard | retval = 0x3C;
|
381 | 64201201 | bellard | break;
|
382 | 64201201 | bellard | case 0x0810: |
383 | 64201201 | bellard | /* Motorola base module extended feature register */
|
384 | 64201201 | bellard | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
385 | 9a64fbe4 | bellard | break;
|
386 | da9b266b | bellard | case 0x0814: |
387 | da9b266b | bellard | /* L2 invalidate: don't care */
|
388 | da9b266b | bellard | break;
|
389 | 9a64fbe4 | bellard | case 0x0818: |
390 | 9a64fbe4 | bellard | /* Keylock */
|
391 | 9a64fbe4 | bellard | retval = 0x00;
|
392 | 9a64fbe4 | bellard | break;
|
393 | 9a64fbe4 | bellard | case 0x081C: |
394 | 9a64fbe4 | bellard | /* system control register
|
395 | 9a64fbe4 | bellard | * 7 - 6 / 1 - 0: L2 cache enable
|
396 | 9a64fbe4 | bellard | */
|
397 | 64201201 | bellard | retval = sysctrl->syscontrol; |
398 | 9a64fbe4 | bellard | break;
|
399 | 9a64fbe4 | bellard | case 0x0823: |
400 | 9a64fbe4 | bellard | /* */
|
401 | 9a64fbe4 | bellard | retval = 0x03; /* no L2 cache */ |
402 | 9a64fbe4 | bellard | break;
|
403 | 9a64fbe4 | bellard | case 0x0850: |
404 | 9a64fbe4 | bellard | /* I/O map type register */
|
405 | da9b266b | bellard | retval = sysctrl->contiguous_map; |
406 | 9a64fbe4 | bellard | break;
|
407 | 9a64fbe4 | bellard | default:
|
408 | 64201201 | bellard | printf("ERROR: unaffected IO port: %04lx read\n", (long)addr); |
409 | 9a64fbe4 | bellard | break;
|
410 | 9a64fbe4 | bellard | } |
411 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval); |
412 | 9a64fbe4 | bellard | |
413 | 9a64fbe4 | bellard | return retval;
|
414 | 9a64fbe4 | bellard | } |
415 | 9a64fbe4 | bellard | |
416 | da9b266b | bellard | static inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl, |
417 | da9b266b | bellard | target_phys_addr_t addr) |
418 | da9b266b | bellard | { |
419 | da9b266b | bellard | if (sysctrl->contiguous_map == 0) { |
420 | da9b266b | bellard | /* 64 KB contiguous space for IOs */
|
421 | da9b266b | bellard | addr &= 0xFFFF;
|
422 | da9b266b | bellard | } else {
|
423 | da9b266b | bellard | /* 8 MB non-contiguous space for IOs */
|
424 | da9b266b | bellard | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
425 | da9b266b | bellard | } |
426 | da9b266b | bellard | |
427 | da9b266b | bellard | return addr;
|
428 | da9b266b | bellard | } |
429 | da9b266b | bellard | |
430 | da9b266b | bellard | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
431 | da9b266b | bellard | uint32_t value) |
432 | da9b266b | bellard | { |
433 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
434 | da9b266b | bellard | |
435 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
436 | da9b266b | bellard | cpu_outb(NULL, addr, value);
|
437 | da9b266b | bellard | } |
438 | da9b266b | bellard | |
439 | da9b266b | bellard | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
440 | da9b266b | bellard | { |
441 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
442 | da9b266b | bellard | uint32_t ret; |
443 | da9b266b | bellard | |
444 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
445 | da9b266b | bellard | ret = cpu_inb(NULL, addr);
|
446 | da9b266b | bellard | |
447 | da9b266b | bellard | return ret;
|
448 | da9b266b | bellard | } |
449 | da9b266b | bellard | |
450 | da9b266b | bellard | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
451 | da9b266b | bellard | uint32_t value) |
452 | da9b266b | bellard | { |
453 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
454 | da9b266b | bellard | |
455 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
456 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
457 | da9b266b | bellard | value = bswap16(value); |
458 | da9b266b | bellard | #endif
|
459 | da9b266b | bellard | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value); |
460 | da9b266b | bellard | cpu_outw(NULL, addr, value);
|
461 | da9b266b | bellard | } |
462 | da9b266b | bellard | |
463 | da9b266b | bellard | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
464 | da9b266b | bellard | { |
465 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
466 | da9b266b | bellard | uint32_t ret; |
467 | da9b266b | bellard | |
468 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
469 | da9b266b | bellard | ret = cpu_inw(NULL, addr);
|
470 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
471 | da9b266b | bellard | ret = bswap16(ret); |
472 | da9b266b | bellard | #endif
|
473 | da9b266b | bellard | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret); |
474 | da9b266b | bellard | |
475 | da9b266b | bellard | return ret;
|
476 | da9b266b | bellard | } |
477 | da9b266b | bellard | |
478 | da9b266b | bellard | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
479 | da9b266b | bellard | uint32_t value) |
480 | da9b266b | bellard | { |
481 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
482 | da9b266b | bellard | |
483 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
484 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
485 | da9b266b | bellard | value = bswap32(value); |
486 | da9b266b | bellard | #endif
|
487 | da9b266b | bellard | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value); |
488 | da9b266b | bellard | cpu_outl(NULL, addr, value);
|
489 | da9b266b | bellard | } |
490 | da9b266b | bellard | |
491 | da9b266b | bellard | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
492 | da9b266b | bellard | { |
493 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
494 | da9b266b | bellard | uint32_t ret; |
495 | da9b266b | bellard | |
496 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
497 | da9b266b | bellard | ret = cpu_inl(NULL, addr);
|
498 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
499 | da9b266b | bellard | ret = bswap32(ret); |
500 | da9b266b | bellard | #endif
|
501 | da9b266b | bellard | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret); |
502 | da9b266b | bellard | |
503 | da9b266b | bellard | return ret;
|
504 | da9b266b | bellard | } |
505 | da9b266b | bellard | |
506 | da9b266b | bellard | CPUWriteMemoryFunc *PPC_prep_io_write[] = { |
507 | da9b266b | bellard | &PPC_prep_io_writeb, |
508 | da9b266b | bellard | &PPC_prep_io_writew, |
509 | da9b266b | bellard | &PPC_prep_io_writel, |
510 | da9b266b | bellard | }; |
511 | da9b266b | bellard | |
512 | da9b266b | bellard | CPUReadMemoryFunc *PPC_prep_io_read[] = { |
513 | da9b266b | bellard | &PPC_prep_io_readb, |
514 | da9b266b | bellard | &PPC_prep_io_readw, |
515 | da9b266b | bellard | &PPC_prep_io_readl, |
516 | da9b266b | bellard | }; |
517 | da9b266b | bellard | |
518 | 64201201 | bellard | #define NVRAM_SIZE 0x2000 |
519 | a541f297 | bellard | |
520 | 26aa7d72 | bellard | /* PowerPC PREP hardware initialisation */
|
521 | c0e564d5 | bellard | static void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, |
522 | c0e564d5 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
523 | c0e564d5 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
524 | c0e564d5 | bellard | const char *initrd_filename) |
525 | a541f297 | bellard | { |
526 | c68ea704 | bellard | CPUState *env; |
527 | a541f297 | bellard | char buf[1024]; |
528 | e5d13e2f | bellard | SetIRQFunc *set_irq; |
529 | 64201201 | bellard | m48t59_t *nvram; |
530 | a541f297 | bellard | int PPC_io_memory;
|
531 | 4157a662 | bellard | int linux_boot, i, nb_nics1, bios_size;
|
532 | 64201201 | bellard | unsigned long bios_offset; |
533 | 64201201 | bellard | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
534 | 3fc6c082 | bellard | ppc_def_t *def; |
535 | 46e50e9d | bellard | PCIBus *pci_bus; |
536 | 64201201 | bellard | |
537 | 64201201 | bellard | sysctrl = qemu_mallocz(sizeof(sysctrl_t));
|
538 | 64201201 | bellard | if (sysctrl == NULL) |
539 | 64201201 | bellard | return;
|
540 | a541f297 | bellard | |
541 | a541f297 | bellard | linux_boot = (kernel_filename != NULL);
|
542 | c68ea704 | bellard | |
543 | c68ea704 | bellard | /* init CPUs */
|
544 | c68ea704 | bellard | |
545 | c68ea704 | bellard | env = cpu_init(); |
546 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
547 | c68ea704 | bellard | |
548 | c68ea704 | bellard | /* Register CPU as a 604 */
|
549 | c68ea704 | bellard | /* XXX: CPU model (or PVR) should be provided on command line */
|
550 | c68ea704 | bellard | // ppc_find_by_name("604r", &def);
|
551 | c68ea704 | bellard | // ppc_find_by_name("604e", &def);
|
552 | c68ea704 | bellard | ppc_find_by_name("604", &def);
|
553 | c68ea704 | bellard | if (def == NULL) { |
554 | c68ea704 | bellard | cpu_abort(env, "Unable to find PowerPC CPU definition\n");
|
555 | c68ea704 | bellard | } |
556 | c68ea704 | bellard | cpu_ppc_register(env, def); |
557 | c68ea704 | bellard | /* Set time-base frequency to 100 Mhz */
|
558 | c68ea704 | bellard | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
559 | a541f297 | bellard | |
560 | a541f297 | bellard | /* allocate RAM */
|
561 | 64201201 | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
562 | 64201201 | bellard | |
563 | 64201201 | bellard | /* allocate and load BIOS */
|
564 | 64201201 | bellard | bios_offset = ram_size + vga_ram_size; |
565 | 64201201 | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
566 | 4157a662 | bellard | bios_size = load_image(buf, phys_ram_base + bios_offset); |
567 | 4157a662 | bellard | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
568 | 64201201 | bellard | fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
|
569 | 64201201 | bellard | exit(1);
|
570 | 64201201 | bellard | } |
571 | 4157a662 | bellard | bios_size = (bios_size + 0xfff) & ~0xfff; |
572 | 4157a662 | bellard | cpu_register_physical_memory((uint32_t)(-bios_size), |
573 | 4157a662 | bellard | bios_size, bios_offset | IO_MEM_ROM); |
574 | 26aa7d72 | bellard | |
575 | a541f297 | bellard | if (linux_boot) {
|
576 | 64201201 | bellard | kernel_base = KERNEL_LOAD_ADDR; |
577 | a541f297 | bellard | /* now we can load the kernel */
|
578 | 64201201 | bellard | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
579 | 64201201 | bellard | if (kernel_size < 0) { |
580 | a541f297 | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
581 | a541f297 | bellard | kernel_filename); |
582 | a541f297 | bellard | exit(1);
|
583 | a541f297 | bellard | } |
584 | a541f297 | bellard | /* load initrd */
|
585 | a541f297 | bellard | if (initrd_filename) {
|
586 | 64201201 | bellard | initrd_base = INITRD_LOAD_ADDR; |
587 | 64201201 | bellard | initrd_size = load_image(initrd_filename, |
588 | 64201201 | bellard | phys_ram_base + initrd_base); |
589 | a541f297 | bellard | if (initrd_size < 0) { |
590 | a541f297 | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
591 | a541f297 | bellard | initrd_filename); |
592 | a541f297 | bellard | exit(1);
|
593 | a541f297 | bellard | } |
594 | 64201201 | bellard | } else {
|
595 | 64201201 | bellard | initrd_base = 0;
|
596 | 64201201 | bellard | initrd_size = 0;
|
597 | a541f297 | bellard | } |
598 | 64201201 | bellard | boot_device = 'm';
|
599 | a541f297 | bellard | } else {
|
600 | 64201201 | bellard | kernel_base = 0;
|
601 | 64201201 | bellard | kernel_size = 0;
|
602 | 64201201 | bellard | initrd_base = 0;
|
603 | 64201201 | bellard | initrd_size = 0;
|
604 | a541f297 | bellard | } |
605 | a541f297 | bellard | |
606 | 64201201 | bellard | isa_mem_base = 0xc0000000;
|
607 | 46e50e9d | bellard | pci_bus = pci_prep_init(); |
608 | da9b266b | bellard | // pci_bus = i440fx_init();
|
609 | da9b266b | bellard | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
610 | da9b266b | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
|
611 | da9b266b | bellard | PPC_prep_io_write, sysctrl); |
612 | da9b266b | bellard | cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); |
613 | 64201201 | bellard | |
614 | a541f297 | bellard | /* init basic PC hardware */
|
615 | 46e50e9d | bellard | vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size, |
616 | fb3444b8 | bellard | vga_ram_size, 0, 0); |
617 | a541f297 | bellard | rtc_init(0x70, 8); |
618 | 64201201 | bellard | // openpic = openpic_init(0x00000000, 0xF0000000, 1);
|
619 | c68ea704 | bellard | isa_pic = pic_init(pic_irq_request, first_cpu); |
620 | 64201201 | bellard | // pit = pit_init(0x40, 0);
|
621 | a541f297 | bellard | |
622 | e5d13e2f | bellard | serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
623 | a541f297 | bellard | nb_nics1 = nb_nics; |
624 | a541f297 | bellard | if (nb_nics1 > NE2000_NB_MAX)
|
625 | a541f297 | bellard | nb_nics1 = NE2000_NB_MAX; |
626 | a541f297 | bellard | for(i = 0; i < nb_nics1; i++) { |
627 | a41b2ff2 | pbrook | if (nd_table[0].model == NULL |
628 | a41b2ff2 | pbrook | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
629 | a41b2ff2 | pbrook | isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]); |
630 | a41b2ff2 | pbrook | } else {
|
631 | a41b2ff2 | pbrook | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
632 | a41b2ff2 | pbrook | exit (1);
|
633 | a41b2ff2 | pbrook | } |
634 | a541f297 | bellard | } |
635 | a541f297 | bellard | |
636 | a541f297 | bellard | for(i = 0; i < 2; i++) { |
637 | 69b91039 | bellard | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
638 | 69b91039 | bellard | bs_table[2 * i], bs_table[2 * i + 1]); |
639 | a541f297 | bellard | } |
640 | a541f297 | bellard | kbd_init(); |
641 | b6b8bd18 | bellard | DMA_init(1);
|
642 | 64201201 | bellard | // AUD_init();
|
643 | a541f297 | bellard | // SB16_init();
|
644 | a541f297 | bellard | |
645 | a541f297 | bellard | fdctrl_init(6, 2, 0, 0x3f0, fd_table); |
646 | a541f297 | bellard | |
647 | 64201201 | bellard | /* Register speaker port */
|
648 | 64201201 | bellard | register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); |
649 | 64201201 | bellard | register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); |
650 | a541f297 | bellard | /* Register fake IO ports for PREP */
|
651 | 64201201 | bellard | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
652 | 64201201 | bellard | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
653 | a541f297 | bellard | /* System control ports */
|
654 | 64201201 | bellard | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
655 | 64201201 | bellard | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
656 | 64201201 | bellard | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
657 | 64201201 | bellard | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
658 | 64201201 | bellard | /* PCI intack location */
|
659 | 64201201 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
|
660 | a4193c8a | bellard | PPC_intack_write, NULL);
|
661 | a541f297 | bellard | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
662 | 64201201 | bellard | /* PowerPC control and status register group */
|
663 | b6b8bd18 | bellard | #if 0
|
664 | a4193c8a | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
|
665 | 64201201 | bellard | cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
|
666 | b6b8bd18 | bellard | #endif
|
667 | a541f297 | bellard | |
668 | 819385c5 | bellard | nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59); |
669 | 64201201 | bellard | if (nvram == NULL) |
670 | 64201201 | bellard | return;
|
671 | 64201201 | bellard | sysctrl->nvram = nvram; |
672 | 64201201 | bellard | |
673 | 64201201 | bellard | /* Initialise NVRAM */
|
674 | 64201201 | bellard | PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
|
675 | 64201201 | bellard | kernel_base, kernel_size, |
676 | b6b8bd18 | bellard | kernel_cmdline, |
677 | 64201201 | bellard | initrd_base, initrd_size, |
678 | 64201201 | bellard | /* XXX: need an option to load a NVRAM image */
|
679 | b6b8bd18 | bellard | 0,
|
680 | b6b8bd18 | bellard | graphic_width, graphic_height, graphic_depth); |
681 | c0e564d5 | bellard | |
682 | c0e564d5 | bellard | /* Special port to get debug messages from Open-Firmware */
|
683 | c0e564d5 | bellard | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
684 | a541f297 | bellard | } |
685 | c0e564d5 | bellard | |
686 | c0e564d5 | bellard | QEMUMachine prep_machine = { |
687 | c0e564d5 | bellard | "prep",
|
688 | c0e564d5 | bellard | "PowerPC PREP platform",
|
689 | c0e564d5 | bellard | ppc_prep_init, |
690 | c0e564d5 | bellard | }; |